EDA设计报告

EDA实验报告多功能数字钟的设计学院院系：物理学与电子技术学院课程名称：EDA技术专业班级：2011级微电子学生姓名：李盛鹏指导教师：田茂设计时间：2013年12月17日一：有关介绍数字钟是一种用数字电路技术实现时、分、秒计时的装置。

在这次设计中，我们采用LED数码管显示时、分、秒，以24小时计时方式，根据数码管动态显示原理来进行显示，数字钟可以手动调整时间，整点报时，以及附加秒表功能。

数字钟的设计方法主要是基于Quartus II软件进行逻辑电路的设计并借助于可编程逻辑器件进行硬件实现，最终本设计实现24小时的时钟计时、整点报时功能，时间重置功能以及秒表功能。

二：实验目的1.了解数字钟的工作原理；2.熟悉用VHDL语言编写驱动七段数码管显示的代码；3.进一步熟悉Quartus II软件；4．秒／分／时／小数点的通过数码管依次显示并正确计数；5．实现整点报时，扬声器发出报时声音；6．时间设置，即手动调时功能：当认为时钟不准确时，可以分别对分／时进行调整；7．秒表功能，即可手动控制秒表的复位、暂停以及开始；三：实验原理多功能数字钟应该具有的功能有：显示时－分－秒、整点报时、小时和分钟可调等基本功能。

首先要知道钟表的工作机理，整个钟表的工作应该是在1Hz 信号的作用下进行，这样每来一个时钟信号，秒增加 1 秒，当秒从59 秒跳转到00 秒时，分钟增加1 分，同时当分钟从59 分跳转到00 分时，小时增加1 小时，但是需要注意的是，小时的范围是从0～23时。

整个秒表的工作应该是在100hz信号的作用的进行，这样每来一个时钟信号，10毫秒位增加 1 秒，当10毫秒位从99 秒跳转到00 秒时，秒增加 1 秒，同时当秒从59 分跳转到00 分时，分钟增加 1 分钟，但是需要注意的是，分钟的范围是从0～59分。

在实验中为了显示的方便，由于分钟和秒钟显示的范围都是从0～59，所以可以用一个3位的二进制码显示十位，用一个四位的二进制码（BCD 码）显示个位，对于小时因为它的范围是从0～23 ，所以可以用一个2 位的二进制码显示十位，用4 位二进制码（BCD 码）显示个位。

实验中由于七段码管是扫描的方式显示，所以虽然时钟需要的是1Hz 时钟信号，但是由于黑金开发板的晶振输出的频率是20Mhz，因此为了得到准确的1Hz 信号，必须对输入的系统时钟进行分频。

而为了实现蜂鸣器的正常工作，需要用到1khz的时钟信号，以及秒表所需的100Hz的时钟信号及时和分调整时所需的2khz的信号，必须对时钟信号再一次分频。

对于整点报时功能，用户可以根据系统的硬件结构和自身的具体要求来设计。

本实验设计的是进行整点的闹铃提醒，让蜂鸣器发出蜂鸣声来实现整点报时，即每当到达整点时，蜂鸣器自动发出5秒蜂鸣声来作为提醒。

四：实验内容本实验的任务就是设计一个多功能数字钟，要求显示格式为小时－分钟－秒钟，整点报时，用蜂鸣器实现5秒的蜂鸣报时。

系统时钟选择时钟模块的20MHz，要得到1Hz 时钟信号，必须对系统时钟进行20000000 次分频。

调整模式的的按键用按键模块的KEY-OK 调节模式，KEY-UP调节时间以及控制秒表的暂停，KEY-LIFT控制秒表的复位，KEY-DOWN 控制时间的暂停，没有按下KEY-OK时，时钟正常工作；按下一次，数码管黑屏；按下两次，切换到调整秒模式，若此时每按下一次KEY-UP，则秒增加一秒；按下三次，切换到调整分钟模式，若此时每按下一次KEY-UP，则分增加一分；按下四次，切换到调整小时模式，若此时每按下一次KEY-UP，则小时增加一小时；按下五次，切换到调整秒表模式，若按下一次KEY-UP，则秒表暂停，再按一次KEY-UP，则秒表继续工作，若按下KEY-LIFT，则此时秒表复位；若按下五次KEY-OK，则数字钟又回到时分秒的正常工作状态下。

五：实验设计（1）顶层实体（如下图）：（2）分频模块：系统时钟选择时钟模块的频率为20MHZ,而实际我们所需要的为1HZ的时钟信号，因此要对系统时钟进行20000000次分频，本实验通过两个分频子程序实现此功能，实现方案如下：VHDL子程序：原理图:如右图.library ieee;use ieee.std_logic_1164. all;entity fre isport(clk ,sel: in std_logic;clk1hz,clk100hz,clk1khz,clk2khz:out std_logic);end fre;architecture beh of fre issignal data1khz,data100hz,data2khz,data1hz : std_logic := '0';beginclk1hz <= data1hz;clk100hz <= data100hz;clk1khz <= data1khz;clk2khz <= data2khz;clk1khz_pro : process(clk) --产生1khz信号variable cnt : integer range 0 to 9999;beginif clk'event and clk='1' thenif cnt = 9999 thencnt := 0 ; data1khz <= not data1khz;elsecnt := cnt + 1;end if;end if;end process clk1khz_pro;clk100hz_pro : process(clk) --产生100hz信号variable cnt : integer range 0 to 99999;beginif clk'event and clk='1' thenif sel='0' then cnt:=0;else if cnt = 99999 thencnt := 0 ; data100hz <= not data100hz;elsecnt := cnt + 1;end if;end if;end if;end process clk100hz_pro;clk2khz_pro : process(clk) --产生2khz信号variable cnt : integer range 0 to 4999;beginif clk'event and clk='1' thenif cnt = 4999 thencnt := 0 ; data2khz <= not data2khz;elsecnt := cnt + 1;end if;end if;end process clk2khz_pro;clk1hz_pro : process(data1khz) --产生1hz 信号variable cnt : integer range 0 to 499;beginif data1khz'event and data1khz='1' thenif sel='0' then cnt:=0;else if cnt = 499 thencnt := 0 ;data1hz <= not data1hz ;elsecnt := cnt + 1;end if;end if;end if;end process clk1hz_pro;end beh;（3）按键部分原理图:如右图.VHDL子程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key_press isport( set ,mode: in std_logic;clk1khz,clk1hz: in std_logic;secout,minout: in std_logic;clk_change,clk2hz_en:out std_logic ;sel,s_ce,m_ce,h_ce,mb_ce:out std_logic;s_en,m_en,h_en,mb_en:out std_logic );end key_press;architecture beh of key_press issignal key1,key2:std_logic;signal sce_reg, mce_reg ,hce_reg,mb_reg:std_logic ;signal ssl,ssen,mmen,hhen,mben:std_logic;signal con : integer range 0 to 5 :=0;--按键按下（延时）beginkey_press2 : process(set,clk1khz)variable cnt :integer range 0 to 999;beginif set='0' thenif clk1khz'event and clk1khz='1'thenif cnt=50 and set='0' thencnt :=cnt+1; key2 <= '1';else cnt:=cnt+1;key2 <= '0';end if;end if;elsecnt:=0; key2<='0';end if;end process key_press2;key_press1 : process(mode,clk1khz)variable cnt :integer range 0 to 999;beginif mode='0' thenif clk1khz'event and clk1khz='1'thenif cnt=50 and mode='0' thencnt :=cnt+1; key1 <= '1';else cnt:=cnt+1;key1 <= '0';end if;end if;elsecnt:=0; key1<='0';end if;end process key_press1;count : process(key1,key2)beginif key1'event and key1='1' thenif con=5 thencon<=0;elsecon<=con+1;end if;end if;end process count;con_pro : process(con)begincase con iswhen 0 => ssl<='1';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';mb_reg <= '0';mben <='0';clk2hz_en <='0';when 1 => ssl<='0';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';mb_reg <= '0';mben <='0';clk2hz_en <='1';when 2 => ssl<='0';sce_reg <= '1';ssen <='1';mce_reg <= '0';mmen <='0';hce_reg <= '0';hhen <='0';mb_reg <= '0';mben <='0';clk2hz_en <='1';when 3 => ssl<='0';sce_reg <= '0';ssen <='0';mce_reg <= '1';mmen <='1';hce_reg <= '0';hhen <='0';mb_reg <= '0';mben <='0';clk2hz_en <='1';when 4 => ssl<='0';sce_reg <= '0';ssen <='0';mce_reg <= '0';mmen <='0';hce_reg <= '1';hhen <='1';mb_reg <= '0';mben <='0';clk2hz_en <='1';when 5 => ssl<='0';sce_reg <= '1';ssen <='1';mce_reg <= '1';mmen <='1';hce_reg <= '1';hhen <='1';mb_reg <= '1';mben <='1';clk2hz_en <='0';when others => ssl<='0';sce_reg <= '0';ssen <='1';mce_reg <= '0';mmen <='1';hce_reg <= '0';hhen <='1';mb_reg <= '0';mben <='0';clk2hz_en <='0';end case;end process con_pro;sel_pro : process(ssl)begincase ssl iswhen '0'=> s_ce<=sce_reg;m_ce<=mce_reg;h_ce<=hce_reg;mb_ce<=mb_reg;clk_change<=key2;when '1'=> s_ce<=ssen;m_ce<=mmen;h_ce<=hhen;mb_ce<=mben;clk_change<=clk1hz;when others=> s_ce<=ssen;m_ce<=secout;h_ce<=minout;clk_change<=clk1hz;end case;end process sel_pro;sel<=ssl;s_en<=ssen;m_en<=mmen;h_en<=hhen;mb_en<=mben;end beh;（4）数字钟部分原理图:VHDL子程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;entity shuzizhong isport(clk_change : in std_logic;s_en,m_en,h_en:in std_logic;sel:in std_logic;secout,minout,hourout :out std_logic;sl,sh,ml,mh,hl,hh:out std_logic_vector(3 downto 0);a:out std_logic_vector(15downto 0));end shuzizhong;architecture behav of shuzizhong issignal low_rega,high_rega,low_regb,high_regb,low_regc,high_regc :std_logic_vector(3 downto 0):="0000";signal sout,mout,hout :std_logic :='0';begin--秒的60进制进制counter_sec_l : process(clk_change,s_en)beginsl<=low_rega;sh<=high_rega;ml<=low_regb;mh<=high_regb;hl<=low_regc;hh<=high_regc;if clk_change'event and clk_change='1' thenif s_en='1' thenif low_rega="1001" thenlow_rega <= "0000";elselow_rega <= low_rega+'1';end if;end if;end if;end process counter_sec_l;counter_sec_h : process(clk_change,s_en,low_rega)beginif clk_change'event and clk_change='1' thenif s_en='1' thenif low_rega="1001" thenif high_rega ="0101"thenhigh_rega <= "0000";elsehigh_rega <= high_rega+'1';end if;end if;end if;end if;end process counter_sec_h;sout <= '1' when low_rega="1001" and high_rega="0101" else '0';----分钟的60进制设置counter_min_l : process(clk_change,m_en)beginif clk_change'event and clk_change='1' thenif m_en='1' thenif sout='1'or sel='0' thenif low_regb="1001" thenlow_regb <= "0000";elselow_regb <= low_regb+'1';end if;end if;end if;end if;end process counter_min_l;counter_min_h : process(clk_change,m_en,low_regb)beginif clk_change'event and clk_change='1' thenif sout='1'or sel='0' thenif m_en='1' thenif low_regb="1001" thenif high_regb ="0101"thenhigh_regb <= "0000";elsehigh_regb <= high_regb+'1';end if;end if;end if;end if;end if;end process counter_min_h;mout <= '1' when low_regb="1001" and high_regb="0101"and sout='1' else '0';--小时的24进制设置counter_hour_l : process(clk_change,h_en)beginif clk_change'event and clk_change='1' thenif h_en='1' thenif mout='1'or sel='0' thenif low_regc="1001"or hout='1' thenlow_regc <= "0000";elselow_regc <= low_regc+'1';end if;end if;end if;end if;end process counter_hour_l;counter_hour_h : process(clk_change,h_en,hout)beginif clk_change'event and clk_change='1' thenif mout='1'or sel='0' thenif h_en='1' thenif hout='1' thenhigh_regc<="0000";else if low_regc="1001" thenhigh_regc <= high_regc+'1';end if;end if;end if;end if;end if;end process counter_hour_h;hout <= '1' when low_regc="0011" and high_regc="0010" else '0';secout<=sout;minout<=mout;hourout<=hout;a<=high_regb&low_regb&high_rega&low_rega ;end behav;（5）秒表部分原理图:VHDL子程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;entity miaobiao isport(clk_100hz,clk1khz: in std_logic;set1 : in std_logic;s_en,m_en,h_en,mb_en:in std_logic;sel:in std_logic;sl0,sh0,ml0,mh0,hl0,hh0:out std_logic_vector(3 downto 0);clk_change:in std_logic);end miaobiao;architecture behav of miaobiao issignal low_rega,high_rega,low_regb,high_regb,low_regc,high_regc :std_logic_vector(3 downto 0):="0000";signal sout,mout,hout :std_logic :='0';signal key2:std_logic;signal con : integer range 0 to 1 :=0;beginprocess(clk1khz)beginif clk_change'event and clk_change='1' thenif mb_en='1' thenif con = 0 thencon <= 1;else con <=0;end if;end if;else con <= con;end if;end process;-- process(con)-- begin-- case con is-- when 0 =>-- when 1 =>-- when others =>-- end case;-- end process;key_press2 : process(set1,clk1khz)variable cnt :integer range 0 to 500;beginif set1='0' thenif clk1khz'event and clk1khz='1'thenif cnt=20 and set1='0' thencnt :=cnt+1; key2 <= '1';else cnt:=cnt+1;key2 <= '0';end if;end if;elsecnt:=0; key2<='0';end if;end process key_press2;--1/100秒的60进制进制counter_sec_l : process(clk_100hz,s_en,key2,clk1khz)beginsl0<=low_rega;sh0<=high_rega;ml0<=low_regb;mh0<=high_regb;hl0<=low_regc;hh0<=hig h_regc;if (key2='1') then low_rega <= "0000";elseif clk_100hz'event and clk_100hz='1' thenif con = 1 thenif s_en='1' thenif low_rega="1001" thenlow_rega <= "0000";elselow_rega <= low_rega+'1';end if;end if;end if;end if;end if;end process counter_sec_l;counter_sec_h : process(clk_100hz,s_en,low_rega)beginif (key2='1') then high_rega <= "0000";elseif clk_100hz'event and clk_100hz='1' thenif s_en='1' thenif con = 1 thenif low_rega="1001" thenif high_rega ="1001"thenhigh_rega <= "0000";elsehigh_rega <= high_rega+'1';end if;end if;end if;end if;end if;end process counter_sec_h;sout <= '1' when low_rega="1001" and high_rega="1001" else '0';--60miao jinzhi counter_min_l : process(clk_100hz,m_en)beginif (key2='1') then low_regb <= "0000";elseif clk_100hz'event and clk_100hz='1' thenif m_en='1' thenif con = 1 thenif sout='1'thenif low_regb="1001" thenlow_regb <= "0000";elselow_regb <= low_regb+'1';end if;end if;end if;end if;end if;end if;end process counter_min_l;counter_min_h : process(clk_100hz,m_en,low_regb)beginif (key2='1') then high_regb <= "0000";elseif clk_100hz'event and clk_100hz='1' thenif sout='1' thenif con = 1 thenif m_en='1' thenif low_regb="1001" thenif high_regb ="0101"thenhigh_regb <= "0000";elsehigh_regb <= high_regb+'1';end if;end if;end if;end if;end if;end if;end process counter_min_h;mout <= '1' when low_regb="1001" and high_regb="0101"and sout='1' else '0';--60fen jinzhicounter_hour_l : process(clk_100hz,h_en)beginif (key2='1') then low_regc <= "0000";elseif clk_100hz'event and clk_100hz='1' thenif h_en='1' thenif mout='1' thenif con = 1 thenif low_regc="1001" thenlow_regc <= "0000";elselow_regc <= low_regc+'1';end if;end if;end if;end if;end if;end if;end process counter_hour_l;counter_hour_h : process(clk_100hz,h_en,hout)beginif (key2='1') then high_regc <= "0000";elseif clk_100hz'event and clk_100hz='1' thenif mout='1' thenif h_en='1' thenif con = 1 thenif low_regc="1001" thenif high_regc ="0101" thenhigh_regc <="0000";elsehigh_regc <= high_regc+'1';end if;end if;end if;end if;end if;end if;end if;end process counter_hour_h;hout <= '1' when low_regc="1001" and high_regc="0101" else '0';end architecture;（6）动态刷新数码管部分原理图:VHDL子程序：library ieee;use ieee.std_logic_1164.all;entity scan isport(clk1khz : in std_logic;sl,sh,ml,mh,hl,hh : in std_logic_vector(3 downto 0);sl0,sh0,ml0,mh0,hl0,hh0 : in std_logic_vector(3 downto 0);clk2hz_en : in std_logic;mb_en : in std_logic;s_ce,m_ce,h_ce : in std_logic;en_out : out std_logic_vector(5 downto 0);dataout : out std_logic_vector(3 downto 0);dian : out std_logic);end scan;architecture beh of scan issignal cnt : integer range 0 to 5;signal en : std_logic_vector(5 downto 0); signal clk2hz : std_logic;signal h_ce_reg,m_ce_reg,s_ce_reg : std_logic;beginh_ce_reg <= not h_ce;m_ce_reg <= not m_ce;s_ce_reg <= not s_ce;cnt_pro : process(clk1khz)beginif clk1khz'event and clk1khz='1' thenif cnt = 5 thencnt <= 0;elsecnt <= cnt + 1;end if;end if;end process cnt_pro;clk2hz_pro :process(clk1khz)variable c : integer range 0 to 499 := 0;beginif clk1khz'event and clk1khz='1' thenif clk2hz_en ='1' thenif c =499 thenc := 0 ; clk2hz <= not clk2hz;elsec := c + 1;end if;elseclk2hz <= '0';end if;end if;end process clk2hz_pro;scan_pro : process(cnt,sl,sh,ml,mh,hl,hh,sl0,sh0,ml0,mh0,hl0,hh0) beginif mb_en='0' thencase cnt iswhen 0 => dataout <= sl;en <= "111110";dian<='0';when 1 => dataout <= sh;en <= "111101";dian<='0';when 2 => dataout <= ml;en <= "111011";dian<='1';when 3 => dataout <= mh;en <= "110111";dian<='0';when 4 => dataout <= hl;en <= "101111";dian<='1';when 5 => dataout <= hh;en <= "011111";dian<='0';when others => null;end case;elsecase cnt iswhen 0 => dataout <= sl0;en <= "111110";dian<='0';when 1 => dataout <= sh0;en <= "111101";dian<='0';when 2 => dataout <= ml0;en <= "111011";dian<='1';when 3 => dataout <= mh0;en <= "110111";dian<='0';when 4 => dataout <= hl0;en <= "101111";dian<='1';when 5 => dataout <= hh0;en <= "011111";dian<='0';when others => null;end case;end if;end process scan_pro;en_out <= en or ((clk2hz & clk2hz) or (h_ce_reg & h_ce_reg)) & ((clk2hz & clk2hz) or (m_ce_reg & m_ce_reg)) & ((clk2hz & clk2hz) or (s_ce_reg & s_ce_reg));end beh;（7）显示数码管部分原理图:VHDL子程序：library ieee;use ieee.std_logic_1164.all;entity display isport(datain : in std_logic_vector(3 downto 0);dataout : out std_logic_vector(7 downto 0);dianin : in std_logic);end display;architecture duan of display isbeginprocess(datain)begincase dianin & datain iswhen "00000" => dataout <="11000000"; --dp,g,f,e,d,c,b,awhen "00001" => dataout <="11111001";when "00010" => dataout <="10100100";when "00011" => dataout <="10110000";when "00100" => dataout <="10011001";when "00101" => dataout <="10010010";when "00110" => dataout <="10000010";when "00111" => dataout <="11111000";when "01000" => dataout <="10000000";when "01001" => dataout <="10010000";when "01010" => dataout <="10111111";when "01011" => dataout <="10000011";when "01100" => dataout <="10100111";when "01101" => dataout <="10100001";when "01110" => dataout <="10000110";when "01111" => dataout <="10001110";when "10000" => dataout <="01000000"; --dp,g,f,e,d,c,b,awhen "10001" => dataout <="01111001";when "10010" => dataout <="00100100";when "10011" => dataout <="00110000";when "10100" => dataout <="00011001";when "10101" => dataout <="00010010";when "10110" => dataout <="00000010";when "10111" => dataout <="01111000";when "11000" => dataout <="00000000";when "11001" => dataout <="00010000";when "11010" => dataout <="00111111";when "11011" => dataout <="00000011";when "11100" => dataout <="00100111";when "11101" => dataout <="00100001";when "11110" => dataout <="00000110";when "11111" => dataout <="00001110";when others => null;end case;end process;end ;（8）整点报时部分原理图:VHDL子程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;--整点报时entity baoshi isport(a:in std_logic_vector(15 downto 0);d:out std_logic);end baoshi;architecture zhong of baoshi issignal beep : std_logic;beginprocess(beep)beginif a<"0000000000000101" then beep<='0';else beep<='1';end if;end process ;d<=beep ;end zhong ;（9）LED灯循环闪烁部分原理图:VHDL子程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY led ISPORT(clk:IN STD_LOGIC;lamp:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END led;ARCHITECTURE fun OF led ISSIGNAL count:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINPROCESS(clk)BEGINIF(rising_edge(clk))THENIF(count<="11")THENIF(count="00")THENlamp<="0001";--循环点亮三只灯ELSIF(count="01")THENlamp<="0010";ELSIF(count="10")THENlamp<="0100";ELSIF(count="11")THENlamp<="1000";END IF;count<=count+1;ELSEcount<="00";END IF;END IF;END PROCESS ;END fun;六：仿真结果七：实验问题（已解决&有待解决）1：刚开始测试时，发现整点时蜂鸣器不能整点报时，检查程序，修改错误，发现原来是程序逻辑有点问题，因而发生了该错误现象。