单片机基础外文翻译参考文献
单片机 外文翻译 外文文献 英文文献 单片机简介 中英对
单片机外文翻译外文文献英文文献单片机简介中英对原文来源图书馆电子资源Single chip brief introductionThe monolithic integrated circuit said that the monolithic micro controller, it is not completes some logical function the chip, but integrates a computer system to a chip on. Summary speaking: A chip has become a computer. Its volume is small, the quality is light, and the price cheap, for the study, the application and the development has provided the convenient condition. At the same time, the study use monolithic integrated circuit is understands the computer principle and the structure best choice.The monolithic integrated circuit interior also uses with the computer function similar module, for instance CPU, memory, parallel main line, but also has with the hard disk behave identically the memory component7 what is different is its these part performance is opposite our home-use computer weak many, but the price is also low, generally does not surpass 10 Yuan then Made some control electric appliance one kind with it is not the 'very complex work foot, We use now the completely automatic drum washer, the platoon petti-coat pipe: VCD and so on Inside the electrical appliances may see its form! It is mainly takes the control section the core part.It is one kind of online -like real-time control computer, online -like is the scene control, needs to have the strong antijamming ability,the low cost, this is also and the off-line type computer (for instance home use PC,) main differenceThe monolithic integrated circuit is depending on the procedure, and may revise. Realizes the different function through the different procedure, particularly special unique some functions, this is other component needs to take the very big effort to be able to achieve, some are the flowered big strength is also very difficult to achieve. One is not the very complex function, if develops in the 50s with the US 74 series, or the 60s's CD4000 series these pure hardware do decides, the electric circuit certainly arc a big PCB board ! But if, if succeeded in the 70s with the US puts in the market the series monolithic integrated circuit, the result will have the huge difference. Because only the monolithic integrated circuit compiles through you the procedure may realize the high intelligence, high efficiency, as well as redundant reliabilityThe CPU is the key component of a digital computer. Its purpose isto decode instruction received from memory and perform transfers, arithmetic, logic, and control operations with data stored in internal registers, memory, or I/O interface units. Externally, the CPU provides one or more buses for transferring instructions, data, and control information to and from components connected to it. A microcontroller is present in the keyboard and in the monitor in the generic computer; thus these components are also shaded. In such microcontrollers, the CPU may be quite different from those discussed in this chapter. The wordlengths may be short, the number of registers small, and the instruction sets limited. Performance, relatively speaking, is poor, but adequatefor the task. Most important, the cost of these microcontrollers is very low, making their use cost effective.Because the monolithic integrated circuit to the cost is sensitive, therefore present occupies the dominant status the software is the most preliminary assembly language7 it was except the binary machine code above the most preliminary language, sincewhy were such preliminary must use?Why high-level did the language already achieve the visualization programming level not to use? The reason is very simple, is the monolithic integrated circuit docs not have home computer such CPU, and also has not looked like the hard disk such mass memory equipment. Inside even if a visualization higher order language compilation script only then a button, also will achieve several dozens K the sizes! Does not speak anything regarding the home use PC hard disk, but says regarding the monolithic integrated circuit cannot accept. The monolithic integrated circuit in the hardware source aspect's use factor must very Gao Caixing, therefore assembly, although primitive actually massively is using, Same truth, if attains supercomputer's on operating system and the application software home use PC to come up the movement, home use PC could also not withstand.It can be said that the 20th century surmounted three "the electricity" the time, namely the electrical time, the Electronic Ageand already entered computer time. However, this kind of computer, usually refers to the personal computer, is called PC machine. It by the main engine, the keyboard, the monitor and so on is composed. Also has a kind of computer, most people actually not how familiar. This kind of computer is entrusts with the intelligence each kind of mechanical monolithic integrated circuit (also to call micro controller). , This kind of computer's smallest system only has used as the name suggests a piece of integrated circuit, then carries on the simple operation and the control. Because its volume is small, usually hides in is accused the machinery "the belly". It in the entire installment, plays is having like the human brains role, it went wrong, the entire installment paralyzed. Now, this kind of monolithic integrated circuit's use domain already very widespread, like the intelligent measuring appliance, the solid work paid by time control, the communication equipment, the guidance system, the domestic electric appliances and so on, Once each product used the monolithic integrated circuit, could get up causes the effect which the product turned to a new generation, often before product range crown by adjective---- …intelligence?, like intelligence washer and so on. Now some factory's technical personnel or other extra-curricular electronic exploiter do certain products, are not theelectric circuit are too complex, is the function is too simple, and is imitated extremely easily. Investigates its reason, possibly on card, in the product has not used on the monolithic integrated circuit or other programmable logical component.单片机简介单片机又称单片微控制器，它不是完成某一个逻辑功能的芯片，而是把一个计算机系统集成到一个芯片上。
单片机英文文献资料及翻译
单片机英文文献资料及翻译单片机(英文：Microcontroller)Microcontroller is a small computer on a single integrated circuit that contains a processor core, memory, and programmable input/output peripherals. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications.A microcontroller's processor core is typically a small, low-power computer dedicated to controlling the operation of the device in which it is embedded. It is often designed to provide efficient and reliable control of simple and repetitive tasks, such as switching on and off lights, or monitoring temperature or pressure sensors.MEMORYMicrocontrollers typically have a limited amount of memory, divided into program memory and data memory. The program memory is where the software that controls the device is stored, and is often a type of Read-Only Memory (ROM). The data memory, on the other hand, is used to store data that is used by the program, and is often volatile, meaning that it loses its contents when power is removed.INPUT/OUTPUTMicrocontrollers typically have a number of programmable input/output (I/O) pins that can be used to interface with external sensors, switches, actuators, and other devices. These pins can be programmed to perform specific functions,such as reading a sensor value, controlling a motor, or generating a signal. Many microcontrollers also support communication protocols like serial, parallel, and USB, allowing them to interface with other devices, including other microcontrollers, computers, and smartphones.APPLICATIONSMicrocontrollers are widely used in a variety of applications, including:- Home automation systems- Automotive electronics- Medical devices- Industrial control systems- Consumer electronics- RoboticsCONCLUSIONIn conclusion, microcontrollers are powerful and versatile devices that have become an essential component in many embedded systems. With their small size, low power consumption, and high level of integration, microcontrollers offer an effective and cost-efficient solution for controlling a wide range of devices and applications.。
单片机英文文献及翻译)
Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。
单片机外文文献翻译(2024)
引言：单片机（Microcontroller）是一种广泛应用于嵌入式系统中的小型计算机芯片。
它集成了处理器核心、存储器、外设接口和时钟电路等核心部件，可以独立运行。
随着全球化的发展，外文文献对于学习和研究单片机领域来说至关重要。
本文翻译的外文文献《MicrocontrollerbasedTrafficLightControlSystem》详细介绍了基于单片机的交通信号灯控制系统。
概述：交通信号灯控制是现代都市交通系统中至关重要的一环。
传统的交通信号灯控制系统通常由定时器控制，不能根据实际交通情况动态调整信号灯的时间。
而基于单片机的交通信号灯控制系统可以实现根据实时交通流量来动态调整信号灯的时间，优化交通效率。
本文将详细介绍该系统的设计和实现。
正文：一、单片机选型1.1.CPU性能：本文选择了一款高性能的32位单片机作为控制核心，它具有较高的处理能力和较大的存储器容量，可以同时处理多条交通路口的信号控制。
1.2.外设接口：该单片机具有丰富的外设接口，可以与交通信号灯、传感器和通信设备等进行连接，实现信号控制和数据交互。
1.3.低功耗设计：为了节约能源和延长系统寿命，在单片机选型时考虑了低功耗设计，降低系统运行的能耗。
二、硬件设计2.1.交通信号灯：在设计交通信号灯时，考虑了日夜可见性和能耗。
采用了高亮度LED作为信号灯光源，同时添加了光敏传感器控制信号灯的亮度，以满足不同时间段的亮度需求。
2.2.传感器：通过安装车辆感应器和行人感应器等传感器，可以在实时监测交通流量的基础上，智能调整信号灯时间，提高路口的交通效率。
2.3.通信设备：在交通信号灯控制系统中引入了通信设备，可以实现各交通路口之间的信息交互和协调控制，提高整体交通系统的效率。
三、软件设计3.1.程序架构：采用了多任务的实时操作系统，将交通信号灯控制、传感器数据处理和通信设备控制等功能分别封装成不同的任务，实现了系统的高效运行和任务调度。
单片机外文翻译外文文献英文文献单片机的发展与应用
单片机外文翻译外文文献英文文献单片机的发展与应用THE Application and Development ofMicrocontroller UnitMonolithic integrated circuits are a computer chip. It uses tec hnology will have a data processing ability of the microprocessor (cpu), storage in rom （program memory and data storage ram ）, the input, output interfaces circuit (I/O) integration interface i tu rned around with a chip in that small, constitutes a very good and the computer hardware system, where the application under the c ontrol of a monolithic integrated circuits can be accurate, fast and efficient procedures provided in advance to complete the task. So, a monolithic integrated circuits will have a computer chip of all t he functions.Thus, the microprocessor （monolithic integrated circuits has generally cpu ）chips are not functional, it can independently com plete modern industrial control required for intelligent control func tions, it is monolithic integrated circuits of the biggest characteristi c.Monolithic integrated circuits, however, and different from mac hines （ a microprocessor chips, the memory chip and input and o utput interfaces chip in with a piece of printed circuit board of a microcomputer ）, Monolithic integrated circuits chip in developing ago, it is only a function vlsi will have a strong, If of application development, it is a small microcomputer control system, but it m achine or a personal computer (pc is essential. the difference betw een).Monolithic integrated circuits of the application of chips at the level of application, the user （monolithic integrated circuits lear ners with users understand the structure of the chip ）monolithic integrated circuits and instruction system, and the integrated use o f technology and system design to the theory and techniques, in th is particular chip design application, thereby, the chip with a parti cular function.Different monolithic integrated circuits have different hardware and software, or the technical features are different, Character de pends on a hardware chip monolithic integrated circuits the intern al structure of the user to use some monolithic integrated circuits, we must know this type of product whether to meet the needs of the facilities and application of the indicators required. The tech nical features include functional characteristics, control and electric al attributes, These information to manufacturers in the technical manual. Software features refers to an instruction system and devel opment support of the environment, the quality of instruction or monolithic integrated circuits for reference, data processing and log ical processing, output characteristics and to the power input requi rements, etc. Development support of the environment, including th e instructions of compatible and portable. support software (contai ns can support the development and application software and hard ware resources. resources). To take advantage of the model of deve lopment of a monolithic integrated circuits application systems, lea rn its structural features and technological characteristic is require d.Monolithic integrated circuits to control system will ever use o f sophisticated electronic circuit or circuit, a control system to achi eve the software controls and enable intelligent, It is monolithic in tegrated circuits to control areas, such as communications products and household appliances, the instruments and processes to contr ol and control devices, theapplication of more monolithic integrate d circuits sector.Monolithic integrated circuits, of course, the application is not limited to the application or the category of the economic perfor mance is more important it is a fundamental change in the traditi onal methods designed to control and mind control techniques. it i s a revolution is an important milestone.Can say now is the policy, a hundred schools of thought conte nd "monolithic integrated circuits, World chip all the company unv eiled his monolithic integrated circuits, from 8, 16 to 32 bits, and,with mainstream c51 series of, and there is not compatible with e ach other, but they, as complementary to monolithic integrated circ uits, the application of the world provide a broad.Throughout monolithic integrated circuits of the development p rocess, the trend of a monolithic integrated circuits, has ：1.the low TDP COMSMcs -51 8031 a series of TDP for 630mw, and now a monolit hic integrated circuits, and generally in 100mw. As to ask for lowe r TDP monolithic integrated circuits, and now each monolithic inte grated circuits are used in the basic cmos (complementary metal o xides semiconductor technology). Like 80c51 adopt a hmos (the hig h density metal oxides semiconductor technology) and chmos (com plementary high density metal oxides semiconductor technology). C mos although TDP low, but owing to their physical characteristics to their work at a speed isn't high enough, but it has a high-spee d chmos TDP and low, these features are more appropriate to ask for lower TDP in a battery operated applications. so this process will be for a period of development. the main way to monolithic i ntegrated circuits。
单片机 英文参考文献 翻译
天津科技大学毕业生外文资料翻译姓名:学院：电子信息与自动化学院专业：测控技术与仪器一．英文原文Progress in ComputersPrestige Lecture delivered to IEE, Cambridge, on 5 February 2009Maurice WilkesThe first stored program computers began to work around 1950. The one we built in Cambridge, the EDSAC was first used in the summer of 1949.These early experimental computers were built by people like myself with varying backgrounds. We all had extensive experience in electronic engineering and were confident that that experience would stand us in good stead. This proved true, although we had some new things to learn. The most important of these was that transients must be treated correctly; what would cause a harmless flash on the screen of a television set could lead to a serious error in a computer.As far as computing circuits were concerned, we found ourselves with an embarass de richess. For example, we could use vacuum tube diodes for gates as we did in the EDSAC or pentodes with control signals on both grids, a system widely used elsewhere. This sort of choice persisted and the term families of logic came into use. Those who have worked in the computer field will remember TTL, ECL and CMOS. Of these, CMOS has now become dominant.In those early years, the IEE was still dominated by power engineering and we had to fight a number of major battles in order to get radio engineering along with the rapidly developing subject of electronics.dubbed in the IEE light current electrical engineering.properly recognised as an activity in its own right. I remember that we had some difficulty in organising a conference because the power engineers’ ways of doing things were not our ways. A minor source of irritation was that all IEE published papers were expected to start with a lengthy statement of earlier practice, something difficult to do when there was no earlier practice Consolidation in the 1960sBy the late 50s or early 1960s, the heroic pioneering stage was over and the computer field was starting up in real earnest. The number of computers in the world had increased and they were much more reliable than the very early ones . To those years we can ascribe the first steps in high level languages and the firstoperating systems. Experimental time-sharing was beginning, and ultimately computer graphics was to come along.Above all, transistors began to replace vacuum tubes. This change presented a formidable challenge to the engineers of the day. They had to forget what they knew about circuits and start again. It can only be said that they measured up superbly well to the challenge and that the change could not have gone more smoothly.Soon it was found possible to put more than one transistor on the same bit of silicon, and this was the beginning of integrated circuits. As time went on, a sufficient level of integration was reached for one chip to accommodate enough transistors for a small number of gates or flip flops. This led to a range of chips known as the 7400 series. The gates and flip flops were independent of one another and each had its own pins. They could be connected by off-chip wiring to make a computer or anything else.These chips made a new kind of computer possible. It was called a minicomputer. It was something less that a mainframe, but still very powerful, and much more affordable. Instead of having one expensive mainframe for the whole organisation, a business or a university was able to have a minicomputer for each major department.Before long minicomputers began to spread and become more powerful. The world was hungry for computing power and it had been very frustrating for industry not to be able to supply it on the scale required and at a reasonable cost. Minicomputers transformed the situation.The fall in the cost of computing did not start with the minicomputer; it had always been that way. This was what I meant when I referred in my abstract to inflation in the computer industry ‘going the other way’. As time goes on people get more for their money, not less.Research in Computer Hardware.The time that I am describing was a wonderful one for research in computer hardware. The user of the 7400 series could work at the gate and flip-flop level and yet the overall level of integration was sufficient to give a degree of reliability far above that of discreet transistors. The researcher, in a university or elsewhere, could build any digital device that a fertile imagination could conjure up. In the Computer Laboratory we built the Cambridge CAP, a full-scale minicomputer with fancy capability logic.The 7400 series was still going strong in the mid 1970s and was used for the Cambridge Ring, a pioneering wide-band local area network. Publication of the design study for the Ring came just before the announcement of the Ethernet. Until these two systems appeared, users had mostly been content with teletype-based local area networks.Rings need high reliability because, as the pulses go repeatedly round the ring, they must be continually amplified and regenerated. It was the high reliability provided by the 7400 series of chips that gave us the courage needed to embark on the project for the Cambridge Ring.The RISC Movement and Its AftermathEarly computers had simple instruction sets. As time went on designers of commercially available machines added additional features which they thought would improve performance. Few comparative measurements were done and on the whole the choice of features depended upon the designer’s intuition.In 1980, the RISC movement that was to change all this broke on the world. The movement opened with a paper by Patterson and Ditzel entitled The Case for the Reduced Instructions Set Computer.Apart from leading to a striking acronym, this title conveys little of the insights into instruction set design which went with the RISC movement, in particular the way it facilitated pipelining, a system whereby several instructions may be in different stages of execution within the processor at the same time. Pipelining was not new, but it was new for small computers The RISC movement benefited greatly from methods which had recently become available for estimating the performance to be expected from a computer design without actually implementing it. I refer to the use of a powerful existing computer to simulate the new design. By the use of simulation, RISC advocates were able to predict with some confidence that a good RISC design would be able to out-perform the best conventional computers using the same circuit technology. This prediction was ultimately born out in practice.Simulation made rapid progress and soon came into universal use by computer designers. In consequence, computer design has become more of a science and less of an art. Today, designers expect to have a roomful of, computers available to do their simulations, not just one. They refer to such a roomful by the attractive name of computer farm.The x86 Instruction SetLittle is now heard of pre-RISC instruction sets with one major exception, namely that of the Intel 8086 and its progeny, collectively referred to as x86. This has become the dominant instruction set and the RISC instruction sets that originally had a considerable measure of success are having to put up a hard fight for survival.This dominance of x86 disappoints people like myself who come from the research wings.both academic and industrial.of the computer field. No doubt, business considerations have a lot to do with the survival of x86, but there are other reasons as well. However much we research oriented people would like to think otherwise. high level languages have not yet eliminated the use of machine code altogether. We need to keep reminding ourselves that there is much to be said for strict binary compatibility with previous usage when that can be attained. Nevertheless, things might have been different if Intel’s major attempt to produce a good RISC chip had been more successful. I am referring to the i860 (not the i960, which was something different). In many ways the i860 was an excellent chip, but its software interface did not fit it to be used in a workstation.There is an interesting sting in the tail of this apparently easy triumph of the x86 instruction set. It proved impossible to match the steadily increasing speed of RISC processors by direct implementation of the x86 instruction set as had been done in the past. Instead, designers took a leaf out of the RISC book; although it is not obvious, on the surface, a modern x86 processor chip contains hidden within it a RISC-style processor with its own internal RISC coding. The incoming x86 code is, after suitable massaging, converted into this internal code and handed over to the RISC processor where the critical execution is performed.In this summing up of the RISC movement, I rely heavily on the latest edition of Hennessy and Patterson’s books on computer design as my supporting authority; see in particular Computer Architecture, third edition, 2003, pp 146, 151-4, 157-8.The IA-64 instruction set.Some time ago, Intel and Hewlett-Packard introduced the IA-64 instruction set. This was primarily intended to meet a generally recognised need for a 64 bit address space. In this, it followed the lead of the designers of the MIPS R4000 and Alpha. However one would have thought that Intel would have stressed compatibility with the x86; the puzzle is that they did the exact opposite.Moreover, built into the design of IA-64 is a feature known as predicationwhich makes it incompatible in a major way with all other instruction sets. In particular, it needs 6 extra bits with each instruction. This upsets the traditional balance between instruction word length and information content, and it changes significantly the brief of the compiler writer.In spite of having an entirely new instruction set, Intel made the puzzling claim that chips based on IA-64 would be compatible with earlier x86 chips. It was hard to see exactly what was meant.Chips for the latest IA-64 processor, namely, the Itanium, appear to have special hardware for compatibility. Even so, x86 code runs very slowly.Because of the above complications, implementation of IA-64 requires a larger chip than is required for more conventional instruction sets. This in turn implies a higher cost. Such at any rate, is the received wisdom, and, as a general principle, it was repeated as such by Gordon Moore when he visited Cambridge recently to open the Betty and Gordon Moore Library. I have, however, heard it said that the matter appears differently from within Intel. This I do not understand. But I am very ready to admit that I am completely out of my depth as regards the economics of the semiconductor industry.AMD have defined a 64 bit instruction set that is more compatible with x86 and they appear to be making headway with it. The chip is not a particularly large one. Some people think that this is what Intel should have done. [Since the lecture was delivered, Intel have announced that they will market a range of chips essentially compatible with those offered by AMD.]The Relentless Drive towards Smaller TransistorsThe scale of integration continued to increase. This was achieved by shrinking the original transistors so that more could be put on a chip. Moreover, the laws of physics were on the side of the manufacturers. The transistors also got faster, simply by getting smaller. It was therefore possible to have, at the same time, both high density and high speed.There was a further advantage. Chips are made on discs of silicon, known as wafers. Each wafer has on it a large number of individual chips, which are processed together and later separated. Since shrinkage makes it possible to get more chips on a wafer, the cost per chip goes down.Falling unit cost was important to the industry because, if the latest chips are cheaper to make as well as faster, there is no reason to go on offering the old ones, at least not indefinitely. There can thus be one product for the entiremarket.However, detailed cost calculations showed that, in order to maintain this advantage as shrinkage proceeded beyond a certain point, it would be necessary to move to larger wafers. The increase in the size of wafers was no small matter. Originally, wafers were one or two inches in diameter, and by 2000 they were as much as twelve inches. At first, it puzzled me that, when shrinkage presented so many other problems, the industry should make things harder for itself by going to larger wafers. I now see that reducing unit cost was just as important to the industry as increasing the number of transistors on a chip, and that this justified the additional investment in foundries and the increased risk.The degree of integration is measured by the feature size, which, for a given technology, is best defined as the half the distance between wires in the densest chips made in that technology. At the present time, production of 90 nm chips is still building upSuspension of LawIn March 1997, Gordon Moore was a guest speaker at the celebrations of the centenary of the discovery of the electron held at the Cavendish Laboratory. It was during the course of his lecture that I first heard the fact that you can have silicon chips that are both fast and low in cost described as a violation of Murphy’s law.or Sod’s law as it is usually called in the UK. Moore said that experience in other fields would lead you to expect to have to choose between speed and cost, or to compromise between them. In fact, in the case of silicon chips, it is possible to have both.In a reference book available on the web, Murphy is identified as an engineer working on human acceleration tests for the US Air Force in 1949. However, we were perfectly familiar with the law in my student days, when we called it by a much more prosaic name than either of those mentioned above, namely, the Law of General Cussedness. We even had a mock examination question in which the law featured. It was the type of question in which the first part asks for a definition of some law or principle and the second part contains a problem to be solved with the aid of it. In our case the first part was to define the Law of General Cussedness and the second was the problem;A cyclist sets out on a circular cycling tour. Derive an equation giving the direction of the wind at any time.The single-chip computerAt each shrinkage the number of chips was reduced and there were fewer wiresgoing from one chip to another. This led to an additional increment in overall speed, since the transmission of signals from one chip to another takes a long time.Eventually, shrinkage proceeded to the point at which the whole processor except for the caches could be put on one chip. This enabled a workstation to be built that out-performed the fastest minicomputer of the day, and the result was to kill the minicomputer stone dead. As we all know, this had severe consequences for the computer industry and for the people working in it.From the above time the high density CMOS silicon chip was Cock of the Roost. Shrinkage went on until millions of transistors could be put on a single chip and the speed went up in proportion.Processor designers began to experiment with new architectural features designed to give extra speed. One very successful experiment concerned methods for predicting the way program branches would go. It was a surprise to me how successful this was. It led to a significant speeding up of program execution and other forms of prediction followedEqually surprising is what it has been found possible to put on a single chip computer by way of advanced features. For example, features that had been developed for the IBM Model 91.the giant computer at the top of the System 360 range.are now to be found on microcomputersMurphy’s Law remained in a state of suspension. No longer did it make sense to build experimental computers out of chips with a small scale of integration, such as that provided by the 7400 series. People who wanted to do hardware research at the circuit level had no option but to design chips and seek for ways to get them made. For a time, this was possible, if not easyUnfortunately, there has since been a dramatic increase in the cost of making chips, mainly because of the increased cost of making masks for lithography, a photographic process used in the manufacture of chips. It has, in consequence, again become very difficult to finance the making of research chips, and this is a currently cause for some concern.The Semiconductor Road MapThe extensive research and development work underlying the above advances has been made possible by a remarkable cooperative effort on the part of the international semiconductor industry.At one time US monopoly laws would probably have made it illegal for UScompanies to participate in such an effort. However about 1980 significant and far reaching changes took place in the laws. The concept of pre-competitive research was introduced. Companies can now collaborate at the pre-competitive stage and later go on to develop products of their own in the regular competitive manner.The agent by which the pre-competitive research in the semi-conductor industry is managed is known as the Semiconductor Industry Association (SIA). This has been active as a US organisation since 1992 and it became international in 1998. Membership is open to any organisation that can contribute to the research effort.Every two years SIA produces a new version of a document known as the International Technological Roadmap for Semiconductors (ITRS), with an update in the intermediate years. The first volume bearing the title ‘Roadmap’ was issued in 1994 but two reports, written in 1992 and distributed in 1993, are regarded as the true beginning of the series.Successive roadmaps aim at providing the best available industrial consensus on the way that the industry should move forward. They set out in great detail.over a 15 year horizon. the targets that must be achieved if the number of components on a chip is to be doubled every eighteen months.that is, if Moore’s law is to be maintained.-and if the cost per chip is to fall.In the case of some items, the way ahead is clear. In others, manufacturing problems are foreseen and solutions to them are known, although not yet fully worked out; these areas are coloured yellow in the tables. Areas for which problems are foreseen, but for which no manufacturable solutions are known, are coloured red. Red areas are referred to as Red Brick Walls.The targets set out in the Roadmaps have proved realistic as well as challenging, and the progress of the industry as a whole has followed the Roadmaps closely. This is a remarkable achievement and it may be said that the merits of cooperation and competition have been combined in an admirable manner.It is to be noted that the major strategic decisions affecting the progress of the industry have been taken at the pre-competitive level in relative openness, rather than behind closed doors. These include the progression to larger wafers.By 1995, I had begun to wonder exactly what would happen when the inevitable point was reached at which it became impossible to make transistors any smaller. My enquiries led me to visit ARPA headquarters in Washington DC, where I was given a copy of the recently produced Roadmap for 1994. This made it plain that seriousproblems would arise when a feature size of 100 nm was reached, an event projected to happen in 2007, with 70 nm following in 2010. The year for which the coming of 100 nm (or rather 90 nm) was projected was in later Roadmaps moved forward to 2004 and in the event the industry got there a little sooner.I presented the above information from the 1994 Roadmap, along with such other information that I could obtain, in a lecture to the IEE in London, entitled The CMOS end-point and related topics in Computing and delivered on 8 February 1996.The idea that I then had was that the end would be a direct consequence of the number of electrons available to represent a one being reduced from thousands to a few hundred. At this point statistical fluctuations would become troublesome, and thereafter the circuits would either fail to work, or if they did work would not be any faster. In fact the physical limitations that are now beginning to make themselves felt do not arise through shortage of electrons, but because the insulating layers on the chip have become so thin that leakage due to quantum mechanical tunnelling has become troublesome.There are many problems facing the chip manufacturer other than those that arise from fundamental physics, especially problems with lithography. In an update to the 2001 Roadmap published in 2002, it was stated that the continuation of progress at present rate will be at risk as we approach 2005 when the roadmap projects that progress will stall without research break-throughs in most technical areas “. This was the most specific statement about the Red Brick Wall, that had so far come from the SIA and it was a strong one. The 2003 Roadmap reinforces this statement by showing many areas marked red, indicating the existence of problems for which no manufacturable solutions are known.It is satisfactory to report that, so far, timely solutions have been found to all the problems encountered. The Roadmap is a remarkable document and, for all its frankness about the problems looming above, it radiates immense confidence. Prevailing opinion reflects that confidence and there is a general expectation that, by one means or another, shrinkage will continue, perhaps down to 45 nm or even less.However, costs will rise steeply and at an increasing rate. It is cost that will ultimately be seen as the reason for calling a halt. The exact point at which an industrial consensus is reached that the escalating costs can no longer be met will depend on the general economic climate as well as on the financial strength of the semiconductor industry itself.。
单片机的外文文献及中文翻译
SCM is an integrated circuit chip，is the use of large scale integrated circuit technology to a data processing capability of CPU CPU random access memory RAM，read—only memory ROM，a variety of I / O port and interrupt system, timers / timer functions (which may also include display driver circuitry，pulse width modulation circuit，analog multiplexer, A / D converter circuit) integrated into a silicon constitute a small and complete computer systems。
SCM is also known as micro—controller （Microcontroller)，because it is the first to be used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor。
The first design is by a large number of peripherals and CPU on a chip in the computer system，smaller, more easily integrated into a complex and demanding on the volume control device which. The Z80 INTEL is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors will be parting ways。
单片机英文参考文献(精选120个)
我国的单片机起步虽然较晚，但经过几十年的发展，也取得了巨大的成就。
不论是工业生产还是社会生活的各个方面都离不开单片机的使用。
下面是搜素整理的单片机英文参考文献的分享，以供参考。
单片机英文参考文献一： [1]Hui Wang. Optimal Design of Single Chip Microcomputer Multi-machine Serial Communication based on Signal VerificationTechnology[J]. International Journal of Intelligent Information and Management Science,2020,9（1）。
[2]Philip J. Basford,Steven J. Johnston,Colin S. Perkins,Tony Garnock-Jones,Fung Po Tso,Dimitrios Pezaros,Robert D. Mullins,Eiko Yoneki,Jeremy Singer,Simon J. Cox. Performance analysis of single board computer clusters[J]. Future Generation ComputerSystems,2020,102. [3]. Computers; Reports from University of Southampton Describe Recent Advances in Computers （Performance Analysis of Single Board Computer Clusters）[J]. Computers, Networks & Communications,2020. [4]Yunyu Cao,Jinjin Dang,Chenxu Cao. Design of Automobile Digital Tire Pressure Detector[J]. Journal of Scientific Research and Reports,2019. [5]Sudad J. Ashaj,Ergun Er?elebi. Reduce Cost Smart Power Management System by Utilize Single Board Computer Artificial Neural Networks for Smart Systems[J]. International Journal of Computational Intelligence Systems,2019. [6]Hanhong Tan*, Yanfei Teng. Design of PWM Lighting brightness Control based on LAN QIAO Cup single Chip Microcomputer[J]. International Journal of Computational and Engineering,2019,4（3）。
电气自动化 单片机 外文文献 英文文献 外文翻译 中英对照
Single-chip1.The definition of a single-chipSingle-chip is an integrated on a single chip a complete computer system .Even though most of his features in a small chip，but it has a need to complete the majority of computer components：CPU，memory，internal and external bus system，most will have the Core.At the same time，such as integrated communication interfaces，timers，real-time clock and other peripheral equipment.And now the most powerful single-chip microcomputer system can even voice ，image，networking，input and output complex system integration on a single chip.Also known as single-chip MCU（Microcontroller），because it was first used in the field of industrial control.Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large numberof peripherals and CPU in a single chip，the computer system so that smaller，more easily integrated into the complex and demanding on the volume control devices.INTEL the Z80 is one of the first design in accordance with the idea of the processor，From then on，the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all the four.One of the most successful is INTELs 8031，because the performance of a simple and reliable access to a lot of good praise.Since then in 8031to develop a single-chip microcomputer system MCS51 series.based on single-chip microcomputer system of the system is still widely used until now.As the field of industrial control requirements increase in the beginning of a 16-bit single-chip，but not ideal because the price has not been very widely used.After the90s with the big consumer electronics product development，single-chip technology is a huge improvement.INTEL i960 series with subsequent ARM in particular ，a broad range of application，quickly replaced by 32-bit single-chip 16-bit single-chip performance has been the rapid increase in processing power compared to the 80s to raise a few hundred times.At present，the high-end 32-bit single-chip frequency over 300MHz，the performance of the mid-90s close on the heels of a special processor，while the ordinary price of the model dropped to one U.S dollars，the most high-end models，only 10 U.S dollars.Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer.In PDAs and cellphones as the coreprocessing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems，so it was up to the application.In fact the number of single-chip is the worlds largest computer.Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration.Phone，telephone，calculator，home applicances，electronic toys，handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip.And personal computers also have a large number of single-chip microcomputer in the workplace.Vehicles equipped with more than 40 Department of the general single-chip ，complex industrial control systems and even single-chip may have hundreds of work at the same time!SCM is not only far exceeds the number of PC and other integrated computing,even more than the number of human beings.2.single-chip introducedSingle-chip,also known as single-chip microcontroller,it is not the completion of a logic function of the chip,but a computer system integrated into a chip.Speaking in general terms: a single chip has become a computer .Its small size,light weight,cheap,for the learning,application and development of facilities provided .At the same time,learning to use the principle of single-chip computer to understand and structure the best choice.Single-chip and computer use is also similar to the module,such as CPU,memory,parallel bus, as well as the role and the same hard memory,is it different from the performance of these components are relatively weak in our home computer a lot,but the price is low ,there is generally no more than 10yuan,,can use it to make some control for a class of electrical work is not very complex is sufficient.We are using automatic drum washing machines, smoke hood,VCD and so on inside the home appliances can see its shadow! It is mainly as part of the core components of the control.It is an online real-time control computer,control-line is at the scene,we need to have a stronger anti-interference ability,low cost,and this is off-line computer(such as home PC)The main difference.By single-chip process,and can be amended.Through different procedures to achieve different functions,in particular the special unique features,this is the need to charge other devices can do a great effort,some of it is also difficult to make great efforts to do so .A function is not very complicated fi the United States the development of the 50s series of 74 or 60 during the CD4000series to get these pure hardware,the circuit must be a big PCB board !However,if the United States if the successful 70s seriesof single-chip market ,the result will be different!Simply because the adoption of single-chip preparation process you can achieve high intelligence,high efficiency and high reliability!Because of cost of single-chip is sensitive,so the dominant software or the lowest level assembly language,which is in addition to the lowest level for more than binary machine code of the language ,since such a low-level so why should we use ?Many of the seniors language has reached a level of visual programming why is it not in use ?The reason is simple ,that is,single-chip computer as there is no home of CPU,also not as hard as the mass storage device.A visualization of small high-level language program,even if there is only one button which will reach the size of dozens of K! For the home PCs hard drive is nothing,but in terms of the single-chip microcomputer is unacceptable.Single-chip in the utilization of hardware resources have to do very high ,so the compilation of the original while still in heavy use .The same token ,if the computer giants operating system and appplications run up to get the home PC,homePCcan not afford to sustain the same.It can be said that the twentieth century across the three “power”of the times,that is ,the electrical era,the electronic age and has now entered the computer age. However ,such a computer,usually refers to a personal computer,or PC.It consisits of the host ,keyboards,displays .And other components.There is also a type of computer,not how most people are familiar with . This computer is smart to give a variety of mechanical single-chip(also known as micro-controller).As the name suggests,these computer systems use only the minimum of an integrated circuit to make a simple calculation and control. Because of its small size,are usually charged with possession of machine in the “belly”in. It in the device,like the human mind plays a role, it is wrong,the entire device was paralyzed .Now,this single chip has a very wide field of use,such as smart meters,real-time industrial control,communications equipment,navigation systems,and household appliances. Once a variety of products with the use of the single-chip ,will be able to play so that the effectiveness of product upgrading,product names often adjective before the word “intelligent”,such as was hing machines and so intelligent.At present,some technical personnel of factories or other amateur electrtonics developers from engaging in certain products ,not the circuit is too complex ,that is functional and easy to be too simple imitation.The reason may be the product not on the cards or the use of single-chip programmable logic device on the other.3.single-chip historysingle-chip 70 was born in the late 20th century,experienced a SCM,MCU,SOC three stages.Single-chip micro-computer 1.SCM that(Single Chip Microcomputer)stage,is mainly a single from to find the best of the best embedded systems architecture.”Innovation model”to be successful,lay the SCM with the general-purpose computers,a completely different path of development . In embedded systems to create an independent development path,Intel Corporation credit.That is 2.MCU microcontroller(Micro Controller Unit)stage,the main direction of technology development: expanding to meet the embedded applications,the target system requirements for the various peripheral circuits and interface circuits,to highlingt the target of intelligent control.It covers all areas related with the objectSystem,therefore,the development of MCU inevitably fall on the heavy electrical,electronics manufacturers. From this point of view ,Intels development gradually MCU has its objective factors.MCU in the development ,the most famous manufacturers when the number of Philips Corporation.Philips in embedded applications for its enormous advantages,the MCS-51 from the rapid deveploment of single-chip micro-computer to the microcontroller.Therefore,when we look back at the path of development of embedded systems,Intel and Philips do not forget the historical merits.3.Single-chip is an independent embedded systems development,to the MCU an important factor in the development stage,is seeking applications to maximize the natural trend .With the mico-electronics technology,IC design,EDA tools development,based on the single-chip SOC design application systems will have greater development. Therefore,the understanding of single-chip micro-computer from a single ,monolithic single-chip microcontroller extends to applications.4.Single-chip applicationsAt present,single-chip microcomputer to infiltrate all areas of our lives,which is very difficult to find the area of almost no traces of single-chip microcomputer.Missile navigation equipment,aircraft control on a variety of instruments,compuer network communications and data transmission,industrial automation,real-time process control and data processing ,are widely used in a variety of smart IC card,limousine civilian security systems,video recorders,cameras,the control of automatic washing machines,as well as program-controllde toys,electronic pet,etc,which are inseparable from the single-chip microcomputer.Not to mention the field of robot automation ,intelligent instrumentation,medical equipment has been. Therefore,the single- chip learning ,development and application to a large number of computer applications and intelligent control of scientists,engineers.Single-chip widely used in instruments and meters,household appliances，medical equipment ,acrospace,specialized equipment and the intellingent management in areas such as process control,generally can be divided into the following areas:1.In the smart application of instrumentationSingle-chip with small size,low power consumption,control,and expansion flexibility , miniaturization and ease of sensors,can be realized,suchvoltage,power,frequency,humidity,temperature,flow,speed,thickness,angle,length,hardness,elemen t,measurement of physical pressure. SCM makes use of digital instrumentation,intelligence,miniaturization and functional than the use of electronic or digital circuitry even stronger.For example,precision measurement equipment(power meter,oscilloscope,and analyzer).2.In the industrial controlMCU can constitute a variety of control systems,data acquisition system.Such as factory assembly line of intelligent management ,intelligent control of the lift ,all kinds of alarm systems ,and computer networks constitute a secondary control system.3.In the applicationof household appliancesIt can be said that almost all home appliances are using the single-chip control,electric rice from favorable,washing machines,refrigerators,air conditioners,color TV and other audio video equipment,and then to the electronic weighing equipment,all kinds ,everywhere.4.On computer networks and communication applications in the field ofGenerally with the modern single-chip communication interface,can be easily carried out with computer carried out with computer data communications,computer networks and in inter-application communications equipment to provide an excellent material conditions,the communications equipment to provide an excellent material condition,from the mobile phone ,telephone , mini-program-controlled switchboards,buiding automated communications system call,the train wireless communications,and then you can see day-to-day work of mobile phones,Mobile communications,such as radios.5.Single-chip in the field of medical equipment applicationsSingle-chip microcomputer in medical devices have a wide range of purpose,such as medical ventilator,various analyzers,monitors,ultrasonic diagnostic equipment and hospital call systems.6.In a variety of large-scale electrical applications of modularSome special single-chip design to achieve a specific function to carry out a variety of modular circuitapplications,without requiring users to understand its internal structure.Integrated single-chip microcomputer such as music ,which seems to be simpleFunctions,a miniature electronic chip in a pure(as distinct from the principle of tape machine),would require a complex similar to the principle of the computer. Such as :music signal to digital form stored in memory(similar to ROM),read out by the microcontroller into analog music signal(similar to the sound card).In large circuits,modular applications that greatly reduces the size ,simplifying the circuit and reduce the damage,error rate ,but also to facilitate the replacement.In addition,single-chip microcomputer in the industrial,commercial,financial,scientific research ,education,defense aerospace and other fields have a wide range of uses.单片机1.单片机定义单片机是一种集成在电路芯片上的完整计算机系统。
(完整版)单片机毕业参考英文文献及翻译
Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces。
This company introduced 8 top-grade one—chip computers of MCS—51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one—chip computer the chips have，such as 8051， 8031, 8751， 80C51BH, 80C31BH，etc。
, their basic composition, basic performance and instruction system are all the same. 8051 daily representatives— 51 serial one-chip computers 。
An one—chip computer system is made up of several following parts: （ 1) One microprocessor of 8 (CPU）。
( 2） At slice data memory RAM (128B/256B）,it use not depositting not can reading /data that write, such as result not middle of operation，final result and data wanted to show, etc. ( 3） Procedure memory ROM/EPROM (4KB/8KB )，is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers， such as 8031 , 8032， 80C ，etc。
单片机 外文翻译 外文文献 英文文献ROM的单片机
单片机外文翻译外文文献英文文献ROM的单片机外文翻译外文原文Method of manufacturing a single chip semiconductor integratedcircuit device including a mask rom in a short timeThis application is based upon and claims the benefit of priorityfrom Japanese patent application No. 2006-207797, filed on Jul. 31, 2006, the disclosure of which is incorporated herein its entirety by reference.BACKGROUND OF THE INVENTIONThis invention relates to a method of manufacturing a single chip semiconductor integrated circuit device (a microcontroller) and a method of debugging a program of the single chip semiconductor integratedcircuit device.As well know in the art, a microcomputer is defined by aminiaturized electronic computer constituted by a microprocessor. The microprocessor is a processor where in a central processing unit (CPU)of the computer is integrated on one or few large-scale integratedcircuits (LSIs). The microcomputer normally comprises the CPU, aninput/output device, and a main memory device. The main memory device comprises a random access memory (RAM) and a read only memory (ROM). An input/output control LSI is used as a connecting circuit portion for the input/output device. A single chip microcomputer is a microcomputerwhere the CPU, the RAM, the ROM, and the input/output LSI are mounted ina one chip. The single chip microcomputer is called a one chip microcomputer.A program is read from an outside of a chip of the microprocessor while the program is preliminarily installed in the inside in the chip of the signal chip microcomputer. The microprocessor is capable of changing processing contents by renewing the program of the outside while it is almost impossible for the single chip microcomputer to change processing contents by a user because the program is already installed in the inside in the chip thereof. Herein, the program is preliminarily stored in the ROM.In addition, as well know in the art, read only memories (ROMs) are broadly divided into mask ROMs wherein wiring of contents is carried out at a manufacturing process in a semiconductor maker and programmable ROMs (PROMs) where a user can electrically write with the program therein.The mask ROMs can be manufactured at the lowest price among the semiconductor memories in principle. Therefore, products having a large memory capacity are manufactured as the mask ROMs. On the other hand, the programmable ROMs have features wherein the writing of the program can carry out by a user at hand. The programmable ROMs are classified into EPROM in a narrow sense wherein the user can program only once, erasable and programmable ROMs (EPROMs) which can be electrically programmed and can be erased by ultraviolet light or the like, and electrically erasable programmable ROMs (EEPROMs).In the EPROM, the user can program and all of data can be erased by irradiating it with ultraviolet light to be enable to rewrite therein. Inasmuch as a glass window for erasing by ultraviolet light is required in the EPROM, the EPROM is commonly contained in a ceramic package. There is a one time programmable ROM (OTP) as the EPROM in a narrow sense. The OPT comprises a semiconductor chip embedded there in that is similar to that of the EPROM but the OTP cannot be erased by ultraviolet light because the OTP comprises a package with no window. By using an ordinary EPROM programmer, the user can program information to each memory cell in the OTP only once. The OTP has a cost which is higher than that of the mast ROM and which is lower than that of the EPROM. There is a flash EEPROM as a kind of the EEROMs. The flash EEPROM is also called a flash memory which can electrically erase all of bit contents (which may erase every block) to rewrite contents therein among the programmable read only memories (PROMs).Such a single chip microcomputer is mounted in an ordinary electric calculator, a printer, a keyboard, a microprocessor-controlled automatic (electric) rice cooker, a microprocessor-controlled camera, an engine controller for an automobile, an so on. Inasmuch as the single chip microcomputer mainly often controls operations of its equipment with it installed in the equipment, the single chip microcomputer may be called a microcontroller. In addition, the microcontroller is a kind of the single chip semiconductor integrated circuit devices.In order to effectively carry out development of the equipment (an electronic device) in which such a single chip microcomputer (microcontroller) is installed, various development systems (development tools) are delivered by semiconductor makers or development tool makers. Inasmuch as the single chip microcomputer (microcontroller) comprises hardware and software which are closely related to each other and has a short time period of development, debug of the software and checking of the hardware must be simultaneously carried out. That is, development of the hardware and the software must often carried out concurrently. In this event, the debug of the software is required with a yet-to-be-completed hardware.There is an emulator as one of debug tools (development tools). Herein, the emulator is a device or a computer program for imitating, by using a system, another system. With the help of the emulator, verification of functional operations of the equipment (electronic device) installed with the software is carried out. Emulators are divided into an in-circuit emulator (ICE) which is used with it directly connected to the equipment (the electronic device) under development and a software emulator using a logic simulator. That is, the in-circuit emulator is a development tool for supporting the verification of the functional operations of the equipment (electronic device) by directly connecting it to the equipment (electronic device) mounting a program-controlled microcontroller under development.Usually, development of the hardware of the microcontroller iscarried out by the semiconductor maker side while development of the software of the microcontroller is carried out by the user side. That is, development of the microcontroller is carried out by cooperative working of the semiconductor maker and the user.Now, the description will proceed to a conventional method of manufacturing ofa microcontroller. Herein, the description will be directed to the method of manufacturing, as an ultimate product, a microcontroller comprising a mask ROM in which an ultimate program is stored.[0013]First of all, between the semiconductor maker and the user, investigation of specifications of the microcontroller (the single chip semiconductor integrated circuit device) to be manufactured is carried out. Herein, the ultimate microcontroller to be manufactured comprises a CPU, an RAM, a mask ROM, and an input/output control LSI which are incorporated into a one chip. In addition, the CPU, the RAM, the mask ROM, and the input/output control LSI are mutually connected to each other via an internal bus. The internal bus comprises an address bus and a data bus.The semiconductor maker provides the user with the emulator (the software emulator and the in-circuit emulator) as the envelopment tool while the user develops, by using the emulator, software (a program) to be stored in the above-mentioned mask ROM.Subsequently, the semiconductor maker designs a product in OTP version and the user carries out debug of the program using the software emulator. Herein, the product in OTP version (a provisional microcontroller) to be designed comprises a CPU, an RAM, the OTP, and an input/output control LSI which are incorporated into a one chip. In other words, the provisional microcontroller is similar in structure to the ultimate microcontroller except that the OTP is used in lieu of the mask ROM. However, any program is not stored in the OTP and storing of the program to the OTP is carried out by the user side in the manner which will later be described. The provisional microcontroller is sealed in a semiconductor package. On the other hand, carried out by the user, debug of the program using the software emulator is carried out with the hardware put into a yet-to-be-completed state.The semiconductor maker provides the user with a plurality of the provisional microcontrollers which are similar in structure to one another. The user stores, by using the EPROM programmer (writer), a provisional program (which is a program debugged by using the software emulator) in the OTP in one selected from the plurality of the provisional microcontrollers, mounts the selected provisional microcontroller in question in an equipment (a target board), andcarries out a test of the provisional program. That is, by using the above-mentioned in-circuit emulator, the user carries out verification of functional operations of the equipment (target board). In the manner which is described above, the OTP is a PROM in which information can bewritten only once. Accordingly, if any correction place (error) is found out in the provisional program by the test, the user stores a corrected provisional program in another provisional microcontroller, and carries out retest and re-correction of the corrected provisional program. That is, the test and the correction (the retest and the re-correction) of the provisional program is repeatedly carried out. By repeating operations of the test and the correction (the retest and the re-correction) for the provisional program, an ultimate program is determined by the user side.On the other hand, after the provisional controllers are provided to the user, the semiconductor maker subsequently carries out design of a produce in mask ROM version. Herein, the product in mask ROM version (an actual microcontroller to bemounted in the equipment) to be designed comprises a CPU, an ROM,the mask ROM, and an input/output control LSI which are incorporated in a one chip. However, at this time instance, the ultimate program has yet to be written in the mask ROM of the actual microcontroller.[0018]The user sends (provides) the above-mentioned determined ultimate program to the semiconductor maker. The semiconductor maker stores, using ion implantation, the ultimate program in the mask ROM of the actual microcontroller, thereby a microcontroller as the ultimate product is manufactured. In addition, the microcontroller manufacturedin the manner which is described above is sealed in a semiconductor package and is produced in large quantity. And, ultimatemicrocontrollers produced in large quantity are provided to the user. [0019]The user mounts the ultimate microcontrollers in the respective equipments (electronic devices), thereby the equipments are produced in large quantity.Although the above-mentioned microcontroller comprises one semiconductor chip, U.S. Pat. No. 7,199,469 or U.S. Pat. No. 7,199,469B2 issued to Ishida et al. discloses a semiconductor device (a microcontroller) having stacked two semiconductor chips sealed with a resin seal member. As the semiconductor device, a semiconductor device called a multi chip package (MCP) type is known. Although ones having various structures are developed and manufactured in the MCP type semiconductor devices, the MCP type semiconductor device comprising the stacked two semiconductor devices sealed with the resin seal member becomes most widespread. Ishida et al. discloses the semiconductordevice wherein a chip for a microcomputer (a first semiconductor chip) and a chip for EEPROM (a second semiconductor chip) are incorporated in a package. That is, Ishida et al. discloses the semiconductor device wherein the chip for EEPROM (the second semiconductor chip) is stackedon the chip for the microcomputer (the first semiconductor chip) and the two chips are sealed with the resin seal member. The chip for the microcomputer comprises a processor unit (CPU), an ROM unit, an RAM unit, a timer unit, an A/D conversion unit, a serial communication interface unit, a data input/output circuit unit, and so on which are mounted on the same board. Those units are mutually connected through a data busand an address bus. The processor unit mainly comprises a central processing portion, a control circuit portion, an arithmetic circuit portion, and so on. The chip for the microcomputer having such a structure is operated by a program. On the other hand, the chip for the EEPROM comprises a serial communication interface unit, a nonvolatile storage unit, and so on which are mounted on the same board. According to Ishida et al., electrical connection between the first semiconductor chip and the second semiconductor chip is carried out by internal leads among leads disposed around the first semiconductor chip and two bonding wires. [0021]In addition, United States Patent Application Publication No. 2002/0027281 A1 or US 2002/0027281 A1 discloses a multi chip package (a semiconductor device) which is capable of controlling a rise in temperature, which occurs inside a package due to heat (self-heating) radiated from a semiconductor chip. According to US 2002/0027281 A1, the multi chip package constructing a microcontroller comprises a lower semiconductor chip on which the microcontroller including a mask ROM is formed and an upper semiconductor chip including flash memory mounted on the lower semiconductor chip. Inasmuch as no transistor is formed on the lower semiconductor chip under the upper semiconductor chip, it is possible to neglect the self-heating in this area. In addition, US 2002/0027281 A1 discloses an embodiment wherein transistors having a mask ROM function are formed on the lower semiconductor chip at a mounting area (a substantially central area) for the upper semiconductor chip and the upper semiconductor chip (the flash memory)is mounted on the mounting area. In this event, the mask ROM function in the lower semiconductor chip is discarded.In the above-mentioned conventional method of manufacturing the microcontroller, the semiconductor maker must carry out design of two kinds of products, namely, design of a product of the OTP version and design of a product of the mask ROM version. As a result, the conventional method is disadvantageous in that it takes very much time (e.g. one year or one and half years) to develop the microcontroller as the ultimate product.In addition, the product of the OTP version and the product of the mask ROM version are a pin-for-pin equivalent in a package state and can be substituted by each other. However, the product of the OTP version and the product of the mask ROM version are different from each other as semiconductor chips and cannot be compatible in characteristics in abundance. That is, when the product of the mask ROM version is replaced with the product of the OTP which is completed with evaluation, there are cases where a malfunction such as no operation occurs. 译文在短时间内制造集成在电路器件中含有掩膜ROM的单片机的方法此应用程序是基于在2006年7月31日从日本申请的专利号2006-207797中，提交了关于披露注册在这里的完整参考，拥有优先索赔利益的权利。
单片机英文文献外文翻译
单片机英文文献Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, even more than the numberof human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART· 6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DA TA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).单片机原理单片机是指一个集成在一块芯片上的完整计算机系统。
单片机 外文翻译 外文文献 英文文献 中英对照 基于C51兼容微(宝典)
附录A 英文原文Design of PWM Controller in a MCS-51 Compatible MCUAuthor . Yue-Li Hu Wei Wang Microelectronic Research Development Center CampusP.O.B.221 149 Yanchang Rd Shanghai 200072 China Introduction PWM technology is a kind of voltage regulation method by controlling the switchfrequency of DC power with fixed voltage to modify the two-end voltage of load. Thistechnology can be used for a variety of applications including motor control temperaturecontrol and pressure control and so on. In the motor control system shown as Fig. 1 throughadjusting the duty cycle of power switch the speed of motor can be controlled. As shown inFig. 2 under the control of PWM signal the average of voltage that controls the speed ofmotor changes with Duty-cycle D t1/T in this Figure thus the motor speed can beincreased when motor power turn on decreased when power turn off.Fig.1: The Relationship between Voltage of Armature and Fig.2 Architecture of PWM Module Therefore the motor speed can be controlled with regularly adjusting the time of turn-onand turn-off. There are three methods could achieve the adjustment of duty cycle: 1 Adjustfrequency with fixed pulse-width. 2 Adjust both frequency and pulse-width. 3 Adjustpulse-width with fixed frequency. Generally there are four methods to generate the PWM signals as the following: 1Generated by the device composed of separate logic components. This method is the originalmethod which now has been discarded. 2 Generated by software. This method need CPU tocontinuously operate instructions to control I/O pins for generating PWM output signals sothat CPU can not do anything other. Therefore the method also has been discarded gradually.3 Generated by ASIC. The ASIC makes a decrease of CPU burden and steady workgenerally has several functions such as over-current protection dead-time adjustment and soon. Then the method has been widely used in many kinds of occasion now. 4 Generated byPWM function module of MCU. Through embedding PWM function module in MCU andinitializing the function PWM pins of MCU can also automatically generate PWM outsignals without CPU controlling only when need to change duty-cycle. It is the method thatwill be implemented in this paper. In this paper we propose a PWM module embedded in a 8051 microcontroller. ThePWM module can support PWM pulse signals by initializing the control register andduty-cycle register with three methods just mentioned above to adjust the duty cycle andseveral operation modes to add flexibility for user. The following section explains the architecture of the PWM module and the architecturesof basic functional blocks. Section3 describes two operation modes. Experimental andsimulation results verifying proper system operation are also shown in that section.Depending on mode of operation the PWM module creates one or more pulse-widthmodulated signals whose duty ratios can be independently adjusted. Implementation of PWM module in MCU Overview of the PWM module A block diagram of PWM module is shown in Fig.3. It is clearly from the diagram thatthe whole module is composed of two sections: PWM signal generator and dead-timegenerator with channel select logic. The PWM function can be started by the user throughimplementing some instructions for initializing the PWM module. In particular the followingpower and motion control applications are supported: DC Motor Uninterruptablel Power Supply UPSThe PWM module also has the following features: Two PWM signal outputs with complementary or independent operation Hardware dead-time generators for complementary mode Duty cycle updates are configurable to be immediated or synchronized to the PWM Fig.3 Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2-output PWM generator shownin Fig.4 is based on a 16-bitresolution counter which creates a pulse-width modulated signal. The system is synthesizedby a system clock signal whose frequency can be divided by 4 times or 12 times throughsetting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON asshown in Fig.4. To PWM0 generator the clock to 16-bit counter will be pre-divided by 4times by default when T3M is set to zero. And the clock will be divided by 12 times whenT3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained indetail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCONChannel-select logic The follow Fig. 5 shows the channel-select logic which is useful in ComplementaryMode. From this diagram it is clear to know that signal CP and CPWM control the source ofPWMH and PWML. And the details about the two control signals will be discussed in thesection 3 and the architecture of dead-time generator will also be discussed in section 5 forthe continuity of Complementary Mode. Fig. 5 Diagram of Channel-select LogicOperation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. Bysetting the corresponding bit CPWM in register PWMCON shown in Fig.6 user can select oneof the two operation modes. When CPWM is set to zero PWM module will work inIndependent Mode whereas PWM module will work in Complimentary Mode. In thefollowing of this section the two operation mode will be explained respectively in detail andthe simulation results of the PWM module from the Synoposys VCS EDA platform whichverify the design will also be shown.Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown inFigure 6. A particular PWM output is in the Independent Output mode when thecorresponding CP bit in the PWMCON register is set to zero.In this case two-channel PWMoutputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0generator and the signal on pin PWM1/PWML is from PWM0 generator. The separate case isachieved by the channel-select logic shown in Fig. 6. The PWM I/O pins are set toindependent mode by default upon advice reset. The dead-time generator is disabled in theIndependent mode. The simulation result is shown in Figure 6 as the following Fig.6 Tr4 andtr3 are run bits to PWM0 and PWM1 respectively. Actually from this diagram Pin P15/P14 of MCU is used for PWMH/ PWML or normal I/O alternatively. Fig6 the Waveform of PWM Outputs in Independent ModeComplementary PWM Output Mode The Complementary Output mode is used to drive inverter loads similar to the oneshown in Figure 7. This inverter topology is typical for DC applications. In ComplementaryOutput Mode the pair of PWM outputs cannot be active simultaneously. The PWM channeland output pin pair are internally configured through channel-select logic as shown in Figure7.A dead-time may be optionally inserted during device switching where both outputs areinactive for a short period. Fig 7 : Typical Load for Complementary PWM Outputs The Complementary mode is selected for PWM I/O pin pair by setting the appropriateCPWM bit in PWMCON. In this case PSEL is in effect. PWMH and PWML will come fromPWM0 generator when PSEL is set to zero when the signals from PWM1 generator is uselesswhereas PWMH and PWML will come from PWM1 generator when PSEL is set to 1 whenthe signals from PWM0 generator is useless. In the process of producing the PWM outputs inComplementary Mode the dead-time will be inserted to be discussed in the following section.Dead-time Control Dead-time generation is automatically enabled when PWM I/O pin pair is operating inthe Complementary Output mode. Because the power output devices cannotswitchinstantaneously some amount of time must be provided between the turn-off event of onePWM output in a complementary pair and the turn-on event of the other transistor. The2-output PWM module has one programmable dead-time with 8-bitregister.Thecomplementary output pair for the PWM module has an 8-bit down counter that is used toproduce the dead-time insertion. As shown in Figure 8 the dead time unit has a rising andfalling edge detector connected to PWM signal from one of PWM generator. The dead timesis loaded into the timer on the detected PWM edge event. Depending on whether the edge isrising or falling one of the transitions on the complementary outputs is delayed until the timercounts down to zero. A timing diagram indicating the dead time insertion for the pair of PWMoutputs is shown in Figure 8a. Fig 8a Dead-time Unit Block Diagram Fig. 8b the Waveforms of PWM Outputs in Complementary ModeConclusions In this paper we have designed PWM module based on an 8-bit MCU compatible with8051 family. The design can generate 2-channel programmable periodic PWM signals withtwo operation mode Independent Mode and Complementary Mode in which dead-time willbe inserted. The simulation results on the EDA platform have proven its correctness andusefulness. 附录B 汉语翻译基于C51 兼容微处理器单片机的PWM 控制器设计Yue-Li Hu Wei Wa 单片机研究与开发中心Campus P.O.B.221 149Yanchang Rd Shanghai 200072 China 导言PWM 技术，是一种电压调节方法，通过控制具有固定电压的直流电源的开关频率来调整两端负荷电压。
单片机的外文文献及中文翻译
单片机的外文文献及中文翻译一、外文文献Title: The Application and Development of SingleChip Microcontrollers in Modern ElectronicsSinglechip microcontrollers have become an indispensable part of modern electronic systems They are small, yet powerful integrated circuits that combine a microprocessor core, memory, and input/output peripherals on a single chip These devices offer significant advantages in terms of cost, size, and power consumption, making them ideal for a wide range of applicationsThe history of singlechip microcontrollers can be traced back to the 1970s when the first microcontrollers were developed Since then, they have undergone significant advancements in technology and performance Today, singlechip microcontrollers are available in a wide variety of architectures and capabilities, ranging from simple 8-bit devices to complex 32-bit and 64-bit systemsOne of the key features of singlechip microcontrollers is their programmability They can be programmed using various languages such as C, Assembly, and Python This flexibility allows developers to customize the functionality of the microcontroller to meet the specific requirements of their applications For example, in embedded systems for automotive, industrial control, and consumer electronics, singlechip microcontrollers can be programmed to control sensors, actuators, and communication interfacesAnother important aspect of singlechip microcontrollers is their low power consumption This is crucial in batterypowered devices and portable electronics where energy efficiency is of paramount importance Modern singlechip microcontrollers incorporate advanced power management techniques to minimize power consumption while maintaining optimal performanceIn addition to their use in traditional electronics, singlechip microcontrollers are also playing a significant role in the emerging fields of the Internet of Things （IoT) and wearable technology In IoT applications, they can be used to collect and process data from various sensors and communicate it wirelessly to a central server Wearable devices such as smartwatches and fitness trackers rely on singlechip microcontrollers to monitor vital signs and perform other functionsHowever, the design and development of systems using singlechip microcontrollers also present certain challenges Issues such as realtime performance, memory management, and software reliability need to be carefully addressed to ensure the successful implementation of the applications Moreover, the rapid evolution of technology requires developers to constantly update their knowledge and skills to keep up with the latest advancements in singlechip microcontroller technologyIn conclusion, singlechip microcontrollers have revolutionized the field of electronics and continue to play a vital role in driving technological innovation Their versatility, low cost, and small form factor make them an attractive choice for a wide range of applications, and their importance is expected to grow further in the years to come二、中文翻译标题：单片机在现代电子领域的应用与发展单片机已成为现代电子系统中不可或缺的一部分。
at89c52单片机中英文资料对照外文翻译文献综述
D.htmlat89c52单片机中英文资料对照外文翻译文献综述at89c52单片机简介中英文资料对照外文翻译文献综述AT89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。
Storage RAM immediately﹑memoy readROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。
Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
单片机英文参考文献
单片机英文参考文献篇一：5-单片机+外文文献+英文文献+外文翻译中英对照AT89C51的介绍（原文出处：http：///resource/）描述AT89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。
和128字节的存取数据存储器（RAM），这种器件采用ATMEL公司的高密度、不容易丢失存储技术生产，并且能够与MCS-51系列的单片机兼容。
片内含有8位中央处理器和闪烁存储单元，有较强的功能的AT89C51单片机能够被应用到控制领域中。
功能特性AT89C51提供以下的功能标准：4K字节闪烁存储器，128字节随机存取数据存储器，32个I/O口，2个16位定时/计数器，1个5向量两级中断结构，1个串行通信口，片内震荡器和时钟电路。
另外，AT89C51还可以进行0HZ的静态逻辑操作，并支持两种软件的节电模式。
闲散方式停止中央处理器的工作，能够允许随机存取数据存储器、定时/计数器、串行通信口及中断系统继续工作。
掉电方式保存随机存取数据存储器中的内容，但震荡器停止工作并禁止其它所有部件的工作直到下一个复位。
引脚描述VCC：电源电压 GND：地 P0口：P0口是一组8位漏极开路双向I/O口，即地址/数据总线复用口。
作为输出口时，每一个管脚都能够驱动8个TTL电路。
当“1”被写入P0口时，每个管脚都能够作为高阻抗输入端。
P0口还能够在访问外部数据存储器或程序存储器时，转换地址和数据总线复用，并在这时激活内部的上拉电阻。
P0口在闪烁编程时，P0口接收指令，在程序校验时，输出指令，需要接电阻。
沈阳航空工业学院电子工程系毕业设计（外文翻译）P1口：P1口一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动4个TTL电路。
对端口写“1”，通过内部的电阻把端口拉到高电平，此时可作为输入口。
因为内部有电阻，某个引脚被外部信号拉低时输出一个电流。
闪烁编程时和程序校验时，P1口接收低8位地址。
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单片机基础外文翻译参考文献(文档含中英文对照即英文原文和中文翻译)原文:Fundamentals of Single-chip MicrocomputerDr. Dobbs MacintoshJournalAbstractT h e s i n gl e-chi p m i c r o com pu t er i s t h e cul m i na t i on of bo t h t h e d e v el opm e nt o f t h e di gi t al c om p ut e r a nd t h e i nt e gra t e d c i r c ui t a rgu a b l y t h e t ow m o s t s i gn i fi c ant i nv en t i on s of t h e 20t h ce n t u r y .T h es e t o w t yp e s o f a rc hi t e c t u r e a r e fo un d i n s i n gl e-c hi pm i c r o com pu t e r.S om e e m p l o y t h e s pl i t p ro gr a m/d at a m em o r y o f t h e H a r v a rd a r ch i t e ct u r e, s ho wn i n F i g.3-5A-1, ot h er s f o l l o w t h e p hi l o so ph y,w i d e l y a d a p t ed f o r ge n e r al-pu rp os e com p ut e rs an d m i c r op r oc e s s o rs,of m ak i n g n o l o gi c al di s t i nc t i on be t w ee n p ro gr a m a n d d at a m em o r y a s i n t h e P r i n c et on ar c hi t e ct u r e.In ge n e r a l t er m s a si n gl e-c hi p m i cro c om put e r i s c ha r ac t e ri z ed b y t h e i n co r po r at i o n o f al l t h e u ni t s o f a c om put e r i n t o a s i n gl e d e vi c e.Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory– Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-level Program Memory Lock• 128 x 8-bit Internal RAM• 32 Programmable I/O Lines• Two 16-bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low-power Idle and Power-down ModesDescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. Theon-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded controlapplications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-orderaddress bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programmingand verification.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When theAT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes programexecution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator ConnectionsFigure 2. External Clock Drive ConfigurationPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms.Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by theRDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operatio n must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erasedby using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.译文:单片机基础摘要：单片机是电脑和集成电路发展的巅峰，有据可查的是它们也是20世纪最意义的两大发明。