ADS设计D触发器

Sheet 1 of 7
D-Type flip-flop (Toggle switch) The D-type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure 1 shows how the flip-flop (latch) can be made using 2-input logic circuits and Figure 2 shows the input and output waveforms The enable pin needs to be high for data to be fed to the outputs Q and Q bar. The output will only change on the falling edge or trailing edge of the applied clk input.
D
NAND
NAND
Q
Enable
NAND
Q
NAND
NOT
Latch
Figure 1 Simple D-type Flip-flop circuit The D type flip-flop has only one input (D for Data) apart from the clock. The INDETERMINATE state is avoided with this flip-flop. When the clock goes high, D (a 0 or a 1) is transferred to Q. When the clock goes low, Q remains unchanged. Q stores the data until the clock goes high again, when new data may be available.
Figure 2 Output waveforms of the D-type flip-flop. In this circuit the Q output changes state on the leading edge of the clock.

Sheet 2 of 7
At A, clock and data are high. Q goes high and stays high until B. At B, clock is high and data is low. Q goes low and stays low until C. At C, clock and data are both high. Q goes high and stays high until E. Q does not change during clock pulse D, because clock and data are still both high. At E, data is low, so Q goes low. At F, data is high so Q goes high. As with the other flip-flop circuits the operation can be improved to eliminate indeterminate states by adding a master latch. The circuit of the master-slave D-type flip-flop is shown in the ADS simulation setup shown in Figure 3. The inverter connected between the two CLK inputs ensures that the two sections will be enabled during opposite half-cycles of the clock signal. Each logic gate is made up of CMOS FETS (based on the 0.8um process) as described in the other tutorials on individual gates.

Sheet 3 of 7
DT
D
VtPulseDT SRC4 Vlow=0 V Vhigh=5 V Delay=25 usec Width=50 usec Period=100 usec Rout=1 Ohm
DT
Clk
VtPulseDT SRC2 Vlow=0 V Vhigh=5 V Delay=0 nsec Width=10 usec Period=20 usec Rout=1 Ohm
V
V_DC SRC1 Vdc=5.0 V
V
D
Vcc A
NAND
V
V
OUT
A
Vcc
NAND
V
Vcc
OUT
A
Vcc
NAND
A
NAND
B
buffered
OUT
B
buffered
OUT
B
Q
buffered
Port D Num=1
B
buffered
NAND_buffered X8
NAND_buffered X7
V
A Vcc
NAND
A
NAND_buffered X2
NAND_buffered X4
Port Q Num=3
V
Vcc A
NAND
V
Vcc
NAND
V
Vcc A
NAND
OUT
OUT
OUT
B
B
Q_bar
buffered
OUT
B
buffered
buffered
Clk
B
buffered
Port Clk Num=1
NAND_buffered X9
Vcc IN
NAND_buffered X6
NAND_buffered X3
NAND_buffered X5
Port Q_bar Num=4
V
OUT
TRANSIENT
Tran Tran1 StopTime=150 usec MaxTimeStep=250
NOT
NOT X10
Figure 3 ADS simulation setup of the master-slave D-type flip-flop circuit. In this simaulation there are two square wave generators, the clock at 50KHz and the data (with a 25us delay) running at 10KHz. The simulation is a time-domain transient.