ADS设计D触发器

Sheet 1 of 7D-Type flip-flop (Toggle switch) The D-type flip-flops are used in prescalar/divider circuits and frequency phase detectors. Figure 1 shows how the flip-flop (latch) can be made using 2-input logic circuits and Figure 2 shows the input and output waveforms The enable pin needs to be high for data to be fed to the outputs Q and Q bar. The output will only change on the falling edge or trailing edge of the applied clk input.DNANDNANDQEnableNANDQNANDNOTLatchFigure 1 Simple D-type Flip-flop circuit The D type flip-flop has only one input (D for Data) apart from the clock. The INDETERMINATE state is avoided with this flip-flop. When the clock goes high, D (a 0 or a 1) is transferred to Q. When the clock goes low, Q remains unchanged. Q stores the data until the clock goes high again, when new data may be available.Figure 2 Output waveforms of the D-type flip-flop. In this circuit the Q output changes state on the leading edge of the clock.Sheet 2 of 7At A, clock and data are high. Q goes high and stays high until B. At B, clock is high and data is low. Q goes low and stays low until C. At C, clock and data are both high. Q goes high and stays high until E. Q does not change during clock pulse D, because clock and data are still both high. At E, data is low, so Q goes low. At F, data is high so Q goes high. As with the other flip-flop circuits the operation can be improved to eliminate indeterminate states by adding a master latch. The circuit of the master-slave D-type flip-flop is shown in the ADS simulation setup shown in Figure 3. The inverter connected between the two CLK inputs ensures that the two sections will be enabled during opposite half-cycles of the clock signal. Each logic gate is made up of CMOS FETS (based on the 0.8um process) as described in the other tutorials on individual gates.Sheet 3 of 7DTDVtPulseDT SRC4 Vlow=0 V Vhigh=5 V Delay=25 usec Width=50 usec Period=100 usec Rout=1 OhmDTClkVtPulseDT SRC2 Vlow=0 V Vhigh=5 V Delay=0 nsec Width=10 usec Period=20 usec Rout=1 OhmVV_DC SRC1 Vdc=5.0 VVDVcc ANANDVVOUTAVccNANDVVccOUTAVccNANDANANDBbufferedOUTBbufferedOUTBQbufferedPort D Num=1BbufferedNAND_buffered X8NAND_buffered X7VA VccNANDANAND_buffered X2NAND_buffered X4Port Q Num=3VVcc ANANDVVccNANDVVcc ANANDOUTOUTOUTBBQ_barbufferedOUTBbufferedbufferedClkBbufferedPort Clk Num=1NAND_buffered X9Vcc INNAND_buffered X6NAND_buffered X3NAND_buffered X5Port Q_bar Num=4VOUTTRANSIENTTran Tran1 StopTime=150 usec MaxTimeStep=250NOTNOT X10Figure 3 ADS simulation setup of the master-slave D-type flip-flop circuit. In this simaulation there are two square wave generators, the clock at 50KHz and the data (with a 25us delay) running at 10KHz. The simulation is a time-domain transient.Sheet 4 of 7The resulting simulation of the circuit shown in Figure 3 is shown in Figure 4.D-type Flip-flop transitions occur on the falling of the Clk input6 5 4Clk ,V3 2 1 0 -1020406080100120140160time, usec6 5 4D, V3 2 1 0 -1020406080100120140160time, usec6 5 4Q, V3 2 1 0 -1020406080100120140160time, usecFigure 4 Simulation of the Master-slave D-type flip-flop. Note that the transitions occur on the falling edge of the applied clock signal+1/2 half clock cycle due to the slave action.Sheet 5 of 7The D-type flip-flop can be configured as a T-type or Toggle flip-flop. With this configuration the Q_bar output is connected to the D input and the signal/clock is connected to the clk input. The output of this flip-flop will have a frequency half that of the input. The ADS simulation of Figure 6 is shown below (Figure 5)D-type Flip-flop transitions occur on the falling of the Clk input. This D-type is configured as a T-type toggle flip-flop6 5 4Clk ,V3 2 1 0 -1 0 6 5 4 20 40 60 80 100 120 140 160time, usecQ, V3 2 1 0 -1 0 20 40 60 80 100 120 140 160time, usecFigure 5 Simulation results of the D-type flip-flop configured as a T-type (Toggle) flipflop by connecting the D input to the Q_bar output. Such circuits are common in frequency prescalar circuits.Sheet 6 of 7VVcc A NAND BbufferedV VVcc OUT A NAND BbufferedVcc A NAND B OUTbufferedVVcc OUT A NAND BbufferedOUTQ Port Q Num=3NAND_buffered X8NAND_buffered X7 VVcc A NAND OUT B ANAND_buffered X2NAND_buffered X4 VVcc A NAND OUTVVcc A NAND OUTVVcc NANDbufferedOUTBbufferedBbufferedClkBbufferedPort Clk Num=1 V V_DC SRC1 Vdc=5.0 VNAND_buffered X9Vcc INNAND_buffered X6 VNAND_buffered X3NAND_buffered X5TRANSIENTOUT NOTNOT X10Tran Tran1 StopTime=150 usec MaxTimeStep=250 nsecDTVtPulseDT SRC2 Vlow=0 V Vhigh=5 V Delay=0 nsec Width=10 usec Period=20 usec Rout=1 OhmClkFigure 6 Transient ADS simulation of a D-type Flip-Flop configured as a T-type flip-flop by connecting the D input to the Q_bar output.Sheet 7 of 7RF Application Phase detectors are part of a Phase Locked Loop (PLL) and can be either analogue eg mixer or digital eg D-type flip-flop. When a mixer is used the output consists of the sum and difference frequencies. In an analogue mixer a number of different frequencies are generated within the mixer namely the sum of the frequencies and the difference frequency (otherwise known as the beatnote) when both input frequencies are the same is the phase difference is zero and the beatnote is DC. Most PLL circuits now use digital phase detectors formed from two D-type flip-flops as shown in Figure 7.VhighD D type Flip-Flop Q1 Q1F1ClkClear VhighNANDD D type Flip-Flop Q2 Q2F2ClkFigure 7 D-type flip-flop application - Phase frequency phase detector。