(1) Hierarchical Design Priciple分层设计原则(1)

specific problems Methods or algorithms can be implemented with Hardware processor + suitable software programs (flexibility) Pentium IV + suitable software programs (highlevel language) TI-DSP + suitable software programs MCU(8051) + suitable software programs (lowlevel language) Dedicated hardware circuits (faster) Old_PCBs (TTL SSI, MSI chips and wires) New_PCBs(some devices, application specific integrated circuit-ASIC, wires)
System Design Hardware:
CPU, RAM, I/O…
Component Design
always @(posedge clk) begin if (sel1) begin out=in1; else out=in2; end end
Software:
C,C++
Synthesis
1. Area (less silicon, less cost, high yield)
2. Speed (design constraint, better
Done by designers + tools
timing performance)
3. Power dissipation (cooling, battery)
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Circuits
Transistor Gate ( 1 gate ~= 2~14 transistors)
A combination of interacting transistors
Circuit
A combination of interacting gates designed to accomplish a specific logical function
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Evolution of Fabrication
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IC Industry
邏輯設計
光罩設計 晶粒測試及切割
封 裝
成品測試
設計
光罩
製造
封裝
測試
長晶
晶圓切割
導線架 化學品
晶圓
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IC Design & IC Fabrication IC Design IC Fabrication
HDL (Hardware Description Language)
always @(IN) begin OUT = (IN[0] | IN[1]) & (IN[2] | IN[3]); end
Mixed HDL & Schematic …
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Hardware Description Language (HDL)
4. Testability (minimize the time spent to test a single chip) 5. Design time (CAD tools)
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Top-Down Design Methodology
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Design Entry for VLSI System
memory ASIC ASIC
CPU I/O
PCI USB UART IEEE 1394
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Digital System
input
0 1 1 0
digital circuit digital circuit
digital circuit
digital circuit === IC (integrated circuit) semiconductor
1. Choice of many design teams
2. Most of usages are familiar with C-like syntax/semantics
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Hierarchy Design (1/2)
Top-Down Design Flow

Defining the target of design (top-module) Subdividing top-module into sub-modules Subdividing sub-module into basic elements
HDLs can be used for both the cell-based
synthesis and FPGA/CPLD implementation
Only Verilog is introduced here
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Why Verilog ?
Verilog History 1. Verilog was written by gateway design automation in the early 1980 2. Cadence acquired gateway in 1990 3. Cadence released Verilog to the pubic domain in 1991 4. In 1995, the language was ratified as IEEE standard 1364 Why Verilog ?
A 0 1
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Y 1 0
A 0 0 1 1
B 0 1 0 1
Y 1 1 1 0
A 0 0 1 1
B 0 1 0 1
Y 1 0 0 0
IC Design (with CMOS)
CMOS Inverter
in out
done by chip designer
One npn transistor and
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Constructing Gates (semiconductor)
It turns out that, because the way a transistor
works, the easiest gates to create are the NOT, NAND, and NOR gates
Choose the design entry method: Schematic Gate level design Intuitive & easy to debug Descriptive & portable Easy to modify
IN[0] IN[1] IN[2] IN[3] OUT
Full-Adder
Design
Sub Module
Sub Module
Sub Module
Sub Module
Basic Basic Basic Basic Basic Basic Basic Basic Element Element Element Element Element Element Element Element
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Hardware Implementation (2/2)

Some hardware circuits + software programs (to solve more complex problems) System on a board (memory, processor, ASIC, I/O, other devices) System on a Chip (SoC) – Current and future work – RISC-ARM
Hierarchical Design Priciple
Dr. Shih-Lun Chen Department of Electronic Engineering Chung Yuan Christian University
Hardware Implementation (1/2)
Methods and algorithms are used to solve some
Testing
Marketing
Fabrication
Placement & Routing
Layout
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Intel CPU
30mm wafer and Pentium 4TM
Photo courtesy of Intel
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Optimization issues for VLSI Design Five optimization issues:
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Hierarchy Design (2/2)
Bottom-Up Design Flow

Implementing basic elements Combining basic elements into sub-module Combining sub-modules into the target of design (top-module)
Design
Sub Module
Sub Module
Sub Module
Sub Module
Basic Basic Basic Basic Basic Basic Basic Basic Element Element Element Element Element Element Element Element