candence使用手册仿真分册实用手册

合集下载

cadence仿真工具介绍

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(11)Chech and Save (12)Save (5)放大、缩小放大、放大 (6)Stretch拉动（保持连接）拉动（保持连接）拉动 (7)copy (8)删除删除
从分类菜单中可以看到命令的快捷键和许多其它命令
(9)undo (10)属性、参数修改属性、属性
出现CIW窗口出现窗口
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• 2. Library 的创建
CIW窗口 Tools New Library 窗口
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CIW窗口 Tools New Library 窗口
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• Cell view 的创建
在terminal中敲命令中敲命令reboot，回车中敲命令，
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• LINUX操作系统常用命令简介操作系统常用命令简介
1.创建目录： >mkdir dirname 创建目录：创建目录 2.改变工作目录：>cd dirname (到下级目录改变工作目录：到下级目录) 改变工作目录到下级目录 > cd .. (到上级目录到上级目录) 到上级目录 3.列出当前工作目录：>pwd 列出当前工作目录：列出当前工作目录 4.列文件清单：>ls dirA 列文件清单：列文件清单 (可以有多个目录名，没有目录名时为当前目录。可以可以有多个目录名，可以有多个目录名没有目录名时为当前目录。加命令选项 -l or -a or -la) 5.复制复制(copy)：>cp fileA fileB (文件复制文件复制) 复制：文件复制 >cp fileA fileB dirA (复制文件到目录复制文件到目录) 复制文件到目录 >cp -r dirA dirB (复制目录复制目录) 复制目录

cadence安装、原理库建库和Concept_HDL使用手册

cadence安装、原理库建库和Concept_HDL使用手册Cadence SPB 使用手册本手册仅供交流，甘振华一、Cadence SPB 安装方法：先在安装盘路径设置cadence_license文件夹，将源文件的crack 文件夹中文件拷贝至cadence_license文件夹里。

设置环境变量：LM_LICENSE_FILE = ******\ , 指向此SPB 的LIC路径。

打开安装源文件disk1，运行，接受协议，直接安装products。

License Manager 信息为空，直接Next。

填写用户信息。

Control file为空，直接Next。

设置安装路径。

Products 全选。

设置工作文件夹路径。

IntelliCAD 可选件，可任选是否安装。

Footprint Viewer 设为默认。

安装文件夹设为默认，点击Next开始安装程序。

安装过程中………………………..，两个extension选择默认“否”确定：无警告。

确定：安装库提示信息。

选择不马上重启计算机，并确定需重启信息，以便继续安装Cadence库文件。

二、安装concept HDL原理库打开源文件夹的disk4，运行文件，安装concept HDL 库文件。

库Component的选择，PSpice可任选。

点击Next进行安装库文件。

安装过程中……………………………….安装结束，点击finish。

安装信息检查与修正检查环境变量LM_LICENSE_FILE = ******\是否被更改若选择安装了PSpice库，则需修正元件库。

打开安装路径下（D:\Cadence\\share\library）的，使用写字板打开编辑：将DEFINE spiceelem ./spiceelem修改为：DEFINE spice_elem ./spice_elem末行留一空行并存储。

重启计算机，安装结束。

三、Concept HDL原理库的建立1、我们先打开Project Management,之后出现Cadence Product Choices这个窗口,选择Allegro PCB Librarian 610(PCB Librarian Expert).点击OK,创建一个新的Library Project.Cadence 原理库的三级结构：按完成,他会提示New project creation successful. 这样一个新的Library Project就完成了.他会进入Allegro PCB Librarian界面.2、我们以74HC374为例介绍如何创建原理用到的元件.在Allegro PCB Librarian界面,我们可以由Part Developer或Library Explorer进入开始创建元件.现在我们从Library Explorer进入.进入Part Developer 界面。

cadence版图仿真教程

Tutorial: Simulating HSpice with the Analog Design Environment1.Make directory called something like cadence.$mkdir cadence2.Change to this directory.$cd cadence3.Start the Cadence Design Framework by typing “icfb &” at the command prompt.$icfb&The first window that appears is called the CIW (Command Interpreter Window).Figure 1 – CIW WindowAnother window that appears is the Library Manager. This window allows you to browse the available libraries and create your own.Figure 2 – Library Manager WindowIn the Library Manager, create a new library called EEE534. Select File->New->Library. This will open a new dialog window, in which you need to enter the name of your library, library path, and "Attach to existing tech library." Fill out the form as shown below, then select OK.Figure 3 – Create Library FormYou should see the library "EEE534" appear in the Library Manager.Figure 4 – Library Manager display newly created libraryNext, select the library you just created in the Library Manager and select File->New->Cell View.... We will create a schematic view of an inverter cell. Simply type in "INV" under cell-name and "schematic" under view. Click OK or hit the Enter key. Note: that the "Tool" is automatically set to "Composer-Schematic", the schematic editor.Figure 5 – Create New File FormAlternatively, you could select the "Composer-Schematic" tool, instead of typing out the view name. This will automatically set the view name to "schematic".After you hit "OK", the blank Composer screen will appear.Figure 6 – Virtuoso Schematic EditorTo generate a schematic, you will need to go through the following steps:•From the Schematic Window, choose Add->instance. The Component Browser, will then pop up.•In the Library field, select NCSU_Analog_Parts. We will place the pmos, nmos, vdd, gnd, vdc, vpulse andcap instances in the Schematic Window from the NCSU_Analog_Parts library asinstructed below.Note: pay special attention to the parameters specified in vdc, vpulse, and cap. These parameters are very important in simulation.Place pmos instance•In Component Browser, select P_Transistors and then pmos.•Place it in the Schematic WindowFigure 7 – Add pmos InstancePlace nmos instance•In Component Browser, select N_Transistors and then nmos.•Place it in the Schematic Window.Figure 8 – Add nmos InstancePlace gnd instance•In Component Browser, select Supply_Nets and then gnd.•Place it in the Schematic Window.Figure 9 – Add gnd Instance Place vdd instance•In Component Browser, select Supply_Nets and then vdd •Place it in the Schematic Window.Figure 10 – Add vdd InstancePlace IN pin•From the Schematic Window menu, select Add -> Pin...•In the Pin Name field , enter IN•In the Direction field, select input•Place it in the Schematic WindowFigure 11 – Add Input PinPlace OUT pin•From the Schematic Window menu, select Add -> Pin...•In the Pin Name field , enter OUT•In the Direction field, select output•Place it in the Schematic WindowFigure 12 – Add Output PinPlace vdc instance•In the Component Browser, select Voltage Sources and then vdc •In the DC voltage field, enter 5 V•Place it in the Schematic WindowFigure 13 – Add vdc SourcePlace vpulse instance•In the Component Browser, select Voltage_Sources and then vpulse •Enter the following values in the form:Figure 14 Edit Object vpulse SourcePlace cap instance•In Component Browser, select R_L_C and then cap•In the Capacitance field, enter OutCap F. (This Design Variable will be used in Artist.) •Place it in the Schematic WindowFigure 15 – Add cap InstancePlace wires•In the Schematic Window menu, select Add -> Wire (narrow)•Place wires to connect all the instances•Select Design -> Check and Save.Look at the CIW. You should see a message that says:Extracting “INV schematic”Schematic check completed with no errors.“EEE534 INV schematic” saved.If you do have some errors or warnings, the CIW will give a short explanation of what those errors are. Errors will also be marked on the schematic with a yellow or white box. Errors must be fixed for your circuit to simulate properly. When you find a warning it is up to you to decide if you shouldfix it or not. The most common warnings occur when there is a floating node or when there are wires that cross but are not connected. Just be sure that you know what effect each of these warning will have on your circuit when you simulate.Your schematic should look like the one shown below.Figure 16 – Completed SchematicIf you would like to learn more about the schematic editor, you can work through chapters 1-5 of the Composer Tutorial that comes with the Cadence documentation. Start the documentation browser by typingcdnshelp &at the command prompt. If you find that you cannot view the figures correctly in the web browser, you can click the View/Print PDF link at the top of the page to launch a PDF viewer for the tutorial. This documentation browser offers many more links for you to learn about the Cadence Design Framework.Simulate the Schematic with HSPICE within Virtuoso Analog Design EnvironmentSet up the Simulation EnvironmentYou are now prepared to simulate your circuit.From the Schematic Window menu, select Tools -> Analog Environment. A window will pop-up. This window is the Analog Design Environment Window.Figure 17 - Analog Design Environment WindowChoose a SimulatorFrom the Analog Design Environment menu, select Setup -> Simulator/Directory/Host. Enter the fields as shown below. Choose hspiceS as your simulator. Your simulation will run in the specified Project Directory. You may choose any valid pathname and filename that you like.Figure 18 Choosing Simulator/Directory/Host FormChoose AnalysisWe will setup to do a Transient Analysis on the circuit that we just produced.From the Analog Design Environment menu, select Analyses -> Choose... Fill out the form with the following values:Figure 19 – Choosing AnalysesAdd a VariableFrom the Analog Design Environment menu, select Variables -> Edit. The Editing Design Variables form will appear. Fill out the form as shown below, and then click Add to send this Variable to the Table of Design Variables.(Recall that we entered the OutCap Design Variable in the Capacitor component while editing the schematic in the previous section.)Figure 20 – Editing Design Variables FormSetup OutputWhen using Transient Analysis, the transient voltage will be saved automatically. We can save the current through capacitor C0 in the schematic by doing the following:From the Analog Design Environment menu, select Outputs -> To be Saved -> Select On Schematic In the Schematic Window, click on the lower terminal (not the wire) of capacitor C0.After you click on the terminal, the Analog Design Environment Window should look like this:Figure 21 Analog Design Environment WindownRun SimulationFrom the Analog Design Environment menu, select Simulation -> Run, Look at the echoing information in the CIW window. If the simulation succeeds, the window will display “...successful.”Figure 22 – CIW after simulationIf the simulation is unsuccessful, then one of the error messages should provide a clue as to what went wrong. Remember that you can move elements around in your schematic by clicking and dragging them. You can delete them by selecting them and pressing the “delete” key. You modify the properties of the elements by selecting them and pressing the “q” key.If you would like to learn more about the Analog Design Environment, select Analog Design Environment->Cadence Analog Design Environment User Guide in the cdnshelp browser window.View WaveformsFrom the Analog Design Environment menu, select Results -> Direct Plot -> Transient Signal. The Waveform Window will then pop up. In the Schematic Window, click on the IN wire and then Click on the OUT wire, then press ESC on your keyboard.The two curves (IN and OUT) will then be displayed in this window:Figure 23 – Waveform ViewerPress the Strip Chart Mode icon (4th icon from right) on the Waveform WindowThe waveforms will then be displayed separately as shown below:Figure 24 – Waveform Viewer, Strip Chart ModeIf you would like to learn more about the Waveform Viewer, select Analog Design Environment->Waveform User Guide in the cdnshelp browser window.Use CalculatorIn Analog Design Environment Window, go to Tools -> Calculator. The Calculator Window will then pop up, as shown below:Figure 25 – CalculatorIn Calculator Window, go to Options -> uncheck RPN. We are going to use the calculator to plot both the current through the capacitor and the absolute value of the capacitor current.In the Calculator Window, click on the tran tab then click the it radio button. In the Schematic Window, click on the lower terminal of the capacitor. Returning to the Calculator Window, the text area at the top should like this:Figure 26 – Calculator after selecting lower capacitor terminalIn the Calculator Window, press the plot icon to plot this waveform in the Waveform Window. In the Calculator Window, select the New Subwindow. In the Calculator Window, press the clear button to erase the text area, select abs, press the “(“ symbol and press the it radio button. In the Schematic Window, click on the lower terminal of the capacitor. Returning to the Calculator Window, press the “)” symbol, the text area at the top should like this:Figure 27 - Calculator after selecting lower capacitor terminalIn the Calculator Window, press the plot button to plot this waveform in the Waveform Window. Your Waveform Window should now look like this:Figure 28 – Waveform Display with current through the capacitor and the absolute value of thecapacitor current。

教学课件Cadence电路仿真

输入工作目录名称
选择原理图编辑工具
原理图绘制软件界面
使用快捷键”i” ,添加元件
选择MOS管
连线
1.新建工作目录
2.绘制原理图 3.仿真条件设置 4.仿真结果输出与保存
பைடு நூலகம் 晶体管特性仿真
Tools->Analog Environment
仿真环境设置界面
变量编辑
分析类型选择
仿真条件设置
1.新建工作目录
2.绘制原理图 3.仿真条件设置 4.仿真结果输出与保存
执行仿真
Simulation->Netlist and Run
选择输出结果
输出特性曲线
1.File->Save as Image
2.输入目录: /mnt/hgfs/C/filename,并保存
3.在windows xp系统下的C盘可以看到所存的文件.
Cadence 电路仿真
1.新建工作目录
2.绘制原理图 3.仿真条件设置 4.仿真结果输出与保存
虚拟机与主机共享设置.
File->New->Library
建立工作目录lab1
选择smic18mmrf
1.新建工作目录
2.绘制原理图 3.仿真条件设置 4.仿真结果输出与保存
File->New->Cell view

教学EN_cadence+spectre+使用手册

CS/EE 5720/6720 – Analog IC Design Tutorial for Schematic Design and Analysis using Spectre Introduction to Cadence EDA:The Cadence toolset is a complete microchip EDA (Electronic Design Automation) system, which is intended to develop professional, full-scale, mixed-signal microchips. The modules included in the toolset are for schematic entry, design simulation, data analysis, physical layout, and final verification. The Cadence tools at our university are the same as those at most every professional mixed-signal microelectronics company in the United States. The strength of the Cadence tools is in its analog design/simulation/layout and mixed-signal verification and is often used in tandem with other tools for digital design/simulation/layout, where complete top-level verification is done in the Cadence tools.An important concept is that the Cadence tools only provide a framework for doing design. Without a foundry-provided design kit, no design can be done. The design rules used by Cadence set up in this class is based for AMI’s C5N process (0.5 micron 3 metal 2 poly process).So, how is Cadence set up?Broadly, there are three sets of files that need to be in place in order to use Cadence.1)The Cadence toolsThese are the design tools provided by the Cadence company. These tools are located in the /home/cadence directory. They are capable of VLSI integration, project management, circuit simulation, design rule verification, and many other things (most of which we won't use).2)The foundry-based design kitAs mentioned before, the Cadence tools have to be supported by a foundry-baseddesign kit. In this class, we use Cadence design kit developed by the North Carolina State University (NCSU CDK). NCSU CDK provides an environment that has been customized with several technology files and a fair amount of custom SKILL code. These files contain information useful for analog/full-custom digital CMOS IC design via the MOSIS IC fabrication service (). This information includes layer definitions (e.g. colors, patterns, etc.), parasitic capacitances, layout cells, SPICE simulation parameters, Diva rules for Design Rule Check (DRC), extraction, and Layout Versus Schematic (LVS) verification, with various GUI enhancements.For more information on the capability of the NCSU CDK, go to/CDKoverview.htmlThis design kit is located in the /home/cadence/ncsu/local directory. All the design parameters that are needed by the Cadence tools are located in various files in the sub-directories you will find here. The nominal spice parameters for n type transistors for AMI’s 0.5 micron process used in this class can be found in /home/cadence/ncsu/local/models/spectre/nom/ami06N.m.3)The set up files in your local cadence directoryThere are set up files that should be in your local Cadence directory (i.e. the directory from which you invoke Cadence) that sets up the required local environmental variables for Cadence to work on your computer terminal. They are as follows:.cdsinit, .cdsplotinit, .simrc (sets up the variables to be used by NCSU CDK).cdsenv (not essential, but sets your preferences which can be different from userto user)Also we need a .cshrc file to source the current version of cadence we are using in this class.Now, of the three sets of files, the first two sets containing the cadence tools and the NCSU CDK have been already set up by the Cadence Administrators for the class. In this tutorial, the process of setting up the required files in your local cadence directory is explained.Setting up Cadence2000Note: People who have already set up Cadence before still need to follow the steps below.Before you start using cadence you need to complete the following steps:1.First, before anything else, make a directory from which to run Cadence. This isimportant so that all of Cadence’s files end up in a consistent location. I recommend making an IC_CAD directory and then under that making a cadence directory:cdmkdir IC_CADmkdir IC_CAD/cadence2.You need to add the following lines in your .tcshrc file (or whatever shell setupfile you use…) Just open it up with emacs and add:set path = (/uusoc/facility/cad_common/local/bin $path)setenv ICDIR IC_CADsetenv CADENCEDIR $ICDIR/cadencesetenv LOCAL_CADSETUP /uusoc/facility/cad_common/local/class/5830/cadence Adding the first line will update your search path to include the path of the customized CAD tool startup scripts. The next lines set your working directory for cadence as ‘IC_CAD/cadence’. The fourth line sets up the path to a directory that contains class-specific settings. After you save this file you can log out and log in again, or you can source it from the command prompt in the following way.:~> source .tcshrcThe sourcing only needs to be done the first time. After that the .tcshrc file will be sourced automatically when you log in and start up a shell.Starting Cadence 2000 and Making a new Working Library Now that you have your own Cadence directory (called IC_CAD/cadence if you’ve followed the directions up to this point), you need to remember to connect to this directory before you start the Cadence tools. That way Cadence will see the init files that you’ve put in that directory, and find the circuits you’ve designed since all the design files will be stored in this directory. In order to organize your new circuits, you now need to create a new library using the Cadence library manager to hold your design files.1. Connect to your class cadence directory (cd ~/IC_CAD/cadence) and run the command ncsu-icfb (this stands for North Carolina State University and “ic f ront to b ack,” in case you’re curious). You should get a window (called the Command Information Window – CIW) as shown below:2. Library Manager will automatically be opened. If not, in the CIW, select Tools →Library Manager…. You should get the following window, with the following list of libraries:3. In order to build your own schematics, you’ll need to define your own library to keep your own circuits in. To create a new working library in the library manager, select File → New → Library. In the Create Library window that appears fill in the Name field as CSEE5720 (or whatever you’d like to call your library). Select ‘Attach to existing tech library’ for Technology Library. Select “UofU AMI 0.6u C5N” process and press OK.Path field is left blank.NOTE: This may take a few minutes to executeNow the working library has been created. All the project cells (components) that you generate should end up in this library. When you start up the Library Manager to begin working on your circuits, make sure you select your own library to work in. Creating a New CellWhen you create a new cell (component in the library), you actually create a view of the cell. For now we’ll be creating “schematic” views, but eventually you’ll have other different views of the same cell. For example, a “layout” view of the same cell will have the composite layout information in it. It’s a different file, but it should represent the same circuit. This will be discussed later in more details. For now, we’re creating a schematic view. To create a cell view, carry out the following steps:Creating the Schematic View of an RC filter1.Select File → New → Cell View… from the Library Manager menu or tothe CIW menu. The Create New File window appears. The Library Name field is CSEE5720. Fill in the Cell Name field as RC_filter. Choose Composer - Schematic from the Tool list and the view name is automatically filled as Schematic. The library path file is automatically set. Click OK.2. A blank window called Virtuoso Schematic Editing: CSEE5720 RC_filterSchematic appears.3.Adding InstancesAn instance (either a gate from the standard cell library, or a cell that you’ve designed earlier) can be placed in the schematic by selecting Add → Instance…or by pressing ‘i’, and the following Component Browser window appears:4.For this example, we need to add the following components: Capacitor of 1 µFand two resistors of 1kΩ ohm and 10kΩ respectively. To add a capacitor of 1 µF, select the NCSU_Analog_Parts Library and the R_L_C menu. Choose cap in the sub-menu that appears. This opens the Add Instance window:Now, enter the capacitance value of 1u F and hit Hide. Place the capacitor in the schematic window.Other instances can be added in the similar fashion as above. Resistors can be found in R_L_C→ res. Enter the required resistor value.To come out of the instance command mode, press Esc. (This is a good command to know about in general. Whenever you want to exit an editing mode that you’re in, use Esc. I sometimes just hit a bunch of Esc’s whenever I’m not doing something else just to make sure I’m not still in a strange mode from the last command. )5.Connecting Instances with WiresTo connect the different instances with wires we select Add → Wire (narrow) or press “w” to activate the wire command. Now go to the node of the instance and left-click on it to draw the wire and left-click on another node to make theconnection. If you need to end the wire at any point other than a node (i.e. to adda pin later on), double left-click at that point. To come out of the wire commandmode, press Esc.6.Adding PinsPins can be added by going to Add → Pin… or pressing “p”. For example, to put two input pins In& gnd, we can fill in the Pin Names field as In gnd (with a space) and the Direction list as input.Now go to the wire where you need to place the pin and left-click on it.Also, add the output pin ‘Out’ in a similar way.7.Other Command FunctionsSome common command modes and functions available under the Add and Edit menus in cadence are:Under Add Menu:Add → Wire (wide) or press “W” ---------- to add a busAdd → Wire name… or press “l” ---------- to name wiresAdd → Note → Note Text… or press “L” ------------ to add a noteUnder Edit Menu:Edit → Undo or press “u”Edit → Stretch or press “m”Edit → Copy or press “c”Edit → Move or press “M”Edit → Delete or press Delete KeyEdit → Rotate or press “r”Edit → Fit or press “f”There are some command modes and functions available under the Windowmenu also.ing all the commands given above the schematic of a RC_filter can beconstructed as shown below.9.Checking and Saving the DesignThe design can be checked and saved by selecting Design → Check and Save or by pressing “X”. For an error free schematic, you should get the followingmessage in the CIW,Extracting “RC_filter schematic”Schematic check completed with no errors.”CSEE5720 RC_filter schematic” saved.Note: The CIW should not show any warnings or errors when you check and save.10.After saving the design with no errors, select Window → Close.Creating a Symbol View of the RC_filterYou have now created a schematic view of your RC_filter. Now you need to create a symbol view if you want to use that circuit in a different schematic.1.In the Vvirtuoso schematic window of the schematic you have created above,select Design → Create Cell View → From Cell View…. A Cell View from Cell View window appears, press OK.2.In the Virtuoso Symbol Editing window that appears, make modifications tomake the symbol look as below. Replace [@partname] with the name RC_filter and move gnd pin to the bottom side of the cell. You may delete[@instanceName]. Save the symbol and exit using Window → Close.3.Now the RC_filter is ready to be used in other schematics.Analysis using SpectreTo simulate this circuit with an analog simulator, you need to tell the simulator what voltages you’ll be using for your signals. You’ll need to use voltage sources that drive the analog simulation right into the schematic and then simulate the schematic with the analog simulator. In this case, the test fixture is the separate schematic that has the circuit you want to test, and the voltage sources that power it up.Make a new schematic view under the library CSEE5720 and name it RC_filter_test. Choose Add → Instance or press “i” and choose the library - CSEE5720, Menu – uncategorized which will lead to sub-menu RC_filter. Place this in the new schematic editor.We intend to do a transient (time domain), ac (frequency domain) and a dc sweep simulation. Hence we need to add three different types of voltage sources as input to the filter (all stacked up in series as shown below). Of these, only one would be active during each type of simulation; the others would be shorted.1.The input voltage source for transient simulation will be vpulse (taken fromNCSU_Analog_parts library, menu: Voltage_Sources) with the following specifications: this source will generate pulses from 0V to 5V with the givenpulse width and period. Notice that we assign it a finite rise and fall time which means that the change from 0V to 5V (or back) isn’t instant, it takes some time.This is a better model for the analog behavior of the circuit than a pure square wave.Voltage 1 0 vVoltage 2 5 vDelay time 0u sRise time 2u sFall time 2u sPulse Width 5m s10msPeriod2.The input voltage source for AC simulation will be vsin (taken fromNCSU_Analog_parts library, menu: Voltage_Sources) with the AC magnitude set to 1 V.3.The input voltage source for DC simulation will be vdc (taken fromNCSU_Analog_parts library, menu: Voltage_Sources). No other specifications need to be entered, as we will be sweeping this voltage value.4.The ground connection to be selected is gnd (found at NCSU_Analog_partslibrary, menu: Supply_Nets). Note there are a many types of ground connections in the sub-menu. Make sure you only select gnd.5.Connect all the symbols with wires. Add the output pin Out as well as label theinput and output wires (Add → Wire Name or press ‘l’ and place the label on the wire)6.Check and save by selecting Design → Check and Save or by pressing “X”. Ifthere are no errors found, your schematic is ready for Spectre Simulation.Simulation Using Analog EnvironmentIn the Schematic Editor, select Tools → Analog Environment. In the Affirma Analog Circuit Design Environment Simulation Window that appears, there are many kinds of simulators and analysis methods. We have set the default to SpectreS simulation and also have set the corresponding model paths and scaling factor. All you need to do in this window is to select the type of analysis you need and then select the nodes at which you want to observe the waveforms. You are encouraged to play around with the various menus and figure out how they make can your analysis easy and interesting.For transient analysis:On selecting Analyses menu, select tran to perform transient analysis. Transient analysis means that you want to simulate the behavior of the circuit over time, as opposed to a dc operating condition in a steady state or a linearized ac frequency-domain analysis. The stimuli has a period of 10 ms, therefore choose a Stop Time of 20 ms (type 20m in the box) to get a simulation over two complete periods. Click OK.The nodes to be plotted directly after simulation can now be chosen by selecting Outputs → To Be Plotted → Select on Schematic.Select the wires to be plotted (in this case the In and Out voltages of the inverter), by clicking on them in the schematic window. When you click on a wire (the blue line), the voltage is chosen to be plotted, and the wire changes color. To plot currents, you will need to click on the corresponding terminal of an instance and there will be a colored circle around that terminal to indicate a current marker.Now choose Simulation → Run or hit the green traffic lights on the right hand side of the window. The simulation starts. Wait for the simulation to complete. A Waveform Window containing 2 curves on top of each other will be now displayed. To get a betterview of the simulated result, press the switch axis mode-button located on the left side of the waveform window.The following Waveform Window showing the input and output of the inverter is now displayed:Take a moment to explore the features available in the Waveform Window. Use the zoom option (by typing z), and magnify an edge. Measure the time between two points using the A and B markers.For DC sweep of the input:You may first want to delete or disable your previous analysis. This can be done by selecting the analysis that you want to disable/delete and then looking for options under Analyses. You may also disable/delete the IN waveform from being plotted for the ac and dc analyses.Now, choose dc under the Analyses menu. Select ‘Component Parameter’ as the sweep variable. Click on the ‘Select Component’ button and the RC_filter schematic is opened in order to select the sweep variable (You may have to click it twice before the schematic shows up. If you are unable to see the circuit in the schematic editor then select the schematic window and press ‘f’). Select the vdc voltage source. This activates another window as shown below. Select the “DC voltage” option.Now, again select the Analyses menu. It should look like this:Enter the sweep range (0 V to 5 V) and sweep type (Linear with step size 0.1 V) as shown above. Run the simulation.Your output should look something like this:For AC analysis and Bode plots:1.You may want to disable the other analyses first and select only OUTwaveform to be plotted.2.Analyses > Choose > ac > Frequency3.Start-Stop > Start: 1 Stop: 1M4.Sweep Type > Logarithmic 10 points per decade5.Simulation > Run6.You will get a plot of Out vs frequency which looks like the figure below.Note: This is not a conventional Bode plot. We must take 20·log10(out) to get the proper plot.7.In the Waveform Window, select Curves > Edit (select /Out and delete it).8.Now in the Analog Artist Window, select Tools > Calculator > vf (thiswould open the schematic window).9.In the schematic, select Out.10.In the Calculator Window you should get VF(*/Out*).11.Next select dB20.12.In the Calculator Window you should get dB20(VF(*/Out*)).13.Now select plot. You should get a DB plot similar to the one shown below.14.Add the phase by doing Tools > Calculator > vf (this would open theschematic window).15.In the schematic, select Out.16.In the Calc ulator Window you should get VF(*/Out*).17.Next, select phase.18.In the Calculator Window you should get phase(VF(*/Out*)).19.Now select plot. You should get a phase plot similar to the one shown below.21。

eetopcn_Cadence_使用参考手册ch1--ch7

Cadence 使用参考手册目录第一章概述 (1)1.1 Cadence 概述 (1)1.2 ASIC 设计流程 (1)第二章Cadence 使用基础 (5)2.1 Cadence 软件的环境设置 (5)2.2 Cadence 软件的启动方法 (10)2.3 库文件的管理 (12)2.4 文件格式的转化 (13)2.5 怎样使用在线帮助 (13)2.6 本手册的组成 (14)第三章Verilog-XL 的介绍 (15)3. 1 环境设置 (15)3.2 Verilog-XL 的启动 (15)3.3 Verilog XL 的界面 (17)3.4 Verilog-XL 的使用示例 (18)3.5 Verilog-XL 的有关帮助文件 (19)第四章电路图设计及电路模拟 (21)4.1 电路图设计工具Composer (21)4.1.1 设置 (21)4.1.2 启动 (22)4.1.3 用户界面及使用方法 (22)4.1.4 使用示例 (24)4.1.5 相关在线帮助文档 (24)4.2 电路模拟工具Analog Artist (24)4.2.1 设置 (24)4.2.2 启动 (25)4.2.3 用户界面及使用方法 (25)4.2.5 相关在线帮助文档 (25)第五章自动布局布线 (27)5.1 Cadence 中的自动布局布线流程 (27)5.2 用AutoAbgen 进行自动布局布线库设计 (28)第六章版图设计及其验证 (30)6.1 版图设计大师Virtuoso Layout Editor (30)6.1.1 设置 (30)6.1.2 启动 (30)6.1.3 用户界面及使用方法 (31)6.1.4 使用示例 (31)6.1.5 相关在线帮助文档 (32)6.2 版图验证工具Dracula (32)6.2.1 Dracula 使用介绍 (32)6.2.2 相关在线帮助文档 (33)第七章skill 语言程序设计 (34)7.1 skill 语言概述 (34)7.2 skill 语言的基本语法 (34)7.3 Skill 语言的编程环境 (34)7.4 面向工具的skill 语言编程 (35)附录1 技术文件及显示文件示例 (60)附录2 Verilog-XL 实例文件 (72)1 Test_memory.v (72)2 SRAM256X8.v (73)3 ram_sy1s_8052 (79)4 TSMC 库文件 (84)附录3 Dracula 命令文件 (359)Cadence 使用说明第1 页共388页概述作为流行的EDA 工具之一Cadence 一直以来都受到了广大EDA 工程师的青睐然而Cadence 的使用之繁琐又给广大初学者带来了不少麻烦作为一位过来人本人对此深有体会本着为初学者抛砖引玉的目的本人特意编写了这本小册子将自己数年来使用Cadence 的经验加以总结但愿会对各位同行有所帮助本册子的本意在于为初学者指路故不会对个别工具进行很详细的介绍只是对初学者可能经常使用的一些工具加以粗略的介绍其中可能还请各位同行加以指正1.1 Cadence 概述Cadence 是一个大型的EDA 软件它几乎可以完成电子设计的方方面面包括ASIC 设计FPGA 设计和PCB 板设计与众所周知的EDA 软件Synopsys相比Cadence 的综合工具略为逊色然而Cadence 在仿真电路图设计自动布局布线版图设计及验证等方面却有着绝对的优势Cadence 与Synopsys的结合可以说是EDA 设计领域的黄金搭档此外Cadence 公司还开发了自己的编程语言skill,并为其编写了编译器由于skill 语言提供编程接口甚至与C 语言的接口所以可以以Cadence 为平台进行扩展用户还可以开发自己的基于Cadence 的工具实际上整个Cadence 软件可以理解为一个搭建在skill语言平台上的可执行文件集所有的Cadence 工具都是用Skill 语言编写的但同时由于Cadence 的工具太多使得Cadence 显得有点凌乱这给初学者带来了更多的麻烦Cadence 包含的工具较多几乎包括了EDA 设计的方方面面本小册子旨在向初学者介绍Cadence 的入门知识所以不可能面面具到只能根据ASIC设计流程介绍一些ASIC 设计者常用的工具例如仿真工具Verilog-xl,布局布线工具Preview 和Silicon Ensemble,电路图设计工具Composer,电路模拟工具Analog Artist,版图设计工具Virtuoso Layout Editor,版图验证工具Dracula最后介绍一下Skill 语言的编程1.2 ASIC 设计流程设计流程是规范设计活动的准则好的设计流程对于产品的成功至关重要本节将通过与具体的EDA 工具Synopsys 和Cadence 相结合概括出Cadence 使用说明第2 页共388页一个实际可行的ASIC 设计的设计流程图1 1 是实际设计过程中较常用的一个流程接下一页Cadence 使用说明第3 页共388页图1 1 ASIC 设计流程图这是深亚微米设计中较常用的设计流程在该设计流程中高层次综合和底层的布局布线之间没有明显的界线高层设计时必须考虑底层的物理实现Cadence 使用说明第4 页共388页高层的划分与布局规划同时由于内核Core 的行为级模型有其物理实现的精确的延时信息使得设计者可在设计的早期兼顾芯片的物理实现从而可以较精确的估计互连的延时以达到关键路径的延时要求同时布局布线后提取的SDF 文件将被反标到综合后的门级网表中以验证其功能和时序是否正确从该流程中可看出在实际设计中较常用到的Cadence 的工具有VerilogHDL 仿真工具Verilog-XL,电路设计工具Composer 电路模拟工具Analog Artist, 版图设计工具Virtuoso Layout Editor,版图验证工具Dracula 和Diva 以及自动布局布线工具Preview 和Silicon Ensemble 本册子将对这些工具作一个初步介绍如果读者想进一步了解某个软件的使用可参考本册子提供的相关在线文档以进一步熟练Cadence 使用手册第二章 Cadence 使用基础第一章Cadence 使用基础2.1 Cadence 软件的环境设置要使用Cadence,必须在自己的计算机上作一些相应的设置这些设置包括很多方面而且不同的工具可能都需要进行各自的设置读者如果遇到这方面的问题可以参考一下openbook 中的Configuration Guides 及各工具的user guide 或者reference,其访问的方法是main menu-> System Administration-> Configuration Guides 但作为初学者只需进行以下几项设置1. .cshrc 文件的设置首先要在自己的.cshrc 文件中设置Cadence 软件所在的路径所使用的licence 文件等下面的代码为.cshrc 中设置的一个简单示例其中Cadence 所在的目录为/EDA04/cds97a/Cadencesetenv CDS_ROOT /EDA04/cds97asetenv CDS_INST_DIR /EDA04/cds97aset path = ($path $CDS_INST_DIR/tools/dfII/bin$CDS_INST_DIR/tools/bin)setenv LM_LICENSE_FILE /EDA04/cds97a/share/license/license.dat 对于某些Cadence 中的工具也必须在.cshrc 中进行一些设置2. .cdsenv 文件设置.cdsenv 文件中包含了Cadence 软件的一些初始设置该文件是用Skill语言写成的Cadence 可直接执行3. .cdsinit 设置与.cdsenv 一样.cdsinit 中也包含了Cadence 软件的一些初始化设置该文件是用Skill 语言写成的在Cadence 启动时会首先自动调用这Cadence 使用手册第二章 Cadence 使用基础两个文件并执行其中的语句若仅为初学可以不编写这两个文件Cadence 会自动调用隐含的设置若想更改设置可参考一些模板文件进行编写在install_dir/tools/dfII/cdsuser 目录下有一些隐含的模板文件下面是一个简单的.cdsinit 文件;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; Tutorial .cdsinit file; By: Cris Reeser/Diane Goldberg; Created: October 10, 1995;; This initialization file contains the settings necessary to ; successfully run the Cell Design tutorial. Some of these may ; be redundant, if your site uses a site initialization file. ; For further information on initialization files, read the; comments in the <install_dir>/samples/local/cdsinit file.; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; Human Interface Environment SettingshiiSetFont("text" "-adobe-courier-bold-r-*-*-12-*") hiSetFormPosition(603:500)hinestLimit = 5hiSetUndoLimit(10)hiExpertMode(nil)window(1)->useScrollbars = twindow(1)->backingStore = tenvSetVal("layout" "xSnapSpacing" 'float 0.5)envSetVal("layout" "ySnapSpacing" 'float 0.5)envSetVal("layout" "segSnapMode" 'string "anyAngle") envSetVal("layout" "stopLevel" 'int 20)envLoadFile("./.cdsenv") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Cadence 使用手册第二章 Cadence 使用基础;;; Bindkey Settingsload(prependInstallPath("samples/local/schBindKeys.il")) load(prependInstallPath("samples/local/leBindKeys.il")) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; RESIZE CIW; CIW; Note, hiFlush() is used as a workaround to display problem with; resizing windows in SKILL.hiFlush()hiResizeWindow(window(1) list(3:3 750:200)) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; Tutorial Customization ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;setSkillPath(". techFiles"); Welcome the userfprintf(poport"************************************************\n")fprintf(poport "Welcome to the SRAM Compiler... %s\n" getShellEnvVar("USER"))printf( " \n" )printf( "Done with initialization.\n" )printf("************************************************\n ")printf( " \n" )printf( " \n" )从中可看出Skill 语言的语法与C 语言的较为类似经过一定的学习后Cadence 使用手册第二章 Cadence 使用基础就很容易掌握4. cds.lib 文件的设置如果用户需要加入自己的库则可以修改自己的库管理文件cds.lib对于初次使用Cadence 的用户Cadence 会在用户的当前目录下生成一个cds.lib 文件用户通过CIW 生成一个库时Cadence 会自动将其加入cds.lib 文件中下面是一个简单的Cadence 库管理文件cds.lib 的示例DEFINE ourTechLib/EDAHOME01/students/dhf/sram/dual/ourTechLibDEFINE sram /EDAHOME01/students/dhf/sram/dual/sram DEFINE basic ${CDS_INST_DIR}/tools/dfII/etc/cdslib/basic DEFINE sample${CDS_INST_DIR}/tools/dfII/samples/cdslib/sampleDEFINE analogLib/EDA04/cds97a/tools/dfII/etc/cdslib/artist/analogLib DEFINE pCells /EDAHOME01/students/dhf/sram/dual/pCells DEFINE hhh /EDAHOME01/students/dhf/sram/dual/hhh其中DEFINE 为库定义的保留字,ourTechLib sram 等为所定义的库的名字最后的字符串为保存库的实际的物理目录5. 技术库的生成技术文件库对于IC 设计而言是非常重要的其中包含了很多设计中所必需的信息对于版图设计者而言技术库就显得更为重要了要生成技术文件库必须先编写技术文件技术文件主要包括层的定义符号化器件的定义层物理以及电学规则和一些针对特定的Cadence工具的规则的定义例如自动布局布线的一些规则版图转换成GDSII时所用到的层号的定义技术文件的编写可参考openbook 中有关技术文件的介绍并参考相应的模板来进行其访问顺序为Main Menu->IC Tools->Design FramWork II->Technology File Help 附录1 中有一个简单的技术文件示例技术文件编好以后就可以按照以下几步生成技术库1 点击CIW 中的File 菜单选择其中的New 项中的Library 项如图2 1 所示弹出图2 2 所示的表格Cadence 使用手册第二章 Cadence 使用基础2 在Name 项中输入所需的名字如myTecLib 保持如图所示的设置点击ok 弹出如图2 3 所示的对话框3 在对话框中输入编好的技术文件名如my.tf 这时技术文件必须在启动Cadence 的当前目录点击ok4 经过一段时间后在CIW 的显示区会出现一个提示Library myTecLib is created successfully.对于非工艺库的生成与工艺库大体相同只是在2 2 中选择attach to exited technology file,并在接下来的过程中选择相应的工艺库图2 1图2 2Cadence 使用手册第二章 Cadence 使用基础图2 36. 显示文件display.drf 的设置display.drf 文件控制Cadence 的显示其基本语法可参考openbook 中的相应的介绍附录1 中包含了一个display.drf 的示例2.2 Cadence 软件的启动方法完成了一些必要的设置对初学者只需设置.cshrc 文件即可其他设置都用隐含设置等熟练了一些之后再进一步优化自己的使用环境就可以启动Cadence 软件启动Cadence 软件的命令有很多不同的启动命令可以启动不同的工具集常用的启动命令有icfb,icca 等也可以单独启动单个工具例如启动Viruoso Layout Editor 可以用layoutPlus 来启动Silicon Ensemble 可以用sedsm 来启动以icfb 为例先在UNIX 提示符下输入icfb& 再按回车经过一段时间就会出现如图2 4 所示的CIW Command Interpreter Window窗口从CIW 窗口就可以调用许多工具并完成许多任务CIW 窗口是使用Cadence 时遇到的第一个窗口是Cadence 主要的用户界面它主要包括以下几个部分1 Title Bar 显示使用的软件名及log 文件目录如图2 4 中的最上一行icfb-log:/ EDAHOME01/students/dhf/CDS.log2 Menu Banner3 Output Area 输出Cadence 对用户命令的反应4 Input Line 可用来输入Skill 命令5 Mouse Bindings Line 显示捆绑在鼠标左中右三键上的快捷键6 Scrolling bar to Scroll Through the Log FileCadence 将许多常用工具集成在一块以完成一些典型的任务图2 5 总结了一些常用的启动命令及其可使用的工具用户可根据自己的需要选择最少的命令集Cadence 使用手册第二章 Cadence 使用基础图2 4 CIW 窗口图2 5 Cadence 启动命令Cadence 使用手册第二章 Cadence 使用基础2.3 库文件的管理启动了Cadence 后就可以利用File 菜单建立自己的工作库点击CIW窗口上的File 菜单选定其中的New lib 项弹出如图2 2 所示的对话框输入库名并选择相应的工艺库然后选择ok,这时在CIW 的显示区会出现如下提示The lib is created successfully!新建的库是一个空的库里面什么也没有用户可在库中生成自己所需的单元例如可以生成一个反相器单元并为其生成一个电路及一个版图视图其流程如下1 选择File 菜单中的New 项并选择Cellview 项则弹出如图2-6 所示的对话框选择所需的库并输入单元名inv 并选择视图类型Schematic 再点击ok 按钮则弹出如图2 7 所示的窗口2 用Add 菜单中的Component 命令调用analogLib 中的单元输入PMOS 和NMOS 管以及电源和地如图2 8 所示3 点击Check and save 命令保存用同样的流程可生成inv 的版图视图利用Tools 中的library manager 可以对库进行管理图2 6Cadence 使用手册第二章 Cadence 使用基础图2 7图2 82.4 文件格式的转化Cadence 有自己的内部数据格式为了与其他EDA 软件之间进行数据交换Cadence 提供内部数据与标准数据格式之间的转换点击CIW 的File 菜单中的Import 可将各种外部数据格式转换成Cadence 内部数据格式利用CIW 的File 菜单中的Export 可将各种Cadence 内部数据格式转换成外部标准数据格式2.5 怎样使用在线帮助学习Cadence 的最好教材是使用在线帮助Cadence 的在线帮助是用openbook 命令来启动的在UNIX 提示符下输入openbook&并回车就可以启动在线帮助要拷贝在线帮助中的文件可以先按下control 键并用左键进行选择然后用copy 进行拷贝如果想要知道一些关于如何使用openbook 的技巧可在系统提示符下输入Cadence 使用手册第二章 Cadence 使用基础openbook help &即可2.6 本手册的组成在本手册中将按照ASIC 设计流程分别在第三章介绍高层的HDL 工具例如Verilog 仿真工具Verilog-xl 第四章介绍电路图设计工具Composer 及电路模拟工具Analog Artist 第五章介绍自动布局布线Preview 和Silicon Ensemble 第六章介绍版图设计工具Virtuoso Layout Editor 和验证工具Dracula 和Diva 第七章将介绍Skill 语言的编程Cadence 使用手册第三章Verilog-XL 的介绍第二章Verilog-XL的介绍人们在进行电子设计时较常用的输入方法有两种一种为硬件描述语言一种为电路图输入随着ASIC 设计技术的发展以HDL 作为输入的设计方法已成为ASIC 设计的主流目前较常用的硬件描述语言有VHDL 和Verilog两种相对而言Verilog 在工业上用的较为平常故本小册子的讨论集中在Verilog 上作为EDA 设计的主流软件之一Cadence 提供了对Verilog 及VHDL 的强大支持尤其是Verilog,Cadence 很早就引入了Verilog,并为其开发了一整套工具而其中最出色的当数Verilog 的仿真工具Verilog-XL Verilog-XL 一直以其友好的用户界面及强大的功能而受到广大Verilog 用户的青睐本章将分五个方面一一对对其进行一个较为详尽的介绍3. 1 环境设置对于一般的Cadence 的用户而言可能不需要进行任何设置就可启动Verilog-XL 用户可输入下列命令看自己是否可访问Verilog-XLwhich verilog如果可以访问Verilog-XL,会有类似如下的反应/EDA04/cds97a/ tools/bin/verilog否则必须在.cshrc 中用set path 命令加入以上路径3.2 Verilog-XL 的启动Verilog-XL 的启动命令为verilog,它可以附带很多可选项下面是其各选项及其意义Valid host command options for verilog:-f <filename> read host command arguments from file-v <filename> specify library file-y <directory> specify library directory-c compile only-s enter interactive mode immediately-i <filename> input from command fileCadence 使用手册第三章Verilog-XL 的介绍-r <filename> restart from a saved data structure-l <filename> set log file name-k <filename> set key file name-u convert identifiers to upper case-t set full trace-q quiet-d decompile data structureSpecial behavioral performance options (if licensed):+turbo speed up behavioral simulation.+turbo+2 +turbo with second level optimizations.+turbo+3 +turbo+2 with third level optimizations.+listcounts generate code for maintaining information for $listcounts+no_turbo don't use a VXL-TURBO license.+noxl disable XL acceleration of gates in all modulesSpecial environment invocation options (if licensed):+gui invoke the verilog graphical environment下面是几个简单的使用示例在UNIX 提示符下输入这些命令即可启动Verilog-XLExample host commands to run VERILOG:verilog sio85.vverilog f1 f2 f3verilog -s sio85.vverilog -r save.dat -l run2.log -k run2.keyverilog -r save.dat -si commands.vicverilog -dqcr save.dat一般较常用的启动方法是verilog –s +gui –v libname –f scriptFile sourcefilename & 其中libname 为所使用的库的名字scriptFile 为用可选项编Cadence 使用手册第三章Verilog-XL 的介绍写的命令文件3.3 Verilog XL 的界面运行以上的启动命令后如果未发生什么错误就会弹出下图所示的用户界面这就是Verilog-XL 的SimControl 窗口,从该图形界面中可控制仿真的执行图3 1 Verilog-XL 的图形界面Verilog-XL 的图形界面主要有以下几个窗口1 SimControlSimControl 窗口是主要的仿真控制窗口当用带有gui 选项的verilog 命令启动Verilog-XL 时就会弹出这个窗口通过这个窗口用户可以显示设计的模块结构运行Verilog-XL 命令设置及显示断点强行给变量赋值等等通过这个窗口可以实现用户与仿真的交互从而达到对仿真的控制2 Navigator通过点击SimControl 窗口右上角的星形图标即可激活Navigator 窗口该窗口可用来图形化显示设计的层次设计中的实体及其变量3 Signal Flow BrowserCadence 使用手册第三章Verilog-XL 的介绍4 Watch Objects Window5 SimWaveSimWave 窗口可以用来显示已经选择并跟踪了的信号的波形3.4 Verilog-XL 的使用示例介绍了Verilog-XL 的启动和用户界面后下面我们将通过一个具体的实例来演示Verilog-XL 的使用在附录2 中有本示例所需的文件在本示例中将对一个SRAM 模块SRAM256X8.v 进行仿真在这个SRAM 模块中又包含了一个子模块ram_sy1s_8052.v 所调用的为TSMC 的0.35um 的库test_bench 为test_memory.v 在该test_bench 中首先对SRAM 进行写然后进行读下面按照一个简单的流程来对这个SRAM 进行模拟1 在UNIX 提示符下输入verilog -c -v tcb773s.v test_memory.v &来对源文件进行调试如果没有错误会显示0 Simulation events2 没有错误之后就可以启动Verilog-XL 的图形界面verilog –s +gui –v tcb773s.v test_memory.v &则会弹出如图3 2 所示的窗口3 跟踪自己所需要的波形信号4 按运行按钮或在命令行输入原点并回车即可运行按停止按钮即可停止停止后波形会自动更新Cadence 使用手册第三章Verilog-XL 的介绍图3 23.5 Verilog-XL 的有关帮助文件与Verilog-XL 有关的帮助文件主要有以下一些Verilog-XL ReferenceVerilog-XL User GuideVerilog-XL TutorialSimCompare User GuideSimWave User GuideVPI User Guide and Reference (formerly PLI 2.0)PLI 1.0 User Guide and ReferencePLI Application Note: Back Annotation and Delay CalculationPLI Application Note: Using the Value Change LinkLMC Hardware Modeling Interface Reference and User GuideGraphical Output for the Verilog Product Family ReferenceSDF Annotator User GuideCentral Delay Calculator Algorithm GuideCadence 使用手册第三章Verilog-XL 的介绍Timing Library Format ReferenceVerilog Language Sensitive Editor User Guide可通过如下顺序对这些文档进行访问Main menu->HDL Tools>Verilog-XLCadence 使用手册第四章电路图设计及电路模拟第四章电路图设计及电路模拟设计的输入除了可以用硬件描述语言如VHDL 及Verilog 外还可以用电路图输入在早期的ASIC 设计中电路图起着更为重要的作用作为流行的EDA 软件,Cadence 提供了一个优秀的电路图编辑工具Composer Composer 不但界面友好操作方便而且功能非常强大电路图设计好后其功能是否正确性能是否优越必须通过电路模拟才能进行验证Cadence 同样提供了一个优秀的电路模拟软件Analog Artist由于Analog Artist 通过Cadence 与Hspice 的接口调用Hspice 对电路进行模拟本章将介绍电路图设计工具Composer 和电路模拟软件Analog Artist 的设置启动界面及使用方法简单的示例以及相关的辅助文件以便读者能对这两种工具有一个初步的理解4.1 电路图设计工具ComposerComposer 是一种设计输入的工具逻辑或者电路设计工程师物理设计工程师甚至PCB 板设计工程师可以用它来支持自己的工作4.1.1 设置对于一般的Cadence 的用户而言可能不需要进行任何设置就可启动Composer 但有时必须设置快捷键否则所有的快捷键就会失灵给使用带来一些不便在设计时快捷键往往会有很大的作用此外在电路设计中可能需要用到一些符号库例如sample 库basic 库analogLib 库只需在cds.lib 文件中加入以下一段代码DEFINE basic ${CDS_INST_DIR}/tools/dfII/etc/cdslib/basicDEFINE sample${CDS_INST_DIR}/tools/dfII/samples/cdslib/sampleDEFINE analogLib/EDA04/cds97a/tools/dfII/etc/cdslib/artist/analogLibCadence 使用手册第四章电路图设计及电路模拟4.1.2 启动Composer 的启动很简单在启动Cadence 后从CIW 窗口中打开或新建一个单元的Schematic 视图就会自动启动Composer 的用户界面用户即可在其中放入单元及连线以构成电路图4.1.3 用户界面及使用方法图4 1 是Composer 的图形界面在该用户界面中大部分面积是右下角的显示区左边的图标是一些常用的工具读者可以自己启动Composer然后熟悉一下Composer 的用户界面下面将简单介绍一下电路图设计及符号Symbol 设计的简单流程图4 1 Composer 的用户界面图4 2 是编辑电路图的一般流程为1 首先用Component 命令调用符号库中的元件来添加元件如图的nand32 添加完所有的元件后就可以加入pin,可通过add 菜单中的pin 项来进行添加3 布线及标线名可通过wire 命令布线通过更改其属性标上线名Cadence 使用手册第四章电路图设计及电路模拟4 添加节点5 加注释6 加整体属性如一些自动布局布线属性图4 2 电路图设计的简单流程符号是用来代表元件的简单符号如反相器用一个三角形代替在Cadence 中当上层调用下层单元和进行上下级映射时通常调用其符号所以符号在电路设计中起着很重要的作用与启动Schematic Editor 类似通过在CIW 窗口中新建或打开一个单元的symbol 视图就可启动Symbol Editor 图4 3 是编辑符号的一般流程主要包括以下几步1 在编辑区加入一些基本的图形2 加入符号的pin3 加入连接基本图形与pin 的线4 加入符号的标记如inv5 加入选择外框6 加入文本注释7 更改整体属性Cadence 使用手册第四章电路图设计及电路模拟图4 3 符号设计的简单流程4.1.4 使用示例在openbook 中有一个关于Composer 的教程如果读者需要经常用到电路图本人建议你不妨去走一遍那个教程对你一定会有帮助的该教程可安如下顺序进行访问Main Menu-> IC Tools->Tutorials-> Composer4.1.5 相关在线帮助文档Composer: Design Entry help4.2 电路模拟工具Analog ArtistCadence 提供进行电路模拟的工具Analog Artist Anglog Artist 通过调用Hspice 进行电路模拟然后进行各种后续处理并显示结果4.2.1 设置在运行Analog Artist 之前必须在.cshrc 中设置以下语句setenv CDS_Netlisting_Mode Analog此外最好能从Cadence 的安装目录的Analog Artist 中拷贝与模拟器相应的初始化文件Cadence 使用手册第四章电路图设计及电路模拟4.2.2 启动Analog Artist 的启动方法有很多种可以从Composer 的Tools 菜单中执行也可以从CIW 的Tools 菜单中执行4.2.3 用户界面及使用方法图4 4 是Analog Artist 的用户界面关于具体的使用方法请参考openbook中的相应手册但有一点想提醒大家大家使用的licence 可能不允许使用Analog Artist 如果在微所使用Analog Artist 且用Hspice 为模拟器似乎激励文件用cdsspice 格式才可调通有兴趣的读者可以一试4.2.5 相关在线帮助文档与Analog artist 相关的在线文档有Analog Artist Simulation HelpCadence 使用手册第四章电路图设计及电路模拟Analog Artist Microwave Design HelpAnalog Artist Mixed-Signal Simulation HelpAnalog Artist Parametric Analysis HelpAnalog Artist Substrate Coupling Analysis (SCA) HelpAnalog Artist SKILL Functions ReferenceAnalog Expression Language ReferenceCadence SPICE ReferenceComponent Description Format User GuideFunctional Block Library ReferenceHSPICE/SPICE Interface and SPICE 2G.6 ReferenceSpectre ReferenceSpectre User GuideSpectreHDL ReferenceSpectreRF HelpSwitched Capacitor Design System HelpAnalog Artist Tutorial: Switched Capacitor DesignVerilog-A Reference通过顺序 Main Menu-> IC Tools->Analog and Mixed Signal Simulation 可以访问Cadence 使用手册第五章自动布局布线第五章自动布局布线5.1 Cadence 中的自动布局布线流程从第一章的ASIC 设计流程中可看到设计输入经过综合和优化后就该对所生成的门级网表进行自动布局布线自动布局布线是连接逻辑设计和物理设计之间的纽带在自动布局布线前必须进行布局规划floorplan ,在Cadence 中进行布局规划的工具为Preview 进行自动布局布线的引擎有四种Block Ensemble Cell Ensemble Gate Ensemble 和Silicon Ensemble 其中Block Ensemble 适用于宏单元的自动布局布线Cell Ensemble 适用于标准单元或标准单元与宏单元相混合的布局布线Gate Ensemble 适合于门阵列的布局布线Silicon Ensemble 主要用在标准单元的布局布线中将Preview 与四种引擎相结合可产生四种不同的自动布局布线环境和流程由于Silicon Ensemble(DSM)的功能很完全几乎可以完成所有复杂的自动布局布线的任务在考虑自动布局布线引擎时我们采用了Silicon Ensemble SRAM 编译器所生成的用于自动布局布线的端口模型为Silicon Ensemble 所要求的格式图5 1 为采用Preview 和Silicon Ensemble 进行自动布局布线的流程图该流程主要由以下几个主要步骤组成1 准备自动布局布线库在进行自动布局布线之前必须准备好相应的库该库中含有工艺数据自动布局布线用的库单元及显示信息库的格式必须为Design Framework II 的数据库格式可以由用户利用版图生成工具Virtuoso Layout Editor 设计产生也可以来自一个由芯片制造厂家和EDA 公司提供的LEF(Library Exchange Format)文件或者从GDSII 生成2 准备用来进行自动布局布线的网表用来进行布局布线的网表可以由硬件描述语言经过综合优化或由电路提取而来所有网表在进行自动布局布线前都必须首先生成对应的autoLayout 视图view3 用Preview 进行布局规划Cadence 使用手册第五章自动布局布线Preview 是 Cadence 的布局规划器它可以用来规划物理设计从而在自动布局布线前预估物理实现的影响在Cadence 中使用Preview 与自动布局布线引擎相结合来进行自动布局布线4 用Silicon Ensemble 进行自动布局布线5 对完成布局布线的版图进行验证生成的版图其连接性是否正确是否符合设计规则是否符合时序要求等等必须通过验证才能确定通过点击Verify&Report 菜单中的相应项可对版图进行连接性设计规则验证并可生成SDFStandard Delay Format 文件通过反标SDF 文件可对原来的门级网表进行仿真从而确定其功能和时序是否正确图5 1 用Preview 和Silicon Ensemble 进行自动布局布线的流程5.2 用AutoAbgen 进行自动布局布线库设计对于不同的自动布局布线引擎,对应的库的数据格式有所不同,用来生成库的工具也不同本SRAM 编译器选择Silicon Ensemble 作为布局布线引擎其对应的库生成工具为AutoAbgen AutoAbgen 可以用来生成与用户设计的版图或版图库所对应的Abstract(即用于自动布局布线的端口模型)可以用AutoAbgen 的AutoAbgen Flow Sequencer form 来生成Abstract 对于单个版图和LEF 文件对于整个物理库其基本流程如下Cadence 使用手册第五章自动布局布线(1) 首先在局部.cdsinit 中设置好AutoAbgen 运行的环境即在.cdsinit 中加入以下语句aabsInstallPath=“<install_dir>/tools/autoAbgen/etc/autoAbgen”load(buildstring(list(aabsInstallPath “aaicca.ile”) “/”))(2) 将AutoAbgen 的初始化文件.autoAbgen 拷入运行目录并用icfb&启动Cadence(3) 点击CIW 窗口中的AutoAbgen 菜单下的AutoAbgen Flow Sequencer 项打开Flow Sequencer Form(4) 选择合适的流程(5) 建立布局布线所需的工艺信息如果在工艺文件中已经包含布局布线的工艺信息可以忽略这一步(6) 建立用来生成Abstract 的版图数据如果所用的版图数据已经是DFII 的版图格式可以忽略这一步(7) 更新单元的属性及其管脚属性由于AutoAbgen 对所操作的版图有些特殊要求所以在生成Abstract 前必须对其属性进行更新以符合AutoAbgen的要求(8) 建立一个库单元将所需建立Abstract 的所有单元包括到里面(9) 填写环境设置表格和运行选项表格输入输出LEF 的文件名如果是对库进行操作(10) 选择Apply 运行AutoAbgen 生成所需的Abstract。

手册大全--candence使用手册仿真分册

Candence使用手册_仿真分册前言PCB仿真Cadence软件是我们公司统一使用的原理图设计、PCB设计、高速仿真的EDA工具。

进行仿真工作需要有很多方面的知识，须对高速设计的理论有较全面的认识，并对具体的单板原理有一定的了解，还需具备仿真库的相关知识等。

在这个分册中仅对仿真软件的使用进行较详细的阐述，还介绍高速设计的一些相关理论，仿真过程是基于Allegro SPB 15.7的PCB SI模块进行的。

其他知识，如仿真库的知识、约束管理器等请参阅专门的使用手册。

在此非常感谢网络南研 EDA和本部 EDA对此手册的支持。

第一章高速设计与PCB仿真流程本章介绍高速PCB仿真设计的基础知识和重要意义，并介绍基于Cadence 的Allegro SPB15.7的PCB仿真流程。

1.1高速信号与高速设计随着通信系统中逻辑及系统时钟频率的迅速提高和信号边沿不断变陡，PCB的走线和板层特性对系统电气性能的影响也越发显著。

对于低频设计,走线和板层的影响要求不高甚至可以完全忽略不计。

当频率超过 50MHz时，PCB走线则必须以传输线考虑，而在评定系统性能时也必须考虑 PCB 板材的电参数影响。

当系统时钟频率达到120MHz及更高时，就只能使用高速电路设计方法，否则基于传统方法设计的PCB将无法工作。

因此，高速电路设计技术已经成为电子系统设计师必须采取的设计手段，只有通过使用高速电路设计师的设计技术，才能实现设计过程的可控性。

高速系统的设计必须面对互连延迟引起的时序问题以及串扰、传输线效应等信号完整性问题。

通常认为如果数字逻辑电路的频率达到或者超过45MHZ~50MHZ，而且工作在这个频率之上的电路占整个电子系统的一定份量（比如说１／３），就称为高速电路。

实际上，信号边沿的谐波频率比信号本身的频率高，是信号快速变化的上升沿与下降沿（或称信号的跳变）引发了信号传输的非预期结果。

因此，通常约定如果线传播延时大于1/2数字信号驱动端的上升时间，则认为此类信号是高速信号并产生传输线效应，见图1－1所示。

cadence版图使用说明

目录目录 (1)设计环境介绍 (2)工作站常用命令 (2)运行Cadence (6)运行Layout (10)运行schematic的编辑 (15)生成schematic symbol (18)运行Artist的仿真环境 (20)设计示例的简单介绍 (21)设计环境介绍典型的全定制Full-Custom模拟集成电路设计环境1. 集成的设计环境－Cadence Design Framework II是众多Cadence 工具集成在一起的统一的界面，通过这个架构,不用繁琐的数据格式转换，就可以方便的从一个工具转到另一个工具。

其中包括很多软件，如：原理图编辑工具-Composer布局编辑工具-Candence virtuoso布局验证编辑工具-Diva, Dracula2. 电路网表或原理图编辑环境－Text editor / schematic editor3. 电路模拟软件－spice操作系统环境和硬件平台1.SUN工作站；UNIX系统2.运行Linux的PC3.作为终端的PC工作站常用命令一、在terminal窗口键入的基本命令：1. ls：列出目录下所有文件。

2. clear：清除terminal窗口里的内容。

3. pwd：显示目前工作的目录。

4. cd：改变当前目录。

5. rm：刪除文件。

6. cp：复制文件。

7. mv：移动文件。

8. mkdir：建立目录。

9. rmdir：刪除目录。

10. find：寻找文件。

11. passwd：改变当前用户密码。

12. finger：显示当前用户信息。

二、基本操作和命令的使用介绍：1.从PC登录工作站，一般使用exeed或Xmanager。

login ：___________(输入username)password：___________(输入密码)2.登出步骤：点击exit3.在线命令说明（以下的example% 表示系统的提示符）example% man [command-name]4. 改变当前目录example% cd [name]Example：example% cd dir1 改变目录位置，至dir1目录下。

Cadence的使用与基本仿真教程

Cadence的使用与基本仿真教程2014/11/9模拟集成电路设计课程实验1Outline启动Cadence新建Library 与Cell View常用快捷键常用库常用库、、器件基本仿真基本仿真指导指导仿真练习a)CS,CG,SF 电路仿真b)差分差分对电路仿真对电路仿真c)CS-CG 电路仿真2014/11/9模拟集成电路设计课程实验2启动Cadence在桌面上鼠标右击在桌面上鼠标右击，，open terminal >cd ~(回到home 目录下)>icfb &启动Cadence 。

上课时部分同学遇到问题是由于没有在home 目录下打开Cadence 2014/11/9模拟集成电路设计课程实验3新建LibraryFile>new>library2014/11/9模拟集成电路设计课程实验4新建Library起个名字>Don’t need a techfile>OK2014/11/9模拟集成电路设计课程实验5打开Library ManagerTools>Library Manager2014/11/9模拟集成电路设计课程实验6显示器件分类Show Category可以显示器件的分类2014/11/9模拟集成电路设计课程实验7显示器件分类例如例如：：在tsmc018rf 库中的分类有库中的分类有：：电容电容、、电阻电阻、、MOS 管等等管等等。

2014/11/9模拟集成电路设计课程实验8新建Cell ViewFile>New>Cell View2014/11/9模拟集成电路设计课程实验9新建Cell View将新建的Cell View 设定在之前新建的Library 下>起个名字>OK 2014/11/9模拟集成电路设计课程实验10快捷键快捷键：：i2014/11/9模拟集成电路设计课程实验11快捷键快捷键：：w2014/11/9模拟集成电路设计课程实验12快捷键快捷键：：c2014/11/9模拟集成电路设计课程实验13快捷键快捷键：：q2014/11/9模拟集成电路设计课程实验14快捷键快捷键：：r2014/11/9模拟集成电路设计课程实验15常用库常用库、、器件2014/11/9模拟集成电路设计课程实验16搭建反相器仿真电路照图搭建反相器仿真电路2014/11/9模拟集成电路设计课程实验17设置PMOS参数：参数：设置PMOS参数将w设置为6μm2014/11/9模拟集成电路设计课程实验18设置电压源vpulse 参数设置vpulse 参数参数：：AC magnitude :1DC voltage:Vdc （设为变量Vdc ）Voltage 1:0Voltage 2:1.8Pulse width :1nPeriod:2n注意注意：：AC 参数的设置不会影响直流工作点DC voltage 决定直流工作点决定直流工作点；；下面四个参数设置时域波形,不影响直流不影响直流。

cadence版图仿真教程

Candence约束管理器分册教程

约束管理器分册第一章约束管理器介绍约束管理器是一个交叉的平台，以工作簿和工作表的形式在Cadence PCB设计流程中用于管理所有工具的高速电子约束。

约束管理器让你定义、查看和校验从原理图到分析到PCB设计实现的设计流程中每一步的约束。

可以使用约束管理器和SigXplorer Expert开发电路的拓扑并得出电子约束，可以包含定制约束、定制测量和定制激励。

本培训教材描述的主要是怎样在约束管理器中提取约束，并且约束如何与原理图和PCB的属性同步。

本教材的内容是约束管理器、Concept HDL和PCB Design的紧密集成的集锦。

所谓约束就是用户定义的限制条件，当在板上走线和放置元件时会遵守这些约束。

电子约束（ECSets）就是限制PCB上与电行为有关的对象，比如可以设置某个网络最大传输延迟为2ns。

教材主要内容如下：•第1章～第7章主要关于原理图约束管理器使用：在约束管理器中提取ECs（电子约束）；在原理图和约束管理器中执行ECO；在Concept和PCB Design中传递ECs。

这部分面向Concept HDL的约束管理器的初学者，但是要熟悉Concept HDL 和PCB Design。

此教材不讨论Concept HDL和PCB Design不同模式和属性的细节，但是会详细地讨论约束管理器过程。

为了快速理解约束管理器的主要特点，可以看看Concept HDL的多媒体教材。

请见Help –Learning Concept HDL–Demos in Concept HDL。

将练习文件project.zip解压缩到一个空的路径\design。

确认设置环境变量CONCEPT_INST_DIR到Cadence 安装路径（一般安装时设置好了）。

第8章～第12章主要关于PCB约束管理器使用，但是省略了与原理图相同的部分。

本培训教材附两个练习文件：project.zip和golderboard.rar。

Cadence 手册详细图解英文版

Cadence IC Design ManualFor EE5518ZHENG Huan QunLin Long YangRevised onMay 2017Department of Electrical & Computer EngineeringNational University of SingaporeContents1 INTRODUCTION (4)1.1 Overview of Design Flow (4)1.2 Getting Started with Cadence (6)1.3 Using Online Help (8)1.4 Exit Cadence (8)2 SCHEMATIC ENTRY (9)2.1 Creating a New Design Library (9)2.2 Creating a Schematic Cellview (10)2.3 Adding Components to Schematic (11)2.4 Adding Pins to Schematic (12)2.5 Adding Wires to Schematic (13)2.6 Saving Your Design (14)3 SYMBOL AND TEST CIRCUIT CREATION (15)3.1 Creating Symbol (15)3.2 Editing Symbol (16)3.3 Building Test Bench (18)4 SIMULATING YOUR CIRCUIT (21)4.1 Start the Simulation Environment (21)4.2 Selecting Project Directory (21)4.3 Setup Model Library (22)4.4 Choosing the Desired Analysis (22)4.5 Setup Variables (23)4.6 Saving Simulation Data (24)4.7 Saving Output for Plotting (24)4.8 Viewing the Netlists (25)4.9 Running the Simulation (25)5 PHYSICAL LAYOUT (28)5.1 Layout vs Symbol of CMOS Devices (28)5.2 Starting Layout Editor (29)5.3 Vias (31)5.4 Changing the Grid (33)5.5 Inserting and Editing Instances (34)5.6 Drawing Shapes / Paths (35)5.7 Creating Pins (36)6 DESIGN VERIFICATION: DRC AND LVS (38)6.1 Performing DRC (38)6.2 Performing LVS (40)6.3 Performing PEX (41)7 POST‐LAYOUT SIMULATION (45)7.1 Simulation the Extracted Cell View (45)8 CONCLUSION (46)1INTRODUCTIONThis manual describes how to use Cadence IC design tools. It covers the whole design cycle, from the front-end to the back-end, i.e., from the pre-layout design to the post-layout design.The manual aims to provide a guide for fresh users. Following the manual, users can start doing analog IC design even though the users don’t have any knowledge of the tools.An inverter is used to illustrate the whole cycle of analog IC design, and Cadence Generic 45nm (cg45nm) kit is the technology library used for implementing the inverter. The method stated in the manual can be applied to other type of analog circuit design.1.1Overview of Design FlowFigure 1 shows a typical analog IC design flow.The design flow starts from schematic entry with the Cadence schematic capture tool –Schematic Editor. Devices or cells from the cg45nm or other libraries are used to build your circuit. Your design is hierarchical; therefore higher level schematics also incorporate cells which you have already developed. The schematics which you enter at this stage therefore typically consist of a number of base library cells and also lower level cells designed yourself.These are described in Sections 2 and 3 of the manual.When you have finished designing a particular circuit, you need to simulate it to ensure that it works as expected. It would be unlikely that your circuit works as expected at the first time so you have to repeat the cycle to improve the circuit, as shown in Figure 1, until the circuit works satisfactorily. This must be done for each sub-circuit of your design and then for the top level design. How to simulate and view the performance of simulation results are presented in Sections 4 of the manual.When the performance of the circuit is satisfactory, it is ready to start the physical design or layout of the circuit. The layout starts with the cell or device placement. Once the cells have been placed, routing can be carried out. Routing connects the cells/device of the design.After finishing placement and routing, the layout has to go through the Design Rule Check (DRC) with rule decks provided by PDK provider, to ensure that there is no design rule violation in the layout. The layout has to be rectified accordingly to the rules’ requirement till it passes DRC.Upon a successful DRC, it is Layout-versus-Schematic (LVS) check, to assure that all connections in the layout are correct. The layout has to be amended accordingly to the schematic If LVS doesn’t pass. DRC has to be done whenever layout is changed. The process is repeated until the LVS passes.Figure 1. Analog IC Design FlowThe next step is parasitic extraction (PEX) to get the extracted view of the circuit, which is used for post–layout simulation. The extracted view includes the parasitic effects in both the instances/devices and the required wiring interconnects of the circuit.Following DRC, LVS and PEX, it is post-layout simulation. The post-layout simulation is essential to make sure that the circuit with the extra parasitic parameters functions well and still meet the design specifications. If the performance of the post-layout simulation is not acceptable, back to the stage of schematic entry to check the circuit. Basically, re-design the circuit is necessary. Repeat the whole flow until the results of the post-layout simulation meet the design specifications.If everything is satisfactory, the next stage is GDSII Generation. It generates a file which depicts the low level geometry of layout. GDSII format is industry standard format suitable fora semiconductor company to fabricate and manufacture the chip of layout. This is briefed inthe last section of the manual.1.2Getting Started with CadenceUpon logging into your account, you will be brought to the Linux Desktop Environment.Right click on the desktop and click Open Terminal to open a “window” on the desktop. This window is the Linux command line prompt at which you can run Linux commands. After running a Linux command, this window also shows the output of the command.The following steps show how to start Cadence with cg45nm kit.A.Create a working directory - project (it can be any name as you like) with thecommand:mkdir projectwhere mkdir is Linux command and the project is the directory name;B.Enter the working directory with the command:cd projectwhere the cd is the Linux command;C.Type the followings commands to do the environment setup for using Cadence Generic45nm PDK.cp /app11/cg45nm/USERS/cds.lib .cp /app11/cg45nm/USERS/assura_tech.lib .cp /app11/cg45nm/USERS/pvtech.lib .D.Start cadence in the working directory – project with the following command:virtuoso &where virtuoso is the command to start Cadence IC design tool.Now, Cadence tools are successfully started. Keeps only the Command Input Window (CIW) which is shown in Figure 2.Figure 2. CIW WindowDo not close this CIW and try to keep it in view whenever you are using Cadence. Error messages and output from some of the tools are always sent to the CIW. If something doesn't appear to be working, always check the CIW for error messages. In addition, the CIW allows the user great control over Cadence by interpreting skill commands which are typed into it.E.In the CIW, select Tools Library Manager. The Library Manager pop up as inFigure 3. The Library Manager is where you create, add, copy, delete and organizeyour libraries and cell views.Figure 3. Library Manager WindowYou can see that the library gpdk045 appears in the Library column of the librarymanager.Now, you have started Cadence tool and loaded the cg45nm kit successfully. There are some documents in /app11/cg45nm/ gpdk045_v4_0/docs, and you can always refer to these documents for the information such as devices, device models, DRC rules and others related to cg45nm kit.Next time, you need only to repeat the steps B and D, for launching Cadence virtuoso and doing your project.1.3Using Online HelpCadence provides a comprehensive online manuals for all Cadence tools. You can launch the online help by typing the following command at the Linux prompt.cdnshelpThis invokes the online software manuals. Alternately, there is a help menu on each Cadence window. Manual which is related to that window related will pop-up once clicking on the help button.1.4Exit CadenceTo exit Cadence, just click on the cross sign X or File Exit in CIW. It is necessary to exit Cadence when it is not in use. Your library file would be locked or cannot edited next time if Cadence was not exited properly.2SCHEMATIC ENTRYNow that Cadence is running, you are almost ready to start entering schematics. However, you must first create a library which will be used to store all the parts of your design. Then, schematic can be created in the library.2.1Creating a New Design LibraryA.In the Library Manager window, select File→New→Library. New Library formpops up as shown in Figure 4.B.In the New Library form referring to Figure 4, key in your design library name(example: test) in the field of Name, and then click Ok.C.Click Ok in the pop-up window - the Technology File for New Library, referring toFigure 5.D.Choose gpdk045 in the Attach Library to Technology Library form, referring toFigure 6, and then click Ok.Figure 4. New Library FormFigure 5. Technology File for New Library FormFigure 6. Attach Library to Technology File FormA new library, named test, should appear in your Library Manager window.2.2 Creating a Schematic CellviewA.In Library Manager, select the Library where you would like to create a schematic. Then,select File→New→Cell View.B.Set up the New File form as Figure 7Figure 7. Create CellViewC.Click OK when done. A blank schematic window for the "inv" (your cell name)schematic appears.Explore the functions available by putting your mouse over the toolbar and fixed menu icons.In addition, note that some of the menu selections have alphabets listed to the right of them. These are bind-key or shortcut-key definitions which are very useful in the long run.Test them out during the schematic drawing in subsequent steps.2.3Adding Components to SchematicFigure 8 shows the schematic which you are going to patch, and the property of each component is listed in Table 1.Figure 8. Inverter CircuitTabel 1. Component Properties of Figure 8: Inverter CircuitComponents Library Name Cell Name PropertiesPMOS gpdk045 pmos1v l:45nm w:120nm (default size)NMOS gpdk045 nmos1v l:45nm w:120nm (default size)Here is the example on how to add component instances by placing cell views from libraries. Type “i” bind-key or select Create Instance in the schematic window or click on the menu bar to display Add Instance form. Then in the Add Instance window, select gpdk045as Library, choose the NMOS transistor by selecting nmos1v in Cell and also choose symbol as View, as shown in Figure 9.Figure 9. Add Instance FormSimilarly, add the pmos1v into the schematic. As an example, here we just keep all theparameters as default.If you place a component with the wrong parameter values, select the component and type “q” bindkey or use the Edit→Properties→Objects command to change the parameters. Use the Edit→Move command or type “m” if you place components in the wrong location.2.4Adding Pins to SchematicYou must place I/O pins in your schematic to identify the inputs and the outputs. A pin can be an input, output or an input-output (bi-directional) pin.Type “p” or select Add →Pin from inv Schematic Window or click the Pin fixed menuicon in the schematic window. The Add Pin form appears as Figure 10.Figure 10. Add Pin FormClick Hide and move you cursor to the Schematic Window. Place pins at the correct places and click right mouse key to rotate the pin if necessary.Add pins according to Table 2, paying attention to the direction.Table 2. Pin Names and Direction of invPin Names DirectionVin InputVout OutputVDD, GND Input-OutputCaution: Do not use the add component form to place schematic pins.2.5 Adding Wires to SchematicAdd wires to connect the components and pins in the design.A.Type “w” or select Add →Wire (narrow) in Schematic Window or click (narrow)fixed menu icon.B.In the schematic window, click on a pin of one of your components as the first pointfor your wiring. A diamond shape appears over the starting point of this wire.C.Follow the prompts at the bottom of the design window and click left mouse key onthe destination point for your wire.D.Continue wiring the schematic. When done wiring, press Esc with your cursor in theschematic window to cancel wiring.2.6Saving Your DesignCheck the design to ensure that it is correct and save the design.A.Click the Check and Save icon in the schematic window.B.Observe the CIW output area, for the information of the check and save action.3SYMBOL AND TEST CIRCUIT CREATIONSymbols are useful when creating designs as it is impractical to show every transistor on the top level schematic. Instead, the symbols of cells are created in order to instantiate them in the higher level schematics and make them more readable (i.e. hierarchical designs). Create a symbol for your design so you can place it in a test circuit for simulation.3.1Creating SymbolA.In the inv schematic window, select Create → Cellview → From Cellview. CellviewFrom Cellview pops up as shown in Figure 11.Figure 11. Cellview From Cellview FormB.Click OK in the Cellview From Cellview form. The Symbol Generation Options formappears as Figure 12. Enter the information listed in Table 3 for the symbol.Table 3: Pin SpectificationsLeft Pins : VinRight Pins : VoutTop Pins: VDDBottom Pins: GNDFigure 12. Symbol Generation Options FormC.Click OK in the Symbol Generation Options form. A window with a symbol createdautomatically by the tools pops up, referring to Figure 13.Figure 13. Symbol Generated AutomaticallyD.Observe the CIW output pane and note the messages stating Adding ‘CDFinformation ...’.3.2Editing SymbolYou can modify the symbol to have a more meaningful shape for easy recognition.A.Move your cursor over the symbol, until the entire green rectangle is highlighted. Clickleft to select it.B.Click Delete icon in the symbol window to delete the green rectangle.C.Select Create→Shape→Polygon. Follow the prompts at the bottom of the symbol, anddraw the triangle shown in Figure 14.D.Type “m” or click Move icon in the symbol window, move the pins to the finaldestination.E.Select [@partName], and use Edit→Properties→Object to change it to inverter asshown in Figure 14.Figure 14. Edit Object Properties FormF.Save your edited symbol view. The final symbol is shown in Figure 15.Figure 15. Symbol of inv3.3Building Test BenchTo test the inverter that you have just built, you need to create a test bench. This test bench will also be used during the post-layout simulation.Creating an inv_test schematic cellview with the below information, following the steps listed in Section 2 – SCHEMATIC ENTRY. The test bench is as shown in Figure 17.Library Name : testCell Name : inv_testView Name : schematicLibrary Name Cell Name Propertiestest inv_testanalogLib Vdc VDDanalogLib vpulse Referring to Figure 16analogLib gnd GNDanalogLib cap 1f FFigure 16. Vpulse FormFigure 17. Test Bench – inv_test for inv CircuitNote:There are wire names Vin and Vout in Figure 17. These can be created by clicking on Create Wire Name on the inv_test schematic window. Key in Vin Vout in the Names field of the Add Wire Name form, and then click Hide. Moving your mouse to the schematic window, click the wire where you want it to be named in the same sequence as typing the names in the Names field.4SIMULATING YOUR CIRCUITBefore starting the simulation, make sure that the schematic (inv_test) is open, then perform the following steps.4.1Start the Simulation EnvironmentIn your schematic window, select Launch →ADE L. The Analog Design Environment (ADE) window appears as shown in Figure 18.Figure 18. ADE Window4.2Selecting Project DirectoryIn the ADE window, select Setup→Simulator/ Directory/ Host. A Choosing Simulator form appears as Figure 19. In the Project Directory blank, type in /var/tmp/(desired folder name) to save your simulation files in the /var/tmp directory on the local server. Click OK to confirm.Figure 19. Choosing Simulator/Directory/Host FormAs each user account has a limited quota, this helps to conserve memory space in your account and prevents you from exceeding your account quota. However, note that contents in this folder is deleted periodically every 30 days automatically.4.3Setup Model LibraryIn the ADE window, select Setup Model Libraries. The Model Library setup form appears. Double click the column of section, and then click the down arrow to choose tt which is typical N and P model parameters. The model library setup for the inv_test circuit is shown in Figure 20. Click ok on the setup form to finish the settings.The information of models can be found in/app11/cg45nm/gpdk045_v4_0/docs/gpdk045_pdk_referenceManual.pdf.Figure 20. Model Library Setup for inv_test4.4Choosing the Desired AnalysisIn the ADE window, click the Choose Analyses icon . The Choosing Analyses form appears. Cadence ADE is able to run several types of simulations consecutively. You are then able to view the signals from different simulations at the same time. In this example, we will do transient analysis, so we shall setup transient analyses through the ADE as Figure 21.Figure 21. Setup for Transient Analyses4.5Setup VariablesThere is a variable, VDD, in the inv_test circuit. We need to set a value to it before starting simulation.In the ADE window, click Variables. Enter the name as the variable name VDD, then set the valueas 1.1, and finally click Ok. Please take note that 1.1v is the nominal voltage for this technology.Figure 22. Editing Design Variables4.6Saving Simulation DataThe simulation environment is configured to save all node voltages in the design by default. In larger designs, where saving all of the data requires too much disk space, you can select a specific set of node to save. Following steps show you how to select terminals to save.A.In the ADE window, select Outputs→Save All.B.The Keep Options form appears. Do not modify the form at this time. However, if youneed to save less data, under the first option “Select signals to output”, Click “selected”.4.7Saving Output for PlottingSelect the signals that you would like to observe.A.Select Outputs→To Be Plotted→Select On Design.B.Note that if you click on wires / nets, voltage signals are selected. If you click onconnection nodes, currents flowing through that note and into the component are saved.C.Follow the prompts at the bottom of the schematic window. Click on the output wireslabeled with Vout and Vin (select the wire that you want to monitor).D.Press Esc with your cursor in the schematic window when finished.Now you have set up the simulation environment which as shown in Figure 23. You can save the simulation state. This saves all the information such as the Model Path, outputs, analyses, environment options, and variables so that you do not need to set these parameters the next time again.Figure 23. ADE window with completed settingsIn the ADE window, select Session→Save State. Tick Cellview and then click OK. You can recall your settings by selecting Session→Load State.4.8Viewing the NetlistsSometimes, you need to view the netlist of your circuit or design. You can do so through the ADE, select Simulation→Netlist→Create / Display / Recreate.If there are any errors encountered during this step, check the messages in the CIW and retrace your steps to see that all data was entered properly.4.9Running the SimulationSelect Simulation→Netlist and Run to start the simulation or click on the Run Simulation icon in the Simulation Window. After the simulation is done, a waveform window will pop up showing the simulation results as Figure 24.Click on the waveform window to separate Vin and Vout.You can create a horizontal or vertical marker by clicking Marker on the waveform window. For example, creating a horizontal marker on Figure 24 with put Y Postion at 0.5*VDD=550mV, and then zoom in. The waveform window will look like Figure 25. Delays of the inverter could be found from the reading on the marker.Figure 24. Output of SimulationFigure 25. Waveform with Marker.Explore the icons on the toolbar as well as the various items on the menu. Try to add markers as that is something that will be used often during your simulations. You can also update the titles and labels on your plot to make them easy to read or more meaningful, if necessary.*Quick Tip : Shortcuts “a” and “b” to place a delta marker where you observe the difference between two points. What does shortcuts “v” and “h” do?There are many other functions available in the calculator tool, explore and play around with them.By now, you have finished pre-layout simulation (schematic level simulation). Next, you need to draw the layout of the inverter circuit and then do post-layout simulation to check your circuitperformance.5 PHYSICAL LAYOUTBy now, you should know how to create and simulate your circuit. Once the performance of your design is satisfactory, the next step in the process of making an integrated circuit chip is to create a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices.Before we get into the layout, first you need to understand the design rules for layout. Design rules give guidelines for generating layouts. They dictate spaces between wells, sizes of contacts, minimum spacing between a poly and a metal, and many other similar rules.Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. Note that the layout is very much process dependent, since every process has a certain fixed number of available masks for layout and fabrication.You may find more details on the Design Rules Manual (DRM):/app11/cg45nm/gpdk045_v_4_0/docs/gpdk045_drc.pdf5.1 Layout vs Symbol of CMOS DevicesIn this section, we look at only three devices: nmos1v and pmos1v. Check the process document, you can find the information for other devices.Figure 26 shows the nmos1v device. From layout view, you can see that the terminal B is the black background of the layout window.Figure 26. Layout vs Symbol of NMOSFigure 27 shows the pmos1v device, which looks similar to NMOS device but with P type implant (orange-stripe layer) and N-well (purple surrounding layer). G D SBFigure 27. Layout vs Symbol of PMOS5.2Starting Layout EditorNow we are going to create a new layout in the cell “inv” in “test” library.A.In Library Manager, select File→New→Cellview ... A Create New File form pops up.B.Select "test" as Library Name; enter "inv" as Cell Name, "layout" as View Name.C.Choose Open with Layout XL, and then click OK.Figure 28. Create Cellview – LayoutUseful layerselectionfeatureFigure 29. Layout WindowCell "inv" with "layout" view in library "test" will be created. It is opened up automatically, followed by inv schematic window, as shown in Figure 29. The layout editor contains two main sub-windows, namely the Layers sub-window on the left and Layout Editing window on the right. Notice the Layers sub-window on the left side of the layout view. This sub-window displays the fabrication layers defined in the technology. You can find the cross sectional profile in the process documents.Each layer is represented by a different color and pattern for easier differentiation. The black background on the right can be interpreted as the p-substrate of the wafer.To hide a layer, use the middle scroll button to click on a layer. To disable a layer from use, use the right mouse button.You might notice that some layer names appear more than once in the Layers sub-window. For example, Metal1 appears two times: one as Metal1 drawing, the other as Metal1 pin. Metal1 drawing is a layer with drawing purpose, and such layers with drawing purposes will be fabricated in the mask. The pin layers are symbolic layers and serve to indicate position of I/O pins and define net names. Such layers are not part of the mask layout and will not be fabricated.5.3ViasVias are used to connect between layers, much like those used in PCB design.There are different types of vias for different layer pairs. Normally a via is only for connecting two successive layers, e.g., Metal 1 and Metal 2. In case there is a metal jump between more than two layers, via stacking is required.In the layout window, click Create→Via or type “o” to bring up the via menu. Place the vias on the layout editing window, you can observe the layers that are involved in each type of via. Experiment with the different modes and configurations in the via menu to create arrays and stacks of vias as well. For example,A.Click on Create→Via, the Create Via window pops up as figure 30 shows.B.Choose M1_PO under Via Definition, and click on the layout window to place it andthen press Esc button to stop the placing. You can change the number of Rows and Columns on the Create Via form.C.To view the layers of M1_PO, click to select it first and then press Shift + f key. Observethe via appears different.D.To check the layers used in via M1_PO, select it and then click Edit→Hierarchy→Flatten as shown in figure 31. Click OK on the pop-up form shown in Figure 32.E.Now, you can separate the layers and check layers’ property to find out the layers’ name.Via M1_PO connects layers Metal 1 and Poly as shown in Figure 33.Try to explore different options (Rows, Columns, Stack, etc.) under via menu by yourself, this will be very helpful for layout drawing.Figure 30. Create Via windowsFigure 31. Edit ViaFigure 32. Flatten FormFigure 33. Via M1_POThe M1_PSUB and M1_NWELL contacts are substrate and n-well contacts that are used to connect the bulks of the NMOS and PMOS respectively. For the inverter circuit used in this manual, the bulks of the NMOS and PMOS need to be connected to ground (GND) and VDD respectively.5.4Changing the GridIn Figure 29, the black window on the right is the layout editing window. The position of the cursor in layout editing window is indicated by the coordinate showed on the top right corner of the window after X: and Y:. The unit here is "µm". Move your cursor around the editing window and see the X: Y: values change with step size 0.1. Change the step size to 0.005 as that is the minimum step size for this technology.From Layout Editing window pull down menu, select Options →Display... change "X Snap Spacing" and "Y Snap Spacing" to 0.005 then click on "OK". Now move the cursor around the editing window again, you will see the X: Y: values change with step size 0.005.There are raw grid and fine grid (as small dots) on the window background. If you cannot clearly see the raw grids, from pull down menu select Window →Zoom out by 2In addition to pull down menu and bind key "z", "Zoom Out" is also listed in the picture tool bar to the left of the window. Find it and try it out.Also you may use up, down, left, and right arrows to move around the design window. You will need to use "Zoom in" and "Zoom out" and those arrows many times throughout your design process. So it's not a bad idea to practice them a little bit now.To save and close the cell view, from Virtuoso Editing window, Select Design →Save.。

Cadence-使用参考手册

Cadence 使用参考手册邓海飞微电子学研究所设计室20XX7月目录概述11.1 Cadence概述11.2 ASIC设计流程1第一章Cadence 使用基础52.1 Cadence 软件的环境设置52.2 Cadence软件的启动方法102.3库文件的管理122.4文件格式的转化132.5 怎样使用在线帮助132.6 本手册的组成14第二章Verilog-XL 的介绍153. 1 环境设置153.2 Verilog-XL的启动153.3 Verilog－XL的界面173.4 Verilog-XL的使用示例183.5 Verilog-XL的有关帮助文件19第四章电路图设计与电路模拟214.1 电路图设计工具Composer (21)4.1.1 设置214.1.2 启动224.1.3 用户界面与使用方法224.1.4 使用示例244.1.5 相关在线帮助文档244.2 电路模拟工具Analog Artist (24)4.2.1 设置244.2.2 启动254.2.3 用户界面与使用方法254.2.5 相关在线帮助文档25第五章自动布局布线275.1 Cadence中的自动布局布线流程275.2 用AutoAbgen进行自动布局布线库设计28第六章版图设计与其验证306.1 版图设计大师Virtuoso Layout Editor (30)6.1.1 设置306.1.2 启动306.1.3 用户界面与使用方法316.1.4 使用示例316.1.5 相关在线帮助文档326.2 版图验证工具Dracula (32)6.2.1 Dracula使用介绍326.2.2 相关在线帮助文档33第七章skill语言程序设计347.1 skill语言概述347.2 skill语言的基本语法347.3 Skill语言的编程环境347.4面向工具的skill语言编程35附录1 技术文件与显示文件示例60附录2 Verilog-XL实例文件721．Test_memory.v (72)2．SRAM256X8.v (73)3．ram_sy1s_8052 (79)4．TSMC库文件84附录3 Dracula 命令文件359概述作为流行的EDA工具之一，Cadence一直以来都受到了广大EDA工程师的青睐。

cadence使用手册

cadence使⽤⼿册⽬录⼀．软件的安装 (3)⼆．Cadence 使⽤环境配置 (11)2.1 capture.ini 的替换 (11)2.2 CIS 环境的配置 (11)2.2.1 映射⽹络驱动器 (11)2.2.2 创建ODBC数据库 (11)2.2.3 软件中配置CIS (14)三．原理图符号创建⽅法 (16)3.1 创建单个元器件符号 (16)3.2 创建复合封装元器件 (19)3.3 ⽤电⼦表格新建元器件： (21) 3.4 ⼤器件的分割 (23)四．原理图的绘制 (25)4.1 新建⼯程⽂件 (25)4.2 原理图⼯作环境的设置 (26)4.2.1 当前⼯作图纸的设置 (26)4.2.2 设置图纸参数 (28)4.2.3 设计模板 (28)4.3 CIS Explorer 的使⽤ (29)4.4 元件管理（part manager） (31) 4.4.1 使⽤ (31)4.4.2 元件更新 (33)4.5 元器件属性查看 (33)五．原理图绘制的后续处理 (35)5.1 位号标注 (35)5.2 DRC检测 (37)5.3 ⽹表的⽣成： (41)5.4 BOM表的⽣成： (44)5.5 Back Annotate ⼯具的使⽤ (44)六． cadence 使⽤规范 (46)6.1. 新原理图封装⼊库流程 (46)6.2原理图符号创建规范 (47)6.2.1管脚分布与排列 (47)6.2.2管脚分布基本原则 (47)6.2.3 件符号命名规范&位号命名规范表 (47)6.3原理图设计规范： (49)6.3.1 基本规范 (49)6.3.2. 差分信号的命名 (49)6.3.3. 时钟信号的命名 (49)6.3.4. 电源信号的命名 (49)6.3.5 ⽂字的放置 (49)6.3.6. 去耦电容 (50)6.3.7. 连线 (50)6.3.8. 标注 (51)6.3.9. 串阻和⽹络命名 (51)6.3.10. 页端⼝符号 (52)6.3.11. 上下拉电阻 (53)6.3.12 总线 (53)6.3.13. 测试点 (53)6.4 原理图符号⼊库申请单填写规范 (53)6.4.1器件类型分类表 (57)6.5 物料编码申请单填写规范 (59)七．软件常见问题 (60)7.1 CIS配置卡死问题 (60)⼀．软件的安装开始安装allegro，\\10.8.106.205\⽆线集群⽂档服务器\交换⽬录\HW_CTRL\Cadence ⽬录下⾯有SPB_OrCAD 16.3 Release.iso镜像⽂件，可以将它拷到本地通过虚拟光驱打开也可以解压后运⾏set up出现下图选中进⾏安装，不要安装点击。

CADENCE仿真流程

CADENCE仿真流程第一章进行SI仿真的PCB板图的准备仿真前的准备工作主要包括以下几点：1、仿真板的准备●原理图设计；●PCB封装设计；●PCB板外型边框（Outline）设计，PCB板禁止布线区划分（Keepouts）；●输出网表（如果是用CADENCE的Concept HDL设计的原理图，可将网表直接Expot 到BRD文件中；如果是用PowerPCB设计的板图，转换到allegro中的板图，其操作见附录一的说明）；●器件预布局（Placement）：将其中的关键器件进行合理的预布局，主要涉及相对距离、抗干扰、散热、高频电路与低频电路、数字电路与模拟电路等方面；●PCB板布线分区（Rooms）：主要用来区分高频电路与低频电路、数字电路与模拟电路以及相对独立的电路。

元器件的布局以及电源和地线的处理将直接影响到电路性能和电磁兼容性能；2、器件模型的准备●收集器件的IBIS模型（网上下载、向代理申请、修改同类型器件的IBIS模型等）●收集器件的关键参数，如T co、Tsetup、Tholdup等及系统有关的时间参数T clock、Tskew、Tjitter●对IBIS模型进行整理、检查、纠错和验证。

3、确定需要仿真的电路部分，一般包括频率较高，负载较多，拓扑结构比较复杂（点到多点、多点到多点），时钟电路等关键信号线第二章IBIS模型的转化和加载CADENCE中的信号完整性仿真是建立在IBIS模型的基础上的，但又不是直接应用IBIS 模型，CADECE的软件自带一个将IBIS模型转换为自己可用的DML（Device Model Library）模型的功能模块，本章主要就IBIS模型的转换及加载进行讲解。

1、IBIS模型到DML模型的转换在Allegro窗口中选择Analyse\SI/EMI SIM\Library，打开“signal analyze library browser”窗口，在该窗口的右下方点击“Translate →”按钮，在出现的下拉菜单中选择“ibis2signois”项，出现“Select IBIS Source File”窗口（图1），选择想要进行转换的源IBIS文件，按下“打开”按钮，出现转换后文件名及路径设置窗口（缺省设置为和源IBIS文件同名并同路径放置，但此处文件名后缀为dml），设置后按下“保存”按钮，出现保存确定窗口（图2）,点击OK按钮即可，随后会出现一个“messages”窗口，该窗口中的报告文件说明在模型转换过程中出现的问题，对其中的“warning”可不用在意，但如果出现“error”则必须进行修改后重新进行模型格式转化直到没有“error”出现为止，此时转换得到的dml文件才是有效的。

Cadence_电原理图输入简易使用手册

Cadence 电路编辑简易使用手册东南大学IC学院实验室2005年11月前言作为流行的EDA工具之一，Cadence一直以来都受到了广大EDA工程师的青睐。

然而Cadence的使用之繁琐，又给广大初学者带来了不少麻烦。

本册子的本意在于为初学者指路，故不会对个别工具进行很详细的介绍，只是对初学者可能经常使用的一些工具加以粗略的介绍。

IC学院实验室工作站安装有Xmanager，本手册将从Xmanager的启动开始介绍。

一、从客户端Xmanger登陆UNIX服务器1、从“开始”—“所有程序”—“Xmanager”—“Xbrowser”，客户端程序找到实验室装载有CANDANCE工具包的Sun－B2500服务器，如图1－1所示：图1－12、双击“Sun－B2500”，显示服务器登陆窗口图1－2，输入网管给你的帐号，确认后出现图1－3，输入密码，并确认（注意：你输入密码时，对话框中不显示任何信息）。

图1－2图1－3如果你输入的帐号密码正确，经过服务器确认后，你就远程登陆到服务器上了（显示图1－4）。

图1－4二、启动Candence在屏幕空白处点击鼠标右键并如图2－1选择“hosts”—“Terminal Console”；图2－1出现Console对话窗口图2－2，图2－2输入icfb&并回车就运行Candence了；运行Candence后就会出现CIW窗口，图2－3；图2－3三、库文件的管理3.1建立自己的工作库启动了Cadence后，就可以利用File菜单建立自己的工作库，点击CIW窗口上的File 菜单，选定其中的New lib项，弹出如图3－1所示的对话框；图3－1输入库名并选择相应的工艺库，然后选择ok,这时在CIW的显示区会出现如下提示：Created library "mylib" as "/space/home/zch/mylib"!3.2在库中生成自己所需的单元新建的库是一个空的库，里面什么也没有，用户可在库中生成自己所需的单元。

cadence 实验手册

Virtuoso Analog Design Environment中文实验手册Version 5.1.41虚拟机：操作平台：Linux AS5 软件版本：IC 5141 实验模块：ADE编译：06级-程涛目录实验一、熟悉Virtuoso Analog Design Environment (1)实验二、Schematic Entry (5)实验三、模拟仿真 (12)实验四、显示仿真结果 (21)实验五、仿真结果分析 (30)实验六、参数分析 (42)实验七、使用OCEAN 和SKILL语言（略） (45)实验八、使用Corner分析工具 (46)实验九、Monte Carlo 分析 (49)实验十、优化分析 (58)实验十一、Component Description Format（CDF）参数 (63)实验十二、Macromodels、Subcircuits和Inline Subcircuits (67)实验十三、例化设计 (73)实验十四、继承连接 (76)实验一、熟悉Virtuoso Analog Design Environment实验步骤：一、登录Linux操作系统，用安装软件的用户登录，最好不要用root用户。

二、打开Linux的终端，进入软件所在文件夹，比如我的是/home/chengtao/adelabic5，输入cd /home/chengtao/adelabic5，即可进入，注意在安装时有一个lnx86.cshrc的文件，在每次进入Cadence之前都应该先运行以下命令：source lnx86.cshrc ，然后再终端中输入icms & ，稍等片刻，即可进入Cadence 图形界面CIW，如下图所示（会弹出一个Cadence的介绍窗口，关闭即可）。

三、打开一个尖峰检测电路。

1、选择Tool下的Library Manager ，即可弹出Library Manager对话框，总共有三栏分别为：Library、Cell、View，只有在Library下有目录，另外两个是空的，点traning，在Cell下便会显示很多目录，我们选择点击peakTestv，在View下会出现一个schematic,双击便会弹出一个对话框，如下图所示：2、选中peakDetectv ，peakDetectv会被白色的正方形线包围，然后依次执行Design—Hierarchy—Descend Edit （可以使用快捷键E），会蹦出一个小对话框，在View Name中选择schematic，点击Ok，则会弹出一个电路图，如下图所示：3、用鼠标选中一个Ampv，按下E键，将ViewName设置为Veriloga，点击OK，即可弹出这个器件的Verilog-a语言描述，可以仔细参考一下，先不要关闭。

Candence部分简单操作说明

Candence部分简单操作说明Candence操作说明之单位转换Setup->Design Parameters->Design如图1；mil为英制单位，millimeter为公制单位毫米（1mil=0.0254mm）。

精度选择Accuracy，mm时应选择最高的4位。

图1.单位选择图2.精度选择Candence操作说明之测量距离Display->Measure然后勾选侧边Find菜单栏的相应类别，然后点击两个需要测量的元素。

Find 菜单栏如图3，其中shape表示封闭图形类；Pin表示器件引脚焊盘类；Via表示过孔类，Text 表示文字类；Cline segs表示PCB走线类；other segs表示除走线外其他线；Figures表示图片类。

图3.Find菜单图4.测量显示测量显示说明：如图4中两个小白色框即鼠标点击的需要测量距离的两元素，本例测量的是走线与焊盘的距离。

Dist表示单击两点直线的距离；Manhattan Dist 表示曼哈顿距离，Dx表示X轴的绝对距离，Dy表示YX轴的绝对距离；Pick Angle表示两点夹角；Air Gap表示所选两元素轮廓最近距离。

Candence操作说明之坐标查看Display->Element然后单击所要查看的元素，显示如图5本例中Find栏选择的是Pin（器件引脚焊盘）。

选择Find栏见图6参考距离测量部分的，其中Symbols表示封装类；Nets表示网络类，Clines表示PCB走线类；Lines表示除了走线外的其他线类。

图5.坐标查看图6.Find选择Candence操作说明之坐标文件导出File->Export->Placement.. ,然后选择导出的路径以及文件名，如图7，；再选择Placement Origin选择以何种方式的圆心：其中Symbol Origin 绘制封装时设定封装圆心；Body Center器件圆心；Pin 1以1脚为圆心。

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Candence使用手册_仿真分册前言PCB仿真Cadence软件是我们公司统一使用的原理图设计、PCB设计、高速仿真的EDA工具。

进行仿真工作需要有很多方面的知识，须对高速设计的理论有较全面的认识，并对具体的单板原理有一定的了解，还需具备仿真库的相关知识等。

在这个分册中仅对仿真软件的使用进行较详细的阐述，还介绍高速设计的一些相关理论，仿真过程是基于Allegro SPB 15.7的PCB SI模块进行的。

其他知识，如仿真库的知识、约束管理器等请参阅专门的使用手册。

在此非常感谢网络南研 EDA和本部 EDA对此手册的支持。

第一章高速设计与PCB仿真流程本章介绍高速PCB仿真设计的基础知识和重要意义，并介绍基于Cadence 的Allegro SPB15.7的PCB仿真流程。

1.1高速信号与高速设计随着通信系统中逻辑及系统时钟频率的迅速提高和信号边沿不断变陡，PCB的走线和板层特性对系统电气性能的影响也越发显著。

对于低频设计,走线和板层的影响要求不高甚至可以完全忽略不计。

当频率超过 50MHz时，PCB走线则必须以传输线考虑，而在评定系统性能时也必须考虑 PCB 板材的电参数影响。

当系统时钟频率达到120MHz及更高时，就只能使用高速电路设计方法，否则基于传统方法设计的PCB将无法工作。

因此，高速电路设计技术已经成为电子系统设计师必须采取的设计手段，只有通过使用高速电路设计师的设计技术，才能实现设计过程的可控性。

高速系统的设计必须面对互连延迟引起的时序问题以及串扰、传输线效应等信号完整性问题。

实际上，信号边沿的谐波频率比信号本身的频率高，是信号快速变化的上升沿与下降沿（或称信号的跳变）引发了信号传输的非预期结果。

因此，通常约定如果线传播延时大于1/2数字信号驱动端的上升时间，则认为此类信号是高速信号并产生传输线效应，见图1－1所示。

信号的传递发生在信号状态改变的瞬间，如上升或下降时间。

信号从驱动端到接收端经过一段固定的延迟时间，如果传输延迟时间小于1/2的上升或下降时间，那么来自接收端的反射信号将在信号改变状态之前到达驱动端。

反之，反射信号将在信号改变状态之后到达驱动端，如果反射信号很强，叠加的波形就有可能会改变逻辑状态。

图1－1 传输线效应1.1.1高速信号的确定上面我们定义了传输线效应发生的前提条件，但是如何得知线延时是否大于1/2驱动端的信号上升时间呢？一般地，信号上升时间的典型值可通过器件手册给出，而信号的传播时间在PCB设计中由实际布线长度决定。

图1－2为信号上升时间和允许的布线长度(延时)的对应关系。

PCB 板上每单位英寸的延时为0.167ns.。

但是，如果过孔多，器件管脚多，网线上设置的约束多，延时将增大。

通常高速逻辑器件的信号上升时间大约为0.2ns。

如果板上有GaAs芯片，则最大布线长度为7.62mm。

图1－2 信号上升时间与允许布线长度的对应关系设Tr为信号上升时间，Tpd 为信号线传播延时(见图1－3)。

如果Tr≥4Tpd，信号落在安全区域。

如果2Tpd≤Tr≤4Tpd，信号落在不确定区域。

如果Tr≤2Tpd，信号落在问题区域。

对于落在不确定区域及问题区域的信号，应该使用高速布线方法。

图1－3 信号传播线延时与上升时间的关系1.1.2 边缘速率引发高速问题EDA设计工程师发现SI问题的起因不仅仅是高速设计。

真正的原因不是系统时钟速率的提高，而是驱动器上升和下降时间的缩短。

随着芯片制造工艺技术的进步及IC制造商转向采用0.25微米或更小工艺，他们所生产的标准元件的裸片尺寸越来越小；边缘速率越来越快，最终会导致PCB 设计中高速问题的产生，而传统的高速分析是不考虑这类问题的。

此外，当IC制造商转向可在更小面积上封装更多功能的高密度器件时，需要开发新型的封装技术。

现在，BGA、CSP和MCM等封装技术都可根据设计要求，在小型封装内提供更多的引脚和更少的封装寄生参数。

尽管这些新型器件体积极小，但它们也有其自身的问题。

例如，互连线较长。

即便不考虑系统时钟速率，高的上升时间和更长的走线长度也让电路板设计工程师面临着严峻的挑战。

只要传输线长度引起的延迟超过驱动器上升/下降时间有效长度的六分之一，就会引起传输线问题。

例如，若上升时间为1 ns，走线边缘速率为每英寸2ns，只要走线长度超过1英寸，就会发生传输线问题。

众所周知，走线长度小于1英寸的电路板极为少见。

因此，采用上升时间为1ns的设计肯定会出现高速设计问题。

随着新型IC工艺的出现，情况会变得越来越糟。

因为上升时间将很快发展到1ns以下。

实际上，大约每隔三年晶体管门长度就会缩短，而其相应的开关速率会增长约30%。

SI问题的表现方式很多。

当边缘速率上升时，时序问题首先暴露出来。

传输线效应造成的阻尼振荡(Ringing)、正尖峰(overshoot)和负尖峰(undershoot)有可能超过规定的噪音容限。

在低速系统中，互连延迟和阻尼振荡可以忽略不计，因为在这种系统中信号有足够的时间达到稳定。

但是当边缘速率加快，系统时钟速率上升时，信号在器件之间的传输时间以及同步准备时间都缩短了。

当边缘速率低于1ns时，串扰问题也出现了。

通常串扰问题出现在高边缘速率、高密度的电路板上，其成因是走线之间的耦合。

亚纳秒级边缘速率会引起高频谐振，很容易耦合到邻近的互连线中，从而造成串扰，拥有大量高速互连的电路板特别容易产生此类问题。

当高速器件的边缘速率低于0.5ns时，电源系统稳定性和EMI等问题也随之产生。

来自大容量数据总线的数据交换速率特别快，当它在电源层中产生足以影响信号的强波纹时，就会产生电源稳定性问题。

高速信号也可能产生辐射，EMI因而也成为要关注的另一个设计问题。

1.1.3 传输线效应PCB板上的走线可等效为下图所示的串联和并联的电容、电阻和电感结构。

串联电阻的典型值0.25-0.55 ohms/foot，因为绝缘层的缘故，并联电阻阻值通常很高。

将寄生电阻、电容和电感加到实际的PCB连线中之后，连线上的最终阻抗称为特征阻抗Zo。

线径越宽，距电源/地越近，或隔离层的介电常数越高，特征阻抗就越小。

如果传输线和接收端的阻抗不匹配，那么输出的电流信号和信号最终的稳定状态将不同，这就引起信号在接收端产生反射，这个反射信号将传回信号发射端并再次反射回来。

随着能量的减弱反射信号的幅度将减小，直到信号的电压和电流达到稳定。

这种效应被称为振荡，信号的振荡在信号的上升沿和下降沿经常可以看到。

注：关于传输线的等效电路请参照电气篇中的―相关计算‖。

图1－４传输线的等效电路基于上述定义的传输线模型，归纳起来，传输线会对整个电路设计带来以下效应。

反射信号Reflected signals延时和时序错误Delay & Timing errors多次跨越逻辑电平门限错误False Switching过冲与下冲Overshoot/Undershoot串扰Induced Noise (or crosstalk)电磁辐射EMI radiation反射信号Reflected signals如果一根走线没有被正确终结(终端匹配)，那么来自于驱动端的信号脉冲在接收端被反射，从而引发不预期效应，使信号轮廓失真。

当失真变形非常显著时可导致多种错误，引起设计失败。

同时，失真变形的信号对噪声的敏感性增加了，也会引起设计失败。

如果上述情况没有被足够考虑，EMI将显著增加，这就不单单影响自身设计结果，还会造成整个系统的失败。

反射信号产生的主要原因：过长的走线；未被匹配终结的传输线，过量电容或电感以及阻抗失配。

图 1－5 反射信号延时和时序错误 Delay & Timing errors：信号延时和时序错误表现为：信号在逻辑电平的高低门限之间变化时保持一段时间信号不跳变，过多的信号延时可能导致时序错误和器件功能的混乱。

通常在有多个接收端时会出现问题，电路设计师必须确定最坏情况下的时间延时以确保设计的正确性。

信号延时产生的原因：驱动过载，走线过长。

图1－６信号延时错误多次跨越逻辑电平门限错误 False Switching：信号在跳变的过程中可能多次跨越逻辑电平门限从而导致这一类型的错误。

多次跨越逻辑电平门限错误是信号振荡的一种特殊的形式，即信号的振荡发生在逻辑电平门限附近，多次跨越逻辑电平门限会导致逻辑功能紊乱。

反射信号产生的原因：过长的走线，未被终结的传输线，过量电容或电感以及阻抗失配。

图1－７逻辑开关错误翻转过冲 Overshoot/Undershoot：过冲来源于走线过长或者信号变化太快两方面的原因。

虽然大多数元件接收端有输入保护二极管保护，但有时这些过冲电平会远远超过元件电源电压范围，损坏元器件。

图1－８信号的上冲与下冲串扰 Induced Noise (or crosstalk) ：串扰表现为在一根信号线上有信号通过时，在PCB板上与之相邻的信号线上就会感应出相关的信号，我们称之为串扰。

信号线距离地线越近，线间距越大，产生的串扰信号越小。

异步信号和时钟信号更容易产生串扰。

因此消除串扰的方法是移开发生串扰的信号或屏蔽被严重干扰的信号。

电磁辐射 EMI radiation ：EMI(Electro-Magnetic Interference)即电磁干扰，产生的问题包含本身产生过量的电磁辐射及受周围电磁辐射干扰两方面。

EMI表现为当数字系统加电运行时，会对周围环境辐射电磁波，从而干扰周围环境中电子设备的正常工作；或者是对周围电磁干扰过于敏感。

1.2 高速PCB仿真的重要意义1.2.1板级 SI仿真的重要意义过去，PCB性能要采用一系列仪器测试电路板原型(通常接近成品)来评定。

电路的复杂性增加之后，多层板和高密度电路板出现了，人们开始用自动布线工具来处理日益复杂的元器件之间的互联。

此后，电路的工作速度不断提高，功能不断翻新，元器件之间连线的物理尺寸和电路板的电特性日益受到关注。

从根本上讲，市场是电路板级仿真的强劲动力。

在激烈竞争的电子行业，快速地将产品投入市场至关重要，传统的PCB设计方法要先设计原理图，然后放置元器件和走线，最后采用一系列原型机反复验证/测试。

修改设计意味着时间上的延迟，这种延迟在产品快速面市的压力下是不能接受的。

图1－9 PCB设计流程比较“第一时间推出产品”的设计目标不只是一句广告词，事实上，这是生死攸关的竞争需要。

在产品设计初期识别、预防和改正设计错误，可以防止电路板出错，这种操作模式比以往任何时候都至关重要，PCB仿真就是最好的方法之一。

板级仿真工具的作用就是在电路板制造前后帮助设计人员更快地开展调试工作。

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