异步FIFO Verilog源代码

end
assign raddr_next = raddr + (rd_en && !empty);
assign raddr_next_gray = (raddr_next>>1)^raddr_next;
assign waddr_gray = (waddr>>1)^waddr;
always @ (posedge rd_clk or posedge rst)
end
end
//写地址下一个值与读地址相等时为满
always @ (posedge wr_clk or posedge rst)
begin
if (rst)
full <= 1'b0;
else if (empty)
full <= 1'b0;
else
full <= (waddr_next_gray==raddr_gray_d2);
begin
if (rst)
begin
raddr_gray_d1 <= 'd0;
raddr_gray_d2 <= 'd0;
end
else
begin
raddr_gray_d1 <= raddr_gray;
raddr_gray_d2 <= raddr_gray_d1;
//----------------------------------------------------------------------------
//Module: async_fifo
//Autห้องสมุดไป่ตู้or:
//Description:
//----------------------------------------------------------------------------
reg [WIDTH-1:0] mem[0:2**DEPTH-1];
reg [DEPTH-1:0] raddr;
reg [DEPTH-1:0] waddr;
wire[DEPTH-1:0] raddr_next;
wire[DEPTH-1:0] raddr_next_gray;
wire[DEPTH-1:0] waddr_gray;
begin
if (rst)
waddr <= 'd0;
else if (wr_en && !full)
waddr <= waddr + 1'd1;
else;
end
always @ (posedge wr_clk)
begin
if (wr_en && !full)
mem[waddr] <= din;
end
end
endmodule
module async_fifo
#(
parameter WIDTH = 16,
parameter DEPTH = 3
)
(
input wire rst,
input wire wr_clk,
input wire wr_en,
input wire[WIDTH-1:0] din,
end
assign waddr_next = waddr + (wr_en && !full);
assign waddr_next_gray = (waddr_next>>1)^waddr_next;
assign raddr_gray = (raddr>>1)^raddr;
always @ (posedge wr_clk or posedge rst)
//Version Modified Data
//1.0 Draft 2015.01.29
//----------------------------------------------------------------------------
input wire rd_clk,
input wire rd_en,
output reg valid,
output reg [WIDTH-1:0] dout,
output reg empty,
output reg full
);
(* RAM_STYLE="BLOCK" *)
else if (rd_en && !empty)
raddr <= raddr + 1'd1;
else;
end
always @ (posedge rd_clk or posedge rst)
begin
if (rst)
valid <= 1'b0;
else
valid <= (rd_en && !empty);
reg [DEPTH-1:0] waddr_gray_d1;
reg [DEPTH-1:0] waddr_gray_d2;
wire[DEPTH-1:0] waddr_next;
wire[DEPTH-1:0] waddr_next_gray;
wire[DEPTH-1:0] raddr_gray;
begin
if (rst)
begin
waddr_gray_d1 <= 'd0;
waddr_gray_d2 <= 'd0;
end
else
begin
waddr_gray_d1 <= waddr_gray;
waddr_gray_d2 <= waddr_gray_d1;
end
always @ (posedge rd_clk or posedge rst)
begin
if (rst)
dout <= 'b0;
else if (rd_en && !empty)
dout <= mem[raddr];
else;
end
always @ (posedge wr_clk or posedge rst)
reg [DEPTH-1:0] raddr_gray_d1;
reg [DEPTH-1:0] raddr_gray_d2;
//双口RAM实现读写数据
always @ (posedge rd_clk or posedge rst)
begin
if (rst)
raddr <= 'd0;
else;
end
//读地址下一个值与写地址相等时为空
always @ (posedge rd_clk or posedge rst)
begin
if (rst)
empty <= 1'b1;
else if (full)
empty <= 1'b0;
else
empty <= (raddr_next_gray==waddr_gray_d2);