51单片机AT89C52中文资料

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AT89C52中英译文

AT89S52主要性能·与MCS-51单片机产品兼容·8K字节在系统可编程Flash存储器·1000次擦写周期·全静态操作：0Hz～33Hz·三级加密程序存储器·32个可编程I/O口线·三个16位定时器/计数器·八个中断源·全双工UART串行通道·低功耗空闲和掉电模式·掉电后中断可唤醒·看门狗定时器·双数据指针·掉电标识符功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。

使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。

片上Flash允许程序存储器在系统可编程，亦适于常规编程器。

在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。

AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2 个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。

另外，AT89S52 可降至0Hz 静态逻辑操作，支持2种软件可选择节电模式。

空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。

掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。

引脚结构8 位微控制器8K 字节在系统可编程Flash引脚描述VCC : 电源GND: 地P0 口：P0口是一个8位漏极开路的双向I/O口。

作为输出口，每位能驱动8个TTL逻辑电平。

对P0端口写“1”时，引脚用作高阻抗输入。

当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。

在这种模式下，P0具有内部上拉电阻。

at89c52单片机简介中英文对照外文翻译文献

at89c52单片机简介中英文对照外文翻译文献中英文资料对照外文翻译A T89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。

Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。

Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。

51单片机AT89C52中文资料

51单片机AT89C52中文资料--------------------------------------------------------------------------------51单片机AT89C52中文资料AT89C52 ATMEL公司生产的低电压，高性能CMOS 8位单片机．片内含8K byTES的可反复擦写的只读程序存储器（PEROM）和256 byTES 。

的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，与标准MCS-51指令系统及8052 产品引脚兼容，片内置通用8位中央处理器（CPU ）和FLASH由存储单元，功能强大AT89C52单片适用于许多较为复杂控制应用场合。

主要性能参数：与Mcs-51产品指令和引脚完全兼容。

8字节可重擦写FLASH闪速存储器1000 次擦写周期全静态操作：0HZ-24MHZ三级加密程序存储器256X8字节内部RAM32个可编程I/0口线3个16 位定时／计数器8个中断源可编程串行UART通道低功耗空闲和掉电模式内部结构图AT89C52内部框图功能特性：AT89C52 提供以下标准功能：8字节FLASH闪速存储器，256字竹内部RAM , 32个I/O口线，3个16 位定时／计数器，一个6向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。

同时，AT89c52可降至OHz的静态逻辑操作，并支持两种软件可选的节电上作模式。

空闲方式停止CPU 的工作，但允许RAM，定时／计数器．串行通信口及中断系统继续工作。

掉电方式保存RAM 中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位.功能引脚说明：Vcc:电源电压GND:地P0：P0口是一组8位漏极开路型双向1/O 口，也即地址/数据总线复用口。

作为输出口用时．每位能吸收电流的方式驱动8个TTL 逻辑门电路，对端口P0 写“1”时，可作为高阻抗输入端用。

AT89C52中文资料

AT89C52中文资料AT89C52的中文资料AT89C52是美国Atmel公司生产的低电压、高性能CMOS 8位单片机，片内含8KB的可反复檫写的程序存储器和12B的随机存取数据存储器（RAM），器件采用Atmel公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内配置通用8位中央处理器（CPU）和Flash存储单元，功能强大的AT89C52单片机可灵活应用于各种控制领域。

AT89C52单片机属于AT89C51单片机的增强型，与Intel 公司的80C52在引脚排列、硬件组成、工作特点和指令系统等方面兼容。

其主要工作特性是：片内程序存储器内含8KB的Flash程序存储器，可擦写寿命为1000次；片内数据存储器内含256字节的RAM；具有32根可编程I/O口线；具有3个可编程定时器；中断系统是具有8个中断源、6个中断矢量、2个级优先权的中断结构；串行口是具有一个全双工的可编程串行通信口；具有一个数据指针DPTR；低功耗工作模式有空闲模式和掉电模式；具有可编程的3级程序锁定位；AT89C52工作电源电压为5（1+0.2）V，且典型值为5V；AT89C52最高工作频率为24MHz。

单片机正常工作时，都需要有一个时钟电路和一个复位电路。

本设计中选择了内部时钟方式和按键电平复位电路，来构成单片机的最小电路。

如图3.1所示。

功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。

使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。

片上Flash允许程序存储器在系统可编程，亦适于常规编程器。

在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。

AT89C52单片机资料手册

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at89c52

AT89C52概述AT89C52是一款高性能的8位单片机，由Atmel公司生产。

它是AT89系列单片机中的一员，采用MCS-51指令集架构，并使用快速闪存储存程序。

AT89C52具有丰富的外设，包括多个输入输出引脚、计时器、串口通信接口等，广泛应用于嵌入式系统、通信设备、工业控制等领域。

主要特性•采用CMOS技术，工作电压范围广泛（2.4V至5.5V）•具有8KB的内部闪存，用于存储程序和数据•提供256字节的内部RAM，可用于数据存储•包含三个计时器/计数器，可用于定时/计数功能•集成两个串口通信接口，方便与外部设备进行数据交互•支持多种中断方式，提供更好的系统响应能力•可编程输入/输出引脚，可用于连接外部设备引脚描述AT89C52具有40个引脚，以下是一些重要引脚的描述：1.P1.0至P1.7: 8位并行输入/输出引脚，可根据需要进行配置。

在配置为输入时，可以连接外部设备并读取输入值；在配置为输出时，可以向外部设备发送数据。

2.P2.0至P2.7: 8位并行输入/输出引脚，也可以根据需要进行配置。

3.P3.0至P3.7: 8位并行输入/输出引脚，同时具有更多功能，包括与外部存储器的数据和地址传输，以及与LCD显示器的连接等。

4.RST: 复位引脚，将其拉低时可以重启单片机。

5.EA/VPP: 外部访问使能/编程电压引脚，可用于提供外部程序存储器的访问或编程电压。

6.XTAL1/XTAL2: 外部晶振引脚，接入适当的晶振电路以提供时钟信号。

闪存编程AT89C52的程序存储在内部闪存中。

要编程AT89C52，可以使用专用的编程器，通过并行端口或串行端口将目标程序下载到芯片中。

编程AT89C52的一般步骤如下：1.选择所需的编程器，并连接到AT89C52的编程接口。

2.打开编程器软件，并选择正确的单片机型号。

3.导入目标程序文件，该文件应该是以二进制格式存储的。

4.配置编程器选项，包括芯片复位方式、编程电压等。

AT89C52单片机介绍

AT89C52单片机介绍
AT89C52是Atmel公司生产的一款经典的8位单片机。

它采用MCS-51系列内核，具有高性能、低功耗和强大的外设功能。

AT89C52是AT89C51的改进版本，具有更高的运行速度和更大的存储空间。

首先，AT89C52采用了高性能的CMOS技术，工作频率高达40MHz，可以实现高效的数据处理和实时控制。

与普通的单片机相比，它具有更快的响应速度和更高的运算能力，可以满足复杂控制系统的要求。

其次，AT89C52具有8KB的内部闪存程序存储器，可以存储用户编写的程序代码。

它还具有256字节的RAM内存和128个IO口，可用于连接各种外部设备和传感器。

此外，AT89C52还支持多种通信接口，如UART、SPI和I2C，方便与其他设备进行数据交换和通信。

此外，AT89C52还具有丰富的开发资源和工具支持。

Atmel公司提供了一套完整的开发套件，包括编译器、调试器和仿真器等，为用户提供方便和高效的开发环境。

并且，AT89C52的软件编程接口也非常友好，可以使用C语言或汇编语言进行编程，灵活性很高。

总之，AT89C52是一款功能强大、性能稳定的8位单片机。

它具有高速运算能力、丰富的外设功能和灵活的IO口控制。

它可以广泛应用于各种控制系统、仪器仪表、家电和智能设备等领域。

同时，它的开发环境和编程接口也很友好，为用户提供了方便和高效的开发工具。

AT89C52单片机简介

AT89C52单片机简介AT89C52是___生产的51系列单片机之一。

它是一个低电压、高性能的CMOS8位单片机，内置8kbytes可反复擦写的Flash只读程序存储器和256bytes的随机存取数据存储器（RAM）。

该器件采用高密度、非易失性存储技术生产，兼容标准MCS-51指令系统。

AT89C52单片机功能强大，适用于许多较复杂的系统控制应用场合。

该单片机有40个引脚，其中32个是外部双向输入/输出（I/O）端口。

此外，它还内含2个外中断口，3个16位可编程定时计数器，2个全双工串行通信口和2个读写口线。

AT89C52可以按照常规方法进行编程，但不支持在线编程（只有S系列的单片机支持在线编程）。

AT89C52将通用的微处理器和Flash存储器结合在一起，特别是可反复擦写的Flash存储器可有效地降低开发成本。

该单片机兼容MCS51指令系统，具有以下特点：8k可反复擦写（>1000次）FlashROM32个双向I/O口256x8bit内部RAM3个16位可编程定时/计数器中断时钟频率0-24MHz2个串行中断可编程UART串行通道2个外部中断源，共6个中断源2个读写中断口线3级加密位低功耗空闲和掉电模式软件设置睡眠和唤醒功能P2口是一个8位双向I/O口，带有内部上拉电阻。

它的输出缓冲级可以驱动4个TTL逻辑门电路。

当对P2口写入“1”时，内部上拉电阻会将端口拉高，使其可以作为输入口。

当被外部信号拉低时，由于存在上拉电阻，会输出一个电流(IIL)。

在访问外部程序存储器或16位地址的外部数据存储器时，P2口会输出高8位地址数据。

而在访问8位地址的外部数据存储器时，P2口会输出P2锁存器的内容。

此外，P2口还会接收高位地址和一些控制信号，用于Flash编程或校验。

P3口也是一个带有内部上拉电阻的8位双向I/O口。

它的输出缓冲级可以驱动4个TTL逻辑门电路。

当对P3口写入“1”时，内部上拉电阻会将端口拉高，使其可以作为输入端口。

单片机89C52中英文对照翻译(经典版)

AT89C52 internal structure analysis DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8Kbytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM contentsbut freezes the oscillator, disabling all other chip functions until the next interruptor hardware reset.Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, eachpin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the following table.Port 1 also receives the low-order address bytes duringFlash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses toexternal data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to externalprogram memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000Hup to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate er software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers:Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each ofthe six interrupt sources in the IP register.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed toexternal memory.On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space.For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 cont ains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirectaddressing, so the upper 128 bytes of data RAM are availableas stack space.Watchdog Timer(One-time Enabled with Reset-out)The WDT is intended as a recovery method in situationswhere the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive anoutput RESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow.The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior toentering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether theWDT continues tocount if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (). From the home page, select ‘Products’,then ‘8051-Architecture Flash Microcontroller’, then‘Product Overview’.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in the AT89C51 and AT89C52. Forfurther information on the timers’ operation, refer to the ATMEL Web site (). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samplesshow a high in one cycle and a low in the next cycle, thecount is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Sin ce two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency.To ensure that a given level is sampled at least once before it changes, the level should be held for at leastone full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 6. In thismode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.译文：89C52的内部结构分析功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。

中英文翻译 AT89C52 单片机

AT89C2051AT89C2051 Reference Manual AT89C2051 is made in the ATMEL Corporation, which is the low-voltage, high-performance CMOS8-bit microcontroller.Tablets containing repeated 2k bytes of program memory erasable read-only (PEROM) and random 128bytes data memory (RAM), device using ATMEL's high density, non-volatile memory technology, Compatible with the standard of MCS-51 instruction set, built-chip 8-bit general-purpose central processing unit and repeatedly write the Flash memory, which can effectively reduce the development costs. AT89C2051 features a powerful single-chip can provide cost-effective in many Applications.AT89C2051 MCU MCU is a series of 51 members, is the 8051 version of SCM. Internal comes with a programmable EPROM 2 k bytes of high-performance microcontrollers. With the industry standard MCS-51 orders and pin-compatible, so it is a powerful micro-controllers, many embedded control applications, it provides a highly flexible and effective solutions. AT89C2051 has the following characteristics: 2 k bytes EPROM, 128 bytes RAM, 15 I / O lines, two 16 regular / counter, two five vector interrupt structure, a full two-way serial port, and includes Precision analog comparator and on-chip oscillator, a 4.25 V to 5.5 V voltage scope of work and 12 MHz/24MHz frequency, and also offers the encryption array of two program memory locking, power-down and the clock circuit. In addition, AT89C2051 also supports two kinds of software-selectable power-saving mode power supply. During my free time, CPU stop and let RAM, timing / counter, serial port and interrupt system to continue to work. Power-down can preserve the contents of RAM, but will stop oscillator chip-to prohibit all the other functions until the next hardware reset.AT89C2051 have two 16 time / counter register Timer0t Timer1. As a timer, each machine cycle register an increase, such registers to counting machine cycle. Because a machine cycle is 12 oscillator cycles, the count rate is the frequency oscillator 1 / 12. As a counter, the register in the corresponding external input pin P3.4/T0 and P3.5/T1 emerged from the 1-0 when the changes by 1. Two machine cycle because of the need to identify a 1-0 change, the largest count rate is the frequency oscillator 1 / 24, the external input P3.2/INT0 and P3.3/INT1 programming, for Measuring the pulse width of the door.Therefore, AT89C2051 constitute the SCM system is a simple structure, the costof the cheapest, most efficient micro-control system, eliminating the external RAM, ROM and interface devices, reducing hardware costs, cost savings, improved The cost-effective system.Clock circuitMCU clock signal used to provide various micro-chip microcontroller operation of the benchmark time, the clock signal is usually used by the form of two circuits: the internal and external shocks oscillation. MCS-51 has a microcontroller internal oscillator for a reverse of the high-gain amplifier, pin XTALl and XTAL2 are here to enlarge the electrical inputs and outputs, as in-house approach, a simple circuit, from the clock Signal relatively stable, and actually used often in this way, as shown in Figure 3-1 in its external crystal oscillator (crystal) or ceramic resonator constituted an internal oscillation, on-chip high-gain amplifier and a reverse Feedback components of the chip quartz crystal or ceramic resonator together to form a self oscillator and generate oscillation clock pulse. Figure 3-1 in the external crystal and capacitors C1 and C2 constitute a parallel resonant circuits, their stability from the oscillation frequency, rapid start-up role, and its value are about 33 PF, crystal frequency of elections 12 MHz.Reset CircuitIn order to initialize the internal MCU some special function register to be reset by the way, will reset after the CPU and system components identified in the initial state, and from the initial state began work properly. MCU is reset on the circuit to achieve, in the normal operation of circumstances, as long as the RST-pin on a two machine cycle time over the high, can cause system reset, but if sustained for the RST-pin HIGH, in a circle on the MCU reset state. After the system will reset input / output (I / 0) home port register for the FFH, stack pointer SP home for 07 H, SBUF built-in value for the indefinite, all the rest of the register-0, the status of internal RAM from the impact of reduction, On the system, when the contents of RAM is volatile. Reset operation There are two situations in which a power-on reset and manual (switch) reduction. The system uses a power-on reset mode. Figure 3-1 in the R0 and C0 formed a power-on reset circuit, and its value for R for 8.2 K, C for the 10 uF.Main features:Compatible the MCS51 command system;Contains the 2KB memory re-programming FLASH (1000);2.7 ~ 6V voltage range;the whole Static work: 0Hz ~ 24KHz;Secrets 2 Program Memory Lock128 × 8-bit internal RAM15 programmable I / O linesTwo 16-bit timer / counter6 interrupt sources, two external interrupt sourcesProgrammable Serial ChannelHigh Precision V oltage Comparator （P1.0，P1.1，P3.6）；Have the output port of the LED direct driveLow-power idle and power-down modeThe pin Picture of AT89C2051Picture one the pin of AT89C2051AT89C2051’s functional description:VCC: Power Supply V oltageGND: landP1 port: P1 mouth is a group of 8-bit bi-directional I / O interface, P1.2 ~ P1.7 provide internal pull-up resistor,P1.0 and P1.1 internal supreme pull-up resistor. P1 mouth output buffer can absorb the current 20mA and direct-drive LED.When Programming and calibration, P1 mouth as the eighth address receive.P3 mouth: P3 port P3.0 ~ P3.5, P3.7 is the internal pull-up resistor with the seven bi-directional I / O interface. Did not bring out the P3.6，It as a generic I / O port, but can not visit. Can be used as a fixed-chip input comparator output signal. when P3 write 1, they were highed the internal pull-up resistor can be raised as an input port.P3 port special function as shown in table 1:Table 1 P3 mouth’s special featuresPIN functional characteristics20191817161514131211GND P3.5P3.4P3.3P3.2XTAL1XTAL2P3.1P3.0RST P3.7P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7VCC 12345678910RST：Reset output. When the oscillator device reset, RST pin to maintain the high level of two machine cycle time.XTAL1: the RP-oscillator amplifier and internal clock generator input.XTAL2: RP-oscillator output amplifier.TimerOverview of the Timer89C2051 single-chip-chip has two 16-bit timer / counter, That is the timer 0 (T0) and Timer 1 (T1). They all have from time to time and event count function, Can be used for timing control, delay of external events, such as counting and testing occasions. Timer’s T0 and T1—— two 16-bit timers in fact is 16-bit counter plus 1. Among them, T0 compositioned by the two 8-bit special function registers TH0 and TL0; T1 posed by the TH1 and TL1. These functions were controled by the special function registers TMOD and TCONWhen set to the work in the timing, Through the pin count of the external pulse signal. When the input pulse signal generated by the falling edge of 1-0, The value of timer plus 1. At of every machine cycle during the S5P2 sampling pin T0 and T1 the input level, if a machine cycle before sample value of 1, The next machine cycle sampling value is 0, The counter plus 1. Since then during S3P1 of the machine cycle, New value will into the counter.so Detection of a 1-0 transition of the two machine cycles,So The maximum count frequency of oscillation frequency of 1 / 24. In addition to the option of work from time to time or count,Each timer / counter have four kinds of work mode, That is, each of timer circuit kinds of four constitute a structural modelTwo low-power modeIdle modeIn idle mode, CPU to maintain sleep and all-chip peripherals remain active, this way generated in Software, At this point, Chip RAM and all the contents of special function registers remain unchanged. Idle mode was terminated by any interrupt request permission to or hardware reset.P1.0 and P1.1 ,in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1."It should be noted that: when uses of hardware reset Termination idle mode, AT89C2051 is usually stopped from the program until the internal reset control of the two machine cycles before the restore procedure Service. In this case the hardware within the prohibition of the reading and writing of internal RAM, However, to allow access to ports, To eliminate the Hardware reset in the idle mode of port accidents may write, In principle, to enter the idle mode of instruction should not be under the command of a pin or an external memory port for a visit.Power-down modeIn power-down mode, the oscillator to stop working, enter the power-down mode ,Instructions, who was the last one, the implementation of the Directive, Chip RAM and all the contents of special function registers the termination of the previous power-down mode be frozen. To withdraw from power-down mode is the only way to reset the hardware, Reset will redefine all the Special Function Registers but Does not change the contents of RAM before the the Vcc work returned to normal levels Shall be null and void and must be reset to maintain a certain period of time in order to restart and oscillator stabilityP1.0 and P1.1 in the non-use of external pull-up resistor on the case should be set to "0", Or in the use of pull-up resistor is set to "1."OscillatorOscillator connected clientXTAL1: RP-oscillator amplifier and internal clock generator inputXTAL2: RP-oscillator amplifier outputCharacteristics of OscillatorXTAL1, XTAL2 ware the RP-chip oscillator amplifier inputs and outputs, Quartzcrystal can be composed of the clock oscillator or ceramic oscillator, For more information from the external input clock driver AT89C2051, XTAL1 input clock signal from, XTAL2 should be left vacant.As the input to the internal circuit is a 2-flip-flop, Therefore, the external clock signal input without special requirements, However, it must comply with the maximum level and minimum norms and timing中文翻译：AT89C2051AT89C2051数据参考手册AT89C2051是美国ATMEL公司生产的低电压、高性能CMOS8位单片机，片内含2k bytes的可反复擦写的只读程序存储器（PEROM）和128bytes的随机数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器和可反复擦写的Flash存储器，可有效地降低开发成本。

51单片机AT89C52中文资料

51单片机AT89C52中文资料--------------------------------------------------------------------------------51单片机AT89C52中文资料AT89C52 ATMEL公司生产的低电压，高性能CMOS 8位单片机．片含8K byTES的可反复擦写的只读程序存储器（PEROM）和256 byTES 。

的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，与标准MCS-51指令系统及8052 产品引脚兼容，片置通用8位中央处理器（CPU ）和FLASH由存储单元，功能强大AT89C52单片适用于许多较为复杂控制应用场合。

主要性能参数：与Mcs-51产品指令和引脚完全兼容。

8字节可重擦写FLASH闪速存储器1000 次擦写周期全静态操作：0HZ-24MHZ三级加密程序存储器256X8字节部RAM32个可编程I/0口线3个16 位定时／计数器8个中断源可编程串行UART通道低功耗空闲和掉电模式部结构图AT89C52部框图功能特性：AT89C52 提供以下标准功能：8字节FLASH闪速存储器，256字竹部RAM , 32个I/O口线，3个16 位定时／计数器，一个6向量两级中断结构，一个全双工串行通信口，片振荡器及时钟电路。

同时，AT89c52可降至OHz的静态逻辑操作，并支持两种软件可选的节电上作模式。

空闲方式停止CPU 的工作，但允许RAM，定时／计数器．串行通信口及中断系统继续工作。

掉电方式保存RAM 中的容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位.功能引脚说明：Vcc:电源电压GND:地P0：P0口是一组8位漏极开路型双向1/O 口，也即地址/数据总线复用口。

作为输出口用时．每位能吸收电流的方式驱动8个TTL 逻辑门电路，对端口P0 写“1”时，可作为高阻抗输入端用。

at89c52单片机介绍

at89c52中文资料介绍AT89C52 ATMEL公司生产的低电压，高性能CMOS 8位单片机．片内含8K byTES的可反复擦写的只读程序存储器（PEROM）和256 byTES 。

的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，与标准MCS-51指令系统及8052 产品引脚兼容，片内置通用8位中央处理器（CPU ）和FLASH 由存储单元，功能强大AT89C52单片适用于许多较为复杂控制应用场合。

主要性能参数：与Mcs-51产品指令和引脚完全兼容。

8字节可重擦写FLASH闪速存储器1000 次擦写周期全静态操作：0HZ-24MHZ三级加密程序存储器256X8字节内部RAM32个可编程I/0口线3个16 位定时／计数器8个中断源可编程串行UART通道低功耗空闲和掉电模式AT89C52内部框图功能特性：AT89C52 提供以下标准功能：8字节FLASH闪速存储器，256字竹内部RAM , 32个I/O口线，3个16 位定时／计数器，一个6向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。

同时，AT89c52可降至OHz的静态逻辑操作，并支持两种软件可选的节电上作模式。

空闲方式停止CPU 的工作，但允许RAM，定时／计数器．串行通信口及中断系统继续工作。

作为输出口用时．每位能吸收电流的方式驱动8个TTL 逻辑门电路，对端口P0 写“1”时，可作为高阻抗输入端用。

在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。

在FLASH由编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。

单片机AT89C52简要说明

附录A 英文原文Microcomputer AT89C52 Synoptic ElucidationThe microcomputer AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator, and clock circuitry.In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning.The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset,for the figure 1.Pin DescriptionVCC:Supply voltage.GND:Ground.Port 0:Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.External pull-ups are required during program verification.Port 1:Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2:Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3:Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG:Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Other- wise, the pin is weakly pulled high. Setting the ALE-disable bit hasno effect if the microcontroller is in external execution mode.PSEN:Program Store Enable is the read strobe to external program memory.When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP:External Access Enable. EA must be strapped to GND in order to enable the图A.1 AT89C52方框图device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the12-volt programming enable voltage(VPP) during Flash programming when 12-volt programming is selected.XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2:Output from the inverting oscillator amplifier.Special Function Registers：Not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate er software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H,RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priori- ties can be set for each of the six interrupt sources in the IP register.Data Memory:The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1:Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.Timer 2:Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON.Timer 2 has three operating modes: capture, auto-reload(up or down counting), and baud rate generator. The modes are selected by bits in T2CON.Timer 2consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition,the maxi- mum count rate is 1/24 of the oscillator frequency.To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.Capture Mode:In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.Auto-Reload (Up or Down Counter):Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically count up when DCEN = 0. In this mode, two option s are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software.If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transi- tion also sets the EXF2 bit. Both the TF2 and EXF2 bits cangenerate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,TH2 and TL2, respect- tively.A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an inter- rupt.Baud Rate Generator：Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or trans- mitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4.The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.The baud rates in Modes 1 and 3 are determined by Timer2’s overflow rate according to the following （A.1）equation.Modes1 and 3 band rates=Timer 2 Overflow Rate16（A.1）The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally,as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency).The baud rate formula is given below（A.2）.modes 1 and 3 band Rate =Oscillator frequency32[65536-(RCAP2H,RCAP2L)]（A.2）where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer Timer 2 as a baud rate generator is showed.This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.附录B 中文翻译单片机AT89C52简要说明AT89C52提供以下标准功能：8k字节Flash闪速存储器，256字节内部RAM，32个I/O口线，3个16位定时/计数器，一个6向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。

AT89C52中文资料

A T89C52中文资料电子驿站http:// E-mail: support@A T89C52是美国A TMEL公司生产的低电压，高性能CMOS 8位单片机，片内含8k bytes的可反复擦写的只读程序存储器（PEROM）和256 bytes的随机存取数据存储器（RAM），器件采用A TMEL公司的高密度、非易失性存储技术生产，与标准MCS-51指令系统及8052产品引脚兼容，片内置通用8位中央处理器（CPU）和Flash存储单元，功能强大A T89C52单片机适合于许多较为复杂控制应用场合。

主要性能参数：·与MCS-51产品指令和引脚完全兼容·8k字节可重擦写Flash闪速存储器·1000次擦写周期·全静态操作：0Hz－24MHz·三级加密程序存储器·256×8字节内部RAM·32个可编程I／O口线·3个16位定时／计数器·8个中断源·可编程串行UART通道·低功耗空闲和掉电模式功能特性概述：A T89C52提供以下标准功能：8k字节Flash闪速存储器，256字节内部RAM，32个I／O口线，3个16位定时／计数器，一个6向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。

同时，A T89C52可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。

空闲方式停止CPU的工作，但允许RAM，定时／计数器，串行通信口及中断系统继续工作。

掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。

AT89C52方框图·P0口：P0口是一组8位漏极开路型双向I ／O 口，也即地址／数据总线复用口。

作为输出口用时，每位能吸收电流的方式驱动8个TTL 逻辑门电路，对端口P0写“l ”时，可作为高阻抗输入端用。

在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。

AT89C52单片机介绍知识讲解

AT89C52单片机介绍在众多的单片机系列中，AT89C52是一种低功耗、高性能CMOS8位微控制器，具有8K在系列可编程Flash存储器。

使用Atmel公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。

片上Flash允许程序存储器在系统可编程，也适用于常规编程。

在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89C52为众多嵌入式控制应用系统提供高灵活、超高效的解决方案。

AT89C52具有以下标准功能：8K字节Flash，256字节RAM，32位I/O口线，3个16位定时器/计数器，一个响亮2级中断结构，全双工串行口，片内晶振及时钟电路。

另外，AT89C52可降至0HZ静态逻辑操作，支持2种软件可选择节电模式。

空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。

掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。

AT89C52单片机为很多嵌入式控制系统提供了一种灵活性高且廉价的方案。

故此选用AT89C52单片机。

1 AT89C52单片机1.1 AT89C52单片机的硬件结构如图3-1所示，为AT89C52的硬件结构图。

AT89C52单片机的内部结构与MCS-51系列单片机的构成基本相同。

CPU是由运算器和控制器所构成的。

运算器主要用来对操作数进行算术、逻辑运算和位操作的。

控制器是单片机的指挥控制部件，主要任务的识别指令，并根据指令的性质控制单片机各功能部件，从而保证单片机各部分能自动而协调地工作。

它的程序存储器为8K字节可重擦写Flash闪速存储器，闪烁存储器允许在线+5V电擦除、电写入或使用编程器对其重复编程。

数据存储器比51系列的单片机相比大了许多为256字节RAM。

AT89C52单片机的指令系统和引脚功能与MCS-51的完全兼容。

图 3-1 单片机89C52结构框图1.2 主要性能参数• 8K字节可重擦写Flash闪速存储器• 1000次可擦写周期•全静态操作：0Hz-24MHz•三级加密程序存储器• 256×8字节内部RAM• 32个可编程I/O口线• 3个16位定时/计数器• 8个中断源•可编程串行UART通道•低功耗空闲和掉电模式图 3-2 AT89C52外部引脚图1.3 AT89C52管脚说明VCC：电源GND：接地P0口：P0口是一个8位漏级开路的双向I/O口。

AT89C52中文原理图规格书

Rev. 0313H–02/00
1
Block Diagram
VCC GND
RAM ADDR. REGISTER
P0.0 - P0.7 PORT 0 DRIVERS
P2.0 - P2.7 PORT 2 DRIVERS
RAM
PORT 0 LATCH
PORT 2 LATCH
QUICK FLASH
PORT 1 LATCH
PORT 3 LATCH
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0 - P1.7
P3.0 - P3.7
BUFFER
PC INCREMENTER
PROGRAM COUNTER
DPTR

2
AT89C52
AT89C52
The AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.

at89c52单片机中英文资料对照外文翻译文献综述

D.htmlat89c52单片机中英文资料对照外文翻译文献综述at89c52单片机简介中英文资料对照外文翻译文献综述AT89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。

Storage RAM immediately﹑memoy readROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。