system verilog 初探

system verilog 初探转载地址：/windzjy/310477/Message.aspx#转载请声明：/Blog/post.aspx?id=310477这是一个sv的验证平台的基本框架，自己画的，对错待证！1，关于clocking block举例如下：待证设计module COUNTER (input Clock, Reset, Enable, Load, UpDn, input [7:0] Data, output reg[7:0] Q); always @(posedge Clock or posedge Reset)if (Reset)Q <= 0;else if (Enable)beginif (Load)Q <= Data;else if (UpDn)Q <= Q + 1;elseQ <= Q - 1;endendmoduletestbench：module Test_Counter_w_clocking;timeunit 1ns;reg Clock = 0, Reset, Enable, Load, UpDn;reg [7:0] Data;wire [7:0] Q;// Clock generatoralwaysbegin#5 Clock = 1;#5 Clock = 0;end// Test programprogram test_counter;// SystemVerilog "clocking block"// Clocking outputs are DUT inputs and vice versaclocking cb_counter @(posedge Clock);default input #1step output #4;output negedge Reset;output Enable, Load, UpDn, Data;input Q;endclocking // Apply the test stimulusinitial begin// Set all inputs at the beginningEnable = 0;Load = 0;UpDn = 1;Reset = 1;##1 cb_counter.Reset <= 0; // Will be applied 4ns after the clock!##1 cb_counter.Enable <= 1;##2 cb_counter.UpDn <= 0;##4 cb_counter.UpDn <= 1;// etc. ...end// Check the results - could combine with stimulus blockinitialbegin##1 // Sampled 1ps (or whatever the precision is) before posedge clock##1 assert (cb_counter.Q == 8'b00000000);##1 assert (cb_counter.Q == 8'b00000000);##2 assert (cb_counter.Q == 8'b00000010);##4 assert (cb_counter.Q == 8'b11111110);// etc. ... end // Simulation stops automatically when both initials have been completed endprogram// Instance the counterCOUNTER G1 (Clock, Reset, Enable, Load, UpDn, Data, Q);// Instance the test program - not required, because program will be// instanced implicitly.// test_COUNTER T1 ();endmodule自己分析的时序，如下图所示：1,接口interface chip_bus; // 定义接口wire read_request, read_grant;wire [7:0] address, data;endinterface: chip_busmodule RAM (chip_bus io, // 使用接口input clk);// 可以使用io.read_request引用接口中的一个信号endmodulemodule CPU(chip_bus io, input clk);...endmodule就像一个数据类型一样，可以用它来定义，或者说引用？2，如果某些变量、函数或其它信息被设计中的所有模块共享，那么我们就可以将它们作为全局声明和语句。

全局声明和语句的一个使用实例如下：reg error _flag; // 全局变量function compare (...); // 全局函数always @(error_flag) // 全局语句...module test;chip1 u1 (...)endmodulemodule chip1 (...);FSM u2 (...);always @(data)error_flag = compare(data, expected);endmodulemodule FSM (...);...always @(state)error_flag = compare(state, expected);endmodule3，抽象数据类型charintshortintlongintbytebitlogic,4 statesshortrealvoidlogic类型能够以下面的任何一种方法赋值：a,通过任意数目的过程赋值语句赋值，能够替代Verilog的reg类型；b,通过单一的连续赋值语句赋值，能够有限制地替代Verilog的wire类型；c,连接到一个单一原语的输出，能够有限制地替代Verilog的wire类型；4,用户定义的数据类型SystemVerilog通过使用typedef提供了一种方法来定义新的数据类型，这一点与C语言类似。

用户定义的类型可以与其它数据类型一样地使用在声明当中。

例如：typedef unsigned int uint;uint a, b;5，枚举类型值从初始值0开始递增，但是我们可以显式地指定初始值。

枚举类型的例子如下：enum {red, yellow, green} RGB;enum {WAIT=2’b01, LOAD, DONE} states;我们还可以使用typedef为枚举类型指定一个名字，从而允许这个枚举类型可以在许多地方使用。

例如：typedef enum {FALSE=1’b0, TRUE} boolean;boolean ready;boolean test_complete;6，结构体和联合体在Verilog语言中不存在结构体或联合体，而结构体或联合体在将几个声明组合在一起的时候非常有用。

SystemVerilog增加了结构体和联合体，它们的声明语法类似于C。

struct {reg [15:0] opcode;reg [23:0] addr;} IR;union {int I;shortreal f;} N;结构体或联合体中的域可以通过在变量名和域名字之间插入句点（.）来引用：IR.opcode = 1; // 设置IR变量中的opcode域N.f = 0.0; // 将N设置成浮点数的值我们可以使用typedef为结构体或联合体的定义指定一个名字。

typedef struct {reg [7:0] opcode;reg [23:0] addr;} instruction; // 命名的结构体instruction IR; // 结构体实例一个结构体可以使用值的级联来完整地赋值，例如：instruction = {5, 200}; //IR = {5,200}???jyz结构体可以作为一个整体传递到函数或任务，也可以从函数或任务传递过来，也可以作为模块端口进行传递。

7，数组8，assertionsassert (A == B); // Asserts that A equals B; if not, an error is generated就是如果在这个时候A不等于B的话，那么就会报出一个错误的信息供你debug。

9,A class is a user-defined data type. Classes consist of data (called properties) and tasksand functions to access the data (called methods). Classes are used in object-oriented programming.In SystemVerilog, classes support the following aspects of object-orientation – encapsulation, data hiding, inheritance and polymorphism.10,Classes may be parameterised in the same way that modules may.class #(parameter int N = 1) Register;It is also possible to pass a data type to a class:class #(parameter type T = int) Register; T data; ... endclass Register Rint;// data is int Register #(bit [7:0]) Rint; // data is bit [7:0]11,One of the key features of object-oriented programming is the ability to create new classes that are based on existing classes. A derived class by default inherits the properties and methods of its parent or base class. However, the derived class may add new properties and methods, or modify the inherited properties and methods. In other words, the new class is a more specialised version of the original class. In SystemVerilog the syntax for deriving or inheriting one class from another is this:class Derived extends BaseClass; // New and overridden property and method declarations. endclass 12,vitual classSometimes, it is useful to create a class without intending to create any objects of the class. The class exists simply as a base class from which other classes can be derived. In SystemVerilog this is called an abstract class and is declared by using the word virtual:virtual class Register; ... endclass13,Traditionally, simulation-based verification has used a directed testing approach. In other words,a testbench implements tests using specific data values.14,struct packed { bit [10:0] ID; // 11-bit identifier bit RTR; // reply required? bit [1:0] rsvd; // "reserved for expansion" bits bit [3:0] DLC; // 4-bit Data Length Code byte data[]; // data payload bit [14:0] CRC; //15-bit checksum } message;We have used struct packed to define a packed data structure. This means that the data structure can be packed into a single vector,15,Constraints direct the random generator to choose values that satisfy the properties you specify in your constraints. Within the limits of your constraints, the values are still randomly chosen. The process of choosing values that satisfy the constraints is called solving. The verification tool thatdoes this is called the solver;16,SystemVerilog 3.1a adds important new constructs to Verilog-2001, including:a, New data types: byte, shortint, int, longint, bit, logic, string, chandle.b, Typedef, struct, union, tagged union, enumc, Dynamic and associative arrays; queuesd, Classese, Automatic/static specification on a per variable instance basisf, Packages and support for Compilation Unitsg, Extensions to Always blocks for modelling combinational, latched or clocked processesh, Jump Statements (return, break and continue)i, Extensions to fork-join, disable and wait to support dynamic processes.j, Interfaces to encapsulate communicationk, Clocking blocks to support cycle-based methodologiesl, Program blocks for describing testsm, Randomization and constraints for random and directed-random verificationn, Procedural and concurrent assertions and Coverage for verificationo, Enhancements to events and new Mailbox and Semaphore built-in classes for inter-process communication.p, The Direct Programming Interface, which allows C functions to be called directly from SystemVerilog (and vice versa) without using the PLI.q, Assertions and Coverage Application Programming Interfaces (APIs) and extensions to the Verilog Procedural Interface(VPI) – details of these are outside the scope of the SystemVerilog Golden Reference Guide17,The clocking event of a clocking block can be accessed directly by using the clocking block name, e.g. @(cb) is equivalent to @(posedge Clk).18,将设计的端口和测试的端口放在同一个interface中，引用的时候可以只引用内部的一个modport 19，The program block can read and write all signals in modules, and can callroutines in modules, but a module has no visibility into a program.用于模块之间进行交互的。