CPU寄存器的设计
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module xianshi(input [3:0]xs,output reg [6:0]l); always @ (xs)
begin
case(xs)
4'b0000: l<=7'b111_1110;
4'b0001: l<=7'b011_0000;
4'b0010: l<=7'b110_1101;
4'b0011: l<=7'b111_1001;
4'b0100: l<=7'b011_0011;
4'b0101: l<=7'b101_1011;
4'b0110: l<=7'b101_1111;
4'b0111: l<=7'b111_0000;
4'b1000: l<=7'b111_1111;
4'b1001: l<=7'b111_1011;
4'b1010: l<=7'b111_0111;
4'b1011: l<=7'b001_1111;
4'b1100: l<=7'b100_1110;
4'b1101: l<=7'b011_1101;
4'b1110: l<=7'b100_1111;
4'b1111: l<=7'b100_0111;
default: l<=7'b000_0000;
endcase
end
endmodule
module show(clk,L3,L2,L1,L0,cout,dig);
input clk;
input[6:0] L3,L2,L1,L0;
output reg [6:0]cout;
output reg [2:0]dig;
reg [9:0]s;
initial s<=0;
always @(negedge clk)
begin
if(s<=39)
s = s+1;
else
s = 0;
end
always @(s)
begin
if(s<=9)
begin
dig = 3'b000;
cout = L3;
end
else if(s<=19)
begin
dig = 3'b001;
cout = L2;
end
else if(s<=29)
begin
dig = 3'b010;
cout = L1;
end
else if(s<=39)
begin
dig = 3'b011;
cout = L0;
end
end
endmodule
module cpu(input clk,input [7:0]D,input [1:0]RA,input Wr,input tongbu, input Rd,input[1:0] M,input reset,output [2:0]dig,output [6:0]cout);
reg[7:0] R0,R1,R2,R3,PC;
reg[7:0] temp;
wire[6:0] L3,L2,L1,L0;
always @(clk)
begin
if(RA == 2'b00&Wr==0&Rd==1) R0 <= D;
if(RA == 2'b00&Wr==1&Rd==0) temp <= R0;
if(RA == 2'b01&Wr==0&Rd==1) R1 <= D;
if(RA == 2'b01&Wr==1&Rd==0) temp <= R1;
if(RA == 2'b10&Wr==0&Rd==1) R2 <= D;
if(RA == 2'b10&Wr==1&Rd==0) temp <= R2;
if(RA == 2'b11&Wr==0&Rd==1) R3 <= D;
if(RA == 2'b11&Wr==1&Rd==0) temp <= R3;
end
always @(negedge tongbu)
begin
if(!reset) PC = 0;
else
begin
if(M == 2'b00) PC = D;
if(M == 2'b01) PC = PC + 1;
if(M == 2'b10) PC = PC - 1;
if(M == 2'b11) PC = PC;
end
end
xianshi x1(PC[7:4],L3);
xianshi x2(PC[3:0],L2);
xianshi x3(temp[7:4],L1);
xianshi x4(temp[3:0],L0);
show s1(clk,L3,L2,L1,L0,cout,dig); endmodule