Verilog_HDL_四位移位乘法器

实验五四位移位乘法器

一、实验代码：（led显示）

module mult(mul,a,b);

output [7:0] mul;

//input ckl;

input [3:0] a,b;

reg [7:0] mul;

wire [3:0] out1,out2,out3,out4;

//wire [3:0] out2;

//wire [3:0] out3;

//wire [3:0] out4;

//如果always快里有问题，用clk进行延时接受，确保无问题

reg [7:0] temp=8'b0;

reg [7:0] temp_mul=8'b0;

multply cheng1(out1,a,b[3]);

multply cheng2(out2,a,b[2]);

multply cheng3(out3,a,b[1]);

multply cheng4(out4,a,b[0]);

always@ (a or b)

begin

temp={4'b0,out1};

temp_mul=temp<<1;

temp={4'b0,out2};

temp_mul=temp_mul+temp;

temp_mul=temp_mul<<1;

temp={4'b0,out3};

temp_mul=temp_mul+temp;

temp_mul=temp_mul<<1;

temp={4'b0,out4};

mul=temp_mul+temp;

end

endmodule

module multply(out,mul4,mul1);

output [3:0] out;

input [3:0] mul4;

input mul1;

reg [3:0] out;

reg [3:0] tem;

always@ (mul4 or mul1)

begin

case(mul1)

1'b0: tem=4'b0;

default: tem=mul4&4'b1111;

endcase

out=tem;

end

endmodule

二、管脚配置：

通过拨动输入：

a[0] input PIN_200

a[1] input PIN_202

a[2] input PIN_203

a[3] input PIN_204

b[0] input PIN_205

b[1] input PIN_206

b[2] input PIN_207

b[3] input PIN_208

led灯输出：

mul[0] output PIN_191

mul[1] output PIN_192

mul[2] output PIN_193

mul[3] output PIN_195

mul[4] output PIN_196

mul[5] output PIN_197

mul[6] output PIN_198

mul[7] output PIN_199

三、实验连线：

通过拨动输入：

K1-K8:11-18

Led灯显示连线：

L1-L8:3-10

四、电路工作原理

手动拨动，开关k1-k8，根据Led灯的显示，亮表示1，不亮表示0来看结果。

五、实验问题

当用八段译码显示管，利用十六进制来表示结果时，遇到一些问题，无法操作成功。总是要么同时选通但只显示一个，要么就是只选通一个。

八段译码显示管显示：

module mult(mul,outa,outb,a,b,clk);

output [7:0] mul;

output outa,outb;

input clk;

input [3:0] a,b;

reg outa;

reg outb;

reg [7:0] mul;

reg te;

wire [3:0] out1,out2,out3,out4;

reg [7:0] temp=8'b0;

reg [7:0] temp_mul=8'b0;

multply cheng1(out1,a,b[3]);

multply cheng2(out2,a,b[2]);

multply cheng3(out3,a,b[1]);

multply cheng4(out4,a,b[0]);

/*

always@(posedge clk)

begin

if(te==0)

begin

outb<=~outb;

outa<=~outa;

te=te+1;

end

end

always@(posedge clk)

begin

if(te==30)

begin outa=outb; outb=~outb; te=te+1; end else if(te==60)

begin outb=outa; outa=~outa; te=0; end else

begin te=te+1; end

end

*/

always@(posedge clk)

begin

if(te<256)

te=te+1;

else

begin

te=0;

outb=~outa;

outa=~outa;

outb=~outb;

end

end

always@ (a or b)

begin

temp={4'b0,out1};

temp_mul=temp<<1;

temp={4'b0,out2};

temp_mul=temp_mul+temp;

temp_mul=temp_mul<<1;

temp={4'b0,out3};

temp_mul=temp_mul+temp;

temp_mul=temp_mul<<1;

temp={4'b0,out4};

temp_mul=temp_mul+temp;

end

always@(posedge clk)

begin

if(outa==0&&outb==1)

begin

case(temp_mul[3:0])

4'h0: mul= 8'h03; //显示0

4'h1: mul = 8'h9f; //显示1

4'h2: mul = 8'h25; //显示2

4'h3: mul= 8'h0d; //显示3

4'h4: mul = 8'h99; //显示4

4'h5: mul = 8'h49; //显示5

4'h6: mul = 8'h41; //显示6

4'h7: mul = 8'h1f; //显示7

4'h8: mul = 8'h01; //显示8

4'h9: mul = 8'h09; //显示9

4'ha: mul = 8'h11; //显示A

4'hb: mul = 8'h01; //显示B

4'hc: mul = 8'h63; //显示C

4'hd: mul = 8'h03; //显示D

4'he: mul = 8'h61; //显示E

4'hf: mul = 8'h71; //显示F

default: ;

endcase

end

else if(outb==0&&outa==1)

begin

case(temp_mul[7:4])

4'h0: mul = 8'h03; //显示0

4'h1: mul = 8'h9f; //显示1

4'h2: mul = 8'h25; //显示2

4'h3: mul = 8'h0d; //显示3

4'h4: mul = 8'h99; //显示4

4'h5: mul = 8'h49; //显示5

4'h6: mul = 8'h41; //显示6

4'h7: mul = 8'h1f; //显示7

4'h8: mul = 8'h01; //显示8

4'h9: mul = 8'h09; //显示9

4'ha: mul = 8'h11; //显示A

4'hb: mul = 8'h01; //显示B

4'hc: mul = 8'h63; //显示C

4'hd: mul = 8'h03; //显示D

4'he: mul = 8'h61; //显示E

4'hf: mul = 8'h71; //显示F

default: ;

endcase

end

else

mul = 8'h03;

end

endmodule

module multply(out,mul4,mul1);

output [3:0] out;

input [3:0] mul4;

input mul1;

reg [3:0] out;

reg [3:0] tem;

always@ (mul4 or mul1)

begin

case(mul1)

1'b0: tem=4'b0;

default: tem=mul4&4'b1111;

endcase

out=tem;

end

endmodule

八段连线问题：

a[0] input PIN_86

a[1] input PIN_87

a[2] input PIN_88

a[3] input PIN_89

b[0] input PIN_90

b[1] input PIN_92

b[2] input PIN_93

b[3] input PIN_94

clk input PIN_191

outa output 83

outb output 85

mul[0] output PIN_200

mul[1] output PIN_202

mul[2] output PIN_203

mul[3] output PIN_204

mul[4] output PIN_205

mul[5] output PIN_206

mul[6] output PIN_207

mul[7] output PIN_208

连线：

K1-K8:45-52

40-T1

41-T2

33-1024HZ

Z8-JX1

module ODD_DIVIDER(

clk_in,

rst_n,

clk_out

);

parameter width=2;

input clk_in;

input rst_n;

output clk_out;

reg [width-1:0] cnt_posedge,cnt_negedge;

reg clk_1toN_p,clk_1toN_n;

always@(posedge clk_in) //上升沿分频，占空比1:2 begin

if(!rst_n)

begin

cnt_posedge<=0;

clk_1toN_p<=0;

end

else if(cnt_posedge==2'b10)

cnt_posedge<=0;

else

begin

cnt_posedge<=cnt_posedge+1;

clk_1toN_p<=~clk_1toN_p;

end

end

always@(negedge clk_in) //下升沿分频，占空比1:2 begin

if(!rst_n)

begin

cnt_negedge<=0;

clk_1toN_n<=0;

end

else if(cnt_negedge==2'b10)

cnt_negedge<=0;

else

begin

cnt_negedge<=cnt_posedge+1;

clk_1toN_n<=~clk_1toN_n;

end

end

assign clk_out=clk_1toN_n||clk_1toN_p; //错位相或endmodule

(((((((三分频50%占空比)))))))

module test_mul_8(mul_a,mul_b,mul_out,reset,clk); input reset,clk,mul_a,mul_b;

output mul_out;

parameter mul_width=8;

parameter mul_result=16;

wire [mul_width-1:0] mul_a;

wire [mul_width-1:0] mul_b;

reg [mul_result-1:0] mul_out;

reg [mul_result-1:0] store0;

reg [mul_result-1:0] store1;

reg [mul_result-1:0] store2;

reg [mul_result-1:0] store3;

reg [mul_result-1:0] store4;

reg [mul_result-1:0] store5;

reg [mul_result-1:0] store6;

reg [mul_result-1:0] store7;

reg [mul_result-1:0] add01;

reg [mul_result-1:0] add23;

reg [mul_result-1:0] add45;

reg [mul_result-1:0] add67;

reg [mul_result-1:0] add0123;

reg [mul_result-1:0] add4567;

always@(posedge clk)

begin

if(!reset)

begin

mul_out<=16'b0000000000000000;

store0<=16'b0000000000000000;

store1<=16'b0000000000000000;

store2<=16'b0000000000000000;

store3<=16'b0000000000000000;

store4<=16'b0000000000000000;

store5<=16'b0000000000000000;

store6<=16'b0000000000000000;

store7<=16'b0000000000000000;

add01<=16'b0000000000000000;

add23<=16'b0000000000000000;

add45<=16'b0000000000000000;

add67<=16'b0000000000000000;

add0123<=16'b0000000000000000;

add4567<=16'b0000000000000000;

end

else

begin

store0<=mul_b[0]?{8'b0,mul_a}:16'b0;

store1<=mul_b[1]?{7'b0,mul_a,1'b0}:16'b0;

store2<=mul_b[2]?{6'b0,mul_a,2'b0}:16'b0;

store3<=mul_b[3]?{5'b0,mul_a,3'b0}:16'b0;

store4<=mul_b[4]?{4'b0,mul_a,4'b0}:16'b0;

store5<=mul_b[5]?{3'b0,mul_a,5'b0}:16'b0;

store6<=mul_b[6]?{2'b0,mul_a,6'b0}:16'b0;

store7<=mul_b[7]?{1'b0,mul_a,7'b0}:16'b0;

add01<=store0+store1;

add23<=store2+store3;

add45<=store4+store5;

add67<=store6+store7;

add0123<=add01+add23;

add4567<=add45+add67;

mul_out<=add0123+add4567;

end

end

endmodule