高速串行接口技术详解

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Hot Design Issues
▪ CMOS serial link transceiver
Framer PLL
Integrated System Design Lab.
DeframeΒιβλιοθήκη Baidu Clock recovery
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Hot Design Issues
▪ CMOS serial link transceiver
PLL
Integrated System Design Lab.
PLL
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High Definition Multimedia Interface (HDMI)
▪ HDMI
– High-definition multi-media interface – Digital video + multi-channel audio interface for
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Computing System
▪ High-speed I/O is needed everywhere
Display Long distance Switch
Graphic Disk LAN
CPU
North Bridge
South Bridge
Memory Local I/O
SAN
Integrated System Design Lab.
Eye diagram Jitter histogram
Integrated System Design Lab.
Tbit Ideal
Timing uncertainty : Jitter Realistic
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Link Performance Metric
▪ Eye diagram example – Near end & far end
Core
▪ Single trace ▪ Plesiochronous ▪ Clock embedded in data ▪ Clock & data recovery
Integrated System Design Lab.
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Parallel vs. Serial
Hardware Complexity
Deframer
Integrated System Design Lab.
Clock recovery
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Link Component
▪ Phase-locked Loop (PLL)
CKi ( fin )
Phase error Loop- Vctr Voltage-Controlled
Detector
Latency
Parallel Bus Low Short
Speed
~ 200Mbps / pin
Manufacturing Cost
High
Serial Link High
Long ~ 10Gbps / pin
or more Low
World is moving toward “serial link” or “serial-link-like parallel bus” !!
Integrated System Design Lab.
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Industry Roadmaps
Year 2005, world is here!!
DVI Fibre Channel PCI Express
SATA SONET/SDH
Ethernet
VGA SXGA UXGA
FC-PI-1 FC-PI-2 10GFC
Detector
Filter
Oscillator
Di 0 1 1 0 1 0 0 1 0 0 0
CKr
Do
Integrated System Design Lab.
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Link Performance Metric
▪ Eye diagram & jitter Tbit
Random bit sequence
PCIe1.0 PCIe2.0(?)
Gen1 Gen2 Gen3
OC-12
OC-48 OC-192
Fast Ethernet
0.1G
Gigabit Ethernet 10G Ethernet
XAUI
1G
10G
OC-768
Data-rate 100G
Integrated System Design Lab.
Framer
High-speed CMOS circuits - Logic gates, analog buffer
PLL
Precise-timing generation - High-frequency, low jitter PLL
High-performance CDR - High-speed NRZ PD - Various CDR architectures
10 ~ 20 cycles / Arithmetic operation 70 cycles / DRAM access
“Pentium 4”
20 ~ 30 cycles / Arithmetic operation 500 ~ 600 cycles / DRAM access
Integrated System Design Lab.
Integrated System Design Lab.
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Introduction
▪ Moore’s law
Growing gap limits system performance!!
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Integrated System Design Lab.
▪ High-speed, low voltage swing interface
Termination
VTT
( R = Z0 )
VRR
Driver
Channel Z0 Z0
DC block
To CDR
Limiting amp
▪ Usually, differential ▪ Small swing - ~ several hundreds mV
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Digital Visual Interface (DVI)
▪ PC display – CRT (analog) LCD (digital) ▪ DVI – Digital Visual Interface
Analog
Digital
Integrated System Design Lab.
Integrated System Design Lab.
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Serial Link Architecture
Transmitter
PCS
Serializer
Transmitter + Receiver = Transceiver
Framer
Channel
PLL Receiver
Deserializer PCS
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Digital System Performance
▪ Performance bottleneck
– The cost of arithmetic operation is cheap now
Computation - bound
Communication - bound
“Pentium Pro”
DVI LVDS
HyperTransport PCI Express
Display SATA
Ethernet
Graphic Disk
Switch
LAN
SONET /SDH
CPU North Bridge
South Bridge
SAN
XDR RDRAM
Memory
Local I/O
Fibre Channel InfiniBand
Eye diagram
Jitter histogram
Jitter PDF = f(x) Bit error!!
Recovered clock
0.5UI
BER f (x)dx f (x)dx
0.5UI
Integrated System Design Lab.
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High-Speed Link Standards
Integrated System Design Lab.
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Link Component
▪ Clock & data recovery (CDR) circuits
Decision circuit
Do
Di
NRZ Phase error Loop- Vctr Voltage-Controlled CKr
consumer electronics – Compatible with DVI
Integrated System Design Lab.
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Serial ATA (SATA)
▪ Next generation ATA bus within PC box ▪ Eliminates fat ATA cables ▪ Point-to-point connection – 1.5G/3G/6G
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Parallel Bus & Serial Link
Core
Parallel Bus Data
I/O
I/O
Clock
Core
▪ Group data (Bus) ▪ Source synchronous ▪ Matched trace
Core
Serial Link
Serial
Data
I/O
I/O
High-Speed Serial Link
Deog-Kyoon Jeong
Seoul National University dkjeong@ee.snu.ac.kr
Outline
▪ Introduction ▪ High-speed I/O overview ▪ Hot design issues ▪ Design examples ▪ Summary
Filter
Oscillator
M
CKo ( fout )
▪ Frequency multiplication: fout = M·fin ▪ Jitter filter ▪ Zero-delay buffer
Integrated System Design Lab.
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Link Component
Integrated System Design Lab.
Channel loss compensation - Equalizer
Deframer
Clock recovery
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Precise Timing generation
▪ VCO noise PLL jitter Data eye jitter ▪ Low noise, high-frequency VCO is required
Framer
PLL Channel
Integrated System Design Lab.
Deframer Clock recovery
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Link Performance Metric
▪ Bit-error rate (BER)
– In most serial link standards, BER < 10-12 is specified
Parallel ATA cabling
Serial ATA cabling
Integrated System Design Lab.
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Transceiver Chip Design
▪ Technology
– CMOS, InP, GaAs, SiGe, BiCMOS … – CMOS will be the eventual winner – Low cost, high-
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Digital Visual Interface (DVI)
▪ TMDS
– Transition minimized differential signaling – EMI reduction
Graphic controller
TMDS encoder TMDS decoder Display controller
integrity
▪ Speed ▪ Power consumption Trade-off!! ▪ Area ▪ Level of integration
– Mixed-signal SoC – Serial link interface + digital circuitry
Integrated System Design Lab.
Integrated System Design Lab.
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Introduction
▪ Moore’s law
– Performance & density improvement in digital system
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