FPGA、VHDL数字钟
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity second is --秒模块
port(reset,inclk,setmin : in std_logic;
dataout : out std_logic_vector(7 downto 0);
enmin : out std_logic);
end second;
architecture behav of second is
signal count_shi,count_ge : std_logic_vector(3 downto 0);
signal count : std_logic_vector(24 downto 0);
signal clk : std_logic;
signal flag_sec : std_logic;
begin
process(inclk) --50MHZ分频为1HZ begin
if(inclk'event and inclk='1')then
if(count=24999999)then
count<="0000000000000000000000000";
clk<=not clk;
else
count<=count+1;
clk<=clk;
end if;
end if;
end process;
process(reset,clk,setmin)
begin
if(reset='1')then
count_shi<="0000";
count_ge<="0000";
elsif(clk'event and clk='1')then
if(count_shi<5)then
if(count_ge<9)then
count_ge<=count_ge+1;
flag_sec<='0';
else
count_ge<="0000";
count_shi<=count_shi+1;
flag_sec<='0';
end if;
else
if(count_ge<9)then
count_ge<=count_ge+1;
flag_sec<='0';
else
count_ge<="0000";
count_shi<="0000";
flag_sec<='1';
end if;
end if;
end if;
end process;
dataout(7 downto 4)<=count_shi;
dataout(3 downto 0)<=count_ge;
enmin<=flag_sec or setmin;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minute is --分模块port(reset,clk,sethour : in std_logic;
dataout : out std_logic_vector(7 downto 0);
enhour : out std_logic);
end minute;
architecture behav of minute is
signal count_shi,count_ge : std_logic_vector(3 downto 0);
signal flag_min : std_logic;
begin
process(reset,clk,sethour)
begin
if(reset='1')then
count_shi<="0000";
count_ge<="0000";
elsif(clk'event and clk='1')then
if(count_shi<5)then
if(count_ge<9)then
count_ge<=count_ge+1;
flag_min<='0';
else
count_ge<="0000";
count_shi<=count_shi+1;
flag_min<='0';
end if;
else
if(count_ge<9)then
count_ge<=count_ge+1;
flag_min<='0';
else
count_shi<="0000";
count_ge<="0000";
flag_min<='1';
end if;
end if;
end if;
end process;
dataout(7 downto 4)<=count_shi;
dataout(3 downto 0)<=count_ge;
enhour<=flag_min or sethour;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour is --时模块port(reset,clk : in std_logic;
dataout : out std_logic_vector(7 downto 0));
end hour;
architecture behav of hour is
signal count_shi,count_ge : std_logic_vector(3 downto 0);
begin
process(reset,clk)
begin
if(reset='1')then
count_shi<="0000";
count_ge<="0000";
elsif(clk'event and clk='1')then
if(count_shi<2)then