清华大学 数字集成系统课件 第九讲Quartus
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Copyright ©
2005 Altera Corporation
Designing with Quartus II
Copyright ©2005 Altera Corporation Objectives
Create a New Quartus II Project Compile a Design into an FPGA
Perform Timing Analysis & Obtain Results Configure an FPGA
Create Simulation Waveform & Simulate a Design
Copyright ©
2005 Altera Corporation Intellectual Property (IP)
−Signal Processing −Communications
−Embedded Processors
z Nios ®II, Nios
Devices (continued)
−MAX ®II
−Mercury ™Devices −ACEX ®Devices −FLEX ®Devices −
MAX
Devices
Tools
−Quartus ®II Software −SOPC Builder −DSP Builder −
Nios II IDE
Devices
−Stratix ®II ™−Cyclone ™II −Stratix GX −Stratix −
Cyclone
Altera Programmable Solutions
Copyright ©2005 Altera Corporation
Quartus II Development System
Fully-Integrated Design Tool
−Multiple Design Entry Methods −Logic Synthesis −Place & Route −Simulation
−Timing & Power Analysis −Device Programming
Copyright ©2005 Altera Corporation More Features
−MegaWizard ®& SOPC Builder Design Tools −LogicLock ™Optimization Tool −PowerPlay Power Analyzer Tool
−NativeLink ®3rd -Party EDA Tool Integration −Debug Tools
z SignalTap ®II z SignalProbe ™
z In-System Memory Content Editor
−Windows, Solaris, HPUX, & Linux Support
Project
Navigator
Status
Window
Message Window 2005 Altera Corporation
Copyright ©
2005 Altera Corporation
Designing with Quartus II
Design Methodology
2005 Altera Corporation
2005 Altera Corporation
Copyright ©
2005 Altera Corporation
Designing with Quartus II
Quartus II Projects
Copyright ©2005 Altera Corporation Quartus II Projects
Description
−Collection of Related Design Files & Libraries −Must Have a Designated Top-Level Entity −Target a Single Device
−
Store Settings in Quartus Settings File (.QSF)
Create New Projects with New Project Wizard
Select & Right-Click
2005 Altera Corporation
Copyright ©
2005 Altera Corporation
Designing with Quartus II
Design Entry
Menu Bar: Edit ⇒Insert Template…or Click on the Shortcut Button
Copyright ©2005 Altera Corporation Schematic Design Entry
Schematic Design Creation
−Draw Schematics Using Library Functions (Blocks)
z Gates, Flip-flops, Pins & Other Primitives z Altera Megafunctions & LPMs
−Create Symbols for Verilog, VHDL, or AHDL Design Files
−Connect All Blocks Using Wires & Busses
Schematic Editor Uses
−Create Simple Test Designs to Understand the Functionality of an Altera Megafunction
z PLL, LVDS I/O, Memory, Etc…
−Create Top-Level Schematic for Easy Viewing & Connection