清华大学 数字集成系统课件 第九讲Quartus

Copyright ©
2005 Altera Corporation
Designing with Quartus II
Copyright ©2005 Altera Corporation Objectives
Create a New Quartus II Project Compile a Design into an FPGA
Perform Timing Analysis & Obtain Results Configure an FPGA
Create Simulation Waveform & Simulate a Design
Copyright ©
2005 Altera Corporation Intellectual Property (IP)
−Signal Processing −Communications
−Embedded Processors
z Nios ®II, Nios
Devices (continued)
−MAX ®II
−Mercury ™Devices −ACEX ®Devices −FLEX ®Devices −
MAX
Devices
Tools
−Quartus ®II Software −SOPC Builder −DSP Builder −
Nios II IDE
Devices
−Stratix ®II ™−Cyclone ™II −Stratix GX −Stratix −
Cyclone
Altera Programmable Solutions
Copyright ©2005 Altera Corporation
Quartus II Development System
Fully-Integrated Design Tool
−Multiple Design Entry Methods −Logic Synthesis −Place & Route −Simulation
−Timing & Power Analysis −Device Programming
Copyright ©2005 Altera Corporation More Features
−MegaWizard ®& SOPC Builder Design Tools −LogicLock ™Optimization Tool −PowerPlay Power Analyzer Tool
−NativeLink ®3rd -Party EDA Tool Integration −Debug Tools
z SignalTap ®II z SignalProbe ™
z In-System Memory Content Editor
−Windows, Solaris, HPUX, & Linux Support
Project
Navigator
Status
Window
Message Window 2005 Altera Corporation
Copyright ©
2005 Altera Corporation
Designing with Quartus II
Design Methodology
2005 Altera Corporation
2005 Altera Corporation
Copyright ©
2005 Altera Corporation
Designing with Quartus II
Quartus II Projects
Copyright ©2005 Altera Corporation Quartus II Projects
Description
−Collection of Related Design Files & Libraries −Must Have a Designated Top-Level Entity −Target a Single Device
−
Store Settings in Quartus Settings File (.QSF)
Create New Projects with New Project Wizard
Select & Right-Click
2005 Altera Corporation
Copyright ©
2005 Altera Corporation
Designing with Quartus II
Design Entry
Menu Bar: Edit ⇒Insert Template…or Click on the Shortcut Button
Copyright ©2005 Altera Corporation Schematic Design Entry
Schematic Design Creation
−Draw Schematics Using Library Functions (Blocks)
z Gates, Flip-flops, Pins & Other Primitives z Altera Megafunctions & LPMs
−Create Symbols for Verilog, VHDL, or AHDL Design Files
−Connect All Blocks Using Wires & Busses
Schematic Editor Uses
−Create Simple Test Designs to Understand the Functionality of an Altera Megafunction
z PLL, LVDS I/O, Memory, Etc…
−Create Top-Level Schematic for Easy Viewing & Connection
Use the Quick Link or
File ⇒New ⇒Schematic File File Extension Is .BDF Copyright ©2005 Altera Corporation
Open the Symbol Window: Use the Toolbar or Double Click Schematic Background
Local Symbols
Created from MegaWizard or
Design Files
Symbol Created in
Project Directory File ⇒Create/Update ⇒
Copyright ©2005 Altera Corporation Megafunctions
Pre-Made Design Blocks
−Ex. Multiply-Accumulate, PLL, Double-Data Rate
Benefits
−Accelerate Design Entry
−Pre-Optimized for Altera Architecture −Add Flexibility
Two Types
−Altera-Specific Megafunctions
−Library of Paramerterized Modules (LPMs)
z Industry Standard Logic Functions
Multiply-Add PLL
Double-Data Rate Locate Documentation in Quartus II Help or the Web
2005 Altera Corporation
Copyright ©2005 Altera Corporation MegaWizard Output File Selection
Default
−HDL Wrapper File
Selectable
−HDL Instantiation Template
−VHDL Component Declaration (CMP)−Quartus II Symbol (BSF)
−Verilog
Black Box
Copyright ©2005 Altera Corporation Memory Editor
Create or Edit Memory Initialization Files in Intel Hex (.HEX) or Altera-Specific (.MIF) Format Design Entry
−Use to Initialize Your Memory Block (Ex. RAM, ROM) during Power-Up
Simulation
−Use to Initialize Memory Blocks before Simulation or after Breakpoints
Copyright ©
2005 Altera Corporation
Change Options & Save
View Options of Memory Editor
Save the Memory File as .HEX or .MIF File
Copyright ©
2005 Altera Corporation
Designing with Quartus II
Quartus II Compilation
Copyright ©2005 Altera Corporation Quartus II Compilation
Synthesis Fitting
Generating Output
−Timing Analysis Output Netlist −Simulation Output Netlists
−Programming/Configuration Output Files
Copyright ©2005 Altera Corporation Three EDA Design Flows
Quartus II Driven Flow
−User Launches other EDA Tools from Quartus II in the Background
−Messages Appear in Quartus II Message Window
Vendor Driven Flow
−User Runs Quartus II in the Background from the 3rd-Party EDA Tool
File Based Flow
−Each Tool Ran Separately
−Files Are Manually Transferred between Tools
Scirocco
Copyright ©2005 Altera Corporation Start Compilation
−Perform Full Compilation Start Analysis & Elaboration
−Check Syntax & Build Database Only
Start Analysis & Synthesis
−Synthesize Code −Estimate Timing Start Fitter
Start Assembler
Start Timing Analysis
Start I/O Assignment Analysis
Start Design Assistant
Processing Options
Processing Toolbar
•Status Bars Scroll to Indicate Progress
•Message Window Displays Informational,
Warning, & Error Messages
Copyright ©2005 Altera Corporation
Contains All Processing Information
•Resource Usage
•Timing Analysis
•Pin-Out File
•Mesage
Copyright ©2005 Altera Corporation
Several Sections Detail the Resource Usage Copyright ©2005 Altera Corporation
Copyright ©2005 Altera Corporation
•Smart Compilation
−Used for Incremental Re-Compilation
−Saves Compiler Time
−Uses More Disk Space
•Enable Incremental Synthesis
Copyright ©2005 Altera Corporation
Right-Click on Hierarchical。