义守大学计算及组织Chapter3ArithmeticforComputers(2)解读

beginning of run
Op sub none add none
Originally for speed (when shift was faster than add) Why it works? -1 + 10000 01111
Chapter 3 — Arithmetic for Computers — 19
§ 3.3 Multiplication
Multiplication

Start with long-multiplication approach
1000 × 1001 1000 0000 0000 1000 1001000
multiplicand multiplier
product
Length of product is the sum of operand lengths
Chapter 3
Arithmetic for Computers
§ 3.1 Introduction
Arithmetic for Computers

Arithmetic and logic operations (ALU) Operations on integers


Addition and subtraction Multiplication and division Dealing with overflow
§ 3.2 Addition and Subtraction
Integer Addition

Example: 7 + 6

Overflow if result out of range

Adding +ve and –ve operands, no overflow Adding two +ve operands
x + 0010two 0011two 0000 0010 0000 0010 00001100two
shift (0 in multiplier) sub (first 1 in multiplier) shift (mid string of 1s) add (prior step had last 1)
Booth’s Algorithm
1. Depending on the current and previous bits, do one of the following: 00: Middle of a string of 0s, no arithmetic op. 01: End of a string of 1s, so add multiplicand to the left half of the product

Overflow if result sign is 1 Overflow if result sign is 0
Chapter 3 — Arithmetic for Computers — 9

Adding two –ve operands

Integer Subtraction

Add negation of second operand Example: 7 – 6 = 7 + (–6)
Chapter 3 — Arithmetic for Computers — 17
Booth’s Algorithm: Motivation
Example: 2 x 6 = 0010 x 0110:
x + + + + 0010two 0011two 0000 0010 0010 0000 00001100two shift (0 in multiplier) add (1 in multiplier) add (0 in multiplier) shift (0 in multiplier)

One cycle per partial-product addition

That’s ok, if frequency of multiplications is low
Chapter 3 — Arithmetic for Computers — 15
Multiplication Example
Can get same result in more than one way:
6 = -2 + 8 0110 = -00010 + 01000 Basic idea: replace a string of 1s with an initial subtract on seeing a one
and add after last one
4b.
0010
0000 1110 0
Chapter 3 — Arithmetic for Computers — 21
Booths Example (2 x -3)
Operation Multiplicand Product next? 0. initial value 0010 0000 1101 0 10 -> sub 1a. P = P - m 1110 +1110 1110 1101 0 shift P(sign ext) 1b. 0010 1111 0110 1 01 -> add 2a. +0010 0001 0110 1 shift P 2b. 0010 0000 1011 0 10 -> sub 3a. +1110 0010 1110 1011 0 shift 3b. 0010 1111 0101 1 11 -> nop 4a 1111 0101 1 shift 4b. 0010 1111 1010 1 done
1110 +1110 1110 0111 0 shift P(sign ext) 11 -> nop, shift 11 -> nop, shift 01 -> add
1b. 2. 3. 4a.
0010 0010 0010
1111 0011 1 1111 1001 1 1111 1100 1
0010 +0010 0001 1100 1 shift done
10: Beginning of a string of 1s, so subtract
multiplicand from the left half of the product 11: Middle of a string of 1s, so no arithmetic op. 2. As in the previous algorithm, shift the Product register right (arithmetically) 1 bit
Use MIPS add, addi, sub instructions On overflow, invoke exception handler


Save PC in exception program counter (EPC) register Jump to predefined handler address mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action
Chapter 3 — Arithmetic for Computers — 13
Multiplication Hardware
Initially 0
Chapter 3 — Arithmetic for Computers — 14
Optimized Multiplier

Perform steps in parallel: add/shift
+7: –6: +1: 0000 0000 … 0000 0111 1111 1111 … 1111 1010 0000 0000 … 0000 0001

Overflow if result out of range

Subtracting two +ve or two –ve operands, no overflow Subtracting +ve from –ve operand
Chapter 3 — Arithmetic for Computers — 20
Booths Example (2 x 7)
Operation
0. initial value 1a. P = P - m
Multiplicand
0010
Product
0000 0111 0
next?
10 -> sub
Chapter 3 — Arithmetic for Computers — 6
32-bit ALU with Set Less Than
Chapter 3 — Arithmetic for Computers — 7
Final 32-bit ALU
Chapter 3 — Arithmetic for Computers — 8

Overflow if result sign is 0 Overflow if result sign is 1

Subtracting –ve from +ve operand

Chapter 3 — Arithmetic for Computers — 10
Dealing with Overflow
Chapter 3 — Arithmetic for Computers — 3
Enhanced Arithmetic Logic Unit

ALU that have NAND/NOR operation
Chapter 3 — Arithmetic for Computers — 4
32-bit ALU
Chapter 3 — Arithmetic for Computers — 11
Overflow Detection for Signed & Unsigned Addition

Signed addition

Unsigned addition
Chapter 3 — Arithmetic for Computers — 12
Chapter 3 — Arithmetic for Computers — 18Байду номын сангаас
Booth’s Algorithm: Rationale
middle of run
end of run Current
bit 1 1 0 0 Bit to Explanation right 0 Begins run of 1s 1 Middle run of 1s 1 End of run of 1s 0 Middle run of 0s Example 00001111000 00001111000 00001111000 00001111000

Some languages (e.g., C) ignore overflow

Use MIPS addu, addui, subu instructions

Other languages (e.g., Ada, Fortran) require raising an exception

Chapter 3 — Arithmetic for Computers — 16
Faster Multiplier

Uses multiple adders

Cost/performance tradeoff

Can be pipelined

Several multiplication performed in parallel
Chapter 3 — Arithmetic for Computers — 5
One-bit ALUs with Set Less Than
•
slt $t0, $s1, $s2 – If $s1 < $s2 $t0= 0…001 else $t0= 0…000 – lsb = signed bit最低位=符号位 – All but the lsb = 0
Representation and operations

Floating-point real numbers

Chapter 3 — Arithmetic for Computers — 2
Constructing a Basic Arithmetic Logic Unit

One-bit ALU that performs AND, OR, and addition