等精度频率计设计VHDL程序

1 -----------------------------------------------------------------------------
2 -- Filename:
3 --
testbench.vhd
4 -- Description:
5 --
6 --
test bench module
7 -- Copyright (c) 2005 by JohnYuan
8 --
9 -- An X.M.U.T. Projects
free to use, but see documentation for conditions
10 --
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66 -- Revision
-- Revision
-- --------
-- 1.0
--
--
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164 .all;
use ieee.std_logic_unsigned .all;
-----------------------------------------------------------------------------
entity yuan is
History:
Date
----------
Nev.6th 2006
Author
---------
YichaoChen;ShiqinHuang
Comment
-----------
Initial revision
port( bclk : in std_logic; --System clk 50MHz
tclk : in std_logic; --Pulse under measure
clr
cl
: in std_logic; --Reset signal
: in std_logic; --MCU test command input
start : out std_logic; --Measure start and stop signal
: in std_logic_vector (2 downto 0); --Data output select
data : out std_logic_vector (7 downto 0)); --Output data to MCU
end yuan;
sel
-----------------------------------------------------------------------------
architecture one of yuan is
signal bzq,tsq:std_logic_vector (31 downto 0);
signal ena:std_logic;
begin
--signal ena equals to start
start <= ena; --
--Data selection command,MCU read data from CPLD
data<=bzq(7 downto 0)
bzq(15 downto 8)
bzq(23 downto 16) when sel="010" else
bzq(31 downto 24) when sel="011" else
tsq(7 downto 0)
tsq(15 downto 8)
tsq(23 downto 16) when sel="110" else
tsq(31 downto 24) when sel="111" else
tsq(31 downto 24);
-----------------------------------------------------------------------------
--Dff
d:process(tclk,clr,cl)
begin
if clr='1' then ena<='0' after 1ns;
elsif tclk'event and tclk='1' then ena <= cl after 1ns;
end if;
end process;
-----------------------------------------------------------------------------
--Measuring counter,clocked by pulse under measure
tf:process(tclk,clr,ena) --
begin
if clr='1' then tsq<=(others=>'0')after 1ns;
elsif tclk'event and tclk='1' then
if ena='1' then tsq <= tsq + 1 after 1ns;
end if;
end if;
end process;
-----------------------------------------------------------------------------
when sel="000" else
when sel="001" else
when sel="100" else
when sel="101" else
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77 --Reference counter,clocked by benchmark pulse bzh:process(bclk,clr,ena) --
begin
if clr='1' then bzq<=(others=>'0')after 1ns;
elsif bclk'event and bclk='1' then
if ena='1' then bzq <= bzq + 1after 1ns;
end if;
end if;
end process;
end one;。