基于VHDL频率计的设计

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频率计

一、实验目的

1.学习并熟悉使用max+plusⅡ软件。

2.掌握各频率计各逻辑模块的功能与设计方法。

二、实验原理

频率测量基本原理是计算每秒钟内待测信号的脉冲个数。要求TESTCTL的计数使能信号TSTEN能产生一个1秒脉宽的周期信号,并对频率计的每一计数器CNT10的ENA使能端进行同步控制。当TSTEN为高电平时,允许计数;为低电频时停止计数,并保持其所计的脉冲信号。在停止计数期间,首先需要一个锁存信号LOAD的上跳沿将计数器在前一秒的计数值锁存进32位锁存器REG32B中,并由周期性的清零信号并不断闪烁。所存信号之后,必需有一清零信号CLR_CNT 对计数器进行清零,为下一秒的计数做准备。测试控制信号发生器的工作时序如图。为了产生这个时序图,需首先建立一个由D触发器构成的二分频器,在每次时钟CLK上沿到来时其值翻转。

三、实验内容和代码

—————————————cnt10——————————————

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CNT10 IS

PORT (CLK: IN STD_LOGIC;

CLR: IN STD_LOGIC;

ENA: IN STD_LOGIC;

CQ: OUT INTEGER RANGE 0 TO 15;

CARRY_OUT :OUT STD_LOGIC );

END CNT10;

ARCHITECTURE behav OF CNT10 IS

SIGNAL CQI: INTEGER RANGE 0 TO 15;

BEGIN

PROCESS(CLK, CLR, ENA)

BEGIN

IF CLR = '1' THEN CQI <= 0;

ELSIF CLK'EVENT AND CLK = '1' THEN

IF ENA = '1' THEN

IF CQI < 9 THEN CQI <= CQI + 1;

ELSE CQI <= 0;END IF;

END IF;

END IF;

END PROCESS;

PROCESS(CQI)

BEGIN

IF CQI = 9 THEN CARRY_OUT <= '1';

ELSE CARRY_OUT <= '0'; END IF;

END PROCESS;

CQ <= CQI;

END behav;

——————————————REG32GB——————————LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG32B IS

PORT (Load : IN STD_LOGIC;

DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END REG32B;

ARCHITECTURE behav OF REG32B IS

BEGIN

PROCESS(Load, DIN)

BEGIN

IF Load'EVENT AND Load='1' THEN DOUT <=DIN;

END IF;

END PROCESS;

END behav; ——————————————TESTCTL——————————LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TESTCTL IS

PORT (CLK : IN STD_LOGIC;

TSTEN : OUT STD_LOGIC;

CLR_CNT : OUT STD_LOGIC;

Load : OUT STD_LOGIC);

END TESTCTL;

ARCHITECTURE behav OF TESTCTL IS

SIGNAL Div2CLK : STD_LOGIC;

BEGIN

PROCESS(CLK)

BEGIN

IF CLK'EVENT AND CLK = '1' THEN

Div2CLK <= NOT Div2CLK;

END IF;

END PROCESS;

PROCESS(CLK, Div2CLK)

BEGIN

IF CLK = '0' AND Div2CLK ='0' THEN CLR_CNT <= '1';

ELSE CLR_CNT <= '0'; END IF;

END PROCESS;

Load <= NOT Div2CLK; TSTEN <= Div2CLK;

END behav;

——————————FREQTEST——————————

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FREQTEST IS

PORT(CLK : IN STD_LOGIC;

FSIN : IN STD_LOGIC;

DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );

END FREQTEST;

ARCHITECTURE struc OF FREQTEST IS

COMPONENT TESTCTL

PORT(CLK : IN STD_LOGIC ; TSTEN : OUT STD_LOGIC ;

CLR_CNT : OUT STD_LOGIC ; Load : OUT STD_LOGIC );

END COMPONENT;

COMPONENT CNT10

PORT(CLK : IN STD_LOGIC ; CLR : IN STD_LOGIC ; ENA : IN STD_LOGIC ;

CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CARRY_OUT : OUT STD_LOGIC);

END COMPONENT;

COMPONENT REG32B

PORT( Load : IN STD_LOGIC;

DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );

END COMPONENT ;

SIGNAL Load1,TSTEN1,CLR_CNT1: STD_LOGIC;

SIGNAL DTO1 : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL CARRY_OUT1: STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN

U1 : TESTCTL PORT MAP(CLK => CLK, TSTEN =>TSTEN1,

CLR_CNT => CLR_CNT1, Load => Load1 );

U2 : REG32B PORT MAP(Load => Load1, DIN => DTO1, DOUT => DOUT );

U3 : CNT10 PORT MAP(CLK => FSIN ,CLR => CLR_CNT1, ENA => TSTEN1,

CQ => DTO1(3 DOWNTO 0), CARRY_OUT => CARRY_OUT1(0) ); U4 : CNT10 PORT MAP(CLK => CARRY_OUT1(0), CLR => CLR_CNT1,

ENA => TSTEN1, CQ => DTO1(7 DOWNTO 4),

CARRY_OUT => CARRY_OUT1(1) );

U5 : CNT10 PORT MAP(CLK => CARRY_OUT1(1), CLR => CLR_CNT1,

ENA => TSTEN1,CQ => DTO1(11 DOWNTO 8),

CARRY_OUT => CARRY_OUT1(2) );

U6 : CNT10 PORT MAP(CLK => CARRY_OUT1(2), CLR => CLR_CNT1,

ENA => TSTEN1,CQ => DTO1(15 DOWNTO 12),

CARRY_OUT => CARRY_OUT1(3) );

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