脉冲序列发生器
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VHDL:序列发生器实现,输出序列暂时选为"111010101 "，你可以根据需要给定输出序列，原代码如下（仿真结果见图）
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sequencer is --11101010--
port(clk : in std_logic;
rst : in std_logic;
seq : out std_logic);
end sequencer;
architecture arch of sequencer is
type state_type is (S0,S1,S2,S3,S4,S5,S6,S7);
signal state : state_type;
begin
P1 : process(clk,rst)
begin
if rst='0' then
state <= S0;
elsif clk'event and clk = '1' then
if state <= S0 then
state <= S1;
elsif state <= S1 then
state <= S2;
elsif state <= S2 then
state <= S3;
elsif state <= S3 then
state <= S4;
elsif state <= S4 then
state <= S5;
elsif state <= S5 then
state <= S6;
elsif state <= S6 then
state <= S7;
elsif state <= S7 then
state <= S0;
else
state <= S0;
end if;
end if;
end process P1;
P2 : process(clk,rst) --11101010--
begin
if rst='0' then
seq <= '0';
elsif clk'event and clk='1' then case state is
when S0=>
seq <= '1';
when S1=>
seq <= '1';
when S2=>
seq <= '1';
when S3=>
seq <= '0';
when S4=>
seq <= '1';
when S5=>
seq <= '0';
when S6=>
seq <= '1';
when S7=>
seq <= '0';
when others=>NULL;
end case;
end if;
end process P2;
end arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY pulsegen IS
PORT(clk,rd:IN BIT;
q:OUT BIT_VECTOR(2 DOWNTO 0));
END pulsegen;
ARCHITECTURE bhv OF pulsegen IS
SIGNAL x,y:BIT_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(clk,rd)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF rd='0' THEN
y<="000";
x<="001";
ELSE
y<=x;
x<=X ROL 1;
END IF;
END IF;
q<=y;
END PROCESS;
END bhv;
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