射频识别技术RFID

1研究背景关键词:RFID 板级标签FPGA 状态机ISO18000—6C

RFID是Radio Frequency Identification的缩写，即射频识别，俗称电子标签。射频识别技术RFID是一种利用无线读写数据，借以识别物品的技术，它是无线通讯技术与半导体技术相结合的产物，是当前应用最广泛的非接触式自动目标识别技术之一。识别系统由阅读器和电子标签组成，通过射频信号自动识别目标对象并获取相关数据，识别工作无须人工干预。RFID技术具有很强的环境适应性，抗干扰能力强，可全天候使用，几乎不受污染与潮湿的影响，同时还避免了机械磨损。RFID标签数据存储容量大、信息处理速度快、存储信息可以自由更改，存储数据可以加密，标签无直接对最终用户开放的物理接口，能更好地保证机具的安全性。另外，还可以用一些加密算法实现信息的安全管理，读写器与标签之间也可相互认证，实现安全通信和存储。RFID 技术涉及信息、制造、材料等诸多高技术领域，涵盖芯片设计与制造、天线设计与制造、标签封装、系统集成、信息安全等技术。随着芯片技术、天线技术和计算机技术的不断发展，RFID系统的体积、功耗越来越小，成本越来越低，功能日趋灵活，操作快捷方便，加上其擅长多目标识别、运动目标识别，方便物品跟踪和管理的突出特点，在各种生产生活领域中得到广泛的应用。在物流系统、零售行业、身份识别、交通管理农牧行业和医药行业等许多领域，RFID识别技术已经成为21世纪最热门的技术之一。

Radio Frequency Identification System RFID contains the electronic tags, readers and applications of three parts. Preservation of electronic tags in general agreement with the format of the data, in practice, the electronic tags attached to the surface of the object to be identified. Reader can be read without contact and identify the tag in the electronic data stored, so as to achieve the purpose of automatic identification of objects. Applicationscollect, process and remote transfer object identification informationthroughcomputers and computer networks.

The carrier frequency ofthe RFID system which meets the ISO/IEC15693 standard is 13.56MHz between the electronic tag and reader. Design a data transmission encodercorresponding four load modulation (high data rate single carrier, high data rate dual-carrier, low- single-carrier data rate, low data rate two-carrier) according to the agreement on ISO15693 RFID on transmitting data to the reader . Reader send data to the electronic tag through the pulse position coding method and electronic tag send Manchester encoded data to the reader.

This paper will elaborate the design of the Manchester encoding module based o n thistan dard. In accordance with the details of function and interface description, and then the sub-module by module design and analysis, hardware Description language used to implement VerilogHDL module function; VerilogHDL of each module testbench source code written test file, then use the ModelSim SE 6.0 functional simulation module; functional verification is correct, the source code input Synopsys Design Compiler, the specified technology library, the preparation of binding document on the design of logic synthesis and optimization. Paper gives the correct functional simulation results obtained show that completing the front-end designed to meet the functional and timing requirements. Logic synthesis has satisfactory result can be successful Manchester encoding.

1.Describeeach module in accordance with the details of function and

interface,divide the modules into sub-modules, design and analysis, and then

implement the function of modules with Veriloghardware Description language;