pld应用程序举例
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pld应用程序举例library ieee;
use ieee.std_logic_1164.all;
entity duanma is
port(fff:out bit_vector(1 to 5); aaa:out bit_vector(1 to 5));
end;
architecture kk of duanma is
begin
fff(1 to 5)<="11111";
aaa(1 to 5)<="11111";
end;
PLD三个数加法编程library ieee;
use ieee.std_logic_1164.all;
entity jw is
port(in1,in2:in integer range 0 to 15; a,b:out std_logic_vector(1 to 7)); end;
architecture gg of jw is
signal he:integer range 0 to 45;
begin
he<=in1+in2;
with he select
a<="1111110" when 0|10|20|30|40, "0110000" when 1|11|21|31|41, "1101101" when 2|12|22|32|42, "1111001" when 3|13|23|33|43, "0110011" when 4|14|24|34|44, "1011011" when 5|15|25|35|45, "1011111" when 6|16|26|36, "1110000" when 7|17|27|37, "1111111" when 8|18|28|38, "1111011" when 9|19|29|39, "0000000" when others;
with he select
b<="0000000" when 0<=he and he<=9,else "0110000" when 10<=he and
he<=19,else
"1101101" when 20<=he and
he<=29,else
"1111001" when 30<=he and
he<=39,else
"0110011" when 40<=he and
he<=39,else
"0000000" when others;
end;
PLD八个按键两个灯library ieee;
use ieee.std_logic_1164.all;
entity guozi3 is
port(in1,in2:in std_logic_vector(1 to 4); a,b:out std_logic_vector(1 to 8)); end;
architecture gg of guozi3 is
begin
with in1 select
"0110000" when "0001", "1101101" when "0010", "1111001" when "0011", "0110011" when "0100", "1011011" when "0101", "1011111" when "0110", "1110000" when "0111",
"1111111" when "1000", "1111011" when "1001", "0000000" when others;
with in2 select
b<="0110000"when "0001", "1101101" when "0010", "1111001" when "0011", "0110011" when "0100", "1011011" when "0101", "1011111" when "0110", "1110000" when "0111", "1111111" when "1000", "1111011" when "1001", "0000000" when others;
end;
PLD顺序语句编程(0加到9) library ieee;
use ieee.std_logic_1164.all;
entity jinchen is
port(in1:in std_logic;
a:out std_logic_vector(1 to 7));
end;
architecture gg of jinchen is signal ss:integer range 0 to 9; begin
process
begin
wait until in1='1';
ss<=ss+1;
if ss=10 then
ss<=0;
end if;
end process;
with ss select
a<="1111110" when 0,
"0110000" when 1,
"1101101" when 2,
"1111001" when 3,
"0110011" when 4,
"1011011" when 5,
"1011111" when 6,
"1110000" when 7,
"1111111" when 8,
"1111011" when 9,
"0000000" when others;
end;
PLD矢量10个操纵2个数码管library ieee;
use ieee.std_logic_1164.all;
entity kongzhi2 is
port (a:out bit_vector(1 to 7);
b:in bit_vector(1 to 10));
end;
architecture ff of kongzhi2 is begin
a<="1111110"
when b="1000000000"else
"0110000"
when b="010*******"else
"1101101"
when b="0010000000"else
"1111001"
when b="1001000000"else
"0110011"
when b="1000100000"else