1790128中文资料
EP1C12F144C7中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」
EP1C6
5,980 20
92,160 2
185
EP1C12
12,060 52
239,616 2
249
EP1C20 20,060
64 294,912
2 301
1
芯片中文手册,看全文,戳
气旋 FPGA系列数据手册
初稿信息
Cyclone器件在四方扁平封装（QFP）,并提供节省空间
FineLine BGA 包（见
Cyclone器件提供一个全局时钟网络和多达两个PLL.全局时钟网络由八 个全局时钟线驱动整个器件.全局时钟网络可以为设备内所有资源 ,如IOEs,LE和存储器块提供时钟.
全局时钟线也可用于控制信号.旋风PLL提供通用与时钟倍频和移相,以 及外部输出高速差分I / O支持时钟.
图1
示出旋风EP1C12装置图.
M4K RAM块与4K位内存加上平价（4,608位）真正双端口存储器 块.这些块宽高达200 MHz提供专用真正双端口,简单双端口或单端 口内存最高可达36位.这些块加在器件分成列在一定LAB之间. Cyclone器件提供嵌入式RAM 60至288千位之间.
每个Cyclone器件I / O引脚由I / O单元（IOE）位于输送 围绕装置外周端部LAB行和列. I / O 引脚支持各种单端和差分I / O标准,如 66 MHz32位PCI标准,并在到LVDS I / O标准 311 Mbps.每个IOE包含一个双向I / O缓冲区和三个寄存器 用于登记输入,输出和输出使能信号.两用 DQS,DQ和DM引脚以及延时链（用于相位对齐DDR 信号）提供与外部存储器设备,诸如接口支持 DDR SDRAM和高达133兆赫（266 Mbps）FCRAM器件.
配置设备配置Cyclone器件.
FM1288中文数据手册(仅供参考)
FM-1288 高性能汽车免提语音理器产前信息本文件包含一个试制产品信息。
规格和试生产资料如有更改恕不另行通知。
富迪科技的产品并不是为了挽救生命或维持生命的应用。
因此，如果这样使用的话迪科技不承担任何责任。
富迪的产品有富迪的书面批准才能用于生命支持设备或系统。
如果有这样的组件故障可合理预期会导致该生命支持设备或系统的失效，或影响的设备或系统的安全性或有效性。
生命支持设备或系统的目的是植入人体，或支持和/或维持和维持和/或保护人类生活。
如果他们失败了，这个假设合理，用户或其他人的健康可能会受到威胁。
在此我们拒绝任何形式的担保，但不限于保证不侵权，还包括对于电路说明和图表说明。
Fortémedia, SAM, ForteVoice, Fortémedia and SAM logos are trademarks of Fortémedia,, Inc.All other trademarks belong to their respective companies.Copyright © 2012 Fortémedia all rights reserved目录1. 简介 (9)1.1概述 (9)1.2个主要特点 (9)1.3引脚配置（LQFP） (10)1.4设备终端功能 (11)1.5部硬件框图 (14)1.6系统应用程序框图 (15)2. 功能描述 (17)2.1概述 (17)2.2串行EEPROM接口（引脚15，16） (17)2.3 UART接口（引脚12，13） (22)2.4 IIC兼容串行接口-SHI（引脚23，24） (24)2.5数字语音数据接口（引脚8，9，10,11） (25)2.5.1 PCM接口主从 (26)2.5.2 IIS接口 (28)2.6 ADC（引脚39，40，41，42，43，44） (33)2.7 DAC（引脚 1，3，47，48） (34)2.8操作模式 (35)2.9电STAP选项（引脚17） (37)2.10静音控制和指示（引脚20，21） (37)2.11扬声器音量控制（引脚25，26） (38)2.12系统时钟输入和产生（引脚27，28） (38)2.13旁路模式（引脚14） (39)3.通过EEPROM，UART，SHI访问fm1288 (40)3.1访问通过EEPROM (41)3.2 通过实例访问EEPROM (42)3.3通过UART访问 (43)3.5通过SHI访问 (44)3.6个例子通过施 (44)4. 电气和时序规 (44)4.1绝对最大额定值 (45)4.2推荐操作条件 (45)4.3直流特性 (46)4.4交流特性 (47)4.5时序特性 (49)5. 语音处理器性能细节 (52)6. 引脚定义细节 (53)7. 封装尺寸（LQFP） (55)8. 订货信息 (56)附录 I：操作所需的外部元件 (57)参考 (59)状态信息本产品数据表的状态是产品信息。
MC1GU128NCYA-0QC00中文资料
MultiMediaCard SpecificationVersion : Ver. 0.9Date 4 – June - 2004Samsung Electronics Co., LTDSemiconductor Flash Memory Product Planning & Applications1 Introduction to the MultiMediaCard ----------------------------------------------------------- 51.1 System Features ----------------------------------------------------------------------------------------- 5-------------------------------------------------------------------------------------- 51.2 ProductModel2 Function Description ------------------------------------------------------------------------------- 72.1 Flash Technology Independence ------------------------------------------------------------------ 72.2 Defect and Error Management --------------------------------------------------------------------- 72.3 Endurance ----------------------------------------------------------------------------------------------- 72.4 Automatic Sleep Mode ------------------------------------------------------------------------------- 72.5 Hot Insertion -------------------------------------------------------------------------------------------- 82.6 MultiMediaCard Mode -------------------------------------------------------------------------------- 82.6.1 MultiMediaCard Standard Compliance ----------------------------------------------------------- 82.6.2 Negotiation Operation Conditions ----------------------------------------------------------------- 82.6.3 Card Acquisition and Identification ---------------------------------------------------------------- 82.6.4 Card Status ---------------------------------------------------------------------------------------------- 82.6.5 Memory Array Partitioning --------------------------------------------------------------------------- 92.6.6 Read and Write Operations ------------------------------------------------------------------------- 92.6.7 Data Transfer Rate ------------------------------------------------------------------------------------102.6.8 Data Protection in the Flash Card -----------------------------------------------------------------10-----------------------------------------------------------------------------------------------------10 2.6.9 Erase2.6.10 Write Protection ----------------------------------------------------------------------------------------102.6.11 Copy Bit ------------------------------------------------------------------------------------------------- 102.6.12 The CSD Register ------------------------------------------------------------------------------------ 112.7 SPI Mode ----------------------------------------------------------------------------------------------- 112.7.1 Negotiating Operation Conditions ---------------------------------------------------------------- 112.7.2 Card Acquisition and Identification --------------------------------------------------------------- 112.7.3 Card Status --------------------------------------------------------------------------------------------- 112.7.4 Memory Array Partitioning -------------------------------------------------------------------------- 112.7.5 Read and Write Operations ------------------------------------------------------------------------- 112.7.6 Data Transfer Rate ------------------------------------------------------------------------------------ 112.7.7 Data Protection in the MultiMediaCard ----------------------------------------------------------- 1212-----------------------------------------------------------------------------------------------------2.7.8 Erase2.7.9 Write Protection ---------------------------------------------------------------------------------------- 123 Product Specifications ----------------------------------------------------------------------------- 133.1 Recommended Operating Conditions ------------------------------------------------------------------------- 133.2 Operating Characteristis ----------------------------------------------------------------- 143.3 System Environmental Specifications ----------------------------------------------------------------- 153.4 System Reliability and Maintenance -------------------------------------------------------------- 153.5 Physical Specifications ------------------------------------------------------------------------------- 164 MultiMediaCard Interface Description --------------------------------------------------------- 174.1 Pin Assignments in MultiMediaCard Mode ------------------------------------------------------- 174.2 Pin Assignments in SPI Mode ---------------------------------------------------------------------- 184.3 MultiMediaCard Bus Topology ---------------------------------------------------------------------- 184.4 SPI Bus Topology -------------------------------------------------------------------------------------------------- 194.4.1 SPI Interface Concept ------------------------------------------------------------------------------------------- 194.4.2 SPI Bus Topology ------------------------------------------------------------------------------------------------ 1920------------------------------------------------------------------------------------------------- 4.5 Registers4.5.1 Operation Condition Register (OCR) ---------------------------------------------------------------------------204.5.2 Card Identification (CID) ------------------------------------------------------------------------------214.5.3 Relative Card Address (RCA) ----------------------------------------------------------------------- 21 4.5.4 Card Specific Data (CSD) ---------------------------------------------------------------------------- 22 4.6 MultiMediaCard Communication -------------------------------------------------------------------- 3030----------------------------------------------------------------------------------------------- 4.6.1 Commands4.7 Read, Write and Erase Time-out Conditions ----------------------------------------------------- 33 4.8 Card Identification Mode ------------------------------------------------------------------------------ 34 4.8.1 Operating Voltage Range Validation --------------------------------------------------------------- 35 4.9 Data Transfer Mode ------------------------------------------------------------------------------------ 35 4.9.1 Block Read ----------------------------------------------------------------------------------------------- 37 4.9.2 Block Write ----------------------------------------------------------------------------------------------- 3738------------------------------------------------------------------------------------------------------ 4.9.3 Erase4.9.4 Write Protect Management -------------------------------------------------------------------------- 38 4.9.5 Card Lock/Unlock Operation ------------------------------------------------------------------------ 38----------------------------------------------------------------------------------------------- 41 4.9.6 Responses4.9.7 Status ------------------------------------------------------------------------------------------------------ 42 4.9.8 Command Response Timing ------------------------------------------------------------------------ 4448 4.9.9 Reset------------------------------------------------------------------------------------------------------ 4.10 SPI Communication ----------------------------------------------------------------------------------- 49 4.10.1 Mode Selection ----------------------------------------------------------------------------------------- 49 4.10.2 Bus Transfer Protection ------------------------------------------------------------------------------ 49 4.10.3 Data Read Overview ---------------------------------------------------------------------------------- 50 4.10.4 Data Write Overview ---------------------------------------------------------------------------------- 51 4.10.5 Erase and Write Protect Management ----------------------------------------------------------- 52 4.10.6 Reading CID/CSD Registers ------------------------------------------------------------------------ 53 4.10.7 Reset Sequence --------------------------------------------------------------------------------------- 53 4.10.8 Error Conditions ---------------------------------------------------------------------------------------- 53 4.10.9 Memory Array Partitioning --------------------------------------------------------------------------- 53 4.10.10 Card Lock/Unlock -------------------------------------------------------------------------------------- 53 4.10.11 Commands ----------------------------------------------------------------------------------------------- 54 4.10.12 Responses ----------------------------------------------------------------------------------------------- 56 4.10.13 Data Tokens --------------------------------------------------------------------------------------------- 58 4.10.14 Data Error Token --------------------------------------------------------------------------------------- 59 4.10.15 Clearing Status Bits ------------------------------------------------------------------------------------ 60 4.11 SPI Bus Timing ----------------------------------------------------------------------------------------- 61 4.12 Error Handling ------------------------------------------------------------------------------------------ 64 4.12.1 Error Correction Code (ECC) ----------------------------------------------------------------------- 64 4.12.2 Cyclic Redundancy Check (CRC) ----------------------------------------------------------------- 642 Function Description2.1 Flash Technology IndependenceThe 512 byte sector size of the MultiMediaCard is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the MultiMediaCard. This command contains the address and the number of sectors to write/read. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the MultiMediaCard uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the MultiMediaCard today will be able to access future MultiMediaCards built with new flash technology without having to update or change host software.2.2 Defect and Error ManagementMultiMediaCards contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. MultiMediaCards do a read after write under margin conditions to verify that the data is written correctly (except in the case of a Write without Erase Command). In the rare case that a bit is found to be defective, MultiMediaCards replace this bad bit with a spare bit within the sector header. If necessary, MultiMediaCards will even replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.The MultiMediaCards soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, MultiMediaCards have innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems.These defect and error management systems coupled with the solid-state construction give MultiMediaCards unparalleled reliability2.3 EnduranceMultiMediaCards have an endurance specification for each sector of 1,000,000 writes (reading a logical sector is unlimited). This is far beyond what is needed in nearly all applications of MultiMediaCards. Even very heavy use of the MultiMediaCard in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the typical device’s five year lifetime. For instance, it would take over 100 years to wear out an area on the MultiMediaCard on which a files of any size (from 512 bytes to capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.With typical applications the endurance limit is not of any practical concern to the vast majority of users.2.4 Automatic Sleep ModeAn important feature of the MultiMediaCard is automatic entrance and exit from sleep mode. Upon completion of an operation, the MultiMediaCard will enter the sleep mode to conserve power if no further commands are received within 5 msec The host does not have to take any action for this to occur. In most systems, the MultiMediaCard is in sleep mode except when the host is accessing it, thus conserving power. When the host is ready to access the MultiMediaCard and it is in sleep mode, any command issued to the MultiMediaCard will cause it to exit sleep and respond. The host does not have to issue a reset first. It may do this if desired, but it is not needed. By not issuing the reset, performance is improved through the reduction of overhead.2.5 Hot InsertionSupport for hot insertion will be required on the host but will be supported through the connector. Connector manufacturers will provide connectors that have power pins long enough to be powered before contact is made with the other pins. Please see connector data sheets for more details. This approach is similar to that used in PCMCIA to allow for hot insertion. This applies to both MultiMediaCard and SPI modes.2.6 MultiMediaCard Mode2.6.1 MultiMediaCard Standard ComplianceThe MultiMediaCard is fully compliant with MultiMediaCard standard specification V3.31.The structure of the Card Specific Data (CSD) register is compliant with CSD structure V1.2.2.6.2 Negotiating Operation ConditionsThe MultiMediaCard supports the operation condition verification sequence defined in the MultiMediaCard standard specifications. The MultiMediaCard host should define an operating voltage range that is not supported by the MultiMediaCard. It will put itself in an inactive state and ignore any bus communication. The only way to get the card out of the inactive state is by powering it down and up again. In addition the host can explicitly send the card to the inactive state by using the GO_INACTIVE_STATE command.2.6.3 Card Acquisition and IdentificationThe MultiMediaCard bus is a single master (MultiMediaCard host) and multi-slaves (cards) bus. The host can query the bus and find out how many cards of which type are currently connected. The MultiMediaCard’s CID register is pre-programmed with a unique card identification number which is used during the acquisition and identification procedureIn addition, the MultiMediaCard host can read the card’s CID register using the READ_CID MultiMediaCard command. The CID register is programmed during the MultiMediaCard testing and formatting procedure, on the manufacturing floor. The MultiMediaCard host can only read this register and not write to it.2.6.4 Card StatusMultiMediaCard status is stored in a 32 bit status register which is sent as the data field in the card respond to host commands. Status register provides information about the card’s current state and completion codes for the last host command. The card status can be explicitly read (polled) with the SEND_STATUS command.2.6.7 Data Protection in the Flash CardEvery sector is protected with an Error Correction Code (ECC). The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.The MultiMediaCard can be considered error free and no additional data protection is needed. However, if an application uses additional, external, ECC protection, the data organization is defined in the user writeable section of the CSD register2.6.8 EraseThe smallest erasable unit in the MultiMediaCard is a erase group. In order to speed up the erase procedure, multiple erase groups can be erased in the same time. The erase operation is divided into two stages.Tagging - Selecting the Sectors for ErasingTo facilitate selection, a first command with the starting address is followed by a second command with the final address, and all erase groups within this range will be selected for erase.Erasing - Starting the Erase ProcessTagging can address erase groups. An arbitrary selection of erase groups may be erased at one time. Tagging and erasing must follow a strict command sequence (refer to the MultiMediaCard standard specification for details).2.6.9 Write ProtectionThe MultiMediaCard erase groups are grouped into write protection groups. Commands are provided for limiting and enabling write and erase privileges for each group individually. The current write protect map can be read using SEND_WRITE_PROT command.In addition two, permanent and temporary, card levels write protection options are available.Both can be set using the PROGRAM_CSD command (see below). The permanent write protect bit, once set, cannot be cleared.The One Time Programmable (OTP) characteristic of the permanent write protect bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.10 Copy BitThe content of an MultiMediaCard can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit is set (marked as a copy) it cannot be cleared.The Copy bit of the MultiMediaCard is programmed (during test and formatting on the manufacturing floor) as a copy. The MultiMediaCard can be purchased with the copy bit set (copy) or cleared, indicating the card is a master.The One Time Programmable (OTP) characteristic of the Copy bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.11 The CSD RegisterAll the configuration information of the MultiMediaCard is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contains the host controlled data - the card Copy and write protection and the user ECC register.The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.2.7 SPI ModeThe SPI mode is a secondary (optional) communication protocol offered for MultiMediaCard. This mode is a subset of the MultiMediaCard protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.2.7.1 Negotiating Operation ConditionsThe operating condition negotiation function of the MultiMediaCard bus is not supported in SPI mode. The host must work within the valid voltage range (2.7 to 3.6 volts) of the card.2.7.2 Card Acquisition and IdentificationThe card acquisition and identification function of the MultiMediaCard bus is not supported in SPI mode. The host must know the number of cards currently connected on the bus. Specific card selection is done via the CS signal.2.7.3 Card StatusIn SPI mode only 16 bits (containing the errors relevant to SPI mode) can be read out of the MultiMediaCard status register.2.7.4 Memory Array PartitioningMemory partitioning in SPI mode is equivalent to MultiMediaCard mode. All read and write commands are byte addressable.2.7.5 Read and Write OperationsIn SPI mode, only single block read/write mode is supported.2.7.6 Data Transfer RateIn SPI mode only block mode is supported. The typical access time (latency) for each data block, in read operation, is 1.5mS. The write typical access time (latency) for each data block, in read operation, is 1.5mS. The write block operation is done in handshake mode. The card will keep DataOut line low as long as the write operation is in progress and there are no write buffers available.2.7.7 Data Protection in the MultiMediaCardSame as for the MultiMediaCard mode.2.7.8 EraseSame as in MultiMediaCard mode2.7.9 Write ProtectionSame as in MultiMediaCard modeFigure 3-1 Timing Diagram of Data Input and Output3.5 Physical SpecificationsDimensions of Normal MMC(24mm x 32mm x 1.4mm)Dimensions of RS-MMC(24mm x 18mm x 1.4mm)rising and falling edges). If the host does not allow the switchable R OD implementation, a fix R CMD can be used. Consequently the maximum operating implementation, a fix R CMD can be used. Consequently the maximum operating frequency in the open drain mode has to be reduced in this case.4.4 SPI Bus Topology4.4.1 SPI Interface ConceptThe Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found on certain Motorola micro-controllers. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As any other SPI device the MultiMediaCard SPI channel consists of the following 4 signals:- CS : Host to card chip select signal- CLK : Host to card clock signal- DataIn : Host to card data signal- DataOut : Card to host data signalAnother SPI common characteristic, which is implemented in the MultiMediaCard card as well, is byte transfers. All data tokens are multiples of 8 bit bytes and always byte aligned to the CS signal. The SPI standard defines the physical link only and not the complete data transfer protocol. The MultiMediaCard uses a subset of the MultiMediaCard protocol and command set.4.4.2 SPI Bus TopologyThe MultiMediaCard card identification and addressing algorithms are replaced by hardware Chip Select (CS) signal. There are no broadcast commands. A card (slave) is selected, for every command, by asserting (active low) the CS signal (see Figure 4-3). The CS signal bust is continuously active for the duration of the SPI transaction (command, response and data). The only exception is card-programming time. At this time the host can de-assert the CS signal without affecting the programming process. The bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This eliminates the ability of executing commands while data is being read or written and, therefore, eliminates the sequential and multi block read/write operations. The SPI channel supports only single block read/write.Figure 4-3 SPI Bus SystemReadThe read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay between the end bit of the read command and the start bit of the data block. This number is card dependent and should be used by the host to calculate throughput and the maximal frequency for stream read.WriteThe R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g. SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands). It should be used by the host to calculate throughput.EraseThe duration of an erase command will be (order of magnitude) the number of sectors to be erased multiplied by the block write delay.4.8 Card Identification ModeAll the data communication in the card identification mode uses only the command line (CMD). MultiMediaCard State Diagram (Card Identification Mode)Figure 4-2 MultiMediaCard State Diagram (Card Identification Mode)The host starts the card identification process in open drain mode with the identification clock rate f OD(generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel card operation during card identification. After the bus is activated the host will request the cards to send their valid operation conditions with the command SEND_OP_COND (CMD1). Since the bus is in open drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in the response to the CMD1 a “wired or” operation condition restrictions of those cards. The host then must pick a common denominator for operation and notify the application that cards with out of range parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State (refer to also Chapter “Operating Voltage Range Validation”). The busy bit in the CMD1 response can be used by a card to tell the host that it is still working on its power-up/reset procedure (e.g. downloading the register information from memory field) and is not ready yet for communication. In this case the host must repeat CMD1 until the busy bit is cleared. After an operating mode is established, the host asks all cards for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2).All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bitstream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a relative card address (RCA, shorter than CID), which will be used to address the card in future communication (faster than with the CID). Once the RCA is received the card transfers to the Standby State and does not react to further identification cycles. The card also switches the output drivers from the open-drain to the push-pull mode in this state. The host repeats the identification process as long as it receives a response (CID) to its identification command (CMD2). When no card responds to this command, all cards have been identified. The time-out condition to recognize this, is waiting for the start bit for more than 5 clock periods after sending CMD24.8.1 Operating Voltage Range ValidationThe MultiMediaCard standards operating range validation is intended to support reduced voltage range MultiMediaCards. The MultiMediaCard supports the range of 2.7 V to 3.6V supply voltage. So the MultiMediaCard sends a R3 response to CMD1 which contains an OCR value of 0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter “Responses”). By omitting the voltage range in the command, the host can query the card stack and determine the common voltage range before sending out-of-range cards into the Inactive State. This bus query should be used if the host is able to select a common voltage range or if a notification to the application of non usable cards in the stack is desired. Afterwards, the host must choose a voltage for operation and reissue CMD1 with this condition sending incompatible cards into the Inactive State.4.9 Data Transfer ModeWhen in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f PushPull clock rate is equal to the slow f OpenDrain clock rate. SEND_CSD (CMD9) allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage capacity, maximum clock rate etc..。
DS12887时钟芯片_中文资料_
DS12887时钟芯片(中文资料一)特点·可作为IBM AT 计算机的时钟和日历·与MC14681B 和DS1287的管脚兼容·在没有外部电源的情况下可工作10年·自带晶体振荡器及电池·可计算到2100年前的秒、分、小时、星期、日期、月、年七种日历信息并带闰年补偿·用二进制码或BCD 码代表日历和闹钟信息·有12和24小时两种制式，12小时制时有AM 和PM提示·可选用夏令时模式·可以应用于MOTOROLA 和INTEL 两种总线·数据/地址总线复用·内建128字节RAM14字节时钟控制寄存器114字节通用RAM·可编程方波输出·总线兼容中断（/IRQ ）·三种可编程中断时间性中断可产生每秒一次直到每天一次中断周期性中断122ms 到500ms时钟更新结束中断管脚名称AD0－AD7－地址/数据复用总线 NC －空脚MOT －总线类型选择（MOTOROLA/INTEL ） CS －片选 AS －ALER/W －在INTEL 总线下作为/WR DS －在INTEL 总线下作为/RD RESET －复位信号 IRQ －中断请求输出 SQW －方波输出 VCC －+5电源 GND －电源地上电/掉电当VCC 高于4.25V200ms 后，芯片可以被外部程序操作；当VCC 低于4.25V 时，芯片处于写保护状态（所有的输入均无效），同时所有输出呈高阻状态；当VCC 低于3V 时，芯片将自动把供电方式切换为由内部电池供电。
管脚功能MOT （总线模式选择）当此脚接到VCC 时，选用的是MOTOROLA 总线时序；当它接到地或不接时，选用的是INTEL 总线时序。
SQW（方波输出）－当VCC低于4.25V时没有作用。
周期性中断率和方波中断频率表寄存器A中的控制位RS3 RS2 RS1 RS0 P1周期中断周期SQW输出频率0 0 0 0 无无0 0 0 1 3.90625ms 256Hz0 0 1 0 7.8125ms 128Hz0 0 1 1 122.070μs 8.192kHz0 1 0 0 244.141μs 4.096 kHz0 1 0 1 488.281μs 2.048 kHz0 1 1 0 976.5625μs 1.024 kHz0 1 1 1 1.953125ms 512 Hz1 0 0 0 3.90625 ms 256 Hz1 0 0 1 7.8125 ms 128 Hz1 0 1 0 15.625 ms 64 Hz1 0 1 1 31.25 ms 32 Hz1 1 0 0 62.5 ms 16 Hz1 1 0 1 125 ms 8 Hz1 1 1 0 250 ms 4 Hz1 1 1 1 500 ms2 HzAD0－AD7（双向数据/地址复用总线）AS（地址锁存）ALEDS（Data Strobe or Read Input） RD当系统选择的是INTEL总线模式时，DS被称作RD。
FPGA可编程逻辑器件芯片EP3C120F780C7N中文规格书
Signal Name Direction DescriptionPlatform Designer Interface Name Note: Because the signals are shared, an interface cannot issue or accept a write response and a read response in the same clock cycle.The following encodings are available:•00: OKAY - Successfulresponse for a transaction.•01: RESERVED -Encoding is reserved.•10: SLAVEERROR - Error from an endpoint slave.Indicates an unsuccessful transaction.•11: DECODEERROR -Indicates an attempted access to an undefined location.For read responses:•One response is sentwith each readdata . Aread burst length of N results in N responses. It is not valid to produce fewer responses, even in the event of an error . It is valid for the response signal values to be different for eachreaddata in the burst.•The interface must have read control signals.Pipeline support is possible with thereaddatavalid signal.•On a read error , thecorresponding readdatais a "don't care".4.3.1.4.2. Write Data Mover Avalon-ST Descriptor SinksThe Write Data Mover has two Avalon-ST sink interfaces to receive the descriptors that define the data transfers to be executed. One of the interfaces receives descriptors for normal data transfers, while the other receives descriptors for high-priority data transfers.The descriptor format for the Write Data Mover is described in the section Descriptor Formats for Data Movers .Note: The user application is responsible for performing the scheduling between priority and normal queues. No arbitration is performed inside the Write Data Mover .4.InterfacesUG-20237 | 2021.03.29Send FeedbackTable 34.Write Data Mover Avalon-ST Normal Descriptor Sink Interface Signal Name DirectionDescription Platform Designer Interface Name wrdm_desc_ready_o O When asserted, this readysignal indicates the normal descriptor queue in the Write Data Mover is ready to accept data. The ready latency of this interface is 3cycles.wrdm_descwrdm_desc_valid_i I When asserted, this signalqualifies valid data on any cycle where data is being transferred to the normal descriptor queue. On each cycle where this signal is active, the queue samples the data.wrdm_desc_data_i[173:0]I [173:160]: reserved. Should be tied to 0.[159:152]: descriptor ID[151:149] : application specific[148]: reserved[147]: single source (4)[146]: immediate (5)[145:128]: number of dwords to transfer up to 1MB[127:64]: destination PCIe address[63:0]: source Avalon-MMaddress / immediate data Table 35.Write Data Mover Avalon-ST Priority Descriptor Sink Interface(4)When the single source bit is set, the same source address is used for all the transfers. If the bit is not set, the address increments for each transfer . Note that in single source mode, the PCIe address and Avalon-MM address must be 64-byte aligned.(5)When set, the immediate bit indicates immediate writes. Immediate writes of one or two dwords are supported. For immediate transfers, bits [31:0] or [63:0] contain the payload for one- or two-dword transfers respectively. The two-dword immediate writes cannot cross a 4k boundary.4.InterfacesUG-20237 | 2021.03.29Send FeedbackSignal Name Direction DescriptionPlatform Designer Interface Namedescriptor queue. On each cycle where this signal is active, the queue samples the data.wrdm_prio_data_i[173:0]I [173:160]: reserved. Should be tied to 0.[159:152]: descriptor ID[151:149] : application specific[148]: reserved[147]: single source[146]: immediate[145:128]: number of dwords to transfer up to 1MB[127:64]: destination PCIe address[63:0]: source Avalon-MMaddress / immediate dataThe Write Data Mover internally supports two queues of descriptors. The priority queue has absolute priority over the normal queue, so it should be used carefully to avoid starving the normal queue.If the Write Data Mover receives a descriptor on the priority interface while processing a descriptor from the normal queue, it switches to processing descriptors from the priority queue after it has completed processing the current descriptor . The Write Data Mover resumes processing descriptors from the normal queue once the priority queue is empty. Do not use the same descriptor ID simultaneously in the two queues as there would be no way to distinguish them on the Status Avalon-ST source interface.The Write Data Mover handles one descriptor at a time. When a descriptor has been processed, the Write Data Mover will read the next descriptor from the priority or normal descriptor interface.Note: There is no buffer to store descriptors inside the Write Data Mover . In Intel's DMA design example, the buffer is located in the external DMA controller and supports up to 128 descriptors.Software should only send new descriptors when the Write Data Mover has processed all previously sent descriptors. The Write Data Mover indicates the completion of the its data processing by performing an immediate write to the system memory using the last descriptor in the descriptor table. For more details, refer to the Write DMA Example section in the P-tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example User Guide (see the link in the Related Information below).Related InformationWrite DMA Example4.InterfacesUG-20237 | 2021.03.29Send Feedback。
OPA128JM中文资料
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
1013 || 1 1015 || 2
nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fA, p-p fA/√Hz
Ω || pF Ω || pF
VOLTAGE RANGE(4)
Common-Mode Input Range
±10 ±12
±10 ±12
±10 ±12
±10 ±12
90dB min q IMPROVED REPLACEMENT FOR AD515
S9S08DZ128资料翻译
MC9S08DZ128MC9S08DZ96MC9S08DV128MC9S08DV96数据手册HCS08微处理控制器MC9S08DZ128第一版2008年5月飞思卡尔半导体MC9S08DZ128系列产品的特性8位HCSO8中央处理单元（CPU）•40-MHz HCS08 CPU（20-MHz总线）•HC08指令集，带附加的BGND指令•支持最多32个中断/复位源片内存储器•整个工作电压和温度范围内可读取/编程/擦除的Flash存储器•最大2K的EEPROM在线可编程内存；支持8字节单页或4字节双页擦除分区；执行Flash程序的同时可进行编程和擦除操作；支持擦除取消操作节能模式•两种非常低功耗停止模式•Reduced power wait mode降低功耗等待模式•超低功耗实时中断，在运行、等待和停止模式下均可操作时钟源选项•振荡器（XOSC）—闭环控制的皮尔斯（Pierce）振荡器；支持范围31.25 kHz至38.4 kHz或1 MHz至16MHz之间的晶体或陶瓷谐振器•多功能时钟生成器（MCG）—PLL和FLL模式（在使用内部温度补偿时FLL能够达到1.5%内的偏差）；带微调功能的内部参考时钟源；带可选择晶体振荡器或陶瓷谐振器的外部参考时钟源系统保护•监视微控制器（计算机）看门狗（COP）复位，支持备用专用1KHZ的内部时钟源或总线时钟操作的选项。
带有可选择的视窗化得操作•带复位和中断的低压检测电路；可选择的电压阀值•支持非法指令代码复位•支持非法操作地址复位•支持Flash与EEPROM块保护•支持时钟信号丢失保护开发支持•单线背景调试接口•总线实时捕获功能的上及在线仿真（ICE）外围设备•ADC（模数转换）24通道- 12位分辨率, 2.5μs转换时间, 自动比较功能，温度传感器，包含内部能兮参考源通道•ACMPx—两个模拟比较器，支持比较器输出的上升，下降或任意边缘触发的中断;可选择与内部能隙参考电压源比较；运行在STOP3模式；•MSCAN— CAN协议- Version 2.0 A, B; 支持标准和扩展数据帧；支持远程帧；5个带FIFO 存储框架的接收缓冲器；灵活的接收识别符过滤器，可编程如下：2 x 32位、4 x 16位或8 x 8位•SCIx—两个SCI，可支持LIN 2.0协议和SAE J2602协议；全双工；主节点支持break 信号生成；从节点支持break信号检测；支持激活边沿唤醒•SPIx—多达两个SPIs;全双工或单线双向;双重缓冲发送与接受;主从模式; 支持高位优先或低位优先的移动•IICx—多达两个IICs; 支持最高100kps的总线负载; 多主节点模式运行;可编程的从地址; 通用呼叫地址; 逐字节传输驱动的中断r•TPMx—一个6通道(TPM1), 一2通道(TPM2)和一个4通道(TPM3);可支持输入捕捉, 输出比较, 或每个通道带缓冲的边沿对齐PWM输出。
飞思卡尔MC9S12XS128技术手册翻译AD
飞思卡尔MC9S12XS128技术手册（AD转换部分）英文资料:飞思卡尔MC9S12XS256RMV1官方技术手册1.1 XS12系列单片机的特点XS12系列单片机特点如下：·16位S12CPU—向上支持S12模糊指令集并去除了其中的MEM, WAV, WAVR, REV, REVW 五条指令；—模块映射地址机制（MMC）；—背景调试模块（BDM）；·CRG时钟和复位发生器—COP看门狗；—实时中断；·标准定时器模块—8个16位输入捕捉或输出比较通道；；—16位计数器，8位精密与分频功能；—1个16位脉冲累加器；·周期中断定时器PIT—4具有独立溢出定时的定时器；—溢出定时可选范围在1到2^24总线时钟；—溢出中断和外部触发器；·多达8个的8位或4个16位PWM通道—每个通道的周期和占空比有程序决定；—输出方式可以选择左对齐或中心对其；—可编程时钟选择逻辑，且可选频率范围很宽；·SPI通信模块—可选择8位或16位数据宽度；—全双工或半双工通信方式；—收发双向缓冲；—主机或从机模式；—可选择最高有效为先输出或者最低有效位先输出；·两个SCI串行通信接口—全双工或半双工模式·输入输出端口—多达91个通用I/O引脚，根据封装方式，有些引脚未被引出；—两个单输入引脚；·封装形式—112引脚薄型四边引线扁平封装（LQFP）；—80引脚扁平封装（QFP）；—64引脚LQFP封装；·工作条件—全功率模式下单电源供电范围3.15V到5V；—CPU总线频率最大为40MHz—工作温度范围–40 C到125 C第十章模拟—数字转换10.1 介绍ADC12B16C是一个16通道，12位，复用方式输入逐次逼近模拟—数字转换器。
ATD的精度由电器规格决定。
10.1.1 特点·可设置8位、10位、12位精度·在停止模式下，ATD转换使用内部时钟·转换序列结束后自动进入低耗电模式·可编程采样时间·转化结果可选择左对齐或右对齐·外部触发控制·转换序列结束后产生中断·模拟输入的16个通道为复用方式·可以选择VRH、VRL、 (VRL+VRH)/2特殊转换方式·转换序列长度1到16·可选择连续转换方式·多通道扫描·任何AD通道均可配置外部触发功能，并且可选择4种额外的触发输入。
AT17C128资料
Pin Configurations20-pin PLCC8-Pin DIP20-Pin SOICFeatures•E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories DesignedTo Store Configuration Programs For Programmable Gate Arrays•Simple Interface to SRAM FPGAs Requires Only One User I/O Pin•Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs,XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000•Cascadable To Support Additional Configurations or Future Higher-density Arrays(17C128 and 17C256 only)•Low-power CMOS EEPROM Process•Programmable Reset Polarity•Available In the Space-efficient Plastic DIP or Surface-mountPLCC and SOIC Packages•In-System Programmable Via 2-Wire Bus•Emulation of 24CXX Serial EPROMs•Available in 3.3V ± 10% LV VersionDescriptionThe AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA ConfigurationEEPROMS (Configurator) provide an easy-to-use, cost-effective configuration mem-ory for Field Programmable Gate Arrays. The AT17 Series is packaged in the 8-pinDIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simpleserial-access procedure to configure one or more FPGA devices. The AT17 Seriesorganization supplies enough memory to configure one or multiple smaller FPGAs.Using a special feature of the AT17 Series, the user can select the polarity of the resetfunction by programming a special EEPROM bit.The AT17 Series can be programmed with industry standard programmers.0391E-A–5/97FPGAConfigurationE2PROM65K, 128K and 256KAT17C65AT17C128AT17C256Controlling The AT17 Series Serial EEPROMsMost connections between the FPGA device and the Serial EEPROM are simple and self-explanatory.•The DA TA output of the AT17 Series drives DIN of the FPGA devices.•The master FPGA CCLK output drives the CLK input of the AT17 Series.•The CEO output of any A T17C/LV128/256 drives the CE input of the next A T17C/LV128/256 in a cascade chain of PROMs.•SER_EN must be connected to V CC.There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics wave-forms.Condition 1The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura-tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17 Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configu-ration cycle.Condition 2The FPGA D/P output drives only the CE input of the AT17 Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone High. A High level on the RESET/OE input to the AT17C/LVxxx – during FPGA reset – clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17 Series does not require an inverter since the RESET polarity is programmable.Block DiagramPin ConfigurationsPLCC/SOIC DIP Pin Pin Name I/O Description21DATA I/O Three-state DATA output for reading. Input/Output pin for programming.42CLKIClock input. Used to increment the internal address and bit counter for reading and programming.63RESET/OERESET/Output Enable input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the addresss and bit counters. A logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE.84CEIChip Enable input. Used for device selection. A Low level on both CE and OE enables the data output driver. A High level on CE disables both the address and bit counters and forces te device into a low power mode. Note this pin will not enable/disable the device in 2-wire Serial mode (ie; when SER_EN is Low).105GND Ground Pin 146CEOOChip Enable Out output. This signal is asserted Low on the clock cycle following the last bit read from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until OE goes High. Thereafter CEO will stay High until the entire PROM is read again and senses the status of RESET polarity.A2IDevice selection input, A2. This is used to enable (or select) the device during programming and when SER_EN is Low (see Programming Guide for more details).177SER_EN ISerial enable is normally high during FPGA loading operations. Bringing SER_EN low, enables the 2-wire serial interface for programming.208V CC+3.3V/+5V power supply pin.Absolute Maximum Ratings*Operating Temperature.........................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature............................-65°C to +150°C Voltage on Any Pinwith Respect to Ground....................-0.1V to V CC + 0.5V Supply Voltage (Vcc)..............................-0.5 V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)...260°C ESD (R ZAP = 1.5K, C ZAP = 100pF) (2000V)FPGA Master Serial Mode SummaryThe I/O and logic functions of the FPGA and their associ-ated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA auto-matically loads the configuration program from an external memory. The Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. Cascading Serial Configuration EEPROMs(AT17C/LV128 and AT17C/LV256)For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cas-caded Configurators provide additional memory (17C/ LV128 and 17C/LV256 only).After the last bit from the first Configurator is read, the next clock signal to the Configurator asserts its CEO output Low and disables its DATA line. The second Configurator recog-nizes the Low level on its CE input and enables its DATA output.Figure 1. Condition 1 Connection After configuration is complete, the address counters of all cascaded Configurators are reset if the reset signal drives the RESET/OE on each Configurator Active.If the address counters are not to be reset upon comple-tion, then the RESET/OE inputs can be tied to ground. For more details, please reference the AT17C Series Program-ming Guide.Programming ModeThe programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire interface. The programming is done at V CC supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel's Con-figuration Memories Application Note for further informa-tion. The AT17C Series parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.0V nominal.AT17C/LVXXX Reset PolarityThe AT17C/LVXXX lets the user choose the reset polarity as either RESET/OE or RESET/OE.Standby ModeThe AT17C/LVXXX enters a low-power standby mode whenever CE is asserted High. In this mode, the Configura-tor consumes less than 1.0 mA of current. The output remains in a high impedance state regardless of the stateof the OE input. Operating ConditionsSymbol Description AT17CXXX AT17LVXXXUnits Min/Max Min/MaxV CC CommercialSupply voltage relative to GND-0°C to +70°C4.75/5.25 3.0/3.6V IndustrialSupply voltage relative to GND-40°C to +85C°4.5/5.5 3.0/3.6V MilitarySupply voltage relative to GND-55°C to +125C4.5/5.5 3.0/3.6VV CC = 5V ± 5% Commercial / 5V ± 10% Ind./Mil.Symbol Description Min Max Units V IH High-level input voltage 2.0V CC V V IL Low-level input voltage00.8VV OH High-level output voltage (I OH = -4 mA)Commercial 3.7VV OL Low-level output voltage (I OL = +4 mA)0.32VV OH High-level output voltage (I OH = -4 mA)Industrial 3.6VV OL Low-level output voltage (I OL = +4 mA)0.37VV OH High-level output voltage (I OH = -4 mA)Military 3.5VV OL Low-level output voltage (I OL = +4 mA)0.4V I CCA Supply current, active mode10mA I L Input or output leakage current (V IN = V CC or GND)-1010µAI CCS Supply current, standby mode A T17C256Commercial75µAIndustrial/Military150µA Supply current, standby mode A T17C128/65Commercial1mAIndustrial/Military2mADC CharacteristicsV CC = 3.3V ± 10%Symbol Description Min Max Units V IH High-level input voltage 2.0V CC V V IL Low-level input voltage00.8VV OH High-level output voltage (I OH = -2.5 mA)Commercial 2.4VV OL Low-level output voltage (I OL = +3 mA)0.4VV OH High-level output voltage (I OH = -2 mA)Industrial 2.4VV OL Low-level output voltage (I OL = +3 mA)0.4VV OH High-level output voltage (I OH = -2 mA)Military 2.4VV OL Low-level output voltage (I OL = +2.5 mA)0.4V I CCA Supply current, active mode5mA I L Input or output leakage current (V IN = V CC or GND)-1010µAI CCS Supply current, standby modeCommercial50µA Industrial/Military100µAAC Characteristics When CascadingAC Characteristics for AT17C256V CC = 5V ± 5% Commercial / V CC = 5V ± 10% Ind./Mil.Symbol Description CommercialIndustrial/Military Units MinMax Min MaxT OE (2)OE to Data Delay 2525ns T CE (2)CE to Data Delay 4545ns T CAC (2)CLK to Data Delay5055ns T OH (2)Data Hold From CE, OE, or CLK 0ns T DF (3)CE or OE to Data Float Delay 5050ns T LC CLK Low Time 2020ns T HC CLK High Time2020ns T SCE CE Setup Time to CLK (to guarantee proper counting)3540ns T HCE CE Hold Time to CLk (to guarantee proper counting)00ns T HOE OE High Time (guarantees counter is reset)2020ns F MAXMAX Input Clock Frequency12.512.5MHzAC Characteristics for AT17C256 When CascadingV CC = 5V ± 5% Commercial / V CC = 5V ± 10% Ind./Mil.Notes:1.Preliminary specifications for military operating range only.2.AC test load = 50 pf.3.Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.Symbol DescriptionCommercialIndustrial/Military Units Min Max Min MaxT CDF (3)CLK to Data Float Delay 5050ns T OCK (2)CLK to CEO Delay 3540ns T OCE (2)CE to CEO Delay 3535ns T OOE (2)RESET/OE to CEO Delay3035nsAC Characteristics for AT17C65/128V CC = 5V ± 5% Commercial / V CC = 5V ± 10% Ind./Mil.Symbol Description CommercialIndustrial/Military Units MinMax Min MaxT OE (2)OE to Data Delay 110150ns T CE (2)CE to Data Delay 5050ns T CAC (2)CLK to Data Delay5055ns T OH (2)Data Hold From CE, OE, or CLK 0ns T DF (3)CE or OE to Data Float Delay 5050ns T LC CLK Low Time 3035ns T HC CLK High Time3035ns T SCE CE Setup Time to CLK (to guarantee proper counting)4550ns T HCE CE Hold Time to CLk (to guarantee proper counting)05ns T HOE OE High Time (guarantees counter is reset)5060ns F MAX (4)MAX Input Clock Frequency1010MHzAC Characteristics for AT17C65/128 When CascadingV CC = 5V ± 5% Commercial / V CC = 5V ± 10% Ind./Mil.Notes:1.Preliminary specifications for military operating range only.2.AC test load = 50 pf.3.Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.4.During cascade F MAX = 8 MHz.Symbol DescriptionCommercialIndustrial/Military Units Min Max Min MaxT CDF (3)CLK to Data Float Delay 5050ns T OCK (2)CLK to CEO Delay 6575ns T OCE (2)CE to CEO Delay 5560ns T OE (2)RESET/OE to CEO Delay5555nsAC CharacteristicsV CC = 3.3V ± 10%Notes:1.Preliminary specifications for military operating range only.2.AC test lead = 50 pf.3.Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV afrom steady state active levels.4.During cascade F MAX = 8 MHz.Symbol Description CommercialIndustrial/Military Units Min Max Min MaxT OE (2)OE to Data Delay 4045ns T CE (2)CE to Data Delay 6060ns T CAC (2)CLK to Data Delay7580ns T OH (2)Data Hold From CE, OE, or CLK 0nsT DF (3)CE or OE to Data Float Delay 5555ns T LC CLK Low Time 2525ns T HC CLK High Time2525ns T SCE CE Setup Time to CLK (to guarantee proper counting)3560ns T HCE CE Hold Time to CLk (to guarantee proper counting)00ns T HOE OE High Time (guarantees counter is reset)2525ns F MAX (4)MAX Input Clock Frequency10810MHzAC Characteristics When CascadingV CC = 3.3V ± 10%Symbol DescriptionCommercialIndustrial/Military Units MinMax Min MaxT CDF (3)CLK to Data Float Delay 6060ns T OCK (2)CLK to CEO Delay 5560ns T OCE (2)CE to CEO Delay 5560ns T OOE (2)RESET/OE to CEO Delay4045nsOrdering Information - 5V DevicesMemorySize (K)Ordering Code Package Operation Range64K A T17C65-10PCA T17C65-10JCA T17C65-10SC 8P320J20SCommercial(0°C to 70°C)A T17C65-10PI A T17C65-10JI A T17C65-10SI 8P320J20SIndustrial(-40°C to 85°C)128K A T17C128-10PCA T17C128-10JCA T17C128-10SC 8P320J20SCommercial(0°C to 70°C)A T17C128-10PI A T17C128-10JI A T17C128-10SI 8P320J20SIndustrial(-40°C to 85°C)256K A T17C256-10PCA T17C256-10JCA T17C256-10SC 8P320J20SCommercial(0°C to 70°C)A T17C256-10PI A T17C256-10JI A T17C256-10SI 8P320J20SIndustrial(-40°C to 85°C)Ordering Information - 3.3V DevicesMemorySize (K)Ordering Code Package Operation Range64K A T17LV65-10PCA T17LV65-10JCA T17LV65-10SC 8P320J20SCommercial(0°C to 70°C)A T17LV65-10PI A T17LV65-10JI A T17LV65-10SI 8P320J20SIndustrial(-40°C to 85°C)128K A T17LV128-10PCA T17LV128-10JCA T17LV128-10SC 8P320J20SCommercial(0°C to 70°C)A T17LV128-10PI A T17LV128-10JI A T17LV128-10SI 8P320J20SIndustrial(-40°C to 85°C)256K A T17LV256-10PCA T17LV256-10JCA T17LV256-10SC 8P320J20SCommercial(0°C to 70°C)A T17LV256-10PI A T17LV256-10JI A T17LV256-10SI 8P320J20SIndustrial(-40°C to 85°C) Package Type8P38-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)20J20-Lead, Plastic J-Leaded Chip Carrier (PLCC)20S20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)。
ENA1P-B28-L00128L中文资料(bourns)中文数据手册「EasyDatasheet - 矽搜」
FDM128 用户指南--中文
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章 5 更新和维护 . . . . . . . . . . . . . . . . . . . . . . . . . . .
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软件更新 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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受监控 LV 设备更新 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
本手册中介绍的特性应该与在线显示的那些特性相同。依据我们的持续改进政策，我们将不断修订内容， 使其更加清楚明了，更加准确。如果您发现手册和在线信息之间存在差异，请以在线信息为准。
DOCA0037ZH-01 04/2014
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相关的文件
文件名称 FDM128 8 个低压设备显示屏 - 说明书 IFM LV 断路器的 Modbus-SL 接口 - 说明书 IFE LV 断路器的 Ethernet 接口 - 说明书 IFE LV 断路器的 Ethernet 接口 - 用户指南 （IEC 版本）
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章 3 配置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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先决条件 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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设置向导 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
本文档对所有 FDM128 显示屏 — 8 个低压设备 均有效。 本文档中描述的设备技术特性在网站上也有提供。要在线访问此信息：
HIBC、UCC EAN-128条形码编码知识介绍
• 自己随意打印条码的：绝对不允许； • 产品包装内条码数量的问题：
• 至少在产品的外包装上要有符合规范的条码，其他条码可以通过转 印来解决。
特别申明
• 关于条码质量问题可以询问上海市技术监督局条 码中心。 • 询问条码是否可以解析，请通过我们软硬件进行 检测，方能确定条形码是否准确。 • 如果对《意见》中的具体条款和操作方法有疑 问，请询问上海市食品药品监督管理局。规来自的HIBC条码（日期格式说明）
规范的UCC/EAN-128条码（标示含义）
AI （00） （01） （02） （10） （11） （13） （15） （17） （21） （30） （37） （240） （241） （250） （251） 定义 包装代码 包装代码 包装代码 追溯商品批号 生产日期 包装日期 最短保存期限 最长保存期限 追溯商品序号 内装商品数量 内装商品最大数量 制造商附加识别号 客户编号 第二序号 来源序号 位数 18 14 14 20位内 6 6 6 6 20位内 8位内 8位内 30位内 30位内 30位内 30位内 定长 是 是 是 否 是 是 是 是 否 否 否 否 否 否 否 校验位 有 有 有 否 否 否 否 否 否 否 否 否 否 否 否
条形码编码知识介绍
上海市红十字会
上海市红十字会救灾物资数据中心 上海市红会信息科技有限公司
符合上海市条码规范的标准
• 条码标准：HIBC、 UCC/EAN-128 • 条码、标签要求：
• 产品条码必须包含主条码（产品识别信息）、次条码（追溯信 息）两条条码。 • 中文标签的建议：建议和注册证一致。
规范的UCC/EAN-128次条码
UCC/EAN-128规范条码举例说明（由左至右） 日期信息：6位定长，至少包含生产日期(11)/有效日期 (17) 之一，最好两都有； 追溯信息：不定长，包含SN(21)/LOT(10)两者之一；
LT1790资料
121790faInput Voltage .......................................................... 20V Specified Temperature RangeCommercial............................................ 0°C to 70°C Industrial............................................–40°C to 85°C Output Short-Circuit Duration......................... IndefiniteORDER PART NUMBERLT1790ACS6-1.25LT1790BCS6-1.25LT1790ACS6-2.048LT1790BCS6-2.048LT1790ACS6-2.5LT1790BCS6-2.5LT1790ACS6-3LT1790BCS6-3LT1790ACS6-3.3LT1790BCS6-3.3LT1790ACS6-4.096LT1790BCS6-4.096LT1790ACS6-5LT1790BCS6-5GND 1GND 2 DNC* 36 V OUT 5 DNC*4 V INTOP VIEWS6 PACKAGE6-LEAD PLASTIC SOT-23T JMAX = 150°C, θJA = 230°C/W *DNC: DO NOT CONNECTABSOLUTE AXI U RATI GSW W WU PACKAGE/ORDER I FOR ATIOU U WOperating Temperature Range(Note 2)........................................... –40°C to 125°C Storage Temperature Range(Note 3)........................................... –65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°COUTPUT VOLTAGE S6PART MARKING**The temperature grades and parametric grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.AVAILABLE OPTIO SUTEMPERATURE RANGEOUTPUT INITIAL TEMPERATURE 0°C to 70°C –40°C to 85°C VOLTAGE ACCURACY COEFFICEINT ORDER PART NUMBER ORDER PART NUMBER 1.250V 0.05%10ppm/°C LT1790ACS6-1.25LT1790AIS6-1.250.1%25ppm/°C LT1790BCS6-1.25LT1790BIS6-1.252.048V 0.05%10ppm/°C LT1790ACS6-2.048LT1790AIS6-2.0480.1%25ppm/°C LT1790BCS6-2.048LT1790BIS6-2.0482.500V 0.05%10ppm/°C LT1790ACS6-2.5LT1790AIS6-2.50.1%25ppm/°C LT1790BCS6-2.5LT1790BIS6-2.53.000V 0.05%10ppm/°C LT1790ACS6-3LT1790AIS6-30.1%25ppm/°C LT1790BCS6-3LT1790BIS6-33.300V 0.05%10ppm/°C LT1790ACS6-3.3LT1790AIS6-3.30.1%25ppm/°C LT1790BCS6-3.3LT1790BIS6-3.34.096V 0.05%10ppm/°C LT1790ACS6-4.096LT1790AIS6-4.0960.1%25ppm/°C LT1790BCS6-4.096LT1790BIS6-4.0965.000V0.05%10ppm/°C LT1790ACS6-5LT1790AIS6-50.1%25ppm/°CLT1790BCS6-5LT1790BIS6-5LT1790AIS6-1.25LT1790BIS6-1.25LT1790AIS6-2.048LT1790BIS6-2.048LT1790AIS6-2.5LT1790BIS6-2.5LT1790AIS6-3LT1790BIS6-3LT1790AIS6-3.3LT1790BIS6-3.3LT1790AIS6-4.096LT1790BIS6-4.096LT1790AIS6-5LT1790BIS6-51.250V2.048V 2.500V3.000V 3.300V4.096V5.000VLTXT LTXU LTPZ LTQA LTXW LTQB LTQC(Note 1)31790faPARAMETERCONDITIONS MIN TYP MAX UNITSOutput Voltage (Notes 3, 4)LT1790A 1.24937 1.250 1.25062V –0.050.05%LT1790B 1.24875 1.250 1.25125V –0.100.10%LT1790AC q 1.24850 1.250 1.25150V q –0.1200.120%LT1790AI q 1.24781 1.250 1.25219V q –0.1750.175%LT1790BC q 1.24656 1.250 1.25344V q –0.2750.275%LT1790BIq 1.24484 1.2501.25516V q –0.41250.4125%Output Voltage Temperature Coefficient (Note 5)T MIN ≤ T A ≤ T MAX LT1790A q 510ppm/°C LT1790B q 1225ppm/°C Line Regulation 2.6V ≤ V IN ≤ 18V50170ppm/V q220ppm/V Load Regulation (Note 6)I OUT Source = 5mA, V IN = 2.8V100160ppm/mA q250ppm/mA I OUT Sink = 1mA, V IN = 3.2V120180ppm/mA q250ppm/mAMinimum Operating Voltage (Note 7)V IN , ∆V OUT = 0.1% I OUT = 0mA 1.952.15V q 2.50V I OUT Source = 5mA q 2.90V I OUT Sink = 1mAq2.95V Supply CurrentNo Load3560µA q75µA Minimum Operating Current—V OUT = –1.25V, ±0.1%100125µA Negative Output (See Figure 7)Turn-On Time C LOAD = 1µF 250µs Output Noise (Note 8)0.1Hz ≤ f ≤ 10Hz 10µV P-P 10Hz ≤ f ≤ 1kHz 14µV RMS Long-Term Drift of Output Voltage (Note 9)50ppm/√kHrHysteresis (Note 10)∆T = 0°C to 70°C q 40ppm ∆T = –40°C to 85°Cq100ppmThe q denotes specifications that apply over the specifiedtemperature range, otherwise specifications are at T A = 25°C. C L = 1µF and V IN = 2.6V, unless otherwise noted.1.25V ELECTRICAL CHARACTERISTICS41790faPARAMETERCONDITIONS MIN TYP MAX UNITSOutput Voltage (Notes 3, 4)LT1790A 2.04697 2.048 2.04902V –0.050.05%LT1790B 2.04595 2.048 2.05005V –0.100.10%LT1790AC q 2.04554 2.048 2.05046V q –0.1200.120%LT1790AI q 2.04442 2.048 2.05158V q –0.1750.175%LT1790BC q 2.04237 2.048 2.05363V q –0.2750.275%LT1790BIq 2.03955 2.0482.05645V q –0.41250.4125%Output Voltage Temperature Coefficient (Note 5)T MIN ≤ T A ≤ T MAX LT1790A q 510ppm/°C LT1790B q 1225ppm/°C Line Regulation 2.8V ≤ V IN ≤ 18V50170ppm/V q220ppm/V Load Regulation (Note 6)I OUT Source = 5mA120200ppm/mA q280ppm/mA I OUT Sink = 3mA130260ppm/mA q450ppm/mADropout Voltage (Note 7)V IN – V OUT , ∆V OUT = 0.1% I OUT = 0mA 50100mV q 500mV I OUT Source = 5mA q 750mV I OUT Sink = 3mAq450mV Supply CurrentNo Load3560µA q75µA Minimum Operating Current—V OUT = –2.048V, 0.1%100125µA Negative Output (See Figure 7)Turn-On Time C LOAD = 1µF 350µs Output Noise (Note 8)0.1Hz ≤ f ≤ 10Hz 22µV P-P 10Hz ≤ f ≤ 1kHz 41µV RMS Long-Term Drift of Output Voltage (Note 9)50ppm/√kHrHysteresis (Note 10)∆T = 0°C to 70°C q 40ppm ∆T = –40°C to 85°Cq100ppmThe q denotes specifications that apply over the specifiedtemperature range, otherwise specifications are at T A = 25°C. C L = 1µF and V IN = 2.8V, unless otherwise noted.2.048V ELECTRICAL CHARACTERISTICS51790faPARAMETERCONDITIONS MIN TYP MAX UNITSOutput Voltage (Notes 3, 4)LT1790A 2.49875 2.5 2.50125V –0.050.05%LT1790B 2.4975 2.5 2.5025V –0.100.10%LT1790AC q 2.4970 2.5 2.5030V q –0.1200.120%LT1790AI q 2.49563 2.5 2.50438V q –0.1750.175%LT1790BC q 2.49313 2.5 2.50688V q –0.2750.275%LT1790BIq 2.48969 2.52.51031V q –0.41250.4125%Output Voltage Temperature Coefficient (Note 5)T MIN ≤ T A ≤ T MAX LT1790A q 510ppm/°C LT1790B q 1225ppm/°C Line Regulation 3V ≤ V IN ≤ 18V50170ppm/V q220ppm/V Load Regulation (Note 6)I OUT Source = 5mA80160ppm/mA q250ppm/mA I OUT Sink = 3mA70110ppm/mA q300ppm/mADropout Voltage (Note 7)V IN – V OUT , ∆V OUT = 0.1% I OUT = 0mA 50100mV q 120mV I OUT Source = 5mA q 450mV I OUT Sink = 3mAq250mV Supply CurrentNo Load3560µA q80µA Minimum Operating Current—V OUT = –2.5V, 0.1%100125µA Negative Output (See Figure 7)Turn-On Time C LOAD = 1µF 700µs Output Noise (Note 8)0.1Hz ≤ f ≤ 10Hz 32µV P-P 10Hz ≤ f ≤ 1kHz 48µV RMS Long-Term Drift of Output Voltage (Note 9)50ppm/√kHrHysteresis (Note 10)∆T = 0°C to 70°C q 40ppm ∆T = –40°C to 85°Cq100ppmThe q denotes specifications that apply over the specifiedtemperature range, otherwise specifications are at T A = 25°C. C L = 1µF and V IN = 3V, unless otherwise noted.2.5V ELECTRICAL CHARACTERISTICS61790faPARAMETERCONDITIONS MIN TYP MAX UNITSOutput Voltage (Notes 3, 4)LT1790A 2.99853 3.0015V –0.050.05%LT1790B 2.99703 3.003V –0.100.10%LT1790AC q 2.996403 3.00360V q –0.1200.120%LT1790AI q 2.994753 3.00525V q –0.1750.175%LT1790BC q 2.991753 3.00825V q –0.2750.275%LT1790BIq 2.9876333.01238V q –0.41250.4125%Output Voltage Temperature Coefficient (Note 5)T MIN ≤ T A ≤ T MAX LT1790A q 510ppm/°C LT1790B q 1225ppm/°C Line Regulation 3.5V ≤ V IN ≤ 18V50170ppm/V q220ppm/V Load Regulation (Note 6)I OUT Source = 5mA80160ppm/mA q250ppm/mA I OUT Sink = 3mA70110ppm/mA q300ppm/mADropout Voltage (Note 7)V IN – V OUT , ∆V OUT = 0.1% I OUT = 0mA 50100mV q 120mV I OUT Source = 5mA q 450mV I OUT Sink = 3mAq250mV Supply CurrentNo Load3560µA q80µA Minimum Operating Current—V OUT = –3V, 0.1%100125µA Negative Output (See Figure 7)Turn-On Time C LOAD = 1µF 700µs Output Noise (Note 8)0.1Hz ≤ f ≤ 10Hz 50µV P-P 10Hz ≤ f ≤ 1kHz 56µV RMS Long-Term Drift of Output Voltage (Note 9)50ppm/√kHrHysteresis (Note 10)∆T = 0°C to 70°C q 40ppm ∆T = –40°C to 85°Cq100ppmThe q denotes specifications that apply over the specified temperaturerange, otherwise specifications are at T A = 25°C. C L = 1µF and V IN = 3.5V, unless otherwise noted.3V ELECTRICAL CHARACTERISTICS71790faPARAMETERCONDITIONS MIN TYP MAX UNITSOutput Voltage (Notes 3, 4)LT1790A 3.29835 3.3 3.30165V –0.050.05%LT1790B 3.2967 3.3 3.3033V –0.100.10%LT1790AC q 3.29604 3.3 3.30396V q –0.1200.120%LT1790AI q 3.29423 3.3 3.30578V q –0.1750.175%LT1790BC q 3.29093 3.3 3.30908V q –0.2750.275%LT1790BIq 3.28639 3.33.31361V q –0.41250.4125%Output Voltage Temperature Coefficient (Note 5)T MIN ≤ T A ≤ T MAX LT1790A q 510ppm/°C LT1790B q1225ppm/°C Line Regulation 3.8V ≤ V IN ≤ 18V50170ppm/V q 220ppm/V Load Regulation (Note 6)I OUT Source = 5mA80160ppm/mA q250ppm/mA I OUT Sink = 3mA70110ppm/mA q300ppm/mADropout Voltage (Note 7)V IN – V OUT , ∆V OUT = 0.1% I OUT = 0mA 50100mV q 120mV I OUT Source = 5mA q 450mV I OUT Sink = 3mAq250mV Supply CurrentNo Load3560µA q80µA Minimum Operating Current—V OUT = –3.3V, 0.1%100125µA Negative Output (See Figure 7)Turn-On Time C LOAD = 1µF 700µs Output Noise (Note 8)0.1Hz ≤ f ≤ 10Hz 50µV P-P 10Hz ≤ f ≤ 1kHz 67µV RMS Long-Term Drift of Output Voltage (Note 9)50ppm/√kHrHysteresis (Note 10)∆T = 0°C to 70°C q 40ppm ∆T = –40°C to 85°Cq100ppmThe q denotes specifications that apply over the specifiedtemperature range, otherwise specifications are at T A = 25°C. C L = 1µF and V IN = 3.8V, unless otherwise noted.3.3V ELECTRICAL CHARACTERISTICS81790faPARAMETERCONDITIONS MIN TYP MAX UNITSOutput Voltage (Notes 3, 4)LT1790A 4.094 4.096 4.098V –0.050.05%LT1790B 4.092 4.096 4.10V –0.100.10%LT1790AC q 4.09108 4.096 4.10092V q –0.1200.120%LT1790AI q 4.08883 4.096 4.10317V q –0.1750.175%LT1790BC q 4.08474 4.096 4.10726V q –0.2750.275%LT1790BIq 4.07910 4.0964.11290V q –0.41250.4125%Output Voltage Temperature Coefficient (Note 5)T MIN ≤ T A ≤ T MAX LT1790A q 510ppm/°C LT1790B q 1225ppm/°C Line Regulation 4.6V ≤ V IN ≤ 18V50170ppm/V q220ppm/V Load Regulation (Note 6)I OUT Source = 5mA80160ppm/mA q250ppm/mA I OUT Sink = 3mA70110ppm/mA q300ppm/mADropout Voltage (Note 7)V IN – V OUT , ∆V OUT = 0.1% I OUT = 0mA 50100mV q 120mV I OUT Source = 5mA q 450mV I OUT Sink = 3mAq250mV Supply CurrentNo Load3560µA q80µA Minimum Operating Current—V OUT = –4.096V, 0.1%100125µA Negative Output (See Figure 7)Turn-On Time C LOAD = 1µF 700µs Output Noise (Note 8)0.1Hz ≤ f ≤ 10Hz 60µV P-P 10Hz ≤ f ≤ 1kHz 89µV RMS Long-Term Drift of Output Voltage (Note 9)50ppm/√kHrHysteresis (Note 10)∆T = 0°C to 70°C q 40ppm ∆T = –40°C to 85°Cq100ppmThe q denotes specifications that apply over the specifiedtemperature range, otherwise specifications are at T A = 25°C. C L = 1µF and V IN = 4.6V, unless otherwise noted.4.096V ELECTRICAL CHARACTERISTICS91790faPARAMETERCONDITIONS MIN TYP MAX UNITSOutput Voltage (Notes 3, 4)LT1790A 4.99755 5.0025V –0.050.05%LT1790B 4.9955 5.005V –0.100.10%LT1790AC q 4.994005 5.00600V q –0.1200.120%LT1790AI q 4.991255 5.00875V q –0.1750.175%LT1790BC q 4.986255 5.01375V q –0.2750.275%LT1790BIq 4.9793855.02063V q –0.41250.4125%Output Voltage Temperature Coefficient (Note 5)T MIN ≤ T A ≤ T MAX LT1790A q 510ppm/°C LT1790B q 1225ppm/°C Line Regulation 5.5V ≤ V IN ≤ 18V50170ppm/V q220ppm/V Load Regulation (Note 6)I OUT Source = 5mA80160ppm/mA q250ppm/mA I OUT Sink = 3mA70110ppm/mA q300ppm/mADropout Voltage (Note 7)V IN – V OUT , ∆V OUT = 0.1% I OUT = 0mA 50100mV q 120mV I OUT Source = 5mA q 450mV I OUT Sink = 3mAq250mV Supply CurrentNo Load3560µA q80µA Minimum Operating Current—V OUT = –5V, 0.1%100125µA Negative Output (See Figure 7)Turn-On Time C LOAD = 1µF 700µs Output Noise (Note 8)0.1Hz ≤ f ≤ 10Hz 80µV P-P 10Hz ≤ f ≤ 1kHz 118µV RMS Long-Term Drift of Output Voltage (Note 9)50ppm/√kHrHysteresis (Note 10)∆T = 0°C to 70°C q 40ppm ∆T = –40°C to 85°Cq100ppmThe q denotes specifications that apply over the specified temperaturerange, otherwise specifications are at T A = 25°C. C L = 1µF and V IN = 5.5V, unless otherwise noted.5V ELECTRICAL CHARACTERISTICSNote 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.Note 2: The LT1790 is guaranteed functional over the operating temperature range of –40°C to 125°C. The LT1790-1.25 at 125°C is typically less than 2% above the nominal voltage. The other voltage options are typically less than 0.25% above their nominal voltage.Note 3: If the part is stored outside of the specified temperature range, the output voltage may shift due to hysteresis.Note 4: ESD (Electrostatic Discharge) sensitive device. Extensive use of ESD protection devices are used internal to the LT1790, however, high electrostatic discharge can damage or degrade the device. Use proper ESD handling precautions.Note 5: Temperature coefficient is measured by dividing the change in output voltage by the specified temperature range. Incremental slope is also measured at 25°C.Note 6: Load regulation is measured on a pulse basis from no load to the specified load current. Output changes due to die temperature change must be taken into account separately.Note 7: Excludes load regulation errors.Note 8: Peak-to-peak noise is measured with a single pole highpass filter at 0.1Hz and a 2-pole lowpass filter at 10Hz. The unit is enclosed in a still air environment to eliminate thermocouple effects on the leads. The test time is 10 seconds. Integrated RMS noise is measured from 10Hz to 1kHz with the HP3561A analyzer.1011Output Voltage Noise SpectrumHOURS080017901.25 G102004006001000LT1790S6-1.25V2 TYPICAL PARTS SOLDERED TO PCBT A = 30°C TIME (SEC)0O U T P U T N O I S E (5µV /D I V )817901.2 G12246107135910kIntegrated Noise 10Hz to 1kHz101I N T E G R A T E D N O I S E (µV R M S )101001213Output Voltage Noise SpectrumC L = 1µFI O = 100µA I O = 0µA I O = 250µATIME (SEC)0O U T P U T N O I S E (10µV /D I V )817902.048 G122461071359HOURS80017901.048 G112004006001000T A = 30°C2 TYPICAL PARTS SOLDERED TO PCB Integrated Noise 10Hz to 1kHz(µV R M S )1001415Output Voltage Noise SpectrumTIME (SEC)0O U T P U T N O I S E (10µV /D I V )817901.5 G122461071359T A = 30°C2 TYPICAL PARTS SOLDERED TO PCB Integrated Noise 10Hz to 1kHz101001k 10kC L = 1µFI O = 0µA I O = 1mAI O = 250µAN O I S E (µV R M S )101001617Output Voltage Noise SpectrumTIME (SEC)0O U T P U T N O I S E (20µV /D I V )817905 G122461071359HOURS80017905 G11–200–40–60–802004006001000T A = 30°C2 TYPICAL PARTS SOLDERED TO PCB Intergrated Noise 10Hz to 1kHzC L = 1µFI O = 0µA I O = 250µAE D N O I S E (µV R M S )10001001819202122Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.2324LT/CPI 0202 1.5K REV A • PRINTED IN USA© LINEAR TECHNOLOGY CORPORA TION 2000Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 q FAX: (408) 434-0507 q 。
MC9S12XS128中文资料
飞思卡尔智能汽车竞赛XS128主要模块实验指导书第一章端口整合模块端口A，B和K为通用I/O接口端口E 整合了IRQ，XIRQ中断输入端口T 整合了1个定时模块端口S 整合了2个SCI模块和1个SPI模块端口M 整合了1个MSCAN端口P 整合了PWM 模块，同时可用作外部中断源输入端口H 和J 为通用I/O接口，同时可用作外部中断源输入端口AD 整合了1个16位通道ATD模块大部分I/O引脚可由相应的寄存器位来配置选择数据方向、驱动能力，使能上拉或下拉式装置。
当用作通用IO口时，所有的端口都有数据寄存器和数据方向寄存器。
对于端口T, S, M, P, H, 和J 有基于每个针脚的上拉和下拉控制寄存器。
对于端口AD 有基于每个针脚的上拉寄存器。
对于端口A、B、E 和K，有一个基于端口的上拉控制寄存器。
对于端口T, S, M, P, H, J, 和AD，有基于每个针脚的降额输出驱动控制寄存器。
对于端口A, B, E, 和K，有一个基于端口的降额输出驱动控制寄存器。
对于端口S、M，有漏极开路（线或）控制寄存器。
对于端口P、H 和J，有基于每个针脚的中断标志寄存器。
纯通用IO端口共计有41个，分别是：PA[7:0]PB[7:0]PE[6:5]PE[3:2]PK[7,5:0]PM[7:6]PH[7:0] (带中断输入)PJ[7:6] (带中断输入)PJ[1:0] (带中断输入)第二章脉冲宽度调制模块XS128具有8位8通道的PWM，相邻的两个通道可以级联组成16位的通道。
PWME：PWM通道使能寄存器。
PWMEx=1将立即使能该通道PWM波形输出。
若两个通道级联组成一个16位通道，则低位通道（通道数大的）的使能寄存器成为该级联通道的使能寄存器，高位通道（通道数小的）的使能寄存器和高位的波形输出是无效的。
PWMPOL：PWM极性寄存器。
PPOLx=1，则该通道的周期初始输出为高电平，达到占空比后变为低电平；相反，若PPOLx=0，则初始输出为低电平，达到占空比后变为高电平。
MT55L128L18P资料
2MbZBT ® SRAMMT55L128L18P1, MT55L64L32P1,MT55L64L36P13.3V V DD , 3.3V I/OFUNCTIONAL BLOCK DIAGRAM128K x 18FUNCTIONAL BLOCK DIAGRAM64K x 32/36NOTE:Functional Block Diagrams illustrate simplified device operation. See truth tables, pin descriptions and timing diagrams for detailed information.cycle. For example, if a WRI TE cycle begins in clock cycle one, the address is present on rising edge one. BYTE WRITEs need to be asserted on the same cycle as the address. The data associated with the address is required two cycles later, or on the rising edge of clock cycle three.Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During a BYTE WRI TE cycle, BWa#controls DQa pins; BWb# controls DQb pins; BWc#controls DQc pins; and BWd# controls DQd pins. Cycle types can only be defined when an address is loaded,i.e., when ADV/LD# is LOW. Parity/ECC bits are only available on the x18 and x36 versions.Micron’s 2Mb ZBT SRAMs operate from a +3.3V V DD power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays.Please refer to Micron’s Web site (/datasheets/zbtds.html ) for the latest data sheet.(ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc# and BWd#) and read/write (R/W#).Asynchronous inputs include the output enable (OE#, which may be tied LOW for control signal mini-mization), clock (CLK) and snooze enable (ZZ, which may be tied LOW if unused). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. MODE may be tied HIGH, LOW or left unconnected if burst is unused. The data-out (Q),enabled by OE#, is registered by the rising edge of CLK.WRITE cycles can be from one to four bytes wide as controlled by the write control inputs.All READ, WRITE, and DESELECT cycles are initi-ated by the ADV/LD# input. Subsequent burst ad-dresses can be internally generated as controlled by the burst advance pin (ADV/LD#). Use of burst mode is optional. I t is allowable to give an address for each individual READ and WRITE cycle. BURST cycles wrap around after the fourth access from a base address.To allow for continuous, 100 percent use of the data bus, the pipelined ZBT SRAM uses a LATE LATE WRITEGENERAL DESCRIPTION (continued)PIN ASSIGNMENT TABLE* Pins 50, 83, and 84 are reserved for address expansion.PIN ASSIGNMENT (Top View)100-Pin TQFPSASANF**NF** ADV/LD# OE# (G#)CKE#R/W#CLKV SSV DDCE2#BWa#BWb#NCNCCE2CE#SASASANCNCVDDQVSSNCDQPaDQaDQaVSSVDDQDQaDQaVSSVDDVDDZZDQaDQaVDDQVSSDQaDQaNCNCVSSVDDQNCNCNCNC/SA**SASASASASASADNUDNUV DDV SSDNUDNUSA0SA1SASASASAMODE(LBO#) NCNCNCVDDQVSSNCNCDQbDQbVSSVDDQDQbDQbVDDVDDVDDVSSDQbDQbVDDQVSSDQbDQbDQPbNCVSSVDDQNCNCNCSASANF**NF** ADV/LD# OE# (G#)CKE#R/W#CLKV SSV DDCE2#BWa#BWb#BWc#BWd#CE2CE#SASANC/DQPb*DQbDQbVDDQVSSDQbDQbDQbDQbVSSVDDQDQbDQbVSSVDDVDDZZDQaDQaVDDQVSSDQaDQaDQaDQaVSSVDDQDQaDQaNC/DQPa*NC/SA**SASASASASASADNUDNUV DDV SSDNUDNUSA0SA1SASASASAMODE(LBO#) NC/DQPc*DQPcDQcVDDQVSSDQcDQcDQcDQcVSSVDDQDQcDQcVDDVDDVDDVSSDQdDQdVDDQVSSDQdDQdDQdDQdVSSVDDQDQdDQdNC/DQPd**NC for x32 version, DQPx for x36 version.**Pins 50, 83, and 84 are reserved for address expansion.PIN DESCRIPTIONSPIN DESCRIPTIONS (continued)PIN LAYOUT (TOP VIEW) 165-PIN FBGAA B C D E F G H J K L M N P RABCDEFGHJKLMNPR2TOP VIEW345678910111ABCDEFGHJKLMNPRABCDEFGHJKLMNPR2TOP VIEW345678910111x18x32/x36*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.FBGA PIN DESCRIPTIONS(continued on next page)FBGA PIN DESCRIPTIONS (continued)(continued on next page)FBGA PIN DESCRIPTIONS (continued)INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)LINEAR BURST ADDRESS TABLE (MODE = LOW)PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)NOTE:Using R/W# and byte write(s), any one or more bytes may bewritten.PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)NOTE:Using R/W# and byte write(s), any one or more bytes may be written.State Diagram for ZBT SRAMNOTE: 1.A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks theclock (CLK) input and does not change the state of the device.KEY:TRUTH TABLE(Notes 5-10)NOTE: 1.CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle is executed first.2.DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.A WRITE ABORT means a WRITE command is given, but no operation is performed.3.OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn offthe output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet anapplication’s requirements.4.If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If itoccurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK EDGE cycle.5.X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.6.BWa# enables WRITEs to Byte “a” (DQa pins); BWb# enables WRITEs to Byte “b” (DQb pins); BWc# enables WRITEs toByte “c” (DQc pins); BWd# enables WRITEs to Byte “d” (DQd pins).7.All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.8.Wait states are inserted by setting CKE# HIGH.9.This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.10.The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.11.The address counter is incremented for all CONTINUE BURST cycles.ABSOLUTE MAXIMUM RATINGS*Voltage on V DD SupplyRelative to V SS ...............................-0.5V to +4.6V Voltage on V DD Q SupplyRelative to V SS ...................................-0.5V to V DDV IN ...........................................-0.5V to V DD Q + 0.5V Storage Temperature (plastic)............-55°C to +150°C Junction Temperature**...................................+150°C Short Circuit Output Current...........................100mA*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.**Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information.DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS(0°C ≤ T A ≤ +70°C; V DD , V DD Q = +3.3V ±0.165V unless otherwise noted)NOTE: 1.All voltages referenced to V SS (GND).2.Overshoot:V IH ≤ +4.6V for t ≤ t KHKH/2 for I ≤ 20mA Undershoot:V IL ≥ -0.7V for t ≤ t KHKH/2 for I ≤ 20mA Power-up:V IH ≤ +3.465V and V DD ≤ 3.135V for t ≤ 200ms 3.MODE pin has an internal pull-up, and input leakage = ±10µA.4.The load used for V OH , V OL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request.5.V DD Q should never exceed V DD . V DD and V DD Q can be externally wired together to the same power supply.TQFP CAPACITANCEFBGA CAPACITANCEI DD OPERATING CONDITIONS AND MAXIMUM LIMITS(0°C ≤ T A≤ +70°C; V DD, V DD Q = +3.3V ±0.165V unless otherwise noted)TQFP THERMAL RESISTANCEFBGA THERMAL RESISTANCENOTE: 1.I DD is specified with no output current and increases with faster cycle times. I DD Q increases with faster cycle times and greater output loading.2.“Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means deviceis active (not in deselected mode).3.Typical values are measured at 3.3V, 25°C, and 10ns cycle time.4.This parameter is sampled.5.Preliminary package data.AC ELECTRICAL CHARACTERISTICS(Notes 6, 8, 9) (0°C ≤ T A≤ +70°C; V DD, V DD Q = +3.3V ±0.165V)NOTE: 1.Measured as HIGH above V IH and LOW below V IL.2.Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.3.This parameter is sampled.4.Output loading is specified with C L = 5pF as shown in Figure 2.5.Transition is measured ±200mV from steady state voltage.6.OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system forturnaround timing.7.This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLKwhen they are being registered into the device. All other synchronous inputs must meet the setup and hold timeswith stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD# is LOW to remain enabled.8.Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.9.A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle isdefined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.AC TEST CONDITIONSInput pulse levels...................................V SS to 3.0V Input rise and fall times..................................1.0ns Input timing reference levels..........................1.5V Output reference levels...................................1.5V Output load.............................See Figures 1 and 2Q50V = 1.5VTFigure 1Q3175pF+3.3VFigure 2LOAD DERATING CURVESThe Micron 128K x 18, 64K x 32, and 64K x 36 ZBTSRAM timing is dependent upon the capacitive loadingon the outputs.Consult the factory for copies of I/O current versusvoltage curves.Output Load EquivalentsSNOOZE MODESNOOZE MODE is a low-current, “power-down”mode in which the device is deselected and current is reduced to I SB 2Z . The duration of SNOOZE MODE is dictated by the length of time the ZZ pin is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z.The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. Whenthe ZZ pin becomes a logic HIGH, I SB 2Z is guaranteed after the time t ZZI is met. Any READ or WRITE opera-tion pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore,SNOOZE MODE must not be initiated until valid pend-ing operations are completed. Similarly, when exiting SNOOZE MODE during t RZZ, only a DESELECT or READ cycle should be given.SNOOZE MODE ELECTRICAL CHARACTERISTICSSNOOZE MODE WAVEFORMINOTE:1.This parameter is sampled.NOTE: 1.For this waveform, ZZ is tied LOW.2.Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.3.CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.4.Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most READ/WRITE TIMINGREAD/WRITE TIMING PARAMETERSNOP, STALL, AND DESELECT CYCLESNOP, STALL AND DESELECT TIMING PARAMETERSNOTE: 1.The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not performed during this cycle.2.For this waveform, ZZ and OE# are tied LOW.3.CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.4.Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most165-PIN FBGANOTE: 1.All dimensions in millimeters MAX or typical where noted.MIN2.Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.100-PIN PLASTIC TQFP (JEDEC LQFP)0.10 +0.10 -0.05DETAIL ANOTE: 1.All dimensions in millimeters MAX or typical here noted.MIN2.Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm perside.8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@, Internet: , Customer Comment Line: 800-932-4992Micron is a registered trademark of Micron Technology, Inc.ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc.,and the architecture is supported by Micron Technology, Inc., and Motorola Inc.REVISION HISTORYRemoved FBGA Part Marking Guide, REV 8/00, FINAL........................................................................August/22/00 Changed FBGA capacitance values, REV 8/00, FINAL.............................................................................August/7/00 C I; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pFC O; TYP 4pF from 6pF; MAX. 5pF from 7pFC CK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pFRemoved IT References, REV 7/00, FINAL.....................................................................................................July/10/00 Added FBGA Part Marking GuideAdded Revision History to DatasheetRemoved IT from Part Number Example, REV 6/00, FINAL.......................................................................June/21/00 Added # of datalines to the databus in x32/36 Block DiagramChanged tKQLZ from 4.0ns MIN to 1.5ns MINAdded Note - “Preliminary Package Data” to FBGA Capacitance and Thermal Resistance TablesChanged heading on Mechanical Drawing from BGA to FBGAAdded 165-Pin FBGA package, REV 3/00, FI NAL.......................................................................................May/23/00 Added PRELI MI NARY PACKAGE DATA to diagram。
AT90CAN128中文资料
特点•高性能，低功耗的A VR ® 8位微控制器•先进的RISC结构- 133 - 最强大的单时钟周期指令执行- 32个8位通用工作寄存器+外设控制寄存器- 全静态工作- 高达16 MIPS的吞吐量为16兆赫- 片2周期乘法器•非挥发性程序和数据存储器- 在系统内32K/64K/128K字节可重编程闪存（A T90CAN32/64/128）•耐久性：10,000写入/擦除周期- 可选启动代码段与独立锁定位•可选启动大小：1K字节，2K字节，4K字节或8K 字节•在系统编程的片上引导程序（CAN总线，UART 的，...）•真正的了解，同时，写操作- 1K/2K/4K字节的EEPROM（耐力：100,000写入/擦除周期）（A T90CAN32/64/128）- 2K/4K/4K字节内部SRAM（AT90CAN32/64/128）- 高达64K字节可选外部存储空间- 编程软件安全锁•JTAG接口（IEEE标准。
1149.1兼容）接口- 边界扫描功能根据JTAG标准- 编程闪存（硬件的ISP）的EEPROM，熔丝位和锁定- 广泛的片上调试支持•CAN控制器的电流及2.0B - 的ISO 16845认证（1）- 15个具有独立完整的邮件对象标识标签和面具- 发送，接收，自动回复和帧缓冲区接收模式- 1Mbits / s的8 MHz的最大传输速率- 冲压时，公车及听力模式（间谍或自动波特）•外设特点- 可编程看门狗定时器，带有片上振荡器- 8位同步Timer/Counter-0•10位预分频器•外部事件计数器•输出比较或8位PWM输出- 8位异步Timer/Counter-2•10位预分频器•外部事件计数器•输出比较或8位PWM输出•32kHz振荡器实时时钟运行- 双通道16位同步Timer/Counters-1＆3 •10位预分频器•输入捕获噪声抵消•外部事件计数器•3输出比较或16位PWM输出•输出比较调制- 8通道，10位SAR ADC•8个单端通道•7个差分通道•2个差分通道，再加上1倍，10倍，或200x中可编程增益- 片内模拟比较器- 字节为导向的两线串行接口- 双可编程串行的USART- 主/从SPI串行接口•编程闪存（硬件的ISP）•特殊的处理器特点- 上电复位和可编程欠压检测- 内部RC振荡器校准- 8个外部中断源- 5睡眠模式：空闲，ADC噪声降低，电力保存，掉电和待机- 软件可选的时钟频率- 全球拉禁用•I / O和软件包- 53可编程I / O口线- 64引脚TQFP和64引脚QFN封装•工作电压：2.7 - 5.5V的•工作温度：工业（-40 °C至+85℃）•最大工作频率：在2.7V 8兆赫，16兆赫在4.5V 注：1。
HA17358中文资料
R1
Q11
Q13
Q10
Q12
Vout
2
HA17358, HA17904 Series
Absolute Maximum Ratings (Ta = 25°C)
Ratings
Item
HA17358 HA17358 HA17904 HA17904 HA17904 HA17904 HA17904
Symbol
dB RL = ∞, RS = 1kΩ, Rf = 100kΩ dB RS = 50Ω, Rf = 5kΩ
V
RS = 1kΩ, Rf = 100kΩ
V V
mA mA µA
mA V/µs dB
RS = 1kΩ, Rf = 100kΩ f = 100Hz, RL = 20kΩ, RS = 1kΩ, Rf = 100kΩ VIN+ = 1V, VIN– = 0V, VOH = 10V VIN– = 1V, VIN+ = 0V, VOL = 2.5V VIN– = 1V, VIN+ = 0V, Vout = 200mV
*Dimension including the plating thickness Base material dimension
0.15 0.12 M
6.50
+ –
0.25 0.15
1.05
0.60
+ –
0.25 0.18
0° – 8°
Hitachi Code JEDEC EIAJ Mass (reference value)
–20 to –20 to –20 to –20 to –40 to –40 to –40 to °C
+75