DS8913中文资料

TL F 7398DS8911 DS8913AM FM TV Sound Up-Conversion Frequency SynthesizerApril 1990DS8911 DS8913AM FM TV Sound Up-Conversion Frequency SynthesizerGeneral DescriptionThe DS8911is a digital Phase-Locked Loop (PLL)frequen-cy synthesizer intended for use as a Local Oscillator (LO)in electronically tuned radios The device is used in conjunc-tion with a serial data controller a loop filter some varactor diodes and several passive elements to provide the local oscillator function for both AM and FM tuningThe conventional superheterodyne AM receiver utilizes a low IF or down conversion tuning approach whereby the IF is chosen to be below the frequencies to be received The DS8911PLL on the other hand utilizes an up-conversion technique in the AM mode whereby the first IF frequency is chosen to be well above the RF frequency range to be tuned This approach eliminates the need for tuned circuits in the AM frontend since the image half IF and other spuri-ous responses occur far beyond the range of frequencies to be tuned Sufficient selectivity and second IF image protec-tion is provided by a crystal filter at the output of the first mixerA significant cost savings can be realized utilizing this up-conversion approach to tuning Removal of the AM tuned circuits eliminates the cost of expensive matched varactor diodes and reduces the amount of labor required for align-ment down from 6adjustments to 2 Additional cost savings are realized because up-conversion enables both the AM and FM bands to be tuned using a single Voltage Controlled Oscillator (VCO)operating between 98and 120MHz (The 2to 1LO tuning range found in conventional AM down con-version radios is reduced to a 10%tuning range 9 94MHz to 11 02MHz)Up-conversion AM tuning is accomplished by first dividing the VCO signal down by a modulus 10to obtain the LO signal This LO in turn is mixed on chip with the RF signal to obtain a first IF at the MIXER output pins This first IF after crystal filtering is mixed (externally)with a reference fre-quency provided by the PLL to obtain a 450kHz second IFfrequency The DS8911derives the 450kHz second IF by mixing an 11 55MHz first IF with a 12 00MHz reference frequencyFM and WB (weather band)tuning is done using the con-ventional down conversion approach Here the VCO signal is buffered to produce the LO signal and then mixed on chip with the RF signal to obtain an IF frequency at the MIXER output pins This IF frequency is typically chosen to be 10 7MHz although placement at 11 50MHz can further enhance AM mode performance and minimize IF circuitryThe PLL provides phase comparator reference frequencies of 10 12 5 25 and 100kHz The tuning resolutions result-ing from these reference frequencies are determined by di-viding the reference by the premix modulus Table II shows the tuning resolutions possibleThe DS8911contains the following logic elements a volt-age controlled oscillator a reference oscillator a 14-bit pro-grammable dual-modulus counter a reference frequency di-vider chain a premix divider a mixer a phase comparator a charge pump an operational amplifier and control circuitry for latched serial data entryThe DS8913includes all the above logic elements except that it requires a 10MHz reference frequency instead of 12MHzFeaturesY Direct synthesis of LW MW SW FM and WB frequenciesY Serial data entry for simplified processor control Y 10 12 5 25 and 100kHz reference frequencies Y 8possible tuning resolutions (see Table II)Y An op amp with high impedance inputs for loop filtering YProgrammable mixer with high dynamic rangeTRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRE TM is a trademark of National Semiconductor Corporation C 1995National Semiconductor CorporationRRD-B30M105 Printed in U S AConnection DiagramPlastic Chip CarrierTL F 7398–8Top ViewOrder Number DS8911V DS8913VSee NS Package Number V28APin DescriptionsV CC1 The V CC1pin provides a5V supply source for all circuitry except the reference divider chain op amp and mix-er sections of the dieV CC2 The V CC2pin provides a12V supply source for the Op ampV CCL The V CCL pin provides an isolated5V supply source for the premix divider and mixer functionsV CCM The V CCM pin provides a5V supply source for the reference oscillator and divider chain down through the50 Hz output thus enabling low standby current for time-of-day clock applicationsGND1 GND2 GNDL and GNDM Provide isolated circuit ground for the various sections of the deviceDATA and CLOCK The DATA and CLOCK inputs are for serial data entry from a controller They are CMOS inputs with TTL logic thresholds The24-bit data stream is loaded into the PLL on the positive transition of the CLOCK The first14bits of the data stream select PLL divide code in binary form MSB first The15th through24th bits select the premix modulus the reference frequency the bit output status and the test operate modes as shown in Tables I through VENABLE The ENABLE input is a CMOS input with a TTL logic threshold The ENABLE input enables data when at a logic‘‘one’’and latches data on the transition to a logic ‘‘zero’’BIT Outputs The open-collector BIT outputs provide either the status of shift register bits22 23 and24or enable access to key internal circuit test nodes The mode for the bit outputs is controlled by shift register bits20and21 In operation the bit outputs are intended to drive radio func-tions such as gain mute and AM FM status These outputs can also be used to program the loop gain by connection of an external resistor to IPROG Bit24output can also be used as a300millisecond timer under control of shift regis-ter bit19 During service testing these pins can be used for the purpose of either monitoring or driving internal logic points as indicated in the TEST MODES description under Table VVCOb and VCOe The Voltage Controlled Oscillator inputs drive the14-bit programmable counter and the premix divid-er These inputs are the base and emitter leads of a transis-tor which require connection of a coil varactor and several capacitors to function as a Colpitts oscillator The VCO is designed to operate up to225MHz The VCO’s minimum operating frequency may be limited by the choice of refer-ence frequency and the961minimum modulus constraint of the31 32dual modulus counterRF a and RF b The Radio Frequency inputs are fed differ-entially into the mixerIMXR The bias current for the mixer is programmed by con-nection of an external resistor to this pin The total mixer output current equals4times the current entering this pin MIXER and MIXER The MIXER outputs are the collectors of the double balanced pair mixer transistors They are in-tended to operate at voltages greater than V CC1OSCb and OSCc The Reference Oscillator inputs are part of an on-chip Pierce oscillator designed to work in conjunc-tion with2capacitors and a crystal resonator The DS8911 requires a12MHz crystal to derive the reference frequen-cies shown in Table II The DS8913requires10MHz crystal The12MHz OSC signal is also used externally as the2nd AM LO to obtain a450kHz2nd IF frequency in the AM mode2MHz The2MHz output is provided to drive a controller’s clock input50Hz The50Hz output is provided as a time reference for radios with time-of-day clocksIPROG The IPROG pin enables the charge pump to be programmed from0 25mA to1 0mA by connection of an external resistor to groundCPO The Charge Pump Output circuit sources current if the VCO frequency is high and sinks current if the VCO frequen-cy is low The CPO is wired directly to the negative input of the loop filter op ampOP AMP The OP AMP output is provided for loop filtering The op amp has high impedance PMOS gate inputs and is wired as a transconductance amplifier filter The op amp’s positive input is internally referenced while its negative input is common with the CPO output2Reference TablesTABLE IBit15Premix Modulus0d11d10TABLE IIBit Reference Tuning Resolution 1617Frequency d1Premix d10Premix 0010kHz10kHz1kHz 0112 5kHz12 5kHz1 25kHz 1025kHz25kHz2 5kHz 11100kHz100kHz10kHzTABLE IIIBit18Mode0Normal Operation1Production Test Mode OnlyThe user should always load Bit18lowTABLE IVBit19Timer0Bit24Status1Bit24for300msTIMER OPERATIONThe timer function is provided for use as a retriggerable ‘‘one shot’’to enable muting for approximately300millisec-onds after station changes The timer is enabled at bit24’s output if the normal operating mode is selected(shift regis-ter bits20and21e‘‘LOW’’)and shift register bit19data is latched as a‘‘HI’’ The timer’s output state will invert imme-diately upon latching bit19‘‘HI’’and remain inverted for approximately300milliseconds If the user readdresses the device with bit19data‘‘LOW’’before the timer finishes itscycle the timer’s BIT24output will finish out the300ms pulse Readdressing the device with bit19‘‘HI’’before the timer finishes its cycle will extend the BIT24output pulse width by300ms Addressing should be performed immedi-ately after the50Hz output transitions‘‘HI’’ BIT24’s output state is not guaranteed during the first300ms after V CC1 power up as a result of a timer reset in progressTABLE VBit FUNCTION OF2021PINS3 4 500Status of Bits22-2401Test mode110Test mode211Test mode3 TEST MODE OPERATIONTest Mode1 Enables the BIT output pins to edge trigger the phase comparator inputs and monitor an internal lock detector BIT22negative edge triggers the reference divid-er input of the phase comparator if the reference divider state is low BIT23provides the open collector ORing of the phase comparator’s pump up and down outputs BIT24 negative edge triggers the N counter input of the phase comparator if the N counter state is preconditioned lowTest Mode2 Enables the BIT outputs to clock the pro-grammable N counter monitor its output and force either its load or count condition BIT22provides the N counter out-put which negative edge triggers the phase comparator and which appears low one N counter clock pulse before it re-loads BIT23positive edge triggers the N counter’s clock input if the prescaler’s output is preconditioned HI BIT24 clears the N counter output so that loading will occur on the next N counter clock edgeTest Mode3 Enables the BIT outputs to clock the50Hz and10kHz reference dividers and monitor the reference divider input to the phase comparator BIT22positive edge clocks the10kHz reference divider chain if the10kHz out-put is preconditioned HI BIT23positive edge clocks the50 Hz divider chain BIT24is the reference divider negative edge trigger input to the phase comparator3Absolute Maximum Ratings(Note1)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply VoltageV CCM7V V CC17V V CC215V Input Voltage7V Output VoltageLogic7V Op Amp and Mixer Outputs15V ESD Sensitivity1000V Storage Temperature Range b65 C to a150 C Lead Temp (Soldering 10seconds)300 C Operating ConditionsMin Max Units V CCM3 55 5VV CC14 55 5VV CC27 012 0V Temperature T A b40a85 C Mixer I BIAS(Mixer a Mixer Current)120mADC Electrical Characteristics(Notes2and3)Symbol Parameter Test Conditions Min Typ Max Units V IH Logic‘‘1’’Input Voltage2 0VV IL Logic‘‘0’’Input Voltage0 8VI IH Logic‘‘1’’Input Current V IN e5 5V10m A I I Logic‘‘1’’Input Current Data Clock and Enable Inputs V IN e7V100m A I IL Logic‘‘0’’Input Current Data Clock and Enable Inputs V IN e0V b10m A V OH Logic‘‘1’’2MHz I OH e b20m A V CCM b0 3V Output VoltageI OH e b400m A V CCM b2VOp Amp I OH e b1 0mA V CC2b1 5VV OL Logic‘‘0’’2MHz I OL e20m A0 3V Output VoltageI OL e400m A0 4V50Hz I OL e250m A0 3VBit Outputs I OL e1mA0 3VOp Amp I OL e1 0mA1 5VV BIAS Op Amp Input V D Op Amp I O Shorted V CC1e5 5V V CC2e12V 200mVCPO e TRI-STATE Op Amp I OH vs I OL AppliedI CEX High Level Bit Outputs V CC1e4 5V V O e8 8V100m AOutput Current50Hz V CCM e3 5V V O e5 5V10m AMixers V CCL e V CC1e4 5V V O e12V100m A I CPO Charge Pump Program0 25mA k I CPO k1 0mA Pump-up b302I PROG a30%Current2I PROG e V CC1 R PROGPump-down b302I PROG a30%Measured I PROG to CPOTRI-STATE0100nA I CCM V CCM Supply Current V CCM e5 5V OSCC e High0 51 0mA(Static)I CC1a V CC1a V CCL V CC e5 5V Bits Hi I MXR and I PROG Open2535mA I CCL Supply CurrentI CC2V CC2Supply Current V CC2e12V1 52 5mA Mixer Mixer a Mixer V CC1e V CCL e5 5V Mixer e Mixer e12V b254IMXR a25% I BIAS Current(Note4)RF IN Mixer Input Max Mixer I BIAS e20mA300mVrms Signal Level RF a or RF b Signal LevelNote1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Temperature Range’’ they are not meant to imply that the device should be operated at these limitsNote2 Unless otherwise specified min max limits apply across the b40 C to a85 C temperature rangeNote3 All currents into device pins are shown as positive out of device pins as negative all voltage referenced to ground unless otherwise noted All values shown as maximum or minimum on absolute value basisNote4 Total mixer output current(Mixer a Mixer)j4times the current into the I MXR pin4AC Electrical Characteristics(Note2)Symbol Parameter Conditions Min Typ Max Units t r20%–80%Rise Time200ns t f80%–20%Fall Time200ns DATA SU Data Setup Time100ns DATA H Data Hold Time100nsV CC1e4 5V to5 5VEN SU Enable Setup Time100ns EN H Enable Hold Time100ns EN PW a Enable Positive Pulse Width200ns CLK PW a Clock Positive Pulse Width200ns CLK PW b Clock Negative Pulse Width200ns VCO f max VCO Max Frequency See Typical Wiring Diagram20225MHz OSC f max Reference Oscillator V CCM e3 5V12MHz Max FrequencyTiming DiagramTL F 7398–10 MICROWIRE TM Bus FormatTL F 7398–195TABLE VI DS8911Tuning CharacteristicsIF Tuning VCOPremix Reference TuningImageMode Frequency Range RangeModulus Frequency Resolution(MHz)(MHz)(MHz)(MHz)(kHz)(kHz)LW11 55 450 145– 290112 4–114 11010122–23 MW11 55 450 515–1 6199 4–110 21010 12 5 25 1001 1 25 2 5 1021–23 SW11 55 4505 94–6 253 5to56 11010 12 5 251 1 25 2 528–30 FM10 787 4–108 198 1–118 8110 12 5 25 10010 12 5 25 100109–130 WB10 7162 4–162 6151–152112 5 2512 5 25140–142 TV110 759 75–87 7570 45–98 451252581–109 TV210 7179 75–215 75169 1–205 112525158–194Input and Output SchematicsTL F 7398–11TL F 7398–126Input and Output Schematics (Continued)TL F 7398–13TL F 7398–14TL F 7398–15TL F 7398–16TL F 7398–17TL F 7398–187Logic DiagramDS8911 DS8913PLL SynthesizerTL F 7398–4 Note1 The14bit programmable N counter is a dual modulus counter with31 32prescaler The minimum continuous modulus of the N counter is 961 (There are a limited number of valid modulus codes below961 )The DS8913has d5Typical Application DiagramAM FM ETR Radio ApplicationTL F 7398–58Wiring DiagramsConfiguration Using PLL and First Mixer FunctionsTL F 7398–20Configuration Using PLL with LO Bypassing MixerThe mixer is de-biased by the100X resistor on the RF apin to act as an output bufferfor the LO signalTL F 7398–219D S 8911 D S 8913A M F M T V S o u n d U p -C o n v e r s i o n F r e q u e n c y S y n t h e s i z e rPhysical Dimensions inches (millimeters)Lit 103661Plastic Chip Carrier (V)Order Number DS8911V DS8913VNS Package Number V28ALIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury to the userNational Semiconductor National Semiconductor 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