A MONOLITHIC 19-BIT 800 HZ LOW POWER MULTI-BIT SIGMA DELTA CMOS ADC USING DATA WEIGHTED AVE

A MONOLITHIC 19-BIT 800 H Z LOW POWER MULTI-BIT SIGMADELTA CMOS ADC USING DATA WEIGHTED A VERAGINGOlivier Nys, Robert HendersonCentre Suisse d’Electronique et de Microtechnique S.A.Jaquet-Droz 1, CH-2007 NeuchâtelAbstract:This paper describes a sigma delta switched capacitor CMOS ADC usingmulti-bit quantization and feedback path for minimum power consumption.Multi-bit quantization has up to now been avoided because the linearity ofthe DAC in the feedback path directly limits the linearity of the wholeconverter. By using data weighted averaging, the non-linearity error relatedto the mismatch of the DAC components is decorrelated from the signal andtransformed into high frequency noise. Hence most of this error is furthereliminated together with the quantization noise by the digital lowpass filter.1. I NTRODUCTIONWhen designing low power high resolution oversampled ADC, 3 main parameters must first be determined : the oversampling frequency, the modulator order and the number of bits for quantization and feedback DAC. In order to allow weak or moderate inversion operation of the OTA’s and thus to reach maximum power efficiency, the sampling frequency is chosen below a critical value fc related to the technology [1]. However, for high resolution converters, the dominant noise source is thermal noise, which imposes a minimum value on the product of the input capacitor size and the sampling frequency. Hence, reducing the sampling frequency much below fc drastically increases the sizes of capacitors and the chip area, without significantly reducing power consumption. For a Nyquist rate of 800 Hz, a relatively large oversampling ratio (~512) can still be selected without significant penalty in power consumption. In this way, a quantization noise level compatible with 19 bit resolution can already be achieved with a third order modulator. The modulator order can be further reduced to 2 with multi-bit quantization and feedback. By so doing, the sensitivity of the converter to overload is reduced. Moreover, multi-bit quantization has a very favourable impact on power consumption. The reason is that the feedback signal tracks the input signal. better As the first integrator accumulates the difference between the input signal and the feedback signal, its slew rate requirements and power consumption can be drastically reduced. The main reason why multibit quantization and feedback has up to now generally been avoided is that the linearity of the DAC directly limits the linearity of the overal converter. In this circuit, this problem has been solved by using data weighted averaging (DWA) [2].2. I MPROVED DAC LINEARITYSwitched capacitor DAC’s are generally realised from an array of identical elementary capacitors. These elementary capacitors are then grouped into binary weighted capacitors, each capacitor being made of a number of elementary capacitors equal to a power of 2. Such DAC’s generally exhibit discontinuities or even non-monotonicities around the middle of their characteristics, corresponding to the switching of the msb’s. These discontinuities can be avoided by selecting all the elementary capacitors according to a thermometrical decoder where only one more capacitor participates to the D/A conversion for each unit increment in the the input code. However, such an algorithm only reduces the differential non-linearity, but not the integral non-linearity. The error related to the mismatch between the DAC capacitors can also be decorrelated from the signal by selecting the capacitors at random [3]. This error is then converted into random noise, the spectrum of which spans up to half the sampling frequency. The advantage is that the components outside the signal baseband are further eliminated by the digital decimation filter. However, the noise power is only attenuated by 3 dB per octave of the oversampling factor. A much greater attenuation can be obtained by using a noise shaping technique in order to move the noise due to mismatch between DAC capacitors outside the baseband. This is achieved by the DWA technique which basically involves cyclically selecting all the DAC capacitors [2, 4, 5], as illustrated in figure 1. This algorithm prevents any capacitor from being selected more than one time more than any other capacitor over an arbitrarily long time period. As this technique performs a first order shaping on the mismatch noise, it is attenuated by 9 dB per octave of oversampling. With an oversampling factor of 512, the mismatch noise is attenuated by 81 dB, and thus becomes negligible with respect to thermal noise.code(k)=4code(k+1)=5code(k+2)=2code(k+3)=3Fig1: Cyclic selection of the capacitors participating in the D/A conversion3. C IRCUIT I MPLEMENTATIONFigure 2 shows the architecture of the sigma delta modulator. This is basically a fully differential second order single loop modulator, using multibit feedback towards both integrators. For improved 1/f noise rejection, correlated double sampling (CDS) is performed within the first integrator. This technique is combined with a chopper at an intermediate and programmable frequency in order to remove the offset due to the charge injection of the sampling switches. The 8pF input capacitors necessary to achieve a thermal noise levelcompatible with 19 bits can be conveniently subdivided into the eight elementary capacitors constituting the 3-bit feedback DAC without area overhead. To increase the input impedance,the sampling capacitors are precharged to coarse copies of the input or reference signals through on-chip buffers [6]. The number of quantization and feedback bits within the sigma delta loop is programmable between 0 and 3. The digital decimation filter is a third order comb filter with programmable decimation factor. The complete test chip including digital filter and control circuitry has been integrated in a 2 µm double poly CMOS process (Fig 3). The analogue and digital parts occupy 4 and 10mm 2 respectively. Total power consumption is 2.7mW from a 5 V power supply, half of the power being due to the digital part.vin-Fig 2: Architecture of the multi-bit sigma delta modulator with cyclic selection of capacitorsFig 3: Chip Photograph4. M EASUREMENT R ESULTSFig. 4a shows the measured resolution as a function of oversampling factor (N). At low N, the resolution is limited by quantization noise and increases by 2.5 bits per octave. At N=128 the resolution begins to be limited by thermal noise and only 0.5 bit per octave of N is gained. The resolution does not saturate even for high N, indicating that 1/f noise is successfully eliminated by the CDS technique. Fig. 4b shows a comparison of the converter linearity error bounds with and without DWA. These curves have been extracted from an LMS fit of data from a ±5V fully-differential DC sweep of the fullscale converter input range. The linearity error without dynamic matching varied greatly from chip to chip whereas that with dynamic matching was reproducible and is related to charge injection. An other observed advantage of multi-bit compared to single bit is the suppression of tones in the quantization noise.b) effect of enabling or disabling DWA on the linearity5. C ONCLUSIONSAn ADC with 19 bits resolution on a 400 Hz bandwidth has been presented, consuming only 2.7 mW thanks to multibit quantization and feedback. The inherent linearity problem of this architecture has been solved using the DWA technique. A reduction of the power consumption by a factor 2 could be expected with a submicron technology, as half of the power is still consumed in the digital part.6. R EFERENCES[1]O. Nys, R. Henderson, “Low Power High Resolution A/D Converters”, Proc. of Midwest Symposium on Circuitsand Systems”, Rio de Janeiro, Brazil, August 13-16,1995.[2]R.T. Baird, T. S. Fiez, “Linearity Enhancement of Multibit ∆Σ A/D and D/A Converters using Data WeightedAveraging”, IEEE Transactions on Circuits and Systems--II: Analog and Digital Signal Processing, Volume 42, No 12, pp. 753-762, December 1995.[3]L. R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters”, IEEE Journal of Solid-State Circuits,Volume SC-24, pp. 267-273, April 1989[4] A. Maloberti, “Convertitore Digitale Analogico Sigma-Delta Multilivello con Matching Dinamico degliElementi ”, Tesi di Laurea, Universita degli Studi di Pavia, 1990-1991[5]O. Nys, R. Henderson, “An Analyis of Dynamic Element Matching Techniques in Sigma-Delta Modulation”, to bepublished at ISCAS 96, Atlanta, 1996,[6]K. Yamamura, A. Nogi, A. Barlow, “ A Low Power 20 Bit Instrumentation Delta-Siigma ADC”, Proc. IEEE CICC,pp. 519-522, San Diego, 1994.。