CLC018AJVJQ中文资料

CLC0188x 8Digital Crosspoint Switch,1.4GbpsGeneral DescriptionNational’s Comlinear CLC018is a fully differential 8x8digital crosspoint switch capable of operating at data rates exceed-ing 1.4Gbps per channel.Its non-blocking architecture uti-lizes eight independent 8:1multiplexers to allow each output to be independently connected to any input and any input to be connected to any or all outputs.Additionally,each output can be individually disabled and set to a high-impedance state.This TRI-STATE ®feature allows flexible expansion to larger switch array sizes.Low channel-to-channel crosstalk allows the CLC018to pro-vide superior all-hostile jitter of 50ps PP .This excellent signal fidelity along with low power consumption of 850mW make the CLC018ideal for digital video switching plus a variety of data communication and telecommunication applications.The fully differential signal path provides excellent noise im-munity,and the I/Os support ECL and PECL logic levels.In addition,the inputs may be driven single-ended or differen-tially and accept a wide range of common mode levels in-cluding the positive supply.Single +5V or −5V supplies or dual +5V supplies are supported.Dual supply mode allows the control signals to be referenced to the positive supply (+5V)while the high-speed I/O remains ECL compatible.The double row latch architecture utilized in the CLC018al-lows switch reprogramming to occur in the background dur-ing operation.Activation of the new configuration occurs with a single “configure”pulse.Data integrity and jitter perfor-mance on unchanged outputs are maintained during recon-figuration.Two reset modes are provided.Broadcast reset results in all outputs being connected to input port DI0.TRI-STATE Reset results in all outputs being disabled.The CLC018is fabricated on a high-performance BiCMOS process and is available in a 64-lead plastic quad flat pack (PQFP).Featuresn Fully differential signal path n Non-Blockingn Flexible expansion to larger array sizes with very low powern Single +5/−5V or dual ±5V operation n TRI-STATE outputsn Double row latch architecture n 64-lead PQFP packageApplicationsn Serial digital video routing (SMPTE 259M)n Telecom/datacom switching n ATM SONETKey Specificationsn High speed:>1.4Gbps n Low jitter:<50ps PP for rates <500Mbps <100ps PP for rates <1.4Gbpsn Low power;850mW with all outputs active n Fast output edge speeds:250psCLC018Block DiagramDS100088-2October 1998CLC0188x 8Digital Crosspoint Switch,1.4Gbps©1998National Semiconductor Corporation Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC–V EE)−0.3V to+6.0V V LL Maximum V CC+6V V LL Minimum V CC−0.5V Storage Temperature Range−65˚C to+150˚C Lead Temp.(Soldering4sec.)+260˚C ESD Rating TBD Package Thermal ResistanceθJA64-Pin PQFP75˚C/WθJC64-Pin PQFP15˚C/W Reliability InformationTransistor Count3000 MTTF(based on limited life test data)TBDRecommended Operating ConditionsSupply Voltage(V CC–V EE) 4.5V to5.5V Operating Temperature−40˚C to+85˚CV LL V CC or V CC+5VElectrical Characteristics(V CC=0V,V EE=−5V,V LL=0V;unless otherwise specified)(Note4).Parameter ConditionsTyp+25˚CMin/Max+25˚CMin/Max−40˚C to+85˚CUnitsDYNAMIC PERFORMANCEMax.Data Rate/Channel(NRZ)(Note5) 1.4Gbps Channel Jitter Data Rate<500Mbps(Note6)50ps PPData Rate<1.4Gbps(Note6)100ps PP Propagation Delay(input to output)0.75ns Propagation Delay Match(Note7)±200ps Output Rise/Fall Time(Note8)250ps Duty Cycle Distortion(Note9)10ps CONTROL TIMING:CONFIGURATIONOA Bus to LOAD↑Setup Time(T1)15ns LOAD↓to OA Bus Hold Time(T2)0nsIA Bus,TRI to LOAD↓Setup Time(T3)5ns LOAD↓to IA Bus,TRI Hold Time(T4)5ns Min Pulse Width:(T5)LOAD10ns CNFG10ns LOAD↑to CNFG↑Delay(T6)0ns CNFG↑to Valid Delay(T7)20ns CNFG↑to Output TRI-STATE Delay(T8)20ns CNFG↑to Output Active Delay(T9)70ns CONTROL TIMING:RESET(Note11)TRI to RES↑Setup Time(T10)5ns RES↓to TRI Hold Time(T11)5ns Min Pulse Width:RES(T12)10ns RES↑to TRI-STATE Mode Delay(T13)20ns RES↑to Broadcast Mode Delay(T14)70ns STATIC PERFORMANCESignal I/O:Min Input Swing,Differential(Note3)150200200mV PP Input Voltage Range Lower Limit−2V Input Voltage Range Upper Limit0.4V Input Bias Current(Notes3,12) 1.50.4/3.10.3/3.8µA/output Output Current(Note3)10.78.53/12.807.20/14.3mA2Electrical Characteristics(Continued)(V CC=0V,V EE=−5V,V LL=0V;unless otherwise specified)(Note4).Parameter ConditionsTyp+25˚CMin/Max+25˚CMin/Max−40˚C to+85˚CUnitsSignal I/O:Output Voltage Swing R LOAD=75Ω800640/960540/1060mV Output Voltage Range Lower Limit−2.5V Output Voltage Range Upper Limit0V Control Inputs:Input Voltage-HIGH V IH min(Note3)−1−0.5−0.5V Input Voltage-LOW V IL max(Note3)−4−4.5−4.5V Input Voltage-HIGH V IH min V LL=+5V(Note3)4 4.5 4.5V Input Voltage-LOW V IL max V LL=+5V(Note3)10.50.5V Input Current-HIGH V IH=V LL(Note3)10.2/2.00.1/2.5µA Input Current-LOW V IL=V LL−5V(Note3)−100−200/10−250/15µA MISCELLANEOUS PERFORMANCEV CC Supply Current All Outputs Active(Notes3,13,14)157127/202119/217mAV CC Supply Current All Outputs TRI-STATE(Note3)73/112/12mAV LL Supply Current V LL=0V(Note3) 2.5 1.7/3.3 1.5/3.5mAV LL Supply Current V LL=+5V(Note3)7mA Input Capacitance 1.5pF Output Capacitance2pFNote1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the devices should be operated at these limits.The table of“Electrical Characteristics”specifies conditions of device operation.Note2:Min/max ratings are based on product characterization and simulation.Individual parameters are tested as noted.Outgoing quality levels are determined from tested parameters.Note3:J-level spec.is100%tested at+25˚C.Note4:V LL and all V EE supply pins are bypassed with0.01µF ceramic capacitor.Note5:Bit error rate less than10−9over50%of the bit cell interval.Note6:Measured using a pseudo-random(223−1pattern)binary sequence with all other channels active with an uncorrelated signal.Note7:Spread in propagation delays for all input/output combinations.Note8:Measured between the20%and80%levels of the waveform.Note9:Difference in propagation delay for output low-to-high vs.output high-to-low transition.Note10:Refer to the Configuration Timing Diagram.Note11:Refer to the Reset Timing Diagram.Note12:The bias current for high speed data input depends on the number of data outputs that are selecting that input.Note13:The V CC supply current is a function of the number of active data outputs.I VCC18*N+7mA where N is an integer from0to8.Note14:I VEE=I VCC+I VLL.3Typical Performance CharacteristicsDS100088-3DS100088-4DS100088-5DS100088-6DS100088-7DS100088-8 4Connection DiagramPin DescriptionsPOWER PINSV CC is the most positive rail for the data path.When the data levels are ECL compatible,then V CC should be connected to GND.For PECL data(+5V referenced ECL),V CC is con-nected to the+5V supply.Please refer to the device opera-tion section in this datasheet for recommendations on the bypassing and ground/power plane requirements of this de-vice.V EE is the most negative rail for the data path.When the data levels are ECL compatible,then V EE is connected to a−5.2V power supply.For PECL data(+5V referenced ECL),V EE is connected to GND.V LL is the logic-level power supply.If the control signals are referenced to+5V,V LL is connected to a+5V supply.If con-trol signals are ECL compatible,V LL is connected to GND. DATA INPUT PINSDI0and DI0through DI7and D17are the data input pins to the CLC018.Depending upon how the Power pins are con-nected(please refer to the Power Pin section above)the data may be either differential ECL,or differential PECL.To drive the CLC018inputs with a single-ended signal,please refer to the section“Using Single-Ended Data”in the OP-ERATION section of this datasheet.DATA OUTPUT PINSDO0and DO0through DO7and DO7are the data output pins of the CLC018.The CLC018outputs are differential cur-rent outputs which can be converted to ECL or PECL com-patible outputs through the use of load resistors.Please re-fer to the“Output Interfacing”paragraph in the OPERATION section of this datasheet for more details.CONTROL PINSIA2,IA1and IA0are the three bit input selection address bus.The input port to be addressed is placed on this bus. IA2is the Most Significant Bit(MSB).If input port6is to be addressed,IA2,IA1,IA0should have1,1,0asserted on them.The IA bus should be driven with CMOS levels,if V LL is+5V.These levels are thus+5V referenced(standard CMOS).If V LL is connected to GND,the input levels are ref-erenced to the−5V and GND supplies.OA2,OA1and OA0are the output selection address bus. The output port selected by the OA bus is connected to the input port selected on the IA bus when the data is loaded into the configuration registers.OA2is the MSB.If OA2,OA1, OA0are set to0,0,1;then output port1will be selected. CS is an active-high chip select input.When CS is high,the RES,LOAD,and CNFG pins will be enabled.LOAD is the latch control for the LOAD register.When LOAD is high,the load register is transparent.Outputs follow the state of the IA bus,and are presented to the inputs of the Configuration register selected by the OA bus.When LOAD is low,the outputs of the Load register are latched.RES is the reset control of the configuration and load regis-ters.A high-going pulse on the RES pin programs the switch matrix to one of two possible states:with TRI low,all outputs are connected to input#0;with TRI high,all outputs are put in TRI-STATE condition.TRI will program the selected output to be in a high imped-ance or TRI-STATE condition.To place an output in TRI-STATE,assert a logic-high level on the TRI input when the desired input and output addresses are asserted on the respective address inputs and strobe the LOAD input as de-picted in the”Configuration Truth Table”.To enable an out-put,assert a logic-low level on the TRI input together with the appropriate addresses and strobe the LOAD input as previ-ously described.CNFG is the configuration register latch control.When CNFG is high the Configuration register is made transparent, and the switch matrix is set to the state loaded into the Load registers.When CNFG is low,the state of the switch matrix is latched.DS100088-9Order Number CLC018AJVJQSee NS Package Number VJE64A 5Timing DiagramsDS100088-10FIGURE1.Timing Diagram—TRI-STATE ResetDS100088-11FIGURE2.Timing Diagram—“Broadcast Reset”6Timing Diagrams(Continued)OperationINPUT INTERFACINGThe inputs to the CLC018are high impedance differential in-puts (see the equivalent input circuit in Figure 4).The CLC018can be operated with either ECL or PECL (+5V ref-erenced ECL),depending upon the power supply connec-tions.The inputs are differential and must both be within the range of V CC –2V to V CC +0.4V in order to function properly.SINGLE ENDED INPUTSDifferential inputs are the preferred method of providing data to the CLC018,however,there are times when the only sig-nal available is single ended.To use the CLC018with a single ended input,the unused input pin needs to be biased at a point higher than the low logic level,and lower than the high logic level.For best noise performance,the middle ofDS100088-12FIGURE 3.Timing Diagram —Switch ConfigurationDS100088-13FIGURE 4.Equivalent Input Circuit7Operation(Continued)the range is best.For ECL signals this point is about2diodedrops below ground.It is possible to bias the unused inputwith a low-pass filtered version of the data,as shown in Fig-ure5.In some coding schemes there are pathological pat-terns that result in long sequences with no data transitions.During these patterns,the bias on the unused input will drifttowards the other input reducing the noise immunity whichmakes this scheme undesirable.The most robust solution forsingle ended inputs is to place a comparator with hysteresisin front of the CLC018.Such a part is the MC10E1652.SeeFigure6for an example of how to hook this up.OUTPUT INTERFACINGThe outputs of the CLC018are differential,current sourceoutputs.They can be converted to ECL compatible levelswith the use of resistive loads as shown in Figure7.The out-put swings will have a similar temperature coefficient to10KECL if a1N4148diode is used to set V OH.For most com-mercial temperature range applications,a75Ωresistor canbe used as shown in Figure8.Many circuits with differentialinputs,such as the CLC016Data Retimer With AutomaticRate Selection,do not require true ECL levels,so the loadresistors can be connected directly to the positive rail asshown in Figure9.POWER SUPPLIES,GROUNDING AND BYPASSINGThe CLC018uses separate power supplies for control anddata circuitry.Data circuitry is supplied via V CC and controlcircuitry via V LL.Supply connection V EE,the negative-mostsupply,is the common return for both.Connection details forthe different powering modes is shown in Table1.Internal and external capacitances,normal and parasitic,must be charged and discharged with changes in output volt-age.Charging current depends upon the size of these ca-pacitances and the rate of change of voltage.At the fast tran-sition times of the CLC016,small amounts of straycapacitance at outputs can produce large output and supplytransient currents.Controlling transient currents requiresparticular attention to minimizing stray capacitances and toproviding effective bypassing in the design.Good and effec-tive bypassing consisting of0.01µF to0.1µF monolithic ce-ramic and4.7µF to10µF,35V tantalum capacitors.Thesecapacitors should be placed as close to power pins as prac-tical and tightly connected to the power plane sandwich us-ing multiple vias.Needless to say,multilayer board technol-ogy should be employed for the CLC018and similar high-frequency-capability devices.CONFIGURING THE SWITCHThe CLC018can be configured so that any output may be in-dependently connected to any input and any input be con-nected to any or all outputs.Each output may be indepen-dently enabled or placed in a high-impedance state.Data controlling the switch matrix and output mode arestored in two ranks of eight,4-bit registers,one register peroutput.The three most-significant bits in each register iden-tify the input to be connected to that output.The least-significant bit controls whether the output is active orTRI-STATE.A particular register in the first rank,the LOADREGISTERS,is selected by a3-bit word placed on the out-DS100088-14FIGURE5.Single Ended Input to CLC018DS100088-15FIGURE6.Single Ended Input to CLC018DS100088-16FIGURE7.Generating10k ECL OutputsDS100088-17FIGURE8.Generating ECL OutputsDS100088-18FIGURE9.Connecting the CLC018to the CLC016 8Operation(Continued)put address(OA)bus.Data to be written into the load regis-ter,consisting of the3-bit address of the input to be con-nected to that output and the output-enable control bit,are placed on the input address(IA)bus.Input data is stored in the load registers at the low-to-high transition of the LOAD input pin with chip-select(CS)high-true.The contents of the load registers are transferred to the second rank of CON-FIGURATION REGISTERS at the low-to-high transition of the CNFG input signal(with CS high).This causes the state of the entire switch matrix to be set to the selected configu-ration.The entire crosspoint may be placed in an initializing state, with all outputs connected to input-0and with all outputs ei-ther enabled or TRI-STATE.To do so,hold TRI low to make outputs active,or high to place outputs in TRI-STATE,and apply a high-going pulse to the RES input pin(with CS high). In summary,outputs are configured by:a)first placing the3-bit address of that output on the OAbus together withb)the3-bit address of the input to be connected to thatoutput on the IA bus,c)the output-enable(TRI-STATE)control bit for that outputon the IA bus,d)making chip-select(CS)true,and thene)providing a high-going pulse to the LOAD input pin.f)Repeat these four steps for each output to be config-ured.The entire crosspoint matrix may now be configured with thedata held in the load registers.To implement the configura-tion,apply a high-going pulse to the CNFG input pin.Thecontents of the load registers are transferred to the configu-ration registers and the new configuration of all crosspointsis effected.The CLC018Configuration Truth Table is shown at the endof the datasheet.EXPANDING THE SWITCH SIZEThe CLC018was designed for easy expansion to larger ar-ray sizes without paying a significant penalty in either speedor power.The power dissipation of the expanded array willbe dominated by the number of active outputs,thereforepower will increase linearly with the array size even thoughthe number of components required increases as the squareof the array size.As an example,a single CLC018can beused for an8x8array,and it will dissipate about0.85W.A32x32array will require16CLC018s and will consume onlyabout4W. 9Operation(Continued)TABLE1.Interfacing of the Power Supplies and Bypass CapacitorsSupply Operation Single−5V Single+5V Dual±5V I/O Data Level ECL PECL ECL Control Signal Low/High−5V/GND GND/+5V GND/+5V Connection10Operation(Continued)EXPANDING THE NUMBER OF INPUT PORTS Expanding the number of inputs in a switch array is accom-plished by wire-ORing the outputs together,and TRI-STATEing the outputs of the CLC018s that do not have their inputs selected.The output bus should be a controlled im-pedance transmission line with proper termination.This is shown in Figure11.The circuit uses a1-of-2decoder with complemented outputs to control the TRI pins of the CLC018s in the array.Thus,all CLC018s are programmed simultaneously,and all of them,except for the one with the selected input,are placed in the TRI-STATE mode.EXPANDING BOTH INPUTS AND OUTPUTSTo increase both the number of inputs and outputs in an ar-ray,apply both the input port and output port expansion tech-niques simultaneously.In Figure12,this is shown for the case of a24input by32output switch array.Note that both input and output busses need to be controlled impedance transmission lines.The CS pins for rows of CLC018s are connected together and become the row select inputs, whereas the TRI pins are connected together for the col-umns of CLC018s and become the column select pins.DS100088-20FIGURE10.8x16Crosspoint Example 11Operation(Continued)DS100088-21FIGURE11.Expanded Input Ports12Operation(Continued)DS100088-22FIGURE12.24x32Output Switch Array13Operation(Continued)CALCULATING THE POWER DISSIPATION IN AN EXPANDED ARRAYThe CLC016dissipates about100mW per active output plus about50mW quiescent power.With all outputs active,this is about850mW.In an expanded array,all devices will dissi-pate quiescent power,but only those devices with active out-puts will dissipate the100mW/output.So,an N-by-M device array(an8xN-input-by-8xM-output switch)with all outputs active will dissipate N x M x50mW+8x M x100mW.A32-input x32-output(4x4device)switch array dissipates4x4 x50mW+8x4x100mW=4W.CONTROLLED IMPEDANCE TRANSMISSION LINES AND OTHER LAYOUT TECHNIQUESAll transmission lines whose length is greater than1⁄4wave-length of the highest frequencies present in the transmitted signal require proper attention to impedance control to avoid distortion of the signal.Digital signals are especially suscep-tible to distortion due to poorly controlled line characteristics and reflections.With its250ps output transitions,which im-ply a bandwidth of4GHz or more,transmission lines driven by the CLC018must be carefully designed and correctly ter-minated.Either microstrip line,which resides on the outer surfaces of a printed circuit board and paired with an image ground plane,or stripline,which is sandwiched in an inner layer between image ground planes,may be used in CLC018designs.With either line type,it is important to maintain a uniform characteristic impedance over the entire extent of the transmission line system.Likewise,the receiv-ing end of these lines must be terminated in a resistance equal to the characteristic impedance to preserve signal fi-delity.Figure13shows representative methods of interfacing to and from the CLC018.Often,when voltage-mode drivers,such as ECL,with low output impedance(also called equivalent generator resis-tance)are used to drive bus networks,a series resistor con-nects the output of the amplifier to the transmission line.This resistor serves both as a termination for any signals travel-ling toward the source-end of the line and as the series leg of a voltage divider(with the transmission line as the shunt leg)to reduce the transmitted signal level.This resistor’s cor-rect value is Z O−R OUT.However,a value equal to Z O may be used successfully in most situations.The receiving end of the line is terminated in a resistance equal to the value of Z O of the receiving end of the line.A resistance equal to the line’s Z O works in most situations.In cases where the bus is heavily loaded,the receiving end termination’s value may need to be reduced to the loaded-Z O of the line.(Please see the material on distributed loading effects on line character-istics in the Fairchild F100K ECL300Series Databook and Design Guide).Current-mode drivers,with their high equivalent generator resistance,when used as bus drivers require a resistance equal to Z O at each end of the bus to either power or ground as appropriate for the design.A detailed discussion of digital transmission line design tech-niques is beyond the scope of this data sheet,but many good references are available from National Semiconductor and others.Extensive material is available in the National In-terface Databook,the Fairchild F100K ECL300Series Da-tabook and Design Guide and the Motorola MECL System Design Handbook.Especially useful is the National Semiconductor Transmis-sion Line RAPIDESIGNER r Sliderule and user manual AN-905.The RAPIDESIGNER is available by calling the Na-tional Semiconductor Customer Response Center in your area and asking for either Literature Number633200-001 (ISO Metric units)or633201-001(English units).The User Manual for both versions is Literature Number100905-002 and is available on our WEB Site at as AN-905.14Operation(Continued)DS100088-23FIGURE13.Input/Output Bussing15Operation(Continued)Configuration Truth TableIA2IA1IA0OA2OA1OA0TRI RES LOAD CNFG CS Condition of Device X X X X X X X X X X0NO CHANGE X X X X X X0I X X1Load I/P0to All O/Ps X X X X X X1I X X1TRI-STATE All O/P0 X X X00010I01TRI-STATE O/P0 X X X00110I01TRI-STATE O/P1 X X X01010I01TRI-STATE O/P2 X X X C B A10I01TRI-STATE O/P CBA ••••••••••••R Q P C B A00I01Load I/P PQR to O/PCBA and Enable O/PCBA ••••••••••••00000000I01Load I/P0to O/P0 00000100I01Load I/P0to O/P1 00001000I01Load I/P0to O/P2 00001100I01Load I/P0to O/P3 00010000I01Load I/P0to O/P4 00010100I01Load I/P0to O/P5 00011000I01Load I/P0to O/P6 00011100I01Load I/P0to O/P7 00100000I01Load I/P1to O/P0 00100100I01Load I/P1to O/P1 00101000I01Load I/P1to O/P2 00101100I01Load I/P1to O/P3••••••••••••00111100I01Load I/P1to O/P7••••••••••••11111000I01Load I/P7to O/P6 11111100I01Load I/P7to O/P7 X X X X X X X00I1Activate NewConfiguration 1617Physical Dimensions inches(millimeters)unless otherwise notedLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant intothe body,or(b)support or sustain life,and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling,canbe reasonably expected to result in a significant injuryto the user.2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system,or to affect its safety or effectiveness.National SemiconductorCorporationAmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5620-6175Fax:81-3-5620-617964-Lead PQFPOrder Number CLC018AJVJQNS Package Number VJE64ACLC188x8DigitalCrosspointSwitch,1.4GbpsNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。