GS8162Z36D-150I中文资料

The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 & x36), or 209-bump (x72) BGA package.
A B C D E F G H J K L M N P R T U V W Rev 10
1 DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD DQD DQD
2 DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC DQH DQH DQH DQH DQPH DQD DQD DQD DQD
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns
280 255 230 200 185 165 mA 330 300 270 230 215 190 mA n/a n/a 350 300 270 245 mA
元器件交易网
The x18 and x36 parts in this specification are Not Recommended for New Design.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
119, 165, & 209 BGA Commercial Temp Industrial Temp
The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.
Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
© 1999, GSI Technology
The x18 and x36 parts in this specification are Not Recommended for New Design.
元器件交易网
GS8162Z72 BGA Pin Description
A
NC
A
A
A
A1
A
A
TDI
A
A0
A
TDO
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
9 A BF BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK
10 DQB DQB DQB DQB DQPF DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE DQE DQE DQE
Functional Description
The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
VDD
MCH
VDD
VDDQ
VSS
VSS
MCL
VSS
VSS
VDDQ
VDD
MCH
VDD
VDDQ
NC
VSS
MCL
VSS
NC
VDDQ
VDD
FT
VDD
VDDQ
VSS
VSS
MCL
VSS
VSS
VDDQ
VDD
MCH
VDD
VDDQ
VSS
VSS
ZZ
VSS
VSS
VDDQ
VDD
VDD
VDD
VDDQ
NC
NC
LBO
PE
NC
A
NC
• 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • User-configurable Pipeline and Flow Through mode • ZQ mode pin for user-selectable high/low output drive • IEEE 1149.1 JTAG-compatible Boundary Scan • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 8M devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down • JEDEC-standard 119-, 165-, or 209-Bump BGA package
TDI
I
TDO
O
TCK
I
VDD
I
VSS
I
VDDQ
I
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
The x18 and x36 parts in this specification are Not Recommended for New Design.
元器件交易网
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 Pad Out—209-Bump BGA—Top View (Package C)
3 A BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS
4
5
6
78E2源自AADVA
E3
BG
NC
W
A
BB
BD
NC
E1
NC
BE
NC
NC
G
NC
NC
VDDQ
VDD
VDD
VDD
VDDQ
VSS
VSS
ZQ
VSS
VSS
VDDQ
275 250 230 195 180 165 mA 320 295 265 225 210 185 mA n/a n/a 335 290 260 235 mA
tKQ tCycle
5.5 6.0 6.5 7.0 7.5 8.5 ns 5.5 6.0 6.5 7.0 7.5 8.5 ns