SIHF9620中文资料
2SA966资料
TOSHIBA Transistor Silicon PNP Epitaxial Type (PCT Process)2SA966Audio Power Amplifier Applications• Complementary to 2SC2236 and 3-W output applications.Absolute Maximum Ratings (Ta = 25°C)Characteristics Symbol Rating UnitCollector-base voltage V CBO −30 V Collector-emitter voltage V CEO −30 V Emitter-base voltage V EBO −5 V Collector current I C−1.5 AEmitter currentI E 1.5 A Collector power dissipation P C 900 mW Junction temperature T j 150 °C Storage temperature rangeT stg−55 to 150°CNote: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in thereliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings.Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“HandlingPrecautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).Unit: mmJEDEC TO-92MOD JEITA ―TOSHIBA 2-5J1A Weight: 0.36 g (typ.)Electrical Characteristics (Ta = 25°C)Characteristics Symbol TestCondition MinTyp.Max UnitCollector cut-off current I CBO V CB = −30 V, I E = 0 ――−100nAEmitter cut-off current I EBO V EB = −5 V, I C = 0 ――−100nA Collector-emitter breakdown voltage V (BR) CEO I C = −10 mA, I B = 0 −30 ―― V Emitter-base breakdown voltage V (BR) EBO I E = −1 mA, I C = 0 −5 ―― VDC current gain h FE(Note)V CE = −2 V, I C = −500 mA 100 ― 320Collector-emitter saturation voltage V CE (sat)I C = −1.5 A, I B = −0.03 A ――−2.0V Base-emitter voltage V BE V CE = −2 V, I C = −500 mA ――−1.0V Transition frequency f T V CE = −2 V, I C = −500 mA ― 120 ― MHz Collector output capacitance C ob V CB = −10 V, I E = 0, f = 1 MHz ― 40 ― pF Note: h FE classification O: 100 to 200, Y: 160 to 320Markinglead (Pb)-free package orlead (Pb)-free finish.indicatorCollector current I C (mA)h FE – ICD C c u r re n t g a i n h F ECollector current I C (mA)V CE (sat) – I CC o l l e c t o r -e m i t t e r s a t u r a t i on v o l t a g eV C E (s a t ) (V )Base-emitter voltage V BE (V)I C – V BEC oll e c t o rc u r r e n t I C (m A )Ambient temperature Ta (°C)P C – TaC o l l e c t o r p owe r d i s s ip a t io n P C (W )Collector-emitter voltage V CE (V)Safe Operating AreaC o l l e c t o r c u r r e n t I C (A )1.00 0 20 40 60 80 100 120 140 160 1800.20.40.60.8−−−−−−−−−−−−−−−−−−Collector-emitter voltage V CE (V)I C – V CEC o l l e c t o r c u r r e n t I C (m A )−−−−−−−−−−−−−−−−−RESTRICTIONS ON PRODUCT USE20070701-EN •The information contained herein is subject to change without notice.•TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk.•The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.• Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.。
ESC60HREF中文资料(List Unclassifed)中文数据手册「EasyDatasheet - 矽搜」
106.68 109.22 121.92 124.46 129.54 149.86
B
+_ 0.20
12.70 15.24 17.78 20.32 22.86
27.94 33.02 35.56 40.64 45.72 48.26
50.80 53.34 58.42 60.96 66.04 68.58
间隙
＃4螺丝
间隙
孔（H）
螺纹
INSERT (I)
浮动
BOBBIN (F)
否安装耳
(N)
.125 [3.18] .135 [3.43]
侧面安装
(S)
芯片中文手册,看全文,戳
材料（绝缘层/触点）
E = PBT /磷青铜（标准） H = PBT /铍铜 R = PPS /磷青铜 A = PPS /铍铜
A
+_.008
0.300 0.400 0.500 0.600 0.700
0.900 1.100 1.200 1.400 1.600 1.700
1.800 1.900 2.100 2.200 2.400 2.500
2.700 2.900 3.000 3.400 3.500 3.900
4.200 4.300 4.800 4.900 5.100 5.900
17.15 24.77
19.69 27.31
22.23 29.85
24.77 32.39
27.31 34.93
32.39 40.01
37.47 45.09
40.01 47.63
45.09 52.71
50.17 57.79
IRF9620中文资料
4-21
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. or 407-727-9207 | Copyright © Intersil Corporation 1999
元器件交易网
IRF9620
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified IRF9620 -200 -200 -3.5 -2 -14 ±20 40 0.32 290 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC
Features
• 3.5A, 200V • rDS(ON) = 1.500Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance
元器件交易网
IRF9620
Data Sheet July 1999 File NumberБайду номын сангаас
2283.2
3.5A, 200V, 1.500 Ohm, P-Channel Power MOSFET
This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17502.
Datasheet MLX90614 中文 数据手册 rev008
单区视场和双区视场 TO-39 封装 红外温度传感器
特性和优点
尺寸小，成本低 易集成 在极宽温度范围内工作，带出厂校准： 传感器工作温度范围：-40…+125˚C 被测目标温度范围：-70…+380˚C Ta 和 To 在 0 到 50° C 时，测量精度可达 0.5° C 高(医疗)精度校准 测量值分辨率 0.02° C 单区视场和双区视场可选 SMBus 兼容数字接口 可配置 PWM 连续输出 3V 或 5V 供电，也可使用 8…16V 供电调制 支持睡眠模式 适合不同应用领域的多种封装方式和测试方式 车用级别标准
3901090614 Rev 008
第 2ห้องสมุดไป่ตู้/ 52 页
数据手册 2013/2/28
MLX90614 系列
单区视场和双区视场 TO-39 封装 红外温度传感器
3 目录
1 功能图 ........................................................................................................................................................................................................ 1 2 概述 ......................................................................................................................................................................
2N5609中文资料
TO-66
Electrical Characteristics Tc=25
SYMBOL ICBO IEBO ICEO VCBO V(BR)CEO VEBO VCEsat-1 VCEsat-2 VCEsat-3 VCEsat-4 hFE-1 hFE-2 hFE-3 hFE-4 VBE(sat)1 VBE(sat)2 VBE(sat)3 fT tf ts PARAMETER Collector-base cut-off current Emitter-base cut-off current Collector-emitter cut-off current Collector-base breakdown voltage Collector-emitter breakdown voltage Emitter-base breakdown voltage Collector-emitter saturation voltages Collector-emitter saturation voltages Collector-emitter saturation voltages Collector-emitter saturation voltages Forward current transfer ratio Forward current transfer ratio Forward current transfer ratio Forward current transfer ratio Base-emitter saturation voltages Base-emitter saturation voltages Base-emitter saturation voltages Transition frequency at f = 1MHz Fall time Tum-off storage time IC=1A,VCE=2V 1.0 V IC=2.5A,VCE=5V 70 200 IC =1A; IB =0.1A 0.5 V IC=10mA,IB=0 80 V CONDITIONS VCB =80V;IE=0 VEB =5V, IC=0 MIN MAX 10 10 UNIT A A
ADC12062CIVF中文资料
TL H 11490ADC12062 12-Bit1 MHz 75 mW A D Converter with Input Multiplexer and Sample HoldDecember1994 ADC1206212-Bit 1MHz 75mW A D Converterwith Input Multiplexer and Sample HoldGeneral DescriptionUsing an innovative multistep conversion technique the12-bit ADC12062CMOS analog-to-digital converter digitizessignals at a1MHz sampling rate while consuming a maxi-mum of only75mW on a single a5V supply TheADC12062performs a12-bit conversion in three lower-res-olution‘‘flash’’conversions yielding a fast A D without thecost and power dissipation associated with true flash ap-proachesThe analog input voltage to the ADC12062is tracked andheld by an internal sampling circuit allowing high frequencyinput signals to be accurately digitized without the need foran external sample-and-hold circuit The multiplexer outputis available to the user in order to perform additional exter-nal signal processing before the signal is digitizedWhen the converter is not digitizing signals it can be placedin the Standby mode typical power consumption in thismode is100m WFeaturesY Built-in sample-and-holdY Single a5V supplyY Single channel or2channel multiplexer operationY Low Power Standby modeKey SpecificationsY Sampling rate1MHz(min)Y Conversion time740ns(typ)Y Signal-to-Noise Ratio f IN e100kHz69 5dB(min)Y Power dissipation(f s e1MHz)75mW(max)Y No missing codes over temperature GuaranteedApplicationsY Digital signal processor front endsY InstrumentationY Disk drivesY Mobile telecommunicationsY Waveform digitizersBlock DiagramTL H 11490–1 Ordering InformationIndustrial(b40 C s T A s a85 )PackageADC12062BIV V44Plastic Leaded Chip CarrierADC12062BIVF VGZ44A Plastic Quad Flat PackageADC12062CIV V44Plastic Leaded Chip CarrierADC12062CIVF VGZ44A Plastic Quad Flat PackageADC12062EVAL Evaluation BoardTRI-STATE is a registered trademark of National Semiconductor CorporationC1995National Semiconductor Corporation RRD-B30M75 Printed in U S AAbsolute Maximum Ratings(Notes1 2)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC e DV CC e AV CC)b0 3V to a6V Voltage at Any Input or Output b0 3V to V CC a0 3V Input Current at Any Pin(Note3)25mA Package Input Current(Note3)50mA Power Dissipation(Note4)875mW ESD Susceptibility(Note5)2000V Soldering Information(Note6)V Package Infrared 15seconds a300 C VF PackageVapor Phase(60seconds)a215 C Infrared(15seconds)a220 C Storage Temperature Range b65 C to a150 C Maximum Junction Temperature(T JMAX)150 C Operating Ratings(Notes1 2)Temperature Range T MIN s T A s T MAX ADC12062BIV ADC12062CIVADC12062BIVF ADC12062CIVF b40 C s T A s a85 C Supply Voltage Range(DV CC e AV CC)4 5V to5 5VConverter Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)Resolution12BitsDifferential Linearity Error T A e25 C g0 4g0 8LSB(max)T MIN to T MAX g0 95LSB(max)Integral Linearity Error T MIN to T MAX(BIV Suffix)g0 4g1 0LSB(max) (Note9)TA e a25 C(CIV Suffix)g0 4g1 0LSB(max)T MIN to T MAX(CIV Suffix)g1 5LSB(max) Offset Error T MIN to T MAX(BIV Suffix)g0 3g1 25LSB(max)T A e a25 C(CIV Suffix)g0 3g1 25LSB(max)T MIN to T MAX(CIV Suffix)g2 0LSB(max) Full Scale Error T MIN to T MAX(BIV Suffix)g0 2g1 0LSB(max)T A e a25 C(CIV Suffix)g0 2g1 0LSB(max)T MIN to T MAX(CIV Suffix)g1 5LSB(max) Power Supply Sensitivity DV CC e AV CC e5V g10%g1 0LSB(max) (Note15)R REF Reference Resistance750500X(min) 1000X(max)V REF(a)V REF a(SENSE)Input Voltage AV CC V(max)V REF(b)V REF b(SENSE)Input Voltage AGND V(min)V IN Input Voltage Range To V IN1 V IN2 or ADC IN AV CC a0 05V V(max)AGND b0 05V V(min) ADC IN Input Leakage AGND to AV CC b0 3V0 13m A(max) C ADC ADC IN Input Capacitance25pFMUX On-Channel Leakage AGND to AV CC b0 3V0 13m A(max)MUX Off-Channel Leakage AGND to AV CC b0 3V0 13m A(max) C MUX Multiplexer Input Cap7pFMUX Off Isolation f IN e100kHz92dB2Dynamic Characteristics(Note10)The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND R S e25X f IN e100kHz 0dB from fullscale and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)SINAD Signal-to-Noise Plus T MIN to T MAX7168 0dB(min) Distortion RatioSNR Signal-to-Noise Ratio T MIN to T MAX7269 5dB(min) (Note11)THD Total Harmonic Distortion T A e a25 C b82b74dBc(max) (Note12)T MIN to T MAX b70dBc(max) ENOB Effective Number of Bits T MIN to T MAX11 511 0Bits(min) (Note13)IMD Intermodulation Distortion f IN e102 3kHz 102 7kHz b80dBc DC Electrical Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limit)V IN(1)Logical‘‘1’’Input Voltage DV CC e AV CC e a5 5V2 0V(min)V IN(0)Logical‘‘0’’Input Voltage DV CC e AV CC e a4 5V0 8V(max) I IN(1)Logical‘‘1’’Input Current0 11 0m A(max) I IN(0)Logical‘‘0’’Input Current0 11 0m A(max)V OUT(1)Logical‘‘1’’Output Voltage DV CC e AV CC e a4 5VI OUT e b360m A2 4V(min)I OUT e b100m A4 25V(min) V OUT(0)Logical‘‘0’’Output Voltage DV CC e AV CC e a4 5V0 4V(max)I OUT e1 6mAI OUT TRI-STATE Output Pins DB0–DB110 13m A(max)Leakage CurrentC OUT TRI-STATE Output Capacitance Pins DB0–DB115pFC IN Digital Input Capacitance4pFDI CC DV CC Supply Current23mA(max) AI CC AV CC Supply Current1012mA(max) I STANDBY Standby Current(DI CC a AI CC)PD e0V20m A3AC Electrical Characteristics The following specifications apply for DV CC e AV CC e a5V V REF a(SENSE)e a4 096V V REF b(SENSE)e AGND and f s e1MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX all other limits T A e T J e a25 CSymbol Parameter ConditionsTyp Limit Units (Note7)(Note8)(Limits)f s Maximum Sampling Rate1MHz(min)(1 t THROUGHPUT)t CONV Conversion Time740600ns(min) (S H Low to EOC High)980ns(max)t AD Aperture Delay20ns (S H Low to Input Voltage Held)t S H S H Pulse Width5ns(min)550ns(max)t EOC S H Low to EOC Low9560ns(min) 125ns(max)t ACC Access Time C L e100pF1020ns(max) (RD Low or OE High to Data Valid)t1H t0H TRI-STATE ControlR L e1k C L e10pF2540ns(max) (RD High or OE Low to Databus TRI-STATE)t INTH Delay from RD Low to INT High C L e100pF3560ns(max)t INTL Delay from EOC High to INT Low C L e100pFb25b35ns(min) b10ns(max)t UPDATE EOC High to New Data Valid515ns(max)t MS Multiplexer Address Setup Time50ns(min) (MUX Address Valid to EOC Low)t MH Multiplexer Address Hold Time50ns(min) (EOC Low to MUX Address Invalid)t CSS CS Setup Time20ns(min) (CS Low to RD Low S H Low or OE High)t CSH CS Hold Time20ns(min) (CS High after RD High S H High or OE Low)t WU Wake-Up Time1m s (PD High to First S H Low)Note1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Electrical Characteris-tics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditionsNote2 All voltages are measured with respect to GND(GND e AGND e DGND) unless otherwise specifiedNote3 When the input voltage(V IN)at any pin exceeds the power supply rails(V IN k GND or V IN l V CC)the absolute value of current at that pin should be limited to25mA or less The50mA package input current limits the number of pins that can safely exceed the power supplies with an input current of25mA to twoNote4 The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX i JA and the ambient temperature T A The maximum allowable power dissipation at any temperature is P D e(T JMAX b T A) i JA or the number given in the Absolute Maximum Ratings whichever is lower i JA for the V (PLCC)package is55 C W i JA for the VF(PQFP)package is62 C W In most cases the maximum derated power dissipation will be reached only during fault conditions4Note5 Human body model 100pF discharged through a1 5k X resistor Machine model ESD rating is200VNote6 See AN-450‘‘Surface Mounting Methods and Their Effect on Product Reliability’’or the section titled‘‘Surface Mount’’found in a current National Semiconductor Linear Data Book for other methods of soldering surface mount devicesNote7 Typicals are at a25 C and represent most likely parametric normNote8 Tested limits are guaranteed to National’s AOQL(Average Outgoing Quality Level)Note9 Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpointsNote10 Dynamic testing of the ADC12062is done using the ADC IN input The input multiplexer adds harmonic distortion at high frequencies See the graph in the Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexerNote11 The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level Harmonics of the input signal are not included in its calculation Note12 The contributions from the first nine harmonics are used in the calculation of the THDNote13 Effective Number of Bits(ENOB)is calculated from the measured signal-to-noise plus distortion ratio(SINAD)using the equation ENOB e(SINAD b 1 76) 6 02Note14 The digital power supply current takes up to10seconds to decay to its final value after PD is pulled low This prohibits production testing of the standby current Some parts may exhibit significantly higher standby currents than the20m A typicalNote15 Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltageTRI-STATE Test Circuit and WaveformsTL H 11490–2TL H 11490–3TL H 11490–4TL H 11490–55Typical Performance CharacteristicsReference VoltageError Change vs Offset and Fullscale vs Reference VoltageLinearity Error Change Input VoltageMux ON Resistance vs vs Temperature Digital Supply Current vs TemperatureAnalog Supply Current on Digital Input PinsStandby Mode vs Voltage Current Consumption in vs Temperature Conversion Time (t CONV )vs TemperatureEOC Delay Time (t EOC )Spectral Response(ADC IN)SINAD vs Input Frequency (ADC IN)SNR vs Input Frequency (ADC IN)THD vs Input Frequency TL H 11490–276Typical Performance Characteristics(Continued)(Through Mux)SINAD vs Input Frequency (Through Mux)SNR vs Input Frequency (Through Mux)THD vs Input Frequency Impedance SNR and THD vs Source Reference VoltageSNR and THD vs TL H 11490–28Timing DiagramsTL H 11490–9FIGURE 1 Interrupt Interface Timing (MODE e 1 OE e 1)7Timing Diagrams (Continued)TL H 11490–10FIGURE 2 High Speed Interface Timing (MODE e 1 OE e 1 CS e 0 RD e 0)TL H 11490–11FIGURE 3 CS Setup and Hold Timing for S H RD and OEConnection DiagramsTL H 11490–13Top ViewTL H 11490–29Top View8Pin DescriptionsAV CC These are the two positive analog supplyinputs They should always be connectedto the same voltage source but arebrought out separately to allow for sepa-rate bypass capacitors Each supply pinshould be bypassed to AGND with a0 1m F ceramic capacitor in parallel with a10m F tantalum capacitorDV CC This is the positive digital supply input Itshould always be connected to the samevoltage as the analog supply AV CC Itshould be bypassed to DGND2with a0 1m F ceramic capacitor in parallel with a10m F tantalum capacitorAGND These are the power supply ground pins DGND1 There are separate analog and digital DGND2ground pins for separate bypassing of theanalog and digital supplies The groundpins should be connected to a stablenoise-free system ground All of theground pins should be returned to thesame potential AGND is the analogground for the converter DGND1is theground pin for the digital control linesDGND2is the ground return for the outputdatabus See Section6 0LAYOUT ANDGROUNDING for more informationDB0–DB11These are the TRI-STATE output pins en-abled by RD CS and OEV IN1 V IN2These are the analog input pins to the mul-tiplexer For accurate conversions no in-put pin(even one that is not selected)should be driven more than50mV belowground or50mV above V CCMUX OUT This is the output of the on-board analoginput multiplexerADC IN This is the direct input to the12-bit sam-pling A D converter For accurate conver-sions this pin should not be driven morethan50mV below AGND or50mV aboveAV CCS0This pin selects the analog input that willbe connected to the ADC12062during theconversion The input is selected based onthe state of S0when EOC makes its high-to-low transition Low selects V IN1 highselects V IN2MODE This pin should be tied to DV CCCS This is the active low Chip Select controlinput When low this pin enables the RDS H and OE inputs This pin can be tiedlowINT This is the active low Interrupt outputWhen using the Interrupt Interface Mode(Figure1) this output goes low when aconversion has been completed and indi-cates that the conversion result is avail-able in the output latches This output isalways high when RD is held low(Figure2)EOC This is the End-of-Conversion control out-put This output is low during a conversion RD This is the active low Read control inputWhen RD is low(and CS is low) the INToutput is reset and(if OE is high)data ap-pears on the data bus This pin can be tiedlowOE This is the active high Output Enable con-trol input This pin can be thought of as aninverted version of the RD input(see Fig-ure6) Data output pins DB0–DB11areTRI-STATE when OE is low Data appearson DB0–DB11only when OE is high andCS and RD are both low This pin can betied highS H This is the Sample Hold control input Theanalog input signal is held and a new con-version is initiated by the falling edge ofthis control input(when CS is low) PD This is the Power Down control input Thispin should be held high for normal opera-tion When this pin is pulled low the devicegoes into a low power standby mode V REF a(FORCE) These are the positive and negative volt-V REF b(FORCE)age reference force inputs respectivelySee Section4 REFERENCE INPUTS formore informationV REF a(SENSE) These are the positive and negative volt-V REF b(SENSE)age reference sense pins respectivelySee Section4 REFERENCE INPUTS formore informationV REF 16This pin should be bypassed to AGND witha0 1m F ceramic capacitorTEST This pin should be tied to DV CC9Functional DescriptionThe ADC12062performs a12-bit analog-to-digital conver-sion using a3step flash technique The first flash deter-mines the six most significant bits the second flash gener-ates four more bits and the final flash resolves the two least significant bits Figure4shows the major functional blocks of the converter It consists of a2 -bit Voltage Estimator a resistor ladder with two different resolution voltage spans a sample hold capacitor a4-bit flash converter with front end multiplexer a digitally corrected DAC and a capacitive volt-age dividerThe resistor string near the center of the block diagram in Figure4generates the6-bit and10-bit reference voltages for the first two conversions Each of the16resistors at the bottom of the string is equal to of the total string resist-ance These resistors form the LSB Ladder and have a voltage drop of of the total reference voltage(V REF a b V REF b)across each of them The remaining resistors form the MSB Ladder It is comprised of eight groups of eight resistors each connected in series(the lowest MSB ladder resistor is actually the entire LSB ladder) Each MSB Ladder section has of the total reference voltage across it Within a given MSB ladder section each of the eight MSB resistors has of the total reference voltage across it Tap points are found between all of the resistors in both the MSB and LSB ladders The Comparator MultipIexer can connect any of these tap points in two adjacent groups of eight to the sixteen comparators shown at the right of Figure4 This function provides the necessary reference voltages to the comparators during the first two flash con-versionsThe six comparators seven-resistor string(Estimator DAC ladder) and Estimator Decoder at the left of Figure4form Note The weight of each resistor on the LSB ladder is actually equivalent to four12-bit LSBs It is called the LSB ladder because it has thehighest resolution of all the ladders in the converter the Voltage Estimator The Estimator DAC connected be-tween V REF a and V REF b generates the reference volt-ages for the six Voltage Estimator comparators The com-parators perform a very low resoIution A D conversion to obtain an‘‘estimate’’of the input voltage This estimate is used to control the placement of the Comparator Multiplex-er connecting the appropriate MSB ladder section to the sixteen flash comparators A total of only22comparators(6 in the Voltage Estimator and16in the flash converter)is required to quantize the input to6bits instead of the64that would be required using a traditional6-bit flashPrior to a conversion the Sample Hold switch is closed allowing the voltage on the S H capacitor to track the input voItage Switch1is in position1 A conversion begins by opening the Sample Hold switch and latching the output of the Voltage Estimator The estimator decoder then selects two adjacent banks of tap points aIong the MSB ladder These sixteen tap points are then connected to the sixteen flash converters For exampIe if the input voltage is be-tween and of V REF(V REF e V REF a b V REF b) the estimator decoder instructs the comparator multiplexer to select the sixteen tap points between and ( and )of V REF and connects them to the sixteen comparators The first flash conversion is now performed producing the first6MSBs of dataAt this point Voltage Estimator errors as large as of V REF will be corrected since the comparators are connect-ed to ladder voltages that extend beyond the range speci-fied by the Voltage Estimator For example if( )V REF k V IN k( )V REF the Voltage Estimator’s comparators tied to the tap points below( )V REF will output‘‘1’’s (000111) This is decoded by the estimator decoder to‘‘10’’ The16comparators will be placed on the MSB ladderTL H 11490–14FIGURE4 Functional Block Diagram10Functional Description(Continued)tap points between( )V REF and( )V REF This overlap of ( )V REF will automatically cancel a Voltage Estimator er-ror of up to256LSBs If the first flash conversion deter-mines that the input voltage is between( )V REF and (( )V REF b LSB 2) the Voltage Estimator’s output code will be corrected by subtracting‘‘1’’ resulting in a corrected value of‘‘01’’for the first two MSBs If the first flash conver-sion determines that the input voltage is between( )V REF b LSB 2)and( )V REF the voltage estimator’s output code is unchangedThe results of the first flash and the Voltage Estimator’s output are given to the factory-programmed on-chip EEPROM which returns a correction code corresponding to the error of the MSB ladder at that tap This code is convert-ed to a voltage by the Correction DAC To generate the next four bits SW1is moved to position2 so the ladder voltage and the correction voltage are subtracted from the input voltage The remainder is applied to the sixteen flash con-verters and compared with the16tap points from the LSB ladderThe result of this second conversion is accurate to10bits and describes the input remainder as a voltage between two tap points(V H and V L)on the LSB ladder To resolve the last two bits the voltage across the ladder resistor(between V H and V L)is divided up into4equal parts by the capacitive voltage divider shown in Figure5 The divider also creates 6LSBs below V L and6LSBs above V H to provide overlap used by the digital error correction SW1is moved to posi-tion3 and the remainder is compared with these16new voltages The output is combined with the results of the Voltage Estimator first flash and second flash to yield the final12-bit resultBy using the same sixteen comparators for all three flash conversions the number of comparators needed by the multi-step converter is significantly reduced when compared to standard multi-step techniquesApplications Information1 0MODES OF OPERATIONThe ADC12062has two interface modes An interrupt read mode and a high speed mode Figures1and2show the timing diagrams for these interfacesIn order to clearly show the relationship between S H CS RD and OE the control logic decoding section of the ADC12062is shown in Figure6Interrupt InterfaceAs shown in Figure1 the falling edge of S H holds the input voltage and initiates a conversion At the end of the conver-sion the EOC output goes high and the INT output goes low indicating that the conversion results are latched and may be read by pulling RD low The falling edge of RD re-sets the INT line Note that CS must be low to enable S H or RDHigh Speed InterfaceThis is the fastest interface shown in Figure2 Here the output data is always present on the databus and the INT to RD delay is eliminatedTL H 11490–15FIGURE5 The Capacitive Voltage Divider11Applications Information (Continued)TL H 11490–16FIGURE 6 ADC Control Logic2 0THE ANALOG INPUTThe analog input of the ADC12062can be modeled as two small resistances in series with the capacitance of the input hold capacitor (C IN ) as shown in Figure 7 The S H switch is closed during the Sample period and open during Hold The source has to charge C IN to the input voltage within the sample period Note that the source impedance of the input voltage (R SOURCE )has a direct effect on the time it takes to charge C IN If R SOURCE is too large the voltage across C IN will not settle to within 0 5LSBs of V SOURCE before the conversion begins and the conversion results will be incor-rect From a dynamic performance viewpoint the combina-tion of R SOURCE R MUX R SW and C IN form a low pass filter Minimizing R SOURCE will increase the frequency re-sponse of the input stage of the converterTypical values for the components shown in Figure 7are R MUX e 100X R SW e 100X and C IN e 25pF The set-tling time to n bits ist SETTLE e (R SOURCE a R MUX a R SW ) C IN n ln (2) The bandwidth of the input circuit isf b 3dB e 1 (2 3 14 (R SOURCE a R MUX a R SW ) C IN )For maximum performance the impedance of the source driving the ADC12062should be made as small as possible A source impedance of 100X or less is recommended A plot of dynamic performance vs source impedance is given in the Typical Performance Characteristics sectionIf the signal source has a high output impedance its output should be buffered with an operational amplifier capable of driving a switched 25pF 100X load Any ringing or instabili-ties at the op amp’s output during the sampling period can result in conversion errors The LM6361high speed op amp is a good choice for this application due to its speed and its ability to drive large capacitive loads Figure 8shows the LM6361driving the ADC IN input of an ADC12062 The 100pF capacitor at the input of the converter absorbs some of the high frequency transients generated by the S H switching reducing the op amp transient response require-ments The 100pF capacitor should only be used with high speed op amps that are unconditionally stable driving ca-pacitive loadsTL H 11490–17FIGURE 7 Simplified ADC12062Input Stage12Applications Information (Continued)TL H 11490–18FIGURE 8 Buffering the Input with an LM6361High Speed Op AmpAnother benefit of using a high speed buffer is improved THD performance when using the multiplexer of the ADC12062 The MUX on-resistance is somewhat non-linear over input voltage causing the RC time constant formed by C IN R MUX and R SW to vary depending on the input voltage This results in increasing THD with increasing frequency Inserting the buffer between the MUX OUT and the ADC IN terminals as shown in Figure 8will eliminate the loading on R MUX significantly reducing the THD of the multiplexed sys-temCorrect converter operation will be obtained for input volt-ages greater than AGND b 50mV and less than AV CC a50mV Avoid driving the signal source more than 300mV higher than AV CC or more than 300mV below AGND If an analog input pin is forced beyond these voltages the cur-rent flowing through that pin should be limited to 25mA or less to avoid permanent damage to the IC The sum of all the overdrive currents into all pins must be less than 50mA When the input signal is expected to extend more than 300mV beyond the power supply limits for any reason (un-known uncontrollable input voltage range power-on tran-sients fault conditions etc )some form of input protection such as that shown in Figure 9 should be usedTL H 11490–19FIGURE 9 Input Protection13Applications Information(Continued)3 0ANALOG MULTIPLEXERThe ADC12062has an input multiplexer that is controlled by the logic level on pin S0when EOC goes low as shown in Figures1and2 Multiplexer setup and hold times with re-spect to the S H input can be determined by these two equationst MS(wrt S H)e t MS b t EOC(min)e50b60e b10ns t MH(wrt S H)e t MH a t EOC(max)e50a125e175ns Note that t MS(wrt S H)is a negative number this indicates that the data on S0must become valid within10ns after S H goes low in order to meet the setup time requirements S0must be valid for a length of(t MH a t EOC(max))b(t MS b t EOC(min))e185ns Table I shows how the input channels are assignedTABLE I ADC12062InputMultiplexer ProgrammingS0Channel0V IN11V IN2The output of the multiplexer is available to the user via the MUX OUT pin This output allows the user to perform addi-tional signal processing such as filtering or gain before the signal is returned to the ADC IN input and digitized If no additional signal processing is required the MUX OUT pin should be tied directly to the ADC IN pinSee Section9 0(APPLICATIONS)for a simple circuit that will alternate between the two inputs while converting at full speed4 0REFERENCE INPUTSIn addition to the fully differential V REF a and V REF b refer-ence inputs used on most National Semiconductor ADCs the ADC12062has two sense outputs for precision control of the ladder voltage These sense inputs compensate for errors due to IR drops between the reference source and the ladder itself The resistance of the reference ladder is typically750X The parasitic resistance(R P)of the package leads bond wires PCB traces etc can easily be0 5X to 1 0X or more This may not be significant at8-bit or10-bit resolutions but at12bits it can introduce voltage drops causing offset and gain errors as large as6LSBsThe ADC12062provides a means to eliminate this error by bringing out two additional pins that sense the exact voltage at the top and bottom of the ladder With the addition of two op amps the voltages on these internal nodes can be forced to the exact value desired as shown in Figure10TL H 11490–20FIGURE10 Reference Ladder Force and Sense Inputs14。
HEDS-9140中文资料
The HEDS-9040 and 9140 provide sophisticated motion control detection at a low cost, making them ideal for high volume applications. Typical applications include printers, plotters, tape drives, and industrial and factory automation equipment.
2.16 (0.085) DEEP
1.78 ± (0.070 ± 0.004)
2.92 ± 0.10 (0.115 ± 0.004)
OPTICAL CENTER
10.16 (0.400)
OPTICAL CENTER LINE
5.46 ± 0.10 (0.215 ± 0.004)
TYPICAL DIMENSIONS IN MILLIMETERS AND (INCHES)
元器件交易网
Three Channel Optical Incremental Encoder Modules
Technical Data
HEDS-9040 HEDS-9140
Features
• Two Channel Quadrature Output with Index Pulse
1.52 (0.060)
DATE CODE
3.73 ± 0.05 (0.147 ± 0.002)
20.8 (0.82)
11.7 (0.46)
2.21 (0.087) 2.54
(0.100)
2.67 (0.105) DIA. MOUNTING THRU HOLE 2 PLACES
AP9620GM中文资料
P-CHANNEL ENHANCEMENT MODE POWER MOSFET▼ Low On Resistance BV DSS -20V C ▼apable of 2.5V Drive R DS(ON)20m Ω ▼Fast SwitchingI D-9.5A▼Simple Drive RequirementDescriptionAbsolute Maximum RatingsSymbol Units V DS V V GSV I D @T A =25℃A I D @T A =70℃A I DMA P D @T A =25℃W W/℃T STG ℃T J℃Symbol Value Unit Rthj-ambThermal Resistance Junction-ambient 3Max.50℃/WData and specifications subject to change without noticePb Free Plating ProductThermal DataParameterTotal Power Dissipation 2.5-55 to 150Operating Junction Temperature Range-55 to 150Linear Derating Factor 0.02Storage Temperature RangeContinuous Drain Current 3-7.6Pulsed Drain Current 1-76ParameterDrain-Source Voltage Gate-Source Voltage Continuous Drain Current 320020502AP9620GMRating -20±8-9.5The Advanced Power MOSFETs from APEC provide the designer with the best combination of fast switching,ruggedized device design, low on-resistance and cost-effectiveness.The SO-8 package is universally preferred for all commercial-industrial surface mount applications and suited for low voltage applications such as DC/DC converters.SSSGDD DDSO-8Electrical Characteristics@T j =25o C(unless otherwise specified)Symbol ParameterTest ConditionsMin.Typ.Max.Units BV DSSDrain-Source Breakdown Voltage V GS =0V, I D =-250uA -20--V ΔB V DSS /ΔT jBreakdown Voltage Temperature Coefficient Reference to 25℃, I D =-1mA--0.037-V/℃R DS(ON)Static Drain-Source On-Resistance 2V GS =-4.5V, I D =-9.5A --20m ΩV GS =-2.5V, I D =-6.0A --35m ΩV GS(th)Gate Threshold Voltage V DS =V GS , I D =-250uA ---1V g fs Forward TransconductanceV DS =-10V, I D =-9.5A -28-S I DSS Drain-Source Leakage Current (T j =25o C)V DS =-20V, V GS =0V ---1uA Drain-Source Leakage Current (T j =70o C)V DS =-16V, V GS =0V ---25uA I GSS Gate-Source Leakage V GS =--nA Q g Total Gate Charge 2I D =-9.5A -30-nC Q gs Gate-Source Charge V DS =-10V -6-nC Q gd Gate-Drain ("Miller") Charge V GS =-5V - 3.5-nC t d(on)Turn-on Delay Time 2V DS =-10V -26-ns t r Rise TimeI D =-9.5A-500-ns t d(off)Turn-off Delay Time R G =6Ω,V GS =-4.5V -70-ns t f Fall Time R D =1.05Ω-300-ns C iss Input Capacitance V GS =0V -2158-pF C oss Output CapacitanceV DS =-15V -845-pF C rssReverse Transfer Capacitancef=1.0MHz -230-pFSource-Drain DiodeSymbol ParameterTest ConditionsMin.Typ.Max.Units I S Continuous Source Current ( Body Diode )V D =V G =0V , V S =-1.2V ---2.08A V SDForward On Voltage 2T j =25℃, I S =-2.5A, V GS =0V---1.2VNotes:1.Pulse width limited by Max. junction temperature.2.Pulse width <300us , duty cycle <2%.3.Surface mounted on 1 in 2 copper pad of FR4 board ; 125 ℃/W when mounted on Min. copper pad.AP9620GM± 8V ±100AP9620GMFig 1. Typical Output Characteristics Fig 2. Typical Output CharacteristicsFig 3. On-Resistance v.s. Gate VoltageFig 4. Normalized On-Resistancev.s. Junction TemperatureFig 5. Maximum Drain Current v.s. Fig 6. Typical Power DissipationCase TemperatureFig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal ImpedanceAP9620GMAP9620GMFig 9. Gate Charge Characteristics Fig 10. Typical Capacitance CharacteristicsFig 11. Forward Characteristic ofFig 12. Gate Threshold Voltage v.s.Reverse DiodeJunction TemperatureAP9620GMFig 13. Switching Time Circuit Fig 14. Switching Time WaveformFig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform。
ERJ-S08F2432V中文资料(panasonic)中文数据手册「EasyDatasheet - 矽搜」
× Resistance Values, or Limiting Element Voltage × Power Rating or max. Overload Voltage listed above
Type
（英制）
ERJS6S (0805) ERJS6Q (0805)
PowerRating电阻
在70℃下 公差
Ambient Temperature (°C)
Type: ERJ S02,S03,S06,S08,S14中 S12中,S1D,S1T（Au类内电极型）
Type: ERJ S6S,S6Q（银钯基内电极型）
Type: ERJ U01, U02, U03, U06, U08, U14, U12,U1D,U1T（银钯基内电极型）
■ 特征
● 高抗硫化通过采用金基内电极来实现（ERJS0 / S1型）
ERJS1T ERJU1T (2512)
额定功率
在70℃下 (W) 0.05 0.1
0.1
0.125
0.25
0.5
0.75
0.75
1.0
限制 因素 电压
(V) 25 50
75
150
200
200
200
200
200
极大 超载 电压
(V) 50 100
150
200
400
400
500
500
500
抵抗性 公差
Example: 222 2.2 k, 1002 10 k
Packaging Methods
Code Packaging C 2 mPrmesspeitdchC,a1r5ri,e0r0T0appcins.g
ELJRF2R2DF中文资料(panasonic)中文数据手册「EasyDatasheet - 矽搜」
10 12 15 18 22 27 33 39 47 56 68 82 100 120 150 180 220 270 330 390 470 560 680 820 1000
±10 %
± 5% ±10 %
V1 : Self Resonant Frequency V2 : DC Resistance
nH
公差
ELJRE1N0DF2
1.0
ELJRE1N2DF2 ELJRE1N5DF2
1.2
1.5
±0.3 nH
ELJRE1N8DF2
1.8
ELJRE2N2DF2
2.2
ELJRE2N7DF2
2.7
ELJRE3N3DF2
3.3
ELJRE3N9JF2
3.9
ELJRE4N7JF2
4.7
ELJRE5N6JF2
5.6
36
5500
0.15
450
36
4800
0.17
450
9
36
4600
0.18
430
36
3550
0.20
430
100.
36
3500
0.28
400
37
2800
0.32
400
37
2800
0.35
400
38
2500
0.41
350
10
39
2300
0.45
350
40
2000
0.50
300
41
2000
0.55
300
40
1800
0.60
300
11
39
IXFH26N60中文资料
Min. Recommended Footprint
© 2000 IXYS All rights reserved
IXYS MOSFETS and IGBTs are covered by one or more of the following U.S. patents: 4,835,592 4,881,106 5,017,508 5,049,961 5,187,117 5,486,715 4,850,072 4,931,844 5,034,796 5,063,307 5,237,481 5,381,025
SIHFU220中文资料
Power MOSFETIRFR220, IRFU220, SiHFR220, SiHFU220Vishay SiliconixFEATURES•Dynamic dV/dt Rating •Repetitive Avalanche Rated •Surface Mount (IRFR220/SiHFR220)•Straight Lead (IRFU220/SiHFU220)•Available in Tape and Reel •Fast Switching •Ease of Paralleling •Lead (Pb)-free AvailableDESCRIPTIONThird generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching,ruggedized device design, low on-resistance and cost-effectiveness.The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU/SiH FU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surcace mount applications.a.See device orientation.Notesb.Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).c.V DD = 50 V, starting T J = 25 °C, L = 14 mH, R G = 25 Ω, I AS = 4.8 A (see fig. 12).d.I SD ≤ 5.2 A, dI/dt ≤ 95 A/µs, V DD ≤ V DS , T J ≤ 150 °C.e. 1.6 mm from case.f.When mounted on 1" square PCB (FR-4 or G-10 material).PRODUCT SUMMARYV DS (V)200R DS(on) (Ω)V GS = 10 V0.80Q g (Max.) (nC)14Q gs (nC) 3.0Q gd (nC)7.9ConfigurationSingleORDERING INFORMATIONPackage DPAK (TO-252)DPAK (TO-252)DPAK (TO-252)DPAK (TO-252)IPAK (TO-251)Lead (Pb)-free IRFR220PbF IRFR220TRLPbF a IRFR220TRPbF a IRFR220TRRPbF a IRFU220PbF SiHFR220-E3SiHFR220TL-E3a SiHFR220T-E3a SiHFR220TR-E3a SiHFU220-E3 SnPbIRFR220IRFR220TRL a IRFR220TR a IRFR220TRR a IRFU220SiHFR220SiHFR220TL aSiHFR220T aSiHFR220TR aSiHFU220ABSOLUTE MAXIMUM RATINGS T C = 25 °C, unless otherwise notedPARAMETER SYMBOL LIMITU NITDrain-Source Voltage V DS 200VGate-Source Voltage V GS ± 20 Continuous Drain CurrentV GS at 10 VT C = 25 °C I D4.8A T C = 100 °C3.0Pulsed Drain Current a I DM 19Linear Derating Factor0.33W/°CLinear Derating Factor (PCB Mount)e 0.020Single Pulse Avalanche Energy b E AS 230mJ Repetitive Avalanche Current a I AR 4.8 A Repetitive Avalanche Energy a E AR 4.2mJMaximum Power Dissipation T C = 25 °CP D 42WMaximum Power Dissipation (PCB Mount)e T A = 25 °C 2.5Peak Diode Recovery dV/dt cdV/dt 5.0V/ns Operating Junction and Storage Temperature Range T J , T stg - 55 to + 150°CSoldering Recommendations (Peak Temperature)for 10 s 260dIRFR220, IRFU220, SiHFR220, SiHFU220Vishay SiliconixNotea.When mounted on 1" square PCB (FR-4 or G-10 material).Notesa.Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).b.Pulse width ≤ 300 µs; duty cycle ≤ 2 %.THERMAL RESISTANCE RATINGSPARAMETER SYMBOL MI.TYP.MAX.U ITMaximum Junction-to-Ambient R thJA --110°C/W Maximum Junction-to-Ambient (PCB Mount)aR thJA --50Maximum Junction-to-Case (Drain)R thJC-- 3.0IRFR220, IRFU220, SiHFR220, SiHFU220Vishay Siliconix TYPICAL CHARACTERISTICSFig. 1 - Typical Output Characteristics, T C = 25 °CIRFR220, IRFU220, SiHFR220, SiHFU220 Vishay SiliconixIRFR220, IRFU220, SiHFR220, SiHFU220Vishay SiliconixFig. 9 - Maximum Drain Current vs. Case TemperatureFig. 10a - Switching Time Test CircuitFig. 10b - Switching Time WaveformsFig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-CaseIRFR220, IRFU220, SiHFR220, SiHFU220Vishay SiliconixFig. 12b - Unclamped Inductive WaveformsFig. 12c - Maximum Avalanche Energy vs. Drain CurrentFig. 13a - Basic Gate Charge WaveformFig. 13b - Gate Charge Test CircuitIRFR220, IRFU220, SiHFR220, SiHFU220Vishay Siliconix Array Fig. 14 - For N-ChannelVishay Siliconix maintains worldwide manufacturing cap ability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andreliability data, see /ppg?91270.Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。
SI8420资料
2500 VRMS isolation Transient Immunity
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 22 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. Package Outline: 8-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
mb89f202中文资料
敞末让开端没。没有有使使用用的的I/O输末入端末进端入会输引出起状误态动后作并和把锁其定敞，开造；成如永其久在性输损入害状，态故，请就用按2照kΩ输或入以末上端的的电处阻理上方拉法或处下理拉该末等端I/。O
• N.C. 管脚的处置
（转下页）
6
系列 MB89202
（承上页） 管脚编号
SH-DIP32*1 SSOP34*3
24-27 26-29
21-23 32 10
23-25 34 10
管脚名称
P40/AN0 |
P43/AN3 P70-P72
VCC VSS
16
17
C
, — 16 22 :*1 DIP-32P-M06 :*2 FPT-34P-M03
（转下页）
2
系列 MB89202
（承上页）
产品型号 参数
MB89202
MB89F202
MB89V201
10 位 A/D 转换器 1A通0/D过位转精8换/度1功6×位能8定(个时转通器换道时/ 计间数：器1输2.出16或µ时s/1基2.定5 时MH器z计) 数器连续激活
Wild 寄存器
位8 × 2
：有 ×：无
MB89202 ×
MB89F202 ×
MB89V201 × ×
■ 产品间的差异
• 存储器容量
使用评价产品进行评价之前， 请先确认其与实际使用产品的差异。
• 屏蔽选项
产品不同，可以选择的项目和指定选项的方法也不同。选择之前，请查阅 “■ 屏蔽选项”一览表。
3
系列 MB89202
■ 管脚图
P33/EC
15
N.C.
16
C
IRF9620中文资料
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2)
BVDSS VGS(TH)
IDSS
ID(ON) IGSS rDS(ON) gfs
ID = -250µA, VGS = 0V, (Figure 10) VGS = VDS, ID = -250µA VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC =125oC VDS > ID(ON) x rDS(ON)MAX, VGS = -10V VGS = ±20V ID = -1.5A, VGS = -10V, (Figures 8, 9) VDS > ID(ON) x rDS(ON)MAX, ID = -1.5A, (Figure 12)
ZX970中文资料(List Unclassifed)中文数据手册「EasyDatasheet - 矽搜」
提供命令功能和通告达
8分在一个区域.这些任意组合 指挥中心可在相同区域内使用. 容易记得好像是命令1命令, 命令2,和命令8做出一个简单过渡调味 RADIONICS用户.
编程.
份接收器,自动检测报告,选择继电器激活,和自定 义文字相关指挥中心和报警器.
当复位报警,布防还是撤防组合火警/盗和 /或门禁系统时,用户应当由名称和编号进行标识.
D7212/D7412G: 最多99个用户 D9112/D9412G: 多达249用户
面板内部时钟应支持Skeds（预定 事件）功能.用户有权选择改变SKED 使用可编程密码激活时间.
远程编程,记录存储,远程控制
和故障排除工具,用于D9412G / D7412G
控制/通讯器.以增强下/上载
能力RAM可以在TCP / IP和动态可使用
主机通信协议（DHCP）配置.
芯片中文手册,看全文,戳
D9412G/D7412G
技术指标
一般
承包商应提供并安装,其中显示在 计划中,RADIONICS D9412G / D7412G 控制/通信.小组应列出 美国防护险商实验室NFPA 72应用程序.
配备一个16字符显示屏,独特火警及爆窃色调,和背 光多键触控板.
D1255,D1256,D1257和有权显示每个检测点功能： 报警,故障,监控,或者是错误,和自定义文本 .此外,扩展寻址点显示应包括失踪和额外点信息. 全系统显示应包括：本地系统测试,传感器复位, 防火测试模式和用户编程提示.
EFD20-3C94中文资料(ferroxcube)中文数据手册「EasyDatasheet - 矽搜」
2008年9月1
Dimensionsin mm.
图1 EFD20/10/7核心一半.
µe
76 121 193 302 380 1570
76 121 193 302 380 1570 1865 1450
76 121 193 302 380 1450
L 测量20
±10 N,除非另有
TOTAL AIR GAP (µm) 960 510 280 160 120 0 960 510 280 160 120 0 0 0 960 510 280 160 120 0
5.2 ±0.3 1.6
14.1 ±0.1
0.6 17.5 ±0.1 21.2最大.
图2 EFD20/10/7线圈架; 8针.
5 17.5
+0.15 1.3 0
绕组数据和区域产品 EFD20线圈架具有 8管脚
单位数
SECTIONS
1
绕组
AREA (mm 2)
26.4
最低 绕组
WIDTH (mm)
13.2
°C, 3.5 s °C, 2 s
handbook, full pagewidth
10马克斯9.5最大 Dimensionsin mm.
14.8最大
10.6 0 0.15 9.23 +00.1 5
14.8 0 0.2 13.2分钟
5 ±0.1 15 ±0.1 20.2最大.
+0.1 3.93 0 5.3 0 0.1
Note 1.也可与后插入针.
平均 长研究
TURN (mm)
36.5
AREA
产品
阂 x仙 (mm 4)
818
类型编号
CSH-EFD20-1S-8P (1)
PCF8820资料
DATA SHEET
PCF8820 67 × 101 Grey-scale/ECB colour dot matrix LCD driver
Product specification File under Integrated Circuits, IC12 2000 Dec 07
The PCF8820 is a low power CMOS LCD row/column driver, designed to drive grey-scale/ ECB colour dot matrix graphic displays at a multiplex rate of 1 : 67. In the partial screen mode, only 8 rows are driven at a multiplex rate of 1 : 8. This chip provides all the necessary display functions, including on-chip generation of the LCD supply voltage and LCD bias voltages. Consequently, fewer external components are required and the power consumption is low. The PCF8820 interfaces with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). All inputs are CMOS compatible. Remark: the waveform generation for ECB colour is identical to that used for grey-scale.
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Power MOSFETIRF9620, SiHF9620Vishay SiliconixFEATURES•Dynamic dV/dt Rating•P-Channel •Fast Switching •Ease of Paralleling •Simple Drive Requirements •Lead (Pb)-free AvailableDESCRIPTIONThird generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching,ruggedized device design, low on-resistance and cost-effectiveness.The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry.Notesa.Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).b.I SD ≤ - 3.5 A, dI/dt ≤ 95 A/µs, V DD ≤ V DS , T J ≤ 150 °C.c. 1.6 mm from case.PRODUCT SUMMARYV DS (V)- 200R DS(on) (Ω)V GS = - 10 V1.5Q g (Max.) (nC)22Q gs (nC)12Qgd (nC)10ConfigurationSingleTO-220GDSORDERING INFORMATIONPackage TO-220Lead (Pb)-free IRF9620PbF SiHF9620-E3 SnPbIRF9620SiHF9620ABSOLUTE MAXIMUM RATINGS T C = 25 °C, unless otherwise notedPA AMETE SYMBOL LIMIT UNIT Drain-Source Voltage V DS- 200VGate-Source Voltage V GS ± 20 Continuous Drain Current V GS at - 10 VT C = 25 °C I D- 3.5A T C = 100 °C- 2.0Pulsed Drain Current a I DM - 14Linear Derating Factor 0.32W/°C Maximum Power Dissipation T C = 25 °CP D 40WPeak Diode Recovery dV/dt bdV/dt - 5.0V/ns Operating Junction and Storage Temperature Range T J , T stg- 55 to + 150°C Soldering Recommendations (Peak Temperature)for 10 s 300c Mounting Torque6-32 or M3 screw 10 lbf · in 1.1N · m * Pb containing terminations are not RoHS compliant, exemptions may applyIRF9620, SiHF9620Vishay SiliconixNotesa.Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).b.Pulse width ≤ 300 µs; duty cycle ≤ 2 %.THERMAL RESISTANCE RATINGSPA AMETE SYMBOL TYP.MAX.UNITMaximum Junction-to-Ambient R thJA -62°C/WCase-to-Sink, Flat, Greased Surface R thCS 0.50-Maximum Junction-to-Case (Drain)R thJC- 3.1IRF9620, SiHF9620Vishay SiliconixTYPICAL CHARACTERISTICS 25 °C, unless otherwise notedFig. 2 - Typical Transfer CharacteristicsFig. 3 - Typical Saturation CharacteristicsFig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to-Case vs. Pulse DurationIRF9620, SiHF9620Vishay SiliconixFig. 8 - Breakdown Voltage vs. TemperatureFig. 10 - Typical Capacitance vs. Drain-to-Source VoltageIRF9620, SiHF9620Vishay SiliconixFig. 12 - Typical On-Resistance vs. Drain CurrentFig. 15 - Clamped Inductive Test CircuitFig. 17a - Switching Time Test Circuit Fig. 17b - Switching Time WaveformsIRF9620, SiHF9620Vishay SiliconixFig. 18a - Basic Gate Charge WaveformVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, andDisclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。