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W3EG7234S265JD3资料

White Electronic DesignsW3EG7234S-D3-JD3-AJD3PRELIMINARY*256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLLDESCRIPTIONThe W3EG7234S is a 32Mx72 Double Data Rate SDRAM memory module based on 128Mb DDRSDRAM component. The module consists of eighteen 32Mx4 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate.Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow thesame device to be useful for a variety of high bandwidth, high performance memory system applications.* T his product is under development, is not qualiﬁ ed or characterized and is subject to change without notice.FEATURESDouble-data-rate architecture Clock speeds: 100MHz and 133MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8)Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power Supply: 2.5V ± 0.20VJEDEC standard 184 pin DIMM package•Package height options: JD3: 30.48mm (1.20") AJD3: 28.70mm (1.13")OPERATING FREQUENCIESDDR266 @CL=2DDR266 @CL=2.5DDR200 @CL=2Clock Speed 133MHz 133MHz 100MHz CL-t RCD -t RP2-2-22.5-3-32-2-2White Electronic DesignsW3EG7234S-D3-JD3-AJD3PRELIMINARYPIN CONFIGURATIONSPIN NAMESA0 – A12Address input (Multiplexed)BA0-BA1Bank Select Address DQ0-DQ63 Data Input/Output CB0-CB7Check bitsDQS0-DQS17Data Strobe Input/Output CK0Clock Input CK0#Clock InputCKE0Clock Enable Input CS0#Chip select Input RAS#Row Address Strobe CAS#Column Address Strobe WE#Write Enable V CC Power SupplyV CCQ Power Supply for DQS V SS GroundV REF Power Supply for Reference V CCSPD Serial EEPROM Power Supply SDA Serial data I/O SCL Serial clockSA0-SA2Address in EEPROM V CCID V CC Identiﬁ cation Flag NCNo Connect RESET#Reset EnablePIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V REF 47DQS893V SS 139V SS 2DQ048A094DQ4140DQS173V SS 49CB295DQ5141A104DQ150V SS 96V CCQ 142CB65DQS051CB397DQS9143V CCQ 6DQ252BA198DQ6144CB77V CC 53DQ3299DQ7145V SS 8DQ354V CCQ 100V SS 146DQ369NC 55DQ33101NC 147DQ3710RESET#56DQS4102NC 148V CC 11V SS 57DQ34103NC 149DQS1312DQ858V SS 104V CCQ 150DQ3813DQ959BA0105DQ12151DQ3914DQS160DQ35106DQ13152V SS 15V CCQ 61DQ40107DQS10153DQ4416*CK162V CCQ 108V CC 154RAS#17*CK1#63WE#109DQ14155DQ4518V SS 64DQ41110DQ15156V CCQ 19DQ1065CAS#111*CKE1157CS0#20DQ1166V SS 112V CCQ 158*CS1#21CKE067DQS5113*BA2159DQS1422V CCQ 68DQ42114DQ20160V SS 23DQ1669DQ43115A12161DQ4624DQ1770V CC 116V SS 162DQ4725DQS271*CK2#117DQ21163*CS3#26V SS 72DQ48118A11164V CCQ 27A973DQ49119DQS11165DQ5228DQ1874V SS 120V CC 166DQ5329A775*CK2#121DQ22167A13*30V CCQ 76*CK2122A8168V CC 31DQ1977V CCQ 123DQ23169DQS1532A578DQS6124V SS 170DQ5433DQ2479DQ50125A6171DQ5534V SS 80DQ51126DQ28172V CCQ 35DQ2581V SS 127DQ29173NC 36DQS382V CCID 128V CCQ 174DQ6037A483DQ56129DQS12175DQ6138V CC 84DQ57130A3176V SS 39DQ2685V CC 131DQ30177DQS1640DQ2786DQS7132V SS 178DQ6241A287DQ58133DQ31179DQ6342V SS 88DQ59134CB4180V CCQ 43A189V SS 135CB5181SA044CB090NC 136V CCQ 182SA145CB191SDA 137CK0183SA246V CC92SCL138CK0#184V CCSPD* Not UsedWhite Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARY FUNCTIONAL BLOCK DIAGRAMWhite Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARYABSOLUTE MAXIMUM RATINGSParameter Symbol Value UnitsVoltage on any pin relative to V SS V IN, V OUT-0.5 to 3.6VVoltage on V CC supply relative to V SS V CC, V CCQ-1.0 to 3.6VStorage Temperature T STG-55 to +150°CPower Dissipation P D27WShort Circuit Current I OS50mANote: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliabilityDC CHARACTERISTICS0°C ≤ T A≤ 70°C, V CC = 2.5V ± 0.2VParameter Symbol Min Max Unit Supply Voltage V CC 2.3 2.7V Supply Voltage V CCQ 2.3 2.7V Reference Voltage V REF 1.15 1.35V Termination Voltage V TT 1.15 1.35VInput High Voltage V IH V REF + 0.15V CCQ + 0.3VInput Low Voltage V IL-0.3V REF -0.15V Output High Voltage V OH V TT + 0.76—V Output Low Voltage V OL—V TT-0.76VCAPACITANCET A = 25°C. f = 1MHz, V CC = 2.5VParameter Symbol Max UnitInput Capacitance (A0-A12)C IN1 6.25pFInput Capacitance (RAS#,CAS#,WE#)C IN2 6.25pFInput Capacitance (CKE0)C IN3 6.25pFInput Capacitance (CK0#,CK0)C IN4 5.5pFInput Capacitance (CS0#)C IN5 6.25pFInput Capacitance (DQS0-DQS17)C IN613pFInput Capacitance (BA0-BA1)C IN7 6.25pFData input/output capacitance (DQ0-DQ63)(DQS)C OUT13pFData input/output capacitance (CB0-CB7)C OUT13pFWhite Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARYI DD SPECIFICATIONS AND TEST CONDITIONS0°C ≤ T A≤ 70°C, V CCQ = 2.5V ± 0.2V, V CC = 2.5V ± 0.2VIncludes PLL and Register PowerParameter Symbol Rank 1ConditionsDDR266@CL=2MaxDDR266@CL=2.5MaxDDR200@CL=2Max UnitsOperating Current I DD0One device bank; Active - Precharge; t RC= t RC (MIN); t CK = t CK (MIN); DQ,DM andDQS inputs changing once per clock cycle;Address and control inputs changing onceevery two cycles.252023852385mAOperating Current I DD1One device bank; Active-Read-PrechargeBurst = 2; t RC = t RC (MIN); t CK = t CK (MIN);l OUT = 0mA; Address and control inputschanging once per clock cycle.270025202520mAPrecharge Power-Down Standby Current I DD2P All device banks idle; Power-down mode;t CK = t CK (MIN); CKE = (low)545454mAIdle Standby Current I DD2F CS# = High; All device banks idle;t CK = t CK (MIN); CKE = High; Addressand other control inputs changing onceper clock cycle. V IN = V REF for DQ, DQSand DM.112010301030mAActive Power-Down Standby Current I DD3P One device bank active; Power-Downmode; t CK (MIN); CKE = (low)450360360mAActive Standby Current I DD3N CS# = High; CKE = High; One devicebank; Active-Precharge;t RC = t RAS (MAX);t CK = t CK (MIN); DQ, DM and DQS inputschanging twice per clock cycle; Addressand other control inputs changing once perclock cycle.121011201120mAOperating Current I DD4R Burst = 2; Reads; Continuous burst; Onedevice bank active; Address and controlinputs changing once per clock cycle; t CK =t CK (MIN); l OUT = 0mA.274526102610mAOperating Current I DD4W Burst = 2; Writes; Continuous burst; Onedevice bank active; Address and controlinputs changing once per clock cycle;t CK = t CK (MIN); DQ,DM and DQS inputschanging once per clock cycle.270025652565mAAuto Refresh Current I DD5t RC = t RC (MIN)377036803645mA Self Refresh Current I DD6CKE ≤ 0.2V329311346mA Operating Current I DD7A Four bank interleaving Reads (BL=4)with auto precharge with t RC=t RC (MIN);t CK=t CK(MIN); Address and control inputschange only during Active Read or Writecommands.486047704770mAWhite Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARYI DD SPECIFICATIONS AND TEST CONDITIONS0°C ≤ T A≤ 70°C, V CCQ = 2.5V ± 0.2V, V CC = 2.5V ± 0.2VIncludes DDR SDRAM components onlyParameter Symbol Rank 1ConditionsDDR266@CL=2MaxDDR266@CL=2.5MaxDDR200@CL=2Max UnitsOperating Current I DD0One device bank; Active - Precharge; t RC= t RC (MIN); t CK = t CK (MIN); DQ,DM andDQS inputs changing once per clock cycle;Address and control inputs changing onceevery two cycles.193518001800mAOperating Current I DD1One device bank; Active-Read-PrechargeBurst = 2; t RC = t RC (MIN); t CK = t CK (MIN);l OUT = 0mA; Address and control inputschanging once per clock cycle.211519351935mAPrecharge Power-Down Standby Current I DD2P All device banks idle; Power-down mode;t CK = t CK (MIN); CKE = (low)545454mAIdle Standby Current I DD2F CS# = High; All device banks idle;t CK = t CK (MIN); CKE = High; Addressand other control inputs changing onceper clock cycle. V IN = V REF for DQ, DQSand DM.810720720mAActive Power-Down Standby Current I DD3P One device bank active; Power-Downmode; t CK (MIN); CKE = (low)450360360mAActive Standby Current I DD3N CS# = High; CKE = High; One devicebank; Active-Precharge;t RC = t RAS (MAX);t CK = t CK (MIN); DQ, DM and DQS inputschanging twice per clock cycle; Addressand other control inputs changing once perclock cycle.900810810mAOperating Current I DD4R Burst = 2; Reads; Continuous burst; Onedevice bank active; Address and controlinputs changing once per clock cycle; t CK =t CK (MIN); l OUT = 0mA.216020252025mAOperating Current I DD4W Burst = 2; Writes; Continuous burst; Onedevice bank active; Address and controlinputs changing once per clock cycle;t CK = t CK (MIN); DQ,DM and DQS inputschanging once per clock cycle.211519801980mAAuto Refresh Current I DD5t RC = t RC (MIN)315030603060mA Self Refresh Current I DD6CKE ≤ 0.2V543636mA Operating Current I DD7A Four bank interleaving Reads (BL=4)with auto precharge with t RC=t RC (MIN);t CK=t CK(MIN); Address and control inputschange only during Active Read or Writecommands.427541854185mAWhite Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARYI DD1 : OPERATING CURRENT: ONE BANK1. Typical Case: V CC =2.5V, T = 25°C2. Worst Case: V CC = 2.7V, T = 10°C3. Only one bank is accessed with t RC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. l OUT = 0mA4. Timing patterns• DDR200 (100MHz, CL = 2) : t CK = 10ns, CL2, BL =4, t RCD = 2*t CK, t RAg = 5*t CKRead: A0 N R0 N N P0 N A0 N - repeat the sametiming with random address changing; 50% of data changing at every burst• DDR266 (133MHz, CL = 2.5) : t CK = 7.5ns, CL =2.5, BL = 4, t RCD = 3*t CK, t RC = 9*t CK, t RAg = 5*t CKRead: A0 N N R0 N P0 N N N A0 N - repeat thesame timing with random address changing; 50% of data changing at every burst• DDR266 (133MHz, CL = 2) : t CK = 7.5ns, CL = 2, BL = 4, t RCD = 3*t CK, t RC = 9*t CK, t RAg = 5*t CKRead: A0 N N R0 N P0 N N N A0 N - repeat thesame timing with random address changing; 50% of data changing at every burst I DD7A: OPERATING CURRENT: FOUR BANKS1. Typical Case: V CC =2.5V, T = 25°C2. Worst Case: V CC = 2.7V, T = 10°C3. Four banks are being interleaved with t RC (min), Burst Mode, Address and Control inputs on NOP edge are not changing.lout = 0mA4. Timing patterns• DDR200 (100MHz, CL = 2) : t CK = 10ns, CL2,BL = 4, t RRD = 2*t CK, t RCD = 3*t CK, Read withautoprechargeRead: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0- repeat the same timing with random addresschanging; 100% of data changing at every burst • DDR266 (133MHz, CL = 2.5) : t CK = 7.5ns, CL =2.5, BL = 4, t RRD = 3*t CK, t RCD = 3*t CK Read withautoprechargeRead: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1R0 - repeat the same timing with random addresschanging; 100% of data changing at every burst • DDR266 (133MHz, CL = 2): t CK = 7.5ns, CL2 = 2,BL = 4, t RRD = 2*t CK, t RCD = 3*t CKRead: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1R0 - repeat the same timing with random addresschanging; 100% of data changing at every burstDETAILED TEST CONDITIONS FOR DDR SDRAM I DD1 & I DD7A Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOPA (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3White Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARYDDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS ANDRECOMMENDED AC OPERATING CONDITIONS0°C ≤ T A ≤ +70°C; V CC = +2.5V ±0.2V, V CCQ = +2.5V ±0.2VAC Characteristics262/265202Parameter Symbol Min Max Min Max Units Notes Access window of DQs from CK, CK#t AC-0.75+0.75-0.8+0.8nsCK high-level width t CH0.450.550.450.55t CK16CK low-level width t CL0.450.550.450.55t CK16 Clock cycle time CL=2.5t CK (2.5)7.513813ns22CL=2t CK (2)7.5/10131013ns22DQ and DM input hold time relative to DQS t DH0.50.6ns14,17 DQ and DM input setup time relative to DQS t DS0.50.6ns14,17 DQ and DM input pulse width (for each input)t DIPW 1.752ns17 Access window of DQS from CK, CK#t DQSCK-0.75+0.75-0.8+0.8nsDQS input high pulse width t DQSH0.350.35t CKDQS input low pulse width t DQSL0.350.35t CKDQS-DQ skew, DQS to last DQ valid, per group, per access t DQSQ0.50.6ns13,14 Write command to ﬁ rst DQS latching transition t DQSS0.75 1.250.75 1.25t CKDQS falling edge to CK rising - setup time t DSS0.20.2t CKDQS falling edge from CK rising - hold time t DSH0.20.2t CKHalf clock period t HP t CH, t CL t CH, t CL ns18 Data-out high-impedance window from CK, CK#t HZ+0.75+0.8ns8,19 Data-out low-impedance window from CK, CK#t LZ-0.75-0.8ns8,20 Address and control input hold time (fast slew rate)t IHf0.90 1.1ns6 Address and control input set-up time (fast slew rate)t ISf0.90 1.1ns6 Address and control input hold time (slow slew rate)t IHs1 1.1ns6 Address and control input setup time (slow slew rate)t ISs1 1.1ns6 Address and control input pulse width (for each input)t IPW 2.2 2.2nsLOAD MODE REGISTER command cycle time t MRD1516nsDQ-DQS hold, DQS to ﬁ rst DQ to go non-valid, per access t QH t HP-t QHS t HP-t QHS ns13,14 Data hold skew factor t QHS0.751nsACTIVE to PRECHARGE command t RAS40120,00040120,000ns15 ACTIVE to READ with Auto precharge command t RAP1520nsACTIVE to ACTIVE/AUTO REFRESH command period t RC6070nsAUTO REFRESH command period t RFC7580ns21White Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARYDDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS ANDRECOMMENDED AC OPERATING CONDITIONS (continued)0°C ≤ T A ≤ +70°C; V CC = +2.5V ±0.2V, V CCQ = +2.5V ±0.2VAC Characteristics262/265202Parameter Symbol Min Max Min Max Units Notes ACTIVE to READ or WRITE delay t RCD1520nsPRECHARGE command period t RP1520nsDQS read preamble t RPRE0.9 1.10.9 1.1t CK19 DQS read postamble t RPST0.40.60.40.6t CKACTIVE bank a to ACTIVE bank b command t RRD1215nsDQS write preamble t WPRE0.250.25t CKDQS write preamble setup time t WPRES00ns10,11 DQS write postamble t WPST0.40.60.40.6t CK9 Write recovery time t WR1515nsInternal WRITE to READ command delay t WTR11t CKData valid output window NA t QH-t DQSQ t QH-t DQSQ ns13 REFRESH to REFRESH command interval t REFC140.6140.6μs12 Average periodic refresh interval t REFI15.615.6μs12 Terminating voltage delay to V CC t VTD00nsExit SELF REFRESH to non-READ command t XSNR7580nsExit SELF REFRESH to READ command t XSRD200200t CKWhite Electronic DesignsW3EG7234S-D3-JD3-AJD3PRELIMINARY11. It is recommended that DQS be valid (HIGH or LOW) on or beforethe WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on t DQSS .12. The refresh period is 64ms. This equates to an average refreshrate of 15.625µs. However, an AUTO REFRESH command must be asserted at least once every 140.6µs; burst refreshing orposting by the DRAM controller greater than eight refresh cycles is not allowed.13. The valid data window is derived by achieving other speciﬁ cations- t HP (t CK/2), t DQSQ , and t QH (t QH = t HP - t QHS ). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.14. Referenced to each output group: x4 = DQS with DQ0-DQ3.15. READs and WRITEs with auto precharge are not allowed to beissued until t RAS (MIN) can be satisﬁ ed prior to the internal precharge command being issued.16. JEDEC speciﬁ es CK and CK# input slew rate must be > 1V/ns(2V/ns differentially).17. DQ and DM input slew rates must not deviate from DQS by morethan 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to t DS and t DH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain.18. t HP min is the lesser of t CL min and t CH min actually applied to thedevice CK and CK# inputs, collectively during bank active.19. t HZ (MAX) will prevail over the t DQSCK (MAX) + t RPST (MAX)condition. t LZ (MIN) will prevail over t DQSCK (MIN) + PRE (MAX) condition.20. For slew rates greater than 1V/ns the (LZ) transition will start about310ps earlier.21. CKE must be active (High) during the entire time a refreshcommand is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t RFC has been satisﬁ ed.22. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).Notes1.All voltages referenced to V SS2. Tests for AC timing, I DD , and electrical AC and DC characteristicsmay be conducted at normal reference / supply voltage levels, but the related speciﬁ cations and device operations are guaranteed for the full voltage range speciﬁ ed.3.Outputs are measured with equivalent load:Output (V OUT )4.AC timing and I DD tests may use a V IL -to-V IH swing of up to 1.5V in the test environment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter speciﬁ cations are guaranteed for the speciﬁ ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between V IL (AC) and V IH (AC).5.The AC and DC input level speciﬁ cations are deﬁ ned in the SSTL_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level).6.For slew rates less than 1V/ns and greater than or equal to 0.5V/ns. If the slew rate is less than 0.5V/ns, timing must be derated: t IS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. t IH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403 and 335, slew rates must be greater than or equal to 0.5V/ns.7.Inputs are not recognized as valid until V REF stabilizes. Exception: during the period before V REF stabilizes, CKE ≤ 0.3 x V CCQ is recognized as LOW.8. t HZ and t LZ transitions occur in the same access time windows asvalid data transitions. These parameters are not referenced to a speciﬁ c voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ).9.The intent of the “Don’t Care” state after completion of thepostamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above V IHDC (MIN) then it must not transition LOW (below V IHDC ) prior to t DQSH (MIN).10. This is not a device limit. The device will operate with a negativevalue, but system performance could be degraded due to bus turnaround.White Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARYORDERING INFORMATION FOR JD3Part Number Speed CAS Latency t RCD t RP Height*W3EG7234S262JD3133MHz/266Mb/s22230.48 (1.20")W3EG7234S265JD3133MHz/266Mb/s 2.53330.48 (1.20")W3EG7234S202JD3100MHz/200Mb/s22230.48 (1.20")PACKAGE DIMENSIONS FOR JD3White Electronic DesignsW3EG7234S-D3-JD3-AJD3PRELIMINARYORDERING INFORMATION FOR AJD3Part Number Speed CAS Latencyt RCD t RP Height*W3EG7234S262AJD3133MHz/266Mb/s 22228.70 (1.13")W3EG7234S265AJD3133MHz/266Mb/s 2.53328.70 (1.13")W3EG7234S202AJD3100MHz/200Mb/s22228.70 (1.13")PACKAGE DIMENSIONS FOR AJD3* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).White Electronic DesignsW3EG7234S-D3-JD3-AJD3PRELIMINARYORDERING INFORMATION FOR D3Part Number Speed CAS Latencyt RCD t RP Height*W3EG7234S262D3133MHz/266Mb/s 22228.58 (1.125")W3EG7234S265D3133MHz/266Mb/s 2.53328.58 (1.125")W3EG7234S202D3100MHz/200Mb/s22228.58 (1.125")PACKAGE DIMENSIONS FOR D3* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).White Electronic Designs W3EG7234S-D3-JD3-AJD3PRELIMINARY Document Title256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLLRevision HistoryRev #History Release Date StatusRev A Created5-21-02Advanced7-04Preliminary Rev 00.1 Updated CAP and I DD specs0.2 Removed "E D" from Part Marking0.3 Added JD3 and AJD3 Package Height Options0.4 Moved datasheet from Advanced to Preliminary0.5 Added new Document Title PageRev 1 1.1 Added AC specs11-04Preliminary Rev 2 2.1 Updated I DD specs12-04Preliminary。

IM04L21B01-63ZH-C_010

第4条(保证)
1 横河软件产品是以其制造完成时的状态或其出厂时的状态提供给用户的。除存储媒体的破损或损坏外，横河及提供方不承担瑕疵担保责任及其他一切保证责任。如用户发现横河软件产品的存储媒体有破损或损坏时，横河仅在其出厂后12个月内, 对其进行无偿更换(仅限于用户承担将该软件的存储媒体送至横河指定经销点的费用的情况。)。且在任何情况下,横河对横河软件产品在质量及性能上的无瑕疵，恰当性，正确性，可靠性，最新性等不作任何的明示或暗示的保证。横河也不保证横河软件产品与其他软件的一致性及兼容性等。横河根据自己的判断，认为有必要时，可以对横河软件产品实施版本升级(以下称“升级”) ，进行无偿或有偿提供。但是，横河并不承担向用户提供升级服务或升级后的产品的义务。根据不同的产品，横河有提供有偿维修服务的可能。维修服务的范围及条件依照横河的另行规定。但是，如果宣传手册或一般规格书中没有明确记载，横河将最多对最新版本及前一版本进行维护。前一版本为升级后5年以内的横河软件产品。另外，关于已经停售的横河软件产品，仅对停售后5年以内的产品实施维修服务。关于标准品以外的横河软件产品，横河不负实施维修措施的义务。对非横河更改或修正的横河软件产品，横河一概不予应对。
本合同适用于横河的以下产品及附带提供的相关资料(以下称“横河软件产品”)。除横河另行规定的情况外，本合同也适用于横河提供的更新版的横河软件产品及功能增加版的横河软件产品。目标产品：DAQSTANDARD for FX1000 (Model FXA120)
第2条(使用权的许可)
1 2 有关横河软件产品，用户须以支付另行商定的使用费为代价，且只可在与以下授权数相同台数的计算机上安装横河软件产品。横河以许可用户自己使用为目的，授予用户非垄断，不可转让的使用权。授权数：1台除横河书面另行许可或规定的情况外，禁止用户实施以下行为。 (a) 复制横河软件产品(允许复制一份以备用为目的软件，但必须注意妥善保管复制软件。) (b) 将横河软件产品或其使用权销售、转租、分发、转让、抵押给第三方或授予第三方再使用权，以及使横河软件产品通过信息网络传播或发送成为可能。 (c) 通过网络在指定电脑以外的电脑上使用横河软件产品。 (d) 通过转存、逆向汇编、逆向编译、反向工程等手段将横河软件产品转换为程序源代码及其他可读取的格式或复制此类转换；通过更改或译成他种语言将横河软件产品转换为横河所提供的形式以外的任何形式或作此类转换尝试。 (e) 解除或试图解除横河软件产品中使用或添加的保护装置(防复制保护装置)。 (f) 删除横河软件产品中显示的著作权、商标、标志及其他标示。横河软件产品及与其相关的一切技术、计算方式、技术诀窍和程序是属于横河或授权于横河再使用权或转让权的第三方的固有财产及商业机密。横河软件产品的权利归横河或相关第三方所有。横河不作将该财产权利转移或转让给用户的任何承诺。不得将前款中所述的固有财产及商业机密及键代码提供给使用横河软件产品时所必须的用户方高级管理人员、职员或与之相当的人员以外的第三方。并且用户应使这些相关人员严守保密义务。本合同被终止或被解除时，向横河退还横河软件产品及其复制软件的同时，必须彻底删除电脑或存储媒体中的复制软件。销毁保存了横河软件产品及其复制软件的存储媒体时，必须彻底删除存储媒体中保存的内容。横河软件产品可能会包含横河从第三方(含横河的关联公司)获得的许可再使用权或转让权的软件程序(以下称 “第三方程序”)。有关第三方程序提供方(以下称“提供方”)规定了与本合同不同的使用许可条件时，优先适用提供方另行提出的相应条件。第三方程序中，也可能含有用户直接从提供方获得使用权的程序。横河软件产品中可能含有已公开的源代码软件(以下称“OSS”)。有关OSS，优先适用其另行被规定的条件。

W3F41A4708AT1F;W3F45C2218AT1F;W3F45C4718AT1F;W3F41A1018AT1F;W3F41A2208AT1F;中文规格书,Datasheet资料

Preliminary AVX W3F41A2208AT Typical Far-side XTALK Elements 1 - 2
Far Side Side Crosstalk Far Crosstalk
Preliminary AVX W3F41A2208AT Typical Far-side XTALK Elements 1 - 3
CASE SIZE & VOLTAGE RATINGS
Part Number W3F41A2208AT W3F41A4708AT W3F41A1018AT W3F45C2218AT W3F45C4718AT W2F43A2208AT W2F43A4708AT W2F43A1018AT Case Size 0612 0612 Current Rating 300 mA 300 mA DC Resistance < 0.6_ < 0.6_ Voltage Rating 100 V 50 V
0 -10 -20 dB -30
1 2 3 4
-40 -50 0.1
1
10
100
1000
10000
FREQUENCY (MHz)
1 2 3 4
Preliminary AVX W3F41A1018AT Typical Far-side XTALK Elements 1 - 2
FarSide Side Crosstalk Crosstalk Far
EMI Filtering, Broadband Filtering, LCD Filtering
W3F41A4708AT S21CURVES Curves W3F41A4708AT S 21
Preliminary AVX W3F41A4708AT Typical S21

Z8F082APJ020SG2156中文资料(zilog)中文数据手册「EasyDatasheet - 矽搜」

高性能8位微控制器Z8喝采！ XP®F082A 列产品规格PS022825-0908版权所有©2008 Zilog公司®公司防护留所有权利.警告：不要使用生命支持生命支持政策ZiLOG产品不得用作生命中关键部件支持设备或系统未经事先书面批准主席和ZILOG股份有限公司总法律顾问.如本文所用生命支持设备或系统是其中（a）打算通过外科手术移植到体内设备,或（b）支持或维持生命,其未履行时,正确使用符合在标签规定使用说明可以合理预期到导致显著伤害使用者.关键部件是在生命支持设备或系统,其不履行可以合理预期造成生命支持设备或系统故障或影响其安全性或效力任何部件.文档免责声明©2008 Zilog公司防护留所有权利.本出版物中关于设备信息,应用程序,或技术描述意在暗示可能用途,并且可以被替代. ZILOG,INC.不承担赔偿责任或提供精度表示资料,设备或技术描述这份文件.作者：Z I L O G A L S O D O E S N O T A S S U M E L I A B I L I T Y F O R I N T E L L E C T U A L P R O P E RT Y 侵权相关以任何方式使用信息,设备或技术此处描述或以其他方式.在本文档中包含信息已经根据机电工程基本原则得到验证.Z8,Z8喝采！和Z8喝采！ XP注册Zilog公司商标.所有其它产品或服务名称均为其各自所有者财产.PS022825-0908iii 修订记录在修订历史记录每个实例反映更改这个文件从以前版本.更多细节,请参见相应页面和适当链接在下表.Date 九月2008修订Level25描写页码增加引用F042A系列回3, 9, 16, 19, 37,251in表1,适用货物,表5,表7,表13,订购信息部分.更改标题Z8喝采！ XP F082A系列并删除引用F042A系列表1,适用货物,表5,表7,表13,订货信息部分.更新图3中,表14,表58通过表60.All2008年5月24十二月2007 2007年7月232210, 41,and95更新表15and表128.更新44, 221功率消耗在电特点一章.修订版本号更新.All2007年6月21PS022825-0908修订记录iv 目录概述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1特征 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .部分选择指南. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .框图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CPU和外设概述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .eZ8 CPU功能. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10位模拟数字转换器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .低功耗运算放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .内部精密振荡器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .温度感应器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .模拟比较器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .外部晶体振荡器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .低电压检测. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .片上调试. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .通用异步接收器/发送器. . . . . . . . . . . . . . . . . . . . . . .计时器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .通用输入/输出. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .直接驱动LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .闪存控制器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .非易失性数据存储. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .中断控制器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .复位控制器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 4 5 5 5 6 6 6 6 6 6 6 7 7 7 7 7 7 8 8引脚说明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9可用软件包. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9引脚配置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9信号说明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11引脚特性. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13地址空间. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15寄存器文件. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .程序存储器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .数据存储器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .闪光信息区. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 15 17 17寄存器映射. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PS022825-0908目录v 复位,停止模式恢复和低电压检测. . . . . . . . . . . . . . 23复位类型. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .复位源. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .上电复位. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .电压欠压复位. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .看门狗定时器复位. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .外部复位输入. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .外部复位指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .片上调试启动重置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .停止模式恢复. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .停止模式恢复使用看门狗定时器超时. . . . . . . . . . . . . . .停止模式恢复使用GPIO端口引脚过渡. . . . . . . . . . . . . . .停止模式恢复使用外部复位引脚. . . . . . . . . . . . . . . . .低电压检测. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .复位寄存器定义. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 25 25 26 27 27 28 28 28 29 29 30 30 30低功耗模式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33STOP模式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HALT模式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .圆周级功率控制. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .功率控制寄存器定义. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 34 34 34通用输入/输出. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37GPIO端口可用性通过设备. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .建筑. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO备用功能. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .直接驱动LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .共享复位引脚. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .共享调试引脚. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .晶体振荡器替代. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 V容差. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .外部时钟设置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO中断. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO控制寄存器定义. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .端口A-D地址寄存器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .端口A-D控制寄存器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .端口A-D数据方向分寄存器. . . . . . . . . . . . . . . . . . . . . . . . . . .端口A-D备用功能子登记. . . . . . . . . . . . . . . . . . . . . . . .37 38 38 39 39 39 40 40 40 45 45 46 46 47 47PS022825-0908目录。

W3EG72129S265JD3中文资料

White Electronic DesignsPRELIMINARY*W3EG72129S-JD31GB – 2x64Mx72 DDR SDRAM REGISTERED w/PLLDESCRIPTIONThe W3E G72129S is a 2x64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eighteen 64Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate.Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.* T his product is under development, is not qualiﬁ ed or characterized and is subject to change without notice.FEATURESDouble-data-rate architectureClock speeds of 100MHz, 133MHz, 166MHz and200MHz Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8)Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power Supply:• V CC = V CCQ = +2.5V (100, 133 and 166MHz)• V CC = V CCQ = +2.6V (200MHz) JEDEC standard 184 pin DIMM package PCB height:• JD3: 30.48mm (1.20")NOTE: C onsult factory for availability of:• RoHS compliant products • Vendor source control options • Industrial temperature optionOPERATING FREQUENCIESDDR400 @CL=3DDR333 @CL=2.5DDR266 @CL=2DDR266 @CL=2DDR266 @CL=2.5DDR200 @CL=2Clock Speed 200MHz 166MHz 133MHz 133MHz 133MHz 100MHz CL-t RCD -t RP3-3-32.5-3-32-2-22-3-32.5-3-32-2-2White Electronic DesignsW3EG72129S-JD3PRELIMINARYPIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V REF 47DQS893V SS 139V SS 2DQ048A094DQ4140DQM83V SS 49CB295DQ5141A104DQ150V SS 96V CCQ 142CB65DQS051CB397DQM0143V CCQ 6DQ252BA198DQ6144CB77V CC 53DQ3299DQ7145V SS 8DQ354V CCQ 100V SS 146DQ369NC 55DQ33101NC 147DQ3710RESET#56DQS4102NC 148V CC 11V SS 57DQ34103NC 149DQM412DQ856V SS 104V CCQ 150DQ3813DQ959BA0105DQ12151DQ3914DQS160DQ35106DQ13152V SS 15V CCQ 61DQ40107DQM1153DQ4416NC 62V CCQ 108V CC 154RAS#17NC 63WE#109DQ14155DQ4518V SS 64DQ41110DQ15156V CCQ 19DQ1065CAS#111CKE1157CS0#20DQ1166V SS 112V CCQ 158CS1#21CKE067DQS5113NC 159DQM522V CCQ 68DQ42114DQ20160V SS 23DQ1669DQ43115A12161DQ4624DQ1770V CC 116V SS 162DQ4725DQS271NC 117DQ21163NC 26V SS 72DQ48118A11164V CCQ 27A973DQ49119DQM2165DQ5228DQ1874V SS 120V CC 166DQ5329A775NC 121DQ22167NC 30V CCQ 76NC 122A8168V CC 31DQ1977V CCQ 123DQ23169DQS1532A578DQS6124V SS 170DQ5433DQ2479DQ50125A6171DQ5534V SS 80DQ51126DQ28172V CCQ 35DQ2581V SS 127DQ29173NC 36DQS382V CCID 128V CCQ 174DQ6037A483DQ56129DQM3175DQ6138V CC 84DQ57130A3176V SS 39DQ2685V CC 131DQ30177DQS1640DQ2786DQS7132V SS 178DQ6241A287DQ58133DQ31179DQ6342V SS 88DQ59134CB4180V CCQ 43A189V SS 135CB5181SA044CB090NC 136V CCQ 182SA145CB191SDA 137CK0183SA246V CC92SCL138CK0#184V CCSPDPIN CONFIGURATIONA0-A12Address input (Multiplexed)BA0-BA1Bank Select Address DQ0-DQ63Data Input/Output CB0-CB7Check bitsDQS0-DQS8Data Strobe Input/Output CK0Clock Input CK0#Clock InputCKE0, CKE1Clock Enable input CS0#, CS1#Chip Select Input RAS#Row Address Strobe CAS#Column Address Strobe DQM0-DQM8Data-in Mask WE#Write EnableV CC Power Supply (2.5V)V CCQ Power Supply for DQS (2.5V)V SS GroundV REF Power Supply for Reference V CCSPD Serial EEPROM Power Supply (2.3V to 3.6V)SDA Serial data I/O SCL Serial clockSA0-SA2Address in EEPROM V CCID V CC Indentiﬁ cation Flag NCNo Connect RESET#Reset EnablePIN NAMESWhite Electronic Designs W3EG72129S-JD3PRELIMINARY FUNCTIONAL BLOCK DIAGRAMWhite Electronic Designs W3EG72129S-JD3PRELIMINARYABSOLUTE MAXIMUM RATINGSParameter Symbol Value Units Voltage on any pin relative to V SS V IN, V OUT-0.5 to 3.6VVoltage on V CC supply relative to V SS V CC, V CCQ-1.0 to 3.6VStorage Temperature T STG-55 to +150°CPower Dissipation P D18WShort Circuit Current I OS50mANote: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliabilityDC CHARACTERISTICS0°C ≤ T A≤ 70°C, V CC = 2.5V ± 0.2VParameter Symbol Min Max Unit Supply Voltage V CC 2.3 2.7VSupply Voltage V CCQ 2.3 2.7V Reference Voltage V REF 1.15 1.35V Termination Voltage V TT 1.15 1.35VInput High Voltage V IH V REF + 0.15V CCQ + 0.3VInput Low Voltage V IL-0.3V REF -0.15VOutput High Voltage V OH V TT + 0.76—VOutput Low Voltage V OL—V TT-0.76VCAPACITANCET A = 25°C. f = 1MHz, V CC = 2.5VParameter Symbol Max UnitInput Capacitance (A0-A12)C IN1 6.5pFInput Capacitance (RAS#,CAS#,WE#)C IN2 6.5pFInput Capacitance (CKE0)C IN3 6.5pFInput Capacitance (CK0#,CK0)C IN4 5.5pFInput Capacitance (CS0#)C IN5 6.5pFInput Capacitance (DQM0-DQM8)C IN68pFInput Capacitance (BA0-BA1)C IN7 6.5pFData input/output capacitance (DQ0-DQ63)(DQS)C OUT8pFData input/output capacitance (CB0-CB7)C OUT8pFWhite Electronic Designs W3EG72129S-JD3PRELIMINARYI DD SPECIFICATIONS AND TEST CONDITIONSRecommended operating conditions, 0°C ≤ T A≤ 70°C, V CCQ = 2.5V ± 0.2V, V CC = 2.5V ± 0.2VIncludes DDR SDRAM component onlyParameter Symbol Conditions DDR400@CL=3MaxDDR333@CL=2.5MaxDDR266@CL=2MaxDDR266@CL=2.5MaxDDR200@CL=2Max UnitsOperating Current I DD0One device bank; Active - Precharge;t RC=t RC (MIN); t CK=t CK (MIN); DQ,DMand DQS inputs changing once perclock cycle; Address and controlinputs changing once every twocycles.49504140414041404140mAOperating Current I DD1One device bank; Active-Read-Precharge Burst = 2; t RC=t RC (MIN);t CK=t CK (MIN); l OUT = 0mA; Addressand control inputs changing once perclock cycle.54904680468046804680mAPrecharge Power-Down Standby Current I DD2P All device banks idle; Power-downmode; t CK=t CK (MIN); CKE=(low)180180180180180rnAIdle Standby Current I DD2F CS# = High; All device banks idle;t CK=t CK (MIN); CKE = high; Addressand other control inputs changingonce per clock cycle. V IN = V REF forDQ, DQS and DM.19801620162016201620mAActive Power-Down Standby Current I DD3P One device bank active; Power-Down mode; t CK (MIN); CKE=(low)16201260126012601260mAActive Standby Current I DD3N CS# = High; CKE = High; One devicebank; Active-Precharge; t RC=t RAS(MAX); t CK=t CK (MIN); DQ, DM andDQS inputs changing twice per clockcycle; Address and other controlinputs changing once per clock cycle.21601800180018001800mAOperating Current I DD4R Burst = 2; Reads; Continuous burst;One device bank active; Addressand control inputs changing onceper clock cycle; T CK= T CK (MIN); l OUT= 0mA.55804770477047704770mAOperating Current I DD4W Burst = 2; Writes; Continuous burst;One device bank active; Addressand control inputs changing once perclock cycle; t CK=t CK (MIN); DQ,DMand DQS inputs changing once perclock cycle.56704590459045904590rnAAuto Refresh Current I DD5t RC = t RC (MIN)83707020702070207020mA Self Refresh Current I DD6CKE ≤ 0.2V180180180180180mA Operating Current I DD7A Four bank interleaving Reads (BL=4)with auto precharge with t RC=t RC(MIN); t CK=t CK (MIN); Address andcontrol inputs change only duringActive Read or Write commands.102609090900090009000mAWhite Electronic Designs W3EG72129S-JD3PRELIMINARYI DD SPECIFICATIONS AND TEST CONDITIONSRecommended operating conditions, 0°C ≤ T A≤ 70°C, V CCQ = 2.5V ± 0.2V, V CC = 2.5V ± 0.2VIncludes PLL and register powerParameter Symbol Conditions DDR400@CL=3MaxDDR333@CL=2.5MaxDDR266@CL=2MaxDDR266@CL=2.5MaxDDR200@CL=2Max UnitsOperating Current I DD0One device bank; Active - Precharge;t RC=t RC (MIN); t CK=t CK (MIN); DQ,DMand DQS inputs changing once perclock cycle; Address and controlinputs changing once every twocycles.55354725472547254725mAOperating Current I DD1One device bank; Active-Read-Precharge Burst = 2; t RC=t RC (MIN);t CK=t CK (MIN); l OUT = 0mA; Addressand control inputs changing once perclock cycle.60755265526552655265mAPrecharge Power-Down Standby Current I DD2P All device banks idle; Power-downmode; t CK=t CK (MIN); CKE=(low)180180180180180rnAIdle Standby Current I DD2F CS# = High; All device banks idle;t CK=t CK (MIN); CKE = high; Addressand other control inputs changingonce per clock cycle. V IN = V REF forDQ, DQS and DM.22901930193019301930mAActive Power-Down Standby Current I DD3P One device bank active; Power-Down mode; t CK (MIN); CKE=(low)16201260126012601260mAActive Standby Current I DD3N CS# = High; CKE = High; One devicebank; Active-Precharge; t RC=t RAS(MAX); t CK=t CK (MIN); DQ, DM andDQS inputs changing twice per clockcycle; Address and other controlinputs changing once per clock cycle.24702110211021102110mAOperating Current I DD4R Burst = 2; Reads; Continuous burst;One device bank active; Addressand control inputs changing onceper clock cycle; T CK= T CK (MIN); l OUT= 0mA.61655355535553555355mAOperating Current I DD4W Burst = 2; Writes; Continuous burst;One device bank active; Addressand control inputs changing once perclock cycle; t CK=t CK (MIN); DQ,DMand DQS inputs changing once perclock cycle.62555535517551755175rnAAuto Refresh Current I DD5t RC = t RC (MIN)89907640760576057605mA Self Refresh Current I DD6CKE ≤ 0.2V455455455455455mA Operating Current I DD7A Four bank interleaving Reads (BL=4)with auto precharge with t RC=t RC(MIN); t CK=t CK (MIN); Address andcontrol inputs change only duringActive Read or Write commands.108459675958595859585mAWhite Electronic Designs W3EG72129S-JD3PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS ANDRECOMMENDED AC OPERATING CONDITIONSNotes 1-5, 7; notes appear following parameter tables; 0°C ≤ T A ≤ +70°C; V CC = +2.5V ±0.2V, V CCQ = +2.5V ±0.2VAC Characteristics403335262263/265202Parameter Symbol Min Max Min Max Min Max Min Max Min Max Units Notes Access window of DQs from CK, CK#t AC-0.7+0.7-0.7+0.7-0.75+0.75-0.75+0.75-0.75+0.75nsCK high-level width t CH0.450.550.450.550.450.550.450.550.450.55t CK16 CK low-level width t CL0.450.550.450.550.450.550.450.550.450.55t CK16 Clock cycle time CL=3t CK (3)57.56137.5137.5137.513ns22CL=2.5t CK (2.5)57.56137.5137.5137.513ns22CL=2t CK (2)7.5137.5137.5131013ns22 DQ and DM input hold time relative to DQS t DH0.40.450.50.50.5ns14,17 DQ and DM input setup time relative to DQS t DS0.40.450.50.50.5ns14,17 DQ and DM input pulse width (for each input)t DIPW 1.75 1.75 1.75 1.75 1.75ns17 Access window of DQS from CK, CK#t DQSCK-0.6+0.6-0.6+0.6-0.75+0.75-0.75+0.75-0.75+0.75nsDQS input high pulse width t DQSH0.350.350.350.350.35t CKDQS input low pulse width t DQSL0.350.350.350.350.35t CKDQS-DQ skew, DQS to last DQ valid, per group,per accesst DQSQ0.40.450.50.50.5ns13,14 Write command to ﬁ rst DQS latching transition t DQSS0.750.75 1.250.75 1.250.75 1.250.75 1.25t CKDQS falling edge to CK rising - setup time t DSS0.20.20.20.20.2t CKDQS falling edge from CK rising - hold time t DSH0.20.20.20.20.2t CKHalf clock period t HP t CH, t CL t CH, t CL t CH, t CL t CH, t CL t CH, t CL ns18 Data-out high-impedance window from CK, CK#t HZ+0.7+0.7+0.75+0.75+0.75ns8,19 Data-out low-impedance window from CK, CK#t LZ-0.7-0.7-0.75-0.75-0.75ns8,20 Address and control input hold time (fast slew rate)t IHf0.60.750.900.900.90ns6 Address and control input set-up time (fast slew rate)t ISf0.60.750.900.900.90ns6 Address and control input hold time (slow slew rate)t IHs0.60.8111ns6 Address and control input setup time (slow slew rate)t ISs0.60.8111ns6 Address and control input pulse width (for eachinput)t IPW 2.2 2.2 2.2 2.2 2.2nsLOAD MODE REGISTER command cycle time t MRD1012151515nsDQ-DQS hold, DQS to ﬁ rst DQ to go non-valid, per access t QH t HP-t QHSt HP-t QHSt HP-t QHS t HP-t QHS t HP-t QHSns13,14Data hold skew factor t QHS0.50.550.750.750.75ns ACTIVE to PRECHARGE command t RAS40 70,00042 70,00040120,00045120,00045120,000ns15 ACTIVE to READ with Auto precharge command t RAP1518152020ns ACTIVE to ACTIVE/AUTO REFRESH commandperiodt RC5560606565nsAUTO REFRESH command period t RFC7072757575ns21White Electronic Designs W3EG72129S-JD3PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS ANDRECOMMENDED AC OPERATING CONDITIONS (continued)Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ T A ≤ +70°C; V CC = +2.5V ±0.2V, V CCQ = +2.5V ±0.2VAC Characteristics403335262263/265202Parameter Symbol Min Max Min Max Min Max Min Max Min Max Units Notes ACTIVE to READ or WRITE delay t RCD1518152020ns PRECHARGE command period t RP1518152020nsDQS read preamble t RPRE0.9 1.10.9 1.10.9 1.10.9 1.10.9 1.1t CK19 DQS read postamble t RPST0.40.60.40.60.40.60.40.60.40.6t CKACTIVE bank a to ACTIVE bank b command t RRD1012151515nsDQS write preamble t WPRE0.250.250.250.250.25t CKDQS write preamble setup time t WPRES00000ns10,11 DQS write postamble t WPST0.40.60.40.60.40.60.40.60.40.6t CK9 Write recovery time t WR1515151515nsInternal WRITE to READ command delay t WTR21111t CKData valid output window NA t QH-t DQSQ t QH-t DQSQ t QH-t DQSQ t QH-t DQSQ t QH-t DQSQ ns13 REFRESH to REFRESH command interval t REFC70.370.370.370.370.3μs12 Average periodic refresh interval t REFI7.87.87.87.87.8μs12 Terminating voltage delay to V CC t VTD00000nsExit SELF REFRESH to non-READ command t XSNR7075757575nsExit SELF REFRESH to READ command t XSRD200200200200200t CKWhite Electronic DesignsW3EG72129S-JD3PRELIMINARY12. The refresh period is 64ms. This equates to an average refreshrate of 15.625µs (256Mb component) or 7.8125µs (512 Mb component). However, an AUTO REFRESH command must be asserted at least once every 140.6µs (256 Mb component) or 70.3µs (512Mb component); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.13. The valid data window is derived by achieving other speciﬁ cations- t HP (t CK/2), t DQSQ , and t QH (t QH = t HP - t QHS ). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.14. Referenced to each output group: x4 = DQS with DQ0-DQ4.15. READs and WRITEs with auto precharge are not allowed to beissued until t RAS (MIN) can be satisﬁ ed prior to the internal precharge command being issued.16. JEDEC speciﬁ es CK and CK# input slew rate must be > 1V/ns(2V/ns differentially).17. DQ and DM input slew rates must not deviate from DQS by morethan 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to t DS and t DH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain.18. t HP min is the lesser of t CL min and t CH min actually applied to thedevice CK and CK# inputs, collectively during bank active.19. This maximum value is derived from the referenced test load. Inpractice, the values obtained in a typical terminated design may reﬂ ect up to 310ps less for t HZ (MAX) and last DVW. t HZ (MAX) will prevail over the t DQSCK (MAX) + t RPST (MAX) condition. t LZ (MIN) will prevail over t DQSCK (MIN) + PRE (MAX) condition.20. For slew rates greater than 1V/ns the (LZ) transition will start about310ps earlier.21. CKE must be active (High) during the entire time a refreshcommand is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later.22. Whenever the operating frequency is altered, not including jitter,the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).Notes1.All voltages referenced to V SS2. Tests for AC timing, I DD , and electrical AC and DC characteristicsmay be conducted at normal reference / supply voltage levels, but the related speciﬁ cations and device operations are guaranteed for the full voltage range speciﬁ ed.3.Outputs are measured with equivalent load:Output (V OUT )Reference Point Ω4.AC timing and I DD tests may use a V IL -to-V IH swing of up to 1.5V in the test environment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter speciﬁ cations are guaranteed for the speciﬁ ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between V IL (AC) and V IH (AC).5.The AC and DC input level speciﬁ cations are deﬁ ned in the SSTL_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level).6.Command/Address input slew rate = 0.5V/ns. For -75 with slew rates 1V/ns and faster, t IS and t IH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: t IS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. t IH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.7.Inputs are not recognized as valid until V REF stabilizes. Exception: during the period before V REF stabilizes, CKE ≤ 0.3 x V CCQ is recognized as LOW.8. t HZ and t LZ transitions occur in the same access time windows asvalid data transitions. These parameters are not referenced to a speciﬁ c voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ).9.The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.10. This is not a device limit. The device will operate with a negativevalue, but system performance could be degraded due to bus turnaround.11. It is recommended that DQS be valid (HIGH or LOW) on or beforethe WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on t DQSS .White Electronic Designs W3EG72129S-JD3PRELIMINARYI DD1 : OPERATING CURRENT : ONE BANK1. Typical Case : V CC=2.5V, T=25°C2. Worst Case : V CC=2.7V, T=10°C3. Only one bank is accessed with t RC (min), BurstMode, Address and Control inputs on NOP edgeare changing once per clock cycle. I OUT = 0mA4. Timing Patterns :• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, t RCD=2*t CK, t RAS=5*t CKRead : A0 N R0 N N P0 N A0 N - repeat thesame timing with random address changing;50% of data changing at every burst• DDR266 (133MHz, CL=2.5) : t CK=7.5ns,CL=2.5, BL=4, t RCD=3*t CK, t RC=9*t CK, t RAS=5*t CKRead : A0 N N R0 N P0 N N N A0 N - repeatthe same timing with random addresschanging; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : t CK=7.5ns, CL=2, BL=4, t RCD=3*t CK, t RC=9*t CK, t RAS=5*t CKRead : A0 N N R0 N P0 N N N A0 N - repeatthe same timing with random addresschanging; 50% of data changing at every burst • DDR333 (166MHz, CL=2.5) : t CK=6ns, BL=4, t RCD=10*t CK, t RAS=7*t CKRead : A0 N N R0 N P0 N N N A0 N - repeatthe same timing with random addresschanging; 50% of data changing at every burst • DDR400 (200MHz, CL=3) : t CK=5ns, BL=4, t RCD=15*t CK, t RAS=7*t CKRead : A0 N N R0 N P0 N N N A0 N - repeatthe same timing with random addresschanging; 50% of data changing at every burst I DD7A : OPERATING CURRENT : FOUR BANKS1. Typical Case : V CC=2.5V, T=25°C2. Worst Case : V CC=2.7V, T=10°C3. Four banks are being interleaved with t RC (min),Burst Mode, Address and Control inputs on NOPedge are not changing. Iout=0mA4. Timing Patterns :• DDR200 (100 MHz, CL=2) : t CK=10ns, CL2, BL=4, t RRD=2*t CK, t RCD=3*t CK, Read withAutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0- repeat the same timing with random addresschanging; 100% of data changing at everyburst• DDR266 (133MHz, CL=2.5) : t CK=7.5ns,CL=2.5, BL=4, t RRD=3*t CK, t RCD=3*t CKRead with AutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 NA1 R0 - repeat the same timing with randomaddress changing; 100% of data changing atevery burst• DDR266 (133MHz, CL=2) : t CK=7.5ns, CL2=2, BL=4, t RRD=2*t CK, t RCD=2*t CKRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 NA1 R0 - repeat the same timing with randomaddress changing; 100% of data changing atevery burst• DDR333 (166MHz, CL=2.5) : t CK=6ns,BL=4, t RRD=3*t CK, t RCD=3*t CK, Read withAutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 NA1 R0 - repeat the same timing with randomaddress changing; 100% of data changing atevery burst• DDR400 (200MHz, CL=3) : t CK=5ns,BL=4, t RRD=10*t CK, t RCD=15*t CK, Read withAutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 NA1 R0 - repeat the same timing with randomaddress changing; 100% of data changing atevery burstDETAILED TEST CONDITIONS FOR DDR SDRAM I DD1 & I DD7ALegend:A = Activate, R = Read, W = Write, P = Precharge, N = NOPA (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3White Electronic Designs W3EG72129S-JD3PRELIMINARYORDERING INFORMATION FOR JD3Part Number Speed CAS Latency t RCD t RP Height*W3EG72129S403JD3200MHz/266Mb/s33330.48 (1.20")W3EG72129S335JD3166MHz/333Mb/s 2.53330.48 (1.20")W3EG72129S262JD3133MHz/266Mb/s22230.48 (1.20")W3EG72129S263JD3133MHz/266Mb/s23330.48 (1.20")W3EG72129S265JD3133MHz/266Mb/s 2.53330.48 (1.20")W3EG72129S202JD3100MHz/200Mb/s22230.48 (1.20") NOTES:• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)• V endor speciﬁ c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualiﬁ ed sourcing options. (M = Micron, S = Samsung & consult factory for others)• Consult factory for availability of industrial temperature (-40°C to 85°C) optionPACKAGE DIMENSIONS FOR JD3* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)White Electronic Designs W3EG72129S-JD3PRELIMINARYDocument Title1GB - 128Mx72 DDR SDRAM REGISTERED w/PLLRevision HistoryRev #History Release Date StatusRev 0Created5-22-02Advanced Rev 1 1.1 Removed "ED" for Part Marking5-04Preliminary10-18-04Preliminary Rev 2 2.1 Added 400MHz Spec2.2 Added AJD3 package option10-05Preliminary Rev 3 3.1 R emoved AJD3 package options.Can not be built with this laminate.。

电磁阀线圈部分参数

电磁线圈 (2) 的电流减小时，控制阀心 (3) 会在复位弹簧 (4) 的作用下返回到中间位置。
提供了手动应急操作 (6)，以便在电磁线圈未通电时也可操作控制阀心 (3)。
型式 .WE 4 ...2X/O…
此型号是具有两个切换位置和两个电磁线圈但不带制动器和弹簧的方向阀。未定义失电情况下的切换位置。
020318通径42x系列最大工作压力210bar最大流量30lminhad6867目录内容特点订货细节优选型号符号插入式连接器功能剖面技术数据特性曲线性能极限单元尺寸页码1223345667特点直动式电磁方向滑阀具有定位销孔且符合iso4401的油口安装面有关底板信息请参阅产品样本re45050另单湿式插脚直流电磁线圈通过整流器可输入交流电压各连接均采用电气连接带保护的手动应急操作型式4we4d2xeg24n9k44we4d2xofeg24n9k44we4e2xeg24n9k44we4j2xeg24n9k44we4y2xeg24n9k4材料编号r900770141r900770145r900770147r900770148r900770149符号uvwmpqrt1示例
37
1 铭牌 2.1 电磁线圈“a”（插入式连接器颜色，灰色） 2.2 电磁线圈“b”（插入式连接器颜色，黑色） 3 手动应急操作“N9” 4 插入式连接器，不带电路，
符合 DIN EN 1753101-803 1) 5 插入式连接器，带电路，
符合 DIN EN 1753101-803 1) 6 用于油口 A，B，P，T 的相同密封圈
弹簧复位
无弹簧复位不带制动器弹簧复位
标准阀
24 V DC
带保护的手动应急操作
= 2X
= 无代码
=O = OF
=E = G24

伦茨(Lenze)82008210系列变频器中文说明书

782031C N Lenze伦茨橾作手册Global Drive8200/8210系列变频器功率范围0.37…11KW怎样用这些操作指令…对特定的功能，可先参考表中的内容，然后根据索引可看到详细的操作说明为了查阅方便操作指南中用了不同的符号，并在重要的条款中做了加黑处理这个符号给出方便操作信息注意!尽可能避免损坏设备注意!操作时小心人身安全Lenze 1本技术说明用于带有以下名牌的设备8201 E.lx.lx 8203 E.lx.lx 8211 E.Ox.lx 8213 E.Ox.lx 8202 E.lx.lx 8204 E.lx.lx 82l2 E.Ox.lx 82l4 E.0x.lx82l5 E.Ox.lx 82l7 E.Ox.lx 82ll E.lx.2x 82l3 E.lx.2x 82l5 E.lx.2x 82l7 E.lx.2x 82O2E.lx.lx.YOO282l6 E.Ox.lx82l8 E.Ox.lx82l2 E.lx.2x82l4 E.lx.2x82l6 E.lx.2x82l8 E.lx.2x82O2 E.2x.lx.YOO2 装配深度减少的改型变频器类型IP2O封装硬件版本号和索引号软件版本和索引号改型编辑：O3.ll.l994 打印日期 O5.l2.l994 改变软件版本号2x 13.02.199507.08.19952 Lenze目录设计和安装8200/8210系列的特点 (6)1.变频器的数据 (7)1.1通用数据 (7)1.2与型号有关的数据 (8)1.3制造商声明 (9)1.3.1直接应用 (9)2.尺寸和安装 (10)2.1安装 (10)2.2外型尺寸 (11)3.01 (14)3.18200系列变频器的主电路连接 (14)3.28210系列的主电路连接 (15)3.3控制接线 (16)3.4控制输入和输出 (17)3.5并联直流母线运行 (18)3.5.1多台变频器的并联 (18)3.5.2直流电压供电 (18)3.6射频干扰的抑制和屏蔽 (19)4.23 (21)4.1操作面板8201BB (21)4.2操作面板的引出端子的8272BB (22)4.3设定电位器 (23)4.4制动斩波器 (23)4.5主电抗器 (25)4.6熔断器 (26)4.7抑制射频干扰滤波器 (27)4.8电机滤波器 (28)4.9电机电压滤波器 (29)4.10附件 (30)编程:1.开关初始化 (31)2 (32)3.显示 (34)3.1运行状态显示 (34)3.2操作面板8201BB (34)3.3显示值 (36)3.4启动显示 (36)4.基本控制操作 (37)4.1操作编程结构 (37)Lenze 34.2参数代码的设定和改变 (37)4.3操作模式 (40)4.4参数集 (40)5.8200变频器的编程 (41)5.1基本设定 (41)5.1.1最小输出频率f mn (41)5.1.2最大频率设定f_ (41)5.1.3加、减速时间设定 (42)5.1.4V/f 额定频率 (42)5.1.5V/f特性和提升电压设定V_ (43)5.2给定值选择 (44)5.2.1模拟量给定值选择 (44)5.2.2通过LCD操作面板给定 (44)5.2.3寸动频率JOG (45)5.2.4模拟电机电位器 (45)5.3UVWXYZ (46)5.3.1控制器使能(RFR) (46)5.3.2改变旋转方向(CW/CCW) (46)5.3.3快速停止(QSP) (47)5.3.4DC 制动(DC INJ) (47)5.3.5改变参数集(PAR) (47)5.3.6跳闸设定(TRIP) (48)5.3.7端子配置一览 (48)5.3.8继电器输出 (49)5.3.9模拟量输出 (50)5.4扩展设置 (51)5.4.1起动选择/瞬间重起动电路 (51)5.4.2最大电流限制 (52)5.4.3I2.t 监视 (53)5.4.4滑差补偿 (53)5.4.5跳闸复位 (54)5.4.6运行时间表 (54)5.4.7软件版本和变频器型号 (54)5.58200系列代码表 (59)6.8210系列变频器编程 (59)6.1基本设置 (59)6.1.1最小输出频率f；^ (59)6.1.2最大输出频率fj/4 (60)6.1.3加速和减速时间 (61)6.1.4V/f额定频率t (62)6.1.5控制方式 (62)6.1.6提升电压V/i n设定 (62)6.2设定值选择 (62)6.2.1模拟量给定值选择 (63)6.2.2通过操作面板给定 (64)4Lenze6.2.3寸动频率(JOG) (64)6.2.4电机电位器 (64)6.3控制端子功能 (65)6.3.1控制器使能(RFR) (65)6.3.2改变旋转方向(CW/CCW) (66)6.3.3快停(QSP) (66)6.3.4直流制动(DC INJ) (66)6.3.5参数集(TRIP)改变 (67)6.3.6跳闸设定 (68)6.3.7端子配置一览 (69)6.3.8继电器输出 (70)6.3.9模拟量输出 (70)6.4扩展设定 (71)6.4.1起动选择/瞬间重起动 (72)6.4.)最大电流限制 (72)6.4.3电机数据输人 (73)6.4.4I2.t 监控 (73)6.4.5滑差补偿 (74)6.4.6斩波频率 (74)6.4.7跳闸复位 (74)6.4.8运行时间表 (74)6.4.9软件版本和变频器型号 (75)6.4.10运行速度显示 (75)6.58210系列代码表 (76)维护1.监视报警 (81)2.故障报警 (81)2.1主电路连接中错误指示 (81)2.2操作中的故障报警 (81)3.故障确定 (83)3.1电机不转 (83)3.2LED绿灯闪烁 (83)3.3LED红灯闪烁(每0.4秒） (83)3.4LED红灯闪烁(每秒） (83)3.5LED 不亮 (83)3.6电机运行不平稳 (83)3.7电机的电流过大 (84)Lenze 58200/8210系列的特点230V电压等级的8200系列包括4种型号的变频器。

DIT双色测温仪数据手册说明书

输出模拟输出数字输出 0-20mA, 4-20mA, 0-5V RS485工作电源±0% 500mA24VDC 2电气参数10 - 95%, 无结露可用现场有烟雾、颗粒物、蒸汽、视场部分遮挡，以及高速移动目标物体的温度测量温度测量范围6003000-℃响应速度小于5ms30DIT DIKAI V26单色，双色测量模式供选择同时模拟和数字输出可编程继电器输出支持多达台系列测温仪的多点网络 .数据采集软件及现场校准软件DIT DIT DIT 1234双色测温仪：采用双色测温方法，即通过目标物体辐射的两个红外波段的能量比值来确定被测物体的温度。

因测量结果取决于两个波段辐射功率之比，所以，辐射能量的部分损失对测量结果没有影响。

可克服传输介质有灰尘、烟雾、水汽，视场局部遮挡和测量距离变化造成的辐射能量衰减而引起的测量误差，特别适用于相对恶劣的测温环境。

金属热加工过程中，金属表面不可避免会快速氧化形成氧化层，氧化层会随温度变化脱落或者皴裂（例如轧钢生产线），皴裂氧化皮和金属本体形成间隙，使得氧化层的温度低于金属本体温度。

测温仪可以很好的克服因此引起的测量误差，使得生产工艺数据可靠且离散性小，便于工艺分析。

测温对于真空或保护气体加热系统也具有较强的优势，可以克服玻璃窗口材料引起的测量误差，让测量值更接近真实值。

测温仪具有目视瞄准系统，非常方便用户安装及实时查看测温仪是否对准目标。

对于密封环境的测量系统，目视瞄准还可以作为炉内工况的观察窗口。

测温仪具有丰富的功能，实时高亮温度测量值显示，用户可选测量方式，测量模式，测温速度，输出规格设置。

完全满足客户各种现场使用需求。

人机交互简单，方便。

单色温度计在使用过程中，会遇到以下几种原因引起的测量误差：、材料氧化表面状态发生改变，或者氧化物和原始材料开裂而引起较大的测量误差。

、材料本身发射率较低而引起的测量误差。

、测量环境恶劣（粉尘，烟雾，水蒸气等）而引起的测量误差。

W78E58中文

W78E58B规格书8位微控制器目录:1.概述 (3)2.特性 (3)3.管脚配置 (4)4.管脚描述 (5)5.方块图 (7)6.功能描述 (8)6.1 RAM (8)6.2 定时器0，1，2 (8)6.3 时钟 (9)6.4 晶体振荡器 (9)6.5 外部时钟 (9)6.6 电源管理 (9)6.7 减少EMI辐射 (9)6.8 复位 (9)6.9 I/O口4 (11)6.10 INT2/INT3 (12)6.11 P4口基地址寄存器 (14)6.12 在线编程（ISP）模式 (15)6.13 在线编程控制寄存器（CHPCON） (17)6.14 F04KBOOT 模式（从LDROM启动） (18)7.保密位 (22)7.1 锁止位 (22)禁止 (22)7.2 MOVC7.3 加密 (22)8.电气特性 (23)8.1 绝对最大额定值 (23)8.2 DC特性 (23)出版日期: December 22, 20048.3 AC特性 (25)8.3.1时钟输入波形 (25)8.3.2程序读取周期 (26)8.3.3数据读取周期 (26)8.3.4数据写周期 (27)8.3.5端口访问周期 (27)9.时序波形图 (28)9.1 程序读取周期 (28)9.2 数据读周期 (28)9.3 数据写周期 (29)9.4 端口访问周期 (29)10.典型应用电路 (30)10.1 扩展的外部程序存储器和石英晶体 (30)10.2 扩展的外部程序存储器和振荡器 (31)11.封装尺寸 (32)11.1 DIP40 (32)11.2 44 管脚PLCC (33)11.3 44 管脚PQFP (34)12.应用指南 (35)12.1 ISP 软件编程示例： (35)13.文件版本描述 (42)1. 概述W78E58B是具有带ISP功能的Flash EPROM的低功耗8位微控制器；ISP功能的Flash EPROM可用于固件升级。

FAN8024BD中文资料

I/O
Pin Function Description
I
CH1 input
- Connection with capacitor
- for CH1
I
OP-AMP CH2 input(+)
I
OP-AMP CH2 input(-)
O OP-AMP CH2 output
I
Feedback for CH1
- Signal Vcc
O Drive3 Output (-)
- Power Ground 2
- Feedback for CH4
- Power Supply 2
- Vcc ground
I
CH3 input
- Connection with capacitor
- for CH4
I
CH4 input
I
Bias voltage input
3. Separation Of Power Supply
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Name IN1
CAP1.1 CAP1.2
IN2.1 IN2.2 OUT2 FB1 VCC PVCC1 PGND1 DO2− DO2+ DO1− DO1+ DO4+ DO4− DO3+ DO3− PGND2 FB4 PVCC2 VCCGND IN3 CAP4.2 CAP4.1 IN4 REF STBY
TSTG
NOTE: 1. When mounted on a 50mm × 50mm × 1mm PCB (Phenolic resin material). 2. Power dissipation is reduced by -13.6mW/°C above Ta = 25°C 3. Should not exeed Pd(Power dissipation) and SOA(Safe operating area).

常用三极管参数大全

玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理玉林万顺达电脑芯片级维修资料 2010-07-20整理。

E103-W08 产品规格书说明书

E103-W08产品规格书2.4G串口WIFI BLE配网低功耗目录第一章概述 (1)1.1简介 (1)1.2功能特点 (1)1.3应用场景 (2)第二章规格参数 (2)2.1极限参数 (2)2.2工作参数 (2)第三章机械尺寸与引脚定义 (3)3.1E103-W08A引脚尺寸图 (3)3.2E103-W08A引脚尺寸图 (4)第四章推荐连线图 (5)第五章功能说明 (5)5.1工作模式 (5)5.1.1TCP通信 (6)5.1.2MQTT通信 (7)5.1.3HTTP通信 (7)5.2TCP心跳包 (7)5.3自动连接 (7)5.4手动连接 (8)5.5手动断开 (8)5.6BLE配网 (8)5.7状态指示 (8)5.8低功耗 (8)5.9注意事项 (9)第六章默认参数 (9)第七章AT指令及参数 (10)7.1错误码表 (11)7.2基本AT指令 (11)7.2.1AT测试指令 (11)7.2.2重启模块 (11)7.2.3恢复出厂参数 (12)7.2.4查询版本信息 (12)7.2.5查询、设置串口参数 (12)7.2.6查询、设置工作模式 (12)7.2.7查询、设置电源模式 (13)7.3WIFI相关AT指令 (13)7.3.1扫描可用AP (13)7.3.2连接到指定AP (13)7.3.3与AP断开连接 (14)7.3.4查询、设置连接模式 (14)7.3.5查询MAC地址 (14)7.3.6查询、设置主机名 (14)7.4TCP相关AT指令 (15)7.4.1查询网络连接状态 (15)7.4.2建立TCP传输 (15)7.4.3关闭TCP传输 (15)7.4.4查询本地IP (15)7.4.5查询、设置多连接 (15)7.4.6查询、设置TCP模式 (15)7.4.7查询、设置是否打印对端IP、端口 (16)7.4.8查询、设置远程目标参数 (16)7.4.9查询、设置心跳数据 (16)7.5MQTT相关AT指令 (17)7.5.1查询、设置MQTT远程目标 (17)7.5.2查询、设置MQTT发布主题 (17)7.5.3查询、设置MQTT订阅主题 (17)7.5.4查询、设置MQTT登录参数 (17)7.5.5查询、设置MQTT连接参数 (18)7.6HTTP相关参数 (18)7.6.1查询、设置远程目标 (18)7.6.2查询、设置URL (18)7.6.3查询、设置数据类型 (18)7.7BLE相关参数 (19)7.7.1查询、设置BLE广播名 (19)7.7.2查询、设置BLE广播间隙 (19)第八章使用教程 (20)8.1TCP通信 (20)8.1.1透传 (20)8.1.2协议传输 (21)8.2HTTP通信 (23)8.3MQTT通信 (23)8.4BLE配网 (24)第九章焊接作业指导 (27)9.1回流焊温度 (27)9.2回流焊曲线图 (27)修订历史 (28)关于我们 (28)免责申明和版权公告本文中的信息，包括供参考的URL地址，如有变更，恕不另行通知。

72042中文资料

SERIES CHCHIME STROBESFeatures• Field Selectable single Stroke or Vibrating operation• Volume and Tone Control• 24 VDC• Low Current Draw with Zero Inrush• Terminals Accept #18 to #12 AWG Wires• Polarized Inputs• Flush or Surface Mount• Synchronized/Non Synchronized Strobes• Field Selectable Candela Strobe (Multi-candelamodels)• Fixed Candela ModelsDescriptionSeries CH Electronic Chimes/Strobes combine a uniquesolid state chime appliance with a range of strobe models.These unique solid-state chime appliances provide fieldselectable single-stroke or vibrating operation with soundlevels adjustable up to 83 dB and tone adjustable from800 to 1200 Hz.They are available in two attractive package styles forflush mounting to standard electrical boxes or convenientsurface mounting.The CH70 model incorporates a patent pending chimemounting plate for faster, easier, level installation with anew aesthetic two (2) screw grill cover for a more pleasingappearance. Additionally, the Series CH70 Chime Strobemodels incorporate the Lower Current, Zero Inrush SeriesRSS Non-Sync/ Sync Strobes (synchronization of thestrobe flash is achieved when used with Gamewell’s SMor DSM sync modules or FF8 Power Supply with PatentedSync Protocol).Series CH Chime Strobes are designed for maximumperformance, reliability and cost-effectiveness whilemeeting or exceeding the latest visible signalingrequirements of NFPA 72 (National Fire Alarm Code),ANSI 117.1 (American National Standard of Accessibleand Usable Buildings and Facilities) and UL Standard1971 (Standard for Signaling Devices for the HearingImpaired). CH Chime Strobes, when properly specifiedand installed in accordance with NFPA/ANSI Standards,can provide the Equivalent Facilitation allowed under ADAAccessibility Guidelines (ADAAG General Section 2.2) bymeeting or exceeding the illumination which results fromthe ADA specified strobe intensity of 75 candela at 50feet. This is an illumination of 0.030 lumens per squarefoot.They incorporate a Xenon flashtube with solid statecircuitry enclosed in a rugged Lexan® lens to providemaximum reliability for effective visual signaling.Engineer SpecificationsThe chime appliances shall be CH Chimes StrobeAppliance. The chime strobes shall be listed under ULStandard 1971 for Signaling Devices for the HearingImpaired. In addition, the strobes shall be certified to meetthe requirements of FCC Part 15, Class B and shallincorporate low temperature compensation to ensure thelowest possible current consumption. All chimes shalluse solid state components and shall provide fieldselectable single stroke or vibrating operation with volumecontrol and tone control.ApprovalsUL 1971, 464 ListedCalifornia State Fire Marshal (CSFM)City of Chicago (BFP) ApprovedMeets ADA accessbility guidelines andOSHA 29 Part 1910.165.CS-2245 Rev. 1102-6Page 1Engineer SpecificationsAll models shall have a sound output of 83 dBA at 10 feet and a listed frequency response rate of 800 to 1200 Hz. All inputs shall employ terminals that accept #12 to #18 AWG wire sizes. The strobe portion of the appliance shall produce a flash rate of one (1) flash per second over the Regulated Input Voltage Range of 16 to 33 VDC for 24 VDC models and shall incorporate a Xenon flashtube enclosed in a rugged Lexan ® lens. The strobe shall be of low current design and shall have Zero Inrush. The strobe intensity shall have a minimum of four (4) field selectable settings and shall be rated per UL 1971 for: 15, 30, 75 or 110 candela (wall mount versions). The switch for selecting the candela setting shall be located on the rear of the appliance in order to prevent tampering from unauthorized persons. When synchronization is required, the strobe portion of the appliance shall be compatible with the SM, DSM sync modules or FF8 Power Supply. The strobes shall not drift out of synchronization at any time during operation. If the sync module or Power Supply fails to operate, (i.e., contacts remain closed), the strobe shall revert to a non-synchronized flash rate. The chime and the chime strobe appliances shall be designed for indoor surface or flush mounting. The Chime Strobe shall be Gamewell MOdel 72041 or 72042.SpecificationsPart No. Model Strobe Anechoic dBA @10’RatedCandela Peak dBA @10’Reverberant CurrentMin Max72041 CH70-24MCW-FR15/30/75/1108352 58*.020 Chime Only 72042 CH70-24MCW-FW10/30/75/1108352 58*.020 Chime Only 71761 CH70-241575W-FR 15/75835258 .085* Multi-candela Average Strobe Current @ 24VDC15CD30CD75CD110CD.047.081.128.166Notes:• Strobes are designed to flash at 1 flash per second minimum from 20-31VDC. Note that NFPA-72(1999) specifies a flash rate of 1 to 2 flashes per second and ADA Guidelines specify a flash rate of 1to 3 flashes per second.• All candela ratings represent minimum effective strobe intensity based on UL 1971.• Series CH Strobe products are UL 1971 for indoor use with a temperature range of 32o F to 120o F(0o C to 49o C) and maximum humidity of 85%.Ordering InformationPart Number DescriptionCH Series provide Synchronized Strobe with 71548 or 71549 Sync Modules72041Selectable Candela Chime Strobe, Wall Mount, 24VDC, Red (CH70-24MCW-FR)72042Selectable Candela Chime Strobe, Wall Mount, 24VDC, White (CH70-24MCW-FW) 7176115/75CD Chime Strobe, .065 Amp, Wall Mount, 24VDC, Red (CH70-241575W-FR) Mounting Accessories for CH Series Chime StrobesBO* 4” Sq. Deep w/Extension Ring70418Backbox, Surface Mount, 5-1/2" x 5-9/16" x 3-9/16", Red (SBB-R)71643Backbox, Surface Mount, 10-15/16" x 6-7/64" x 1-11/16", Red (SBL2-R)68292Plate, Semi-Flush, 6" Square x 5/16"D, Red (SFP-R)71317Molded Extender, 5-1/4" Square x 25/32"D, Red (ISP-R)71318Retrofit Plate, 8" x 5-7/8" x 13/32", Red (RP-R)BO* Items purchased by others. For more details, refer to CS-2248.CS-2245 Rev. 1102-6Page 2。

W742E813资料

Preliminary W742E81A/W742C81A4-BIT MICROCONTROLLERPublication Release Date: April 2000- 1 - Revision A11. GENERAL DESCRIPTIONThe W742E81A/W742C81A is a high-performance 4-bit microcontroller (µC) that provides an LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers (for two oscillators) in dual-clock operation, a 40 × 4 LCD driver, six 4-bit I/O ports (including 1 output port for LED driving), and one channel DTMF generator. There are also five interrupt sources and 16-levels subroutine nesting for interrupt applications. The W742E81A/W742C81A operates on very low current and has two power reduction modes, that is the dual-clock slow operation and STOP mode, which help to minimize power dissipation.2. FEATURES• Operating voltage: 2.4V −3.8V• Dual-clock operation or single-clock operation (By option) • Main-oscillator− Connect to 3.58 MHz crystal or 400 KHz that can be selected by option code − Crystal or RC oscillator can be selected by code option (W742E81A) − Connect to 2 MHz typical RC oscillator (W742C81A)• Sub-oscillator− Connect to 32768 Hz crystal only• Memory− 16384 x 16 bits program flash EEPROM (including 64K x 4 bit look-up table) − 2048 x 4 bits data RAM (including 16 nibbles x 16 pages working registers) − 40 x 4 LCD data RAM• 24 input/output pins− Port for input only: 1 ports/4 pins(RC)− Input/output ports: 3 ports/12 pins(RA, RB & RD)− High sink current output port for LED driving: 1 port /4 pins(RE) − Port for output only: 1 port/ 4 pins(RF)• Power-down mode− Hold function: no operation (main-oscillator and sub-oscillator still operate) − Stop function: no operation (main-oscillator and sub-oscillator are stopped)− Dual-clock slow operation mode: system is operated by the sub-oscillator (F OSC =Fs and Fm is stopped)• Five types of interrupts− Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1) − One external interrupts (RC Port)Preliminary W742E81A/W742C81A- 2 -• LCD driver output− 40 segments x 4 commons − 1/4 duty 1/3 bias driving mode− Clock source should be the sub-oscillator clock in the dual-clock operation mode• MFP output pin− Output is software selectable as modulating or nonmodulating frequency − Works as frequency output specified by Timer 1• DTMF output pin− Output is one channel Dual Tone Multi-Frequency signal for dialling• Two built-in 14-bit frequency dividers− Divider0: the clock source is the output of the main-oscillator− Divider1: the clock source is the output of the sub-oscillator (dual-clock mode) or the Fosc/128 (single-clock mode)• Two built-in 8-bit programmable countdown timers− Timer 0: one of two internal clock frequencies (F OSC /4 or F OSC /1024) can be selected− Timer 1: with auto-reload function and one of three internal clock frequencies (F OSC, F OSC /64 or Fs) can be selected by MR1 register; and the specified frequency can be delivered to MFP pin• Built-in 18/15-bit watchdog timer selectable for system reset; enable the watch dog timer or not isdetermined by code option• Powerful instruction set: 142 instructions • 16-levels subroutine (include interrupt) nestingPreliminary W742E81A/W742C81APublication Release Date: April 2000- 3 - Revision A13. PIN CONFIGURATIONFor W742E81APreliminary W742E81A/W742C81A- 4 -For W742C810Preliminary W742E81A/W742C81APublication Release Date: April 2000- 5 - Revision A14. PIN DESCRIPTIONPreliminary W742E81A/W742C81A- 6 -Pin Description, continuedSYMBOL I/O FUNCTIONV PP I Voltage control pin for the flash EEPROM programming, erasing and verifying. This pin has the built-in pull-low resistor.MODEIThis pin can be used as mode selection control; data read/write clock; program/erase control or address counter control in the flash EEPROM erasing, programming or verifying mode. This pin has the built-in pull-low resistor.DATA I/O Data I/O pin with the built-in pull-low resistor.5. BLOCK DIAGRAMPreliminary W742E81A/W742C81APublication Release Date: April 2000- 7 - Revision A16. FUNCTIONAL DESCRIPTION 6.1 Program Counter (PC)Organized as an 14-bit binary counter (PC0 to PC13), the program counter generates the addresses of the 16384 × 16 on-chip ROM containing the program instruction words. Before the jump or subroutine call instructions are to be executed, the destination ROM page must be determined firstly. The confirmation of the ROM page can be done by executing the MOV ROMPR, #I or MOV ROMPR, R instruction. When the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. The format used is shown below. Table 1 Vector address and interrupt priorityITEMADDRESS INTERRUPT PRIORITYInitial Reset 0000H - INT 0 (Divider0) 0004H 1st INT 1 (Timer 0) 0008H 2nd INT 2 (Port RC) 000CH 3rd INT 3 (Divider1) 0014H 4th INT 4 (Timer 1) 0020H 5th JP Instruction XXXXH - Subroutine CallXXXXH-6.2 Stack Register (STACK)The stack register is organized as 49 bits x 16 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. (Refer to Table 8) When the stack register is pushed over the sixteen levels, the contents of the first level will be lost. In other words, the stack register is always sixteen levels deep.6.3 Program Memory (ROM)The read-only memory (ROM) is used to store program codes; and the look-up table is arranged as 65536 x 4 bits. The program ROM is divided into eight pages; the size of each page is 2048 x 16 bits. So the total ROM size is 16384 x 16 bits. Before the jump or subroutine call instructions are to be executed, the destination ROM page must be determined firstly. The ROM page can be selected by executing the MOV ROMPR,#I or MOV ROMPR, R instruction. But the branch decision instructions (e.g. JB0, SKB0, JZ, JC, ...) must jump to the same ROM page which the branch decision instructions are in. The whole ROM can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 65536 elements. Instruction MOVC R is used to read the look-up table content and transfer table data to the RAM. But before reading the addressed look-up table content, the content of the look-up table pointer (TAB) must be determined firstly. The address of the look-up table element is allocated by the content of TAB. The MOV TAB0 (TAB1, TAB2, TAB3), R instructions are used to allocate the address of the wanted look-up table element. The TAB0 register stores the LSB 4 bits of the look-up table address.Preliminary W742E81A/W742C81A- 8 -The organization of the program memory is shown in Figure 6-1.Figure 6-1 Program Memory Organization6.3.1 ROM Page Register (ROMPR)The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows:0123ROMPRNote: W means write only.Bit 3 is reserved.Bit 2, Bit 1, Bit 0 ROM page preselect bits: 000 = ROM page 0 (0000H - 07FFH) 001 = ROM page 1 (0800H - 0FFFH) 010 = ROM page 2 (1000H - 17FFH) 011 = ROM page 3 (1800H - 1FFFH) 100 = ROM page 4 (2000H - 27FFH) 101 = ROM page 5 (2800H - 2FFFH) 110 = ROM page 6 (3000H - 37FFH) 111 = ROM page 7 (3800H - 3FFFH)Preliminary W742E81A/W742C81APublication Release Date: April 2000- 9 - Revision A16.4 Data Memory (RAM)6.4.1 ArchitectureThe static data memory (RAM) used to store data is arranged as 2048 × 4 bits. The data RAM is divided into sixteen banks; each bank has 128 × 4 bits. Executing the MOV DBKR,WR or MOV DBKR,#I instruction can determine which data bank is used. The data memory can be addressed directly or indirectly. But the data bank must be confirmed firstly; and the page in the data bank will be done in the indirect addressing mode, too. In indirect addressing mode, each data bank will be divided into eight pages. Before the data memory is addressed indirectly, the page which the dataFigure 6-2 Data Memory OrganizationThe 1st and 2nd data bank (00H to 7FH & 80H to FFH) in the data memory can also be used as the working registers (WR). It is also divided into sixteen pages. Each page contains 16 working registers. When one page is used as WR, the others can be used as the normal data memory. The WR page can be switched by executing the MOV WRP,R or MOV WRP,#I instruction. The data memory cannot operate directly with immediate data, but the WR can do. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next sub-section.6.4.2 Page Register (PAGE)The page register is organized as a 4-bit binary register. The bit descriptions are as follows:0123PAGENote: R/W means read/write available.Bit 3 is reserved.Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits: 000 = Page 0 (00H - 0FH)Preliminary W742E81A/W742C81A- 10 -001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) 111 = Page 7 (70H - 7FH)6.4.3 WR Page Register (WRP)The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows:0123WRPNote: R/W means read/write available.Bit 3, Bit 2, Bit 1, Bit 0 Working registers page preselect bits: 0000 = WR Page 0 (00H - 0FH) 0001 = WR Page 1 (10H - 1FH) 0010 = WR Page 2 (20H - 2FH) 0011 = WR Page 3 (30H - 3FH) 0100 = WR Page 4 (40H - 4FH) 0101 = WR Page 5 (50H - 5FH) 0110 = WR Page 6 (60H - 6FH) 0111 = WR Page 7 (70H - 7FH) 1000 = WR Page 8 (80H - 8FH) 1001 = WR Page 9 (90H - 9FH) 1010 = WR Page A (A0H - AFH) 1011 = WR Page B (B0H - BFH) 1100 = WR Page C (C0H - CFH) 1101 = WR Page D (D0H - DFH) 1110 = WR Page E (E0H - EFH) 1111 = WR Page F (F0H - FFH)6.4.4 Data Bank Register (DBKR)The data bank register is organized as a 4-bit binary register. The bit descriptions are as follows:0123DBKRNote: R/W means read/write available.Preliminary W742E81A/W742C81APublication Release Date: April 2000- 11 - Revision A1Bit 3, Bit 2, Bit 1, Bit 0 Data memory bank preselect bits: 0000 = Data bank 0 (000H - 07FH) 0001 = Data bank 1 (080H - 0FFH) 0010 = Data bank 2 (100H - 17FH) 0011 = Data bank 3 (180H - 1FFH) 0100 = Data bank 4 (200H - 27FH) 0101 = Data bank 5 (280H - 2FFH) 0110 = Data bank 6 (300H - 37FH) 0111 = Data bank 7 (380H - 3FFH) 1000 = Data bank 8 (400H - 47FH) 1001 = Data bank 9 (480H - 4FFH) 1010 = Data bank A (500H - 57FH) 1011 = Data bank B (580H - 5FFH) 1100 = Data bank C (600H - 67FH) 1101 = Data bank D (680H - 6FFH) 1110 = Data bank E (700H - 77FH) 1111 = Data bank F (780H - 7FFH)6.5 Accumulator (ACC)The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.6.6 Arithmetic and Logic Unit (ALU)This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions:• Logic operations: ANL, XRL, ORL• Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,SKB3• Shift operations: SHRC, RRC, SHLC, RLC• Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INCAfter any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOV R, CF.6.7 Main-OscillatorThe W742E81A/W742C81A provides a crystal or RC oscillation circuit to generate the system clock through external connections. If a crystal oscillator is used, The 3.58 MHz or 400KHz crystal must be connected to XIN1 and XOUT1, and a capacitor must be connected to XIN1 and V SS if an accurate frequency is needed.Preliminary W742E81A/W742C81A- 12 -Figure 6-3 System Clock Oscillator Configuration6.8 Sub-OscillatorThe sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the 32768 Hz crystal could be connected to XIN2 and XOUT2, and it would not be oscillated in STOP mode.6.9 DividersEach divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts. When the main oscillator starts action, the Divider0 is incremented by each clock (F OSC ). When an overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. And the last 4-stage of the Divider0 can be reset by executing CLR DIVR0 instruction.If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs in dual-clock mode or Fosc/128 in single-clock mode). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. And the last 4-stage of the Divider1 can be reset by executing CLR DIVR1 instruction. Same as EVF.0, the EVF.4 is set to 1 periodically. But there are two period time (125 mS & 500mS) that can be selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected; SCR.3 = 1, the 125 mS period time is selected.6.10 Dual-clock operationThis operation mode is selected by option code. In the dual-clock mode, the clock source of the LCD frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the signal-clock mode, the clock source of the LCD frequency selector will be Fm/128(Fm : main oscillator clock, See figure 6-4). So before the STOP instruction is executing, the LCD must be turned off in the signal-clock mode or dual-clock mode .In this dual-clock mode, the normal operation is performed by generating the system clock from the main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation is performed by resetting or setting the bit 0 of the System clock Control Register (SCR). If the SCR.0 is reset to 0, the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dual-clock mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the SCR.1 is set to 1.Preliminary W742E81A/W742C81APublication Release Date: April 2000- 13 - Revision A1When the SCR is set or reset, we must care the following cases:1. X000B → X011B: we should not exchange the F OSC from Fm into Fs and disable Fm simultaneously. We could first exchange the F OSC from Fm into Fs, then disable the main-oscillator. So it should be X000B →X001B →X011B.2. X011B → X000B: we should not enable Fm and exchange the F OSC from Fs into Fm simultaneously. We could first enable the main-oscillator; the 2nd step is calling a delay subroutine to wait the main-oscillator oscillating stably; then exchange the F OSC from Fs into Fm is the last step. So it should be X011B →X001B →delay the Fm oscillating stably time →X000B. The suggestion of the Fm oscillating stably time is3.5 mS for 455 KHz and 0.8ms for 4 MHz. We must remember that the X010B state is inhibitive, because it will induce the system shutdown. The organization of the dual-clock operation mode is shown in Figure 6-4.Figure 6-4 Organization of the dual-clock operation modePreliminary W742E81A/W742C81A- 14 -6.11 WatchDog Timer (WDT) and WatchDog Timer Register(WDTR)The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled, and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is F OSC /2048. The input clock of the WDT can be switched to F OSC /16384 (or F OSC /2048) by setting WDTR.3 to 1. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The WDT overflow period is 1 S when the sub-system clock (Fs) is 32 KHz and WDT clock input is Fs/2048. When the corresponding option code bit of the WDT set to 0, the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 6-5.Figure 6-5 Organization of Divider0, Divider1 and WatchDog TimerPreliminary W742E81A/W742C81APublication Release Date: April 2000- 15 - Revision A10123WDTRNote: R/W means read/write available, R means read only. Power On reset default is : 0000Bit 3 = 0 F OSC/2048(Select Divider0) or Fss/2048(Select Divider1) as the WDT source. = 1 F OSC/16384(Select Divider0) or Fss/16384(Select Divider1) as the WDT source. Bit 2 = 0 Select Divider0. = 1 Select Divider1. Bit 1 = 0 Refer to Table 2. = 1 Refer to Table 2. Bit 0 = 0 No time out. = 1 Time out.WDTR.0 will be set to one when WDT time out and can be reset to zero by: Power On Reset, RESET pin, CLR WDTTable 2 The bit 1 of WatchDog Timer Register (WDTR) reset itemRESET ITEMWDTR.1 = 1 WDTR.1 = 0 Program Counter (PC) 0000H 0000H Stack Pointer (SP)- Reset ROMPR, PAGE, DBKR, WRP, ACC, CF, ZF, SCR registers- Reset IEF, HEF, SEF, HCF, PEF, EVF flags IEF = ResetReset DIV0, DIV1- Reset TM0, TM1, MR0, MR1 registers - Reset Timer 0 input clock - FOSC/4 Timer 1 input clock - FOSC MFP output - Low PM0 register- Reset PM1, PM2, PM5 registers - Set (1111B) PSR0 register- Reset Input/output ports RA, RB, RD - Input mode Output ports RE, RF - High RA, RB ports output type - CMOS type RC port pull-high resistors- Disable Input clock of the watchdog timer - FOSC/2048DTMF output - Hi-Z BUZCR register - ResetFLCD- Q5 to Q9 ResetLCD display - OFF LCDR- ResetSegment output mode-LCD drive output-: keep the statusNote: SCR.2 is reservedPreliminary W742E81A/W742C81A- 16 -6.12 Timer/Counter6.12.1 Timer 0 (TM0)Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TM0H),R instructions are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to 0, and the specified value can be loaded into TM0. Then we can set MR0.3 to 1, that will cause the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decreases and underflow to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag has been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set (HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as F OSC /1024 or F OSC /4 by setting MR0.0 to 1 or resetting MR0.0 to 0. The default timer value is F OSC /4. The organization of Timer 0 is shown in Figure 6-6. If the Timer 0 clock input is F OSC /4:Desired Timer 0 interval = (preset value +1) × 4 × 1/F OSC If the Timer 0 clock input is F OSC /1024:Desired Timer 0 interval = (preset value +1) × 1024 × 1/F OSCPreset value: Decimal number of Timer 0 preset value F OSC : Clock oscillation frequencyFigure 6-6 Organization of Timer 0Preliminary W742E81A/W742C81APublication Release Date: April 2000- 17 - Revision A16.12.2 Timer 1 (TM1)Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6-7. Timer 1 can be used as to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: F OSC /64, F OSC , or Fs. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is F OSC . When the MOV TM1L, R or MOV TM1H,R instruction is executed, the specified data are loaded into the auto-reload buffer; but the TM1 down-counting will keep going on. If the bit 3 of MR1 is set (MR1.3 = 1), the content of the auto-reload buffer will be loaded into the TM1 down counter, and Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the timer decreases and underflow to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. Then, if interrupt enable flag 7 has been set to 1 (IEF.7 = 1), an interrupt is executed; if hold mode release enable flag 7 is set to 1 (HEF.7 = 1), the hold state is terminated. The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.In a case where Timer 1 clock input is F T :Desired Timer 1 interval = (preset value +1) / F TDesired frequency for MFP output pin = F T ÷ (preset value + 1) ÷ 2 (Hz) Preset value: Decimal number of Timer 1 preset value F OSC : Clock oscillation frequencyFigure 6-7 Organization of Timer 1Preliminary W742E81A/W742C81A- 18 -For example, when F T equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below.MOV WR,TM1 can read back the content of TM1, It will save the TM1 MSB to WR and the TM1 LSB to ACC.Table 3 The relation between the tone frequency and the present value of TM1C C #BG F E D A ##D ##G FA EN O T TM1 preset value & MFP frequency 3rd octave4th octave5th octave261.63277.18293.66311.13329.63349.23369.99392.00415.30440.00466.16493.88523.25554.37587.33622.25659.26698.46739.99783.99830.61880.00932.23987.77260.06277.69292.57309.13327.68372.36390.09420.10443.81442.813EH 3AH 37H 34H 31H 2EH 2BH 29H 26H 22H 24H 20H468.11496.481EH 1CH 1BH 19H 18H 16H 15H 14H 13H 12H 11H 10H528.51564.96585.14630.15655.36712.34744.72780.19819.20862.84910.22963.76130.81138.59146.83155.56164.81174.61185.00196.00207.65220.00233.08246.947CH 75H 6FH 68H 62H 5DH 58H 53H 4EH 45H 49H 41H131.07138.84146.28156.03165.49174.30184.09195.04207.39221.40234.05248.24Tone frequency Tone frequencyTM1 preset value & MFP frequency Tone frequency TM1 preset value & MFP frequencyNote: Central tone is A4 (440 Hz).6.12.3 Mode Register 0 (MR0)Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows:0123MR0Note: W means write only.Bit 0 = 0 The fundamental frequency of Timer 0 is F OSC /4. = 1 The fundamental frequency of Timer 0 is F OSC /1024. Bit 1 & Bit 2 are reservedBit 3 = 0 Timer 0 stops down-counting. = 1 Timer 0 starts down-counting.Preliminary W742E81A/W742C81APublication Release Date: April 2000- 19 - Revision A16.12.4 Mode Register 1 (MR1) & MFP Control Pin (BUZCR)Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows:0123MR1Note: W means write only.Bit 0 = 0 The internal fundamental frequency of Timer 1 is F OSC . = 1 The internal fundamental frequency of Timer 1 is F OSC /64. Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.= 1 The fundamental frequency source of Timer 1 is the sub-oscillator frequency Fs (32768 Hz). Bit 2 is reserved.Bit 3 = 0 Timer 1 stops down-counting. = 1 Timer 1 starts down-counting.MFP control pin is organized as a 4-bit binary register.0123BUZCRNote: W means write only.Bit 0 = 0 The specified waveform of the MFP generator is delivered to the MFP output pin. = 1 The specified frequency of Timer 1 is delivered to the MFP output pin. Bit 1, Bit 2 & Bit 3 are reserved.6.13 InterruptsThe W742E81A/W742C81A provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and one external interrupt source (port RC). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the µC will enter hold mode again. The operation flow chart is shown in Figure 6-9. The control diagram is shown in Figure 6-9.Preliminary W742E81A/W742C81A- 20 -Figure 6-8 Interrupt event control diagram6.14 Stop Mode OperationIn stop mode, all operations of the µC cease, and the MFP pin is kept to high. The µC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the RC). When the designated signal is accepted, the µC awakens and executes the next instruction. To prevent erroneous execution, the NOP instruction should follow the STOP command. But In the dual-clock slow operation mode, the STOP instruction will also disable the sub-oscillator oscillating; all operations of the µC cease.6.14.1 Stop Mode Wake-up Enable Flag for RC Port (SEF)The stop mode wake-up flag for port RC is organized as an 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:SEF 0123Note: W means write only.SEF.0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0 SEF.1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1Preliminary W742E81A/W742C81APublication Release Date: April 2000- 21 - Revision A1SEF.2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2 SEF.3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.36.15 Hold Mode OperationIn hold mode, all operations of the µC cease, except for the operation of the oscillator, Timer, Divider, LCD driver, DTMF generator and MFP generator. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of five ways: by the action of timer 0, timer 1, divider 0, divider 1, the RC port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart.Figure 6-9 Hold Mode and Interrupt Operation Flow Chart。

NJW0302G;NJW0281G;中文规格书,Datasheet资料

NJW0281G (NPN)NJW0302G (PNP)Preferred Devices Complementary NPN-PNP Power Bipolar TransistorsThese complementary devices are lower power versions of the popular NJW3281G and NJW1302G audio output transistors. With superior gain linearity and safe operating area performance, these transistors are ideal for high fidelity audio amplifier output stages and other linear applications.Features•ăExceptional Safe Operating Area•ăNPN/PNP Gain Matching within 10% from 50 mA to 3 A•ăExcellent Gain Linearity•ăHigh BVCEO•ăHigh Frequency•ăThese are Pb-Free DevicesBenefits•ăReliable Performance at Higher Powers•ăSymmetrical Characteristics in Complementary Configurations •ăAccurate Reproduction of Input Signal•ăGreater Dynamic Range•ăHigh Amplifier BandwithApplications•ăHigh-End Consumer Audio Products♦ăHome Amplifiers♦ăHome Receivers•ăProfessional Audio Amplifiers♦ăTheater and Stadium Sound Systems♦ăPublic Address Systems (PAs)MAXIMUM RATINGSRating Symbol Value UnitCollector-Emitter Voltage V CEO250Vdc Collector-Base Voltage V CBO250Vdc Emitter-Base Voltage V EBO 5.0Vdc Collector-Emitter Voltage - 1.5 V V CEX250VdcCollector Current - Continuous-Peak (Note 1)I C1530AdcBase Current - Continuous I B1.5AdcTotal Power Dissipation @ T C = 25°C P D150WattsOperating and Storage Junction Temperature Range T J, T stg-65 to+150°CStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.Pulse Test: Pulse Width = 5.0 ms, Duty Cycle < 10%.15 AMPERES COMPLEMENTARY SILICON POWER TRANSISTORS250 VOLTS, 150 WATTSDevice Package ShippingORDERING INFORMATIONTO-3PCASE 340ABMARKINGDIAGRAMPreferred devices are recommended choices for future use and best overall value.NJW0302G TO-3P(Pb-Free)30 Units/Rail NJW0281G TO-3P(Pb-Free)30 Units/Railxxxx= 0281 or 0302G= Pb-Free PackageA= Assembly LocationY= YearWW= Work WeekNJWxxxGAYWWTHERMAL CHARACTERISTICSCharacteristicSymbol Value Unit Thermal Resistance, Junction-to-CaseR θJC0.83°C/WELECTRICAL CHARACTERISTICS (T C = 25°C unless otherwise noted)CharacteristicSymbolMinMaxUnitOFF CHARACTERISTICSCollector-Emitter Sustaining Voltage (I C = 30 mA, I B = 0)V CEO(sus)250-V Collector Cutoff Current (V CB = 250 V, I E = 0)I CBO -10m A Emitter Cutoff Current (V EB = 5.0 V, I C = 0)I EBO- 5.0m AON CHARACTERISTICS DC Current Gain(I C = 0.5 A, V CE = 5.0 V)(I C = 1.0 A, V CE = 5.0 V)(I C = 3.0 A, V CE = 5.0 V)h FE757575150150150-Collector-Emitter Saturation Voltage (I C = 5.0 A, I B = 0.5 A)V CE(sat)- 1.0V Base-Emitter On Voltage (I C = 5.0 A, V CE = 5.0 V)V BE(on)- 1.2V DYNAMIC CHARACTERISTICSCurrent-Gain - Bandwidth Product(I C = 1.0 A, V CE = 5.0 V, f test = 1.0 MHz)f T 30-MHz Output Capacitance(V CB = 10 V, I E = 0, f test = 1.0 MHz)C ob-400pF160T C , CASE TEMPERATURE (°C)40601001201608014020Figure 1. Power Derating 020406080100140120P D , P O W E R D I S S I P A T I O N (W)0.010.11101001101001000V CE , COLLECTOR-EMITTER VOLTAGE (V)I C , C O L L E C T O R C U R R E N T (A )Figure 2. Safe Operating Area00.20.40.60.811.21.40.010.1110100I C , COLLECTOR CURRENT (A)Figure 3. NJW0281G DC Current GainFigure 4. NJW0302G DC Current Gainh F E , D C C U R R E N T G A I NI C , COLLECTOR CURRENT (A)Figure 5. NJW0281G Base-Emitter Voltage I C , COLLECTOR CURRENT (A)0.010.1110100Figure 6. NJW0302G Base-Emitter VoltageV B E (o n ), B A S E -E M I T T E R V O L T A G E (V )I C , COLLECTOR CURRENT (A)V B E (o n ), B A S E -E M I T T E R V O L T A G E (V )h F E , D C C U R R E N T G A I N0.050.111050-0.10.40.91.41.92.40.050.111050Figure 7. NJW0281G Saturation Voltage 0.010.11100.010.1110100I C , COLLECTOR CURRENT (A)V C E (s a t ), C O L L E C T O R -E M I T T E R S A T U R A T I O N V O L T A G E (V)0.010.11100.010.1110100Figure 8. NJW0302G Saturation VoltageI C , COLLECTOR CURRENT (A)V C E (s a t ), C O L L E C T O R -E M I T T E R S A T U R A T I O N V O L T A G E (V )0102030405060700.010.1110Figure 9. NJW0281G Current Gain BandwidthProduct I C , COLLECTOR CURRENT (A)f T , C U R R E N T G A I N B A N D W I D T H P R O D U C T (M H z )Figure 10. NJW0302G Current Gain BandwidthProductI C , COLLECTOR CURRENT (A)f T , C U R R E N T G A I N B A N D W I D T H P R O D U C T (M H z )01020304050600.010.1110PACKAGE DIMENSIONSTO-3P-3LD CASE 340AB-01ISSUE ADIM A MIN NOM MAX MILLIMETERS 19.7019.9020.10B 15.4015.6015.80C 4.60 4.80 5.00D 0.80 1.00 1.20E 1.45 1.50 1.65G 5.45 BSC H 1.20 1.40 1.60J 0.550.600.75K 19.8020.0020.20L 18.5018.7018.90U 5.00 REF P 3.30 3.50 3.70Q 3.10 3.20 3.50W2.803.00 3.20NOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS3.DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP.4.DIMENSION A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.F 1.80 2.00 2.20SEATING PLANEFUON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION分销商库存信息:ONSEMINJW0302G NJW0281G。

W741E203资料

4-BIT FLASH MICROCONTROLLERPublication Release Date: March 1998Table of Contents--GENERAL DESCRIPTION.........................................................................................................................2 FEATURES.................................................................................................................................................2 PIN CONFIGURATIONS............................................................................................................................3 PIN DESCRIPTION....................................................................................................................................4 BLOCK DIAGRAM......................................................................................................................................5 FUNCTIONAL DESCRIPTION...................................................................................................................6 ABSOLUTE MAXIMUM RATINGS .............................................................................................................28 DC CHARACTERISTICS............................................................................................................................29 AC CHARACTERISTICS............................................................................................................................30 PAD ASSIGNMENT & POSITIONS............................................................................................................31 TYPICAL APPLICATION CIRCUIT.............................................................................................................32 INSTRUCTION SET TABLE.......................................................................................................................33 PACKAGE DIAMENSIONS (79)GENERAL DESCRIPTIONThe W741E20X is a high-performance 4-bit microcontroller (µC) that provides an flash EEPROM for the program memory. The device contains a 4-bit ALU, two 8-bit timers, a divider, a serial port, and five 4-bit I/O ports (including 3 output port for LED driving). There are also seven interrupt sources and 8-level subroutine nesting for interrupt applications. The W741E20X has two power reduction modes, hold mode and stop mode, which help to minimize power dissipation.The W741E20X is suitable for end product manufacturer engineering testing and earlier samples before mass production.FEATURES•Operating voltage: 2.4V−5.5V•Crystal or RC oscillation circuit can be selected by the code option− Crystal/Ceramic oscillator: up to 4 MHz− RC oscillator: up to 4 MHz• Both in crystal or RC oscillator operation mode, high-frequency (400 KHz to 4 MHz) or low-frequency (32.768 KHz) oscillation must be determined by the code option• Memory− 2048 × 16 bit program flash EEPROM (including 2K × 4 bit look-up table)− 128 × 4 bit data RAM (including 16 working registers)•21 input/output pins− Input/output ports: 4 ports/16 pins− Serial input/output port: 1 port /4 pins (high sink current for LED driving)− MFP output pin: 1 pin (MFP)• Power-down mode− Hold function: no operation (except for oscillator)− Stop function: no operation (including oscillator)•Seven types of interrupts− Five internal interrupts (Divider 0, Timer 0, Timer 1, and Serial I/O)− Two external interrupts (Port RC and INT pin)•MFP output pin− Output is software selectable as modulating or nonmodulating frequency− Works as frequency output specified by Timer 1•Built-in 14-bit clock frequency divider circuit•Two built-in 8-bit programmable countdown timers− Timer 0: One of two internal clock frequencies (F OSC/4 or F OSC/1024) can be selected− Timer 1: Offers auto-reload function and one of two internal clock frequencies (F OSC or F OSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin)•Built-in 18/14-bit watchdog timer selectable for system reset•Powerful instruction set: 118 instructions•8-level subroutine (include interrupt) nestingPublication Release Date: March 1998 • One serial transmission/receiver port specified by software • Up to 1 µS instruction cycle (with 4 MHz operating frequency) • Packaged in 18-pin, 20-pin, 28-pin PDIP and 20-pin, 28-pin SOPPIN CONFIGURATIONSPIN DESCRIPTIONNote: There are internal pull-high resistors in these pins of W741C20X.Publication Release Date: March 1998 BLOCK DIAGRAMFUNCTIONAL DESCRIPTIONProgram Counter (PC)Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses of the 2048 × 16 on-chip flash EEPROM containing the program instruction. When the jump or subroutine call instructions or the interrupt or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. The format used is shownStack Register (STACK)The stack register is organized as 11 bits × 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep.Program Memory (flash EEPROM)The flash EEPROM is used to store program codes; the look-up table is arranged as 2048 × 4 bits. The first three quarters of flash EEPROM (000H to 5FFH) are used to store instruction codes only, but the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. There are two registers (TABL and TABH) to be used in look-up table addressing and they are controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is executed, the contents of the look-up table location address specified by TABH, TABL and ACC will be read and transferred to the data RAM. Refer to the instruction table for more details. The organization of the program memory is shown in Figure 1.Publication Release Date: March 1998Figure 1. Program Memory OrganizationData Memory (RAM)1. ArchitectureThe static data memory (RAM) used to store data is arranged as 128 × 4 bits. The data memory can be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.Figure 2. Data Memory OrganizationThe first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next section.2. Page Register (PAGE)The page register is organized as a 4-bit binary register. The bit descriptions are as follows:PAGENote: R/W means read/write available.Bit 3 is reserved.Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits:000 = Page 0 (00H - 0FH)001 = Page 1 (10H - 1FH)010 = Page 2 (20H - 2FH)011 = Page 3 (30H - 3FH)100 = Page 4 (40H - 4FH)101 = Page 5 (50H - 5FH)110 = Page 6 (60H - 6FH)111 = Page 7 (70H - 7FH)Accumulator (ACC)The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.Arithmetic and Logic Unit (ALU)This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions:•Logic operations: ANL, XRL, ORL•Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3 •Shift operations: SHRC, RRC, SHLC, RLC•Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INCAfter any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOVA R, CF.Publication Release Date: March 1998 Clock GeneratorThe W741E20X provides a crystal or RC oscillation circuit selected by option codes to generate the system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN and XOUT, and the capacitor must be connected if an accurate frequency is needed. When a crystal oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is used, a resistor in the range of 20 K Ω to 1.6 M Ω must be connected to XIN and XOUT, as shown in Figure 3. The system clock frequency range is from 32 KHz to 4 MHz. One machine cycle consists of a four-phase system clock sequence and can run up to 1 µS with a 4 MHz system clock.Figure 3. Oscillator ConfigurationDivider 0Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as shown in Figure 4. When the system starts, the divider is incremented by each system clock (Fosc). When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider 0 can be reset by executing CLR DIVR0 instruction. If the oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1 periodically at each 500 mS interval.Watchdog Timer (WDT)The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is F OSC /1024. The input clock of the WDT can be switched to F OSC /16384 (or F OSC /1024) by executing the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun overflow period is 468.75 mS when the system clock (F OSC ) is 32 KHz and WDT clock input is F OSC /1024. When the corresponding option code bit of the WDT is set to 0, the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.Figure 4. Organization of Divider and Watchdog TimerParameter Flag (PMF)The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:123PMFNote: W means write only.Bit 0, Bit 1 & Bit 2 are reserved.Bit 3 = 0 The fundamental frequency of the watch dog timer is Fosc/1024.= 1 The fundamental frequency of the watch dog timer is Fosc/16384.At initial reset, bit 3 of PMF is set to "0".Publication Release Date: March 1998 Timer/CounterTimer 0 (TM0)Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L(TM0H), R or MOV TM0, #I instruction. When the MOV TM0L (TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting), the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1). The Timer 0 clock input can be set as F OSC /1024 or F OSC /4 by setting MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is F OSC /4. The organization of Timer 0 is shown in Figure 5.If the Timer 0 clock input is Fosc/4, then: Desired time 0 interval = (preset value +1) × 4 × 1/Fosc If the Timer 0 clock input is Fosc/1024, then:Desired time 0 interval = (preset value +1) × 1024 × 1/Fosc Preset value: Decimal number of Timer 0 preset value Fosc: Clock oscillation frequencyFigure 5. Organization of Timer 0Timer 1 (TM1)Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: Fosc/64, Fosc, or an external clock from the RC.0input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is Fosc. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L, R or MOV TM1H,R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into auto-reload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.If the Timer 1 clock input is F T, then :Desired Timer 1 interval = (preset value +1) / F TDesired frequency for MFP output pin = F T ÷ (preset value + 1) ÷ 2 (Hz) Preset value: Decimal number of Timer 1 preset value, and Fosc: Clock oscillation frequencyFigure 6. Organization of Timer 1Publication Release Date: March 1998 For example, when F T equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below.3 45Tone frequency TM1 preset value &MFP frequency Tonefrequency TM1 preset value & MFP frequency Tone frequency TM1 preset value & MFP frequencyC 130.81 7CH 131.07 261.63 3EH 260.06 523.25 1EH 528.51C#138.59 75H 138.84 277.18 3AH 277.69 554.37 1CH 564.96 T D 146.83 6FH 146.28 293.66 37H 292.57 587.33 1BH 585.14 D# 155.56 68H 156.03 311.13 34H 309.13 622.25 19H 630.15 O E 164.81 62H 165.49 329.63 31H 327.68 659.26 18H 655.36 F 174.61 5DH 174.30 349.23 2EH 372.36 698.46 16H 712.34 N F# 185.00 58H 184.09 369.99 2BH 390.09 739.99 15H 744.72 G 196.00 53H 195.04 392.00 29H 420.10 783.99 14H 780.19 E G#207.65 4EH 207.39 415.30 26H 443.81 830.61 13H 819.20 A 220.00 49H 221.40 440.00 24H 442.81 880.00 12H 862.84 A# 233.08 45H 234.05 466.16 22H 468.11 932.23 11H 910.22B246.94 41H 248.24 493.88 20H 496.48 987.77 10H 963.76Note: Central tone is A4 (440 Hz).Mode Register 0 (MR0)Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to controlthe operation of Timer 0. The bit descriptions are as follows:0123MR0Note: W means write only.Bit 0 = 0 The fundamental frequency of Timer 0 is F OSC /4. = 1 The fundamental frequency of Timer 0 is F OSC /1024. Bit 1 & Bit 2 are reservedBit 3 = 0 Timer 0 stops down-counting. = 1 Timer 0 starts down-counting.Mode Register 1 (MR1)Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows:0123MR1Note: W means write only.Bit 0 = 0 The internal fundamental frequency of Timer 1 is Fosc. = 1 The internal fundamental frequency of Timer 1 is Fosc/64.Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin.Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin. = 1 The specified frequency of Timer 1 is delivered at the MFP output pin.Bit 3 = 0 Timer 1 stops down-counting. = 1 Timer 1 starts down-counting.Input/Output Ports RA, RBPort RA consists of pins RA.0 to RA.3 and Port RB consists of pins RB.0 to RB.3. At initial reset, input/output ports RA and RB are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R operate the output functions. For more details, refer to the instruction table and Figure 7.Figure 7. Architecture of RA & RB Input/Output PinsPublication Release Date: March 1998 Port Mode 0 Register (PM0)The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows:PM00123Note: W means write only.Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 0 = 1 RB port is NMOS open drain output type. Bit 2 & Bit 3 are reserved.Port Mode 1 Register (PM1)The port mode 1 register is organized as 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows:PM10123Note: W means write only.Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin At initial reset, port RA is input mode (PM1 = 1111B).Port Mode 2 Register (PM2)The port mode 2 register is organized as 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows:PM20123Note: W means write only.Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin At initial reset, the port RB is input mode (PM2 = 1111B).Port Mode 3 Register (PM3)Port Mode 3 Register is organized as a 4-bit binary register (PM3.0 to PM3.3). PM3 can be used to determine the operating mode of the output port RE and the clock rate of the serial I/O function. The PM3 control diagram is shown in Figure 8. The bit descriptions are as follows:123PM3Note: W means write only.Bit 0 is reserved.Bit 1 = 0 The output of the port RE is the output of the internal parallel port RT.= 1 The port RE works as the serial input/output port. Bit 2 is reserved.Bit 3 = 0 Serial Tx rate = Fosc/2= 1 Serial Tx rate = Fosc/256Figure 8. PM3 Control DiagramPort Mode 4 Register (PM4)The port mode 4 register is organized as 4-bit binary register (PM4.0 to PM4.3). PM4 can be used to control the input/output mode of port RC. PM4 is controlled by the MOV PM4, #I instruction. The bit descriptions are as follows:PM40123Note: W means write only.Publication Release Date: March 1998 Bit 0 = 0 RC.0 works as output pin; Bit 0 = 1 RC.0 works as input pin Bit 1 = 0 RC.1 works as output pin; Bit 1 = 1 RC.1 works as input pin Bit 2 = 0 RC.2 works as output pin; Bit 2 = 1 RC.2 works as input pin Bit 3 = 0 RC.3 works as output pin; Bit 3 = 1 RC.3 works as input pin At initial reset, port RC is input mode (PM4 = 1111B).Port Mode 5 Register (PM5)The port mode 5 register is organized as 4-bit binary register (PM5.0 to PM5.3). PM5 can be used to control the input/output mode of port RD. PM5 is controlled by the MOV PM5, #I instruction. The bit descriptions are as follows:PM50123Note: W means write only.Bit 0 = 0 RD.0 works as output pin; Bit 0 = 1 RD.0 works as input pin Bit 1 = 0 RD.1 works as output pin; Bit 1 = 1 RD.1 works as input pin Bit 2 = 0 RD.2 works as output pin; Bit 2 = 1 RD.2 works as input pin Bit 3 = 0 RD.3 works as output pin; Bit 3 = 1 RD.3 works as input pinAt initial reset, the port RB is input mode (PM2 = 1111B). Input/Output Ports RC, RDPort RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. At initial reset, input/output ports RC and RD are both in input mode. When RC and RD are used as output ports, the CMOS type is the only ouput driving type. Each pin of port RC or RD can be specified as input or output mode independently by the PM4 and PM5 registers. The MOVA R, RC or MOVA R, RD instructions operate the input functions and the MOV RC, R or MOV RD, R operate the output functions. When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) records the status of port RC, and that can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. Before the port mode of the RC port is changed from output mode to input mode in the hold mode release and interrupt application, the output value must be preset to the same as the system status to prevent the undesired signal change being accepted. When the interrupt of RC port is accepted, the corresponding event flag (EVF.2) will be reset, but the content of PSR0 should not be changed except the CLR PSR0 or MOV PEF,#I instruction being executed or performing the reset function. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. The RD port is used as the I/O port only. Refer to Figure 9, Figure 10 and the instruction table for more details.Figure 9. Architecture of RC & RD Input/Output PinsPort Enable Flag (PEF)The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or preform interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:PEF 0123Note: W means write only.PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.Port Status Register 0 (PSR0)Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read orcleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:0123PSR0Note: R means read only.Publication Release Date: March 1998 Bit 0 = 1 Signal change at RC.0 Bit 1 = 1 Signal change at RC.1 Bit 2 = 1 Signal change at RC.2 Bit 3 = 1 Signal change at RC.3Figure 10. Input Architecture of Ports RCOutput Port REOutput port RE can be used as an output of the internal RT port, or as a serial input/output port. The control flow is shown in Figure 8. When bit 1 of port mode 3 register (PM3) equals to 0, port RE works as an output of internal port RT. When the MOV RE, R instruction is executed, the data in the RAM will be output to port RT through port RE. When RE works as a parallel output port, it provides a high sink current to drive LEDs. When bit 1 of MR0 equals to 1, the RE port works as a serial input/output port, and RE.0 to RE.3 are used as DOUT, CLKO, DIN, and CLKI, respectively. In this case, the DIN pin will has a built-in pull-high resistor. The serial I/O functions are controlled by the instructions SOP R and SIP R. The functions of the two instructions are described below:(1) When the SIP R instruction is executed, the data will be loaded from the serial input buffer to the ACC and RAM first, and bit 1 of port status register 2 will automatically be set to "1" (BUSYI = 1). Then the CLKI pin will send out 8 clocks and the data from the DIN pin will be loaded to SIB at the rising edge of the CLKI pin. After the 8 clocks have been sent, BUSYI will be reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is executed; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. Users can check the status of PSR2.1 (BUSYI) to know whether the serial input process is completed or not. If a serial input process is not completed, and the SIP R instruction is executed again, the data will be lost. The timing is shown in Figure 11.Figure 11. Timing of the Serial Input Function (SIP R)Publication Release Date: March 1998 (2) When the SOP R instruction is executed, the data will be loaded to the serial output buffer (SOB) and bit 3 of port status register 2 will be set to "1" (BUSYO = 1). Then the CLKO pin will send out 8 clocks and the data in SOB will be sent out at the falling edge of the CLKO pin. After the 8 clocks have been sent, BUSYO will be reset to "0" and EVF.6 will be set to "1." At this time, if IEF.6 has been set (IEF.6 = 1), an interrupt is executed; if HEF.6 has been set (HEF.6 = 1), the hold state is terminated. Users can check the status of PSR2.3 (BUSYO) to know whether the serial output process is completed or not. If a serial output process is not completed, and the SOP R instruction is executed again, the data will be lost. The timing is shown in Figure 12.Figure 12. Timing of the Serial Output Function (SOP R)In the above description, the low nibble location of the serial input/output register is contributed to the ACC, and the high nibble is to R. The port status register 2 (PSR2) including BUSYI, and BUSYO can be read out or cleared by the MOVA R, PSR2, or CLR PSR2 instruction.Port Status Register 2 (PSR2)Port status register 2 is organized as 4-bit binary register (PSR2.0 to PSR2.3). PSR2 is controlled by the MOVA R, PSR2, and CLR PSR2 instructions. The bit descriptions are as follows:123PSR2Note: R means read only.Bit 0 is reserved.Bit 1 (BUSYI):Serial port input busy flag.Bit 2 is reserved.Bit 3 (BUSYO):Serial port output busy flag.MFP Output Pin (MFP)The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096Hz, 2048Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown as below.(Fosc = 32.768 KHz)R6 R5 R4 R3 R2 R1 R0 FUNCTION R7levelLow0 0 0 0 0 0Hz1280 0 0 0 0 1Hz640 0 0 0 1 0Hz80 0 0 0 1 0 04Hz0 0 1 0 0 00 1 0 0 0 0 2 HzHz1 0 0 0 0 01level0 0 0 0 0 0HighHz1280 0 0 0 0 1Hz0 0 0 0 1 0648Hz1 0 0 0 1 0 0Hz0 0 1 0 0 04Hz20 1 0 0 0 0Hz11 0 0 0 0 0Hz0 0 0 0 0 020480 0 0 0 0 1 2048 Hz * 128 Hz64Hz*0 0 0 0 1 02048Hz1 0 0 0 0 1 0 0 2048 Hz * 8 Hz4Hz*Hz20480 0 1 0 0 02Hz*0 1 0 0 0 0Hz20481Hz*20481 0 0 0 0 0Hz。

ZLG72128数据手册

4.2.1 系统寄存器 SystemReg（地址：00H）················································ 9
4.2.2 键值寄存器 Key（地址：01H）························································ 9
1.2 描述
ZLG72128 是广州周立功单片机科技有限公司自行设计的数码管显示驱动及键盘扫描管理芯片。能够直接驱动 12 位共阴式数码管（或 96 只独立的 LED），同时还可以扫描管理多达 32 只按键。其中有 8 只按键还可以作为功能键使用，就像电脑键盘上的 Ctrl、Shift、Alt 键一样。另外 ZLG72128 内部还设置有连击计数器，能够使某键按下后不松手而连续有效。采用 I2C 总线方式，与微控制器的接口仅需两根信号线。该芯片为工业级芯片，抗干扰能力强，在工业测控中已有大量应用。
第 2 章引脚功能说明
表 2.1 引脚功能表
引脚名称 RST GND VCAP VDD
PWR_CTRL KEY_INT SDA SCL
4.3.5 左移命令(ShiftLeft)······································································ 12
4.3.6 循环左移命令(CyclicShiftLeft)························································· 12
电气特性（Vcc=5.0V，TA =25℃）
符号 VCC ICC ICC IIO
VIH
VIL
VOH
VOL