第三部分9：SynplifyPro入门胶片

attribute应用实例(3)
syn_maxfan module test (registered_data_out, clock, data_in); output [31:0] registered_data_out; input clock; input [31:0] data_in /* synthesis syn_maxfan=1000 */; reg [31:0] registered_data_out /* synthesis syn_maxfan=1000 */; syn_multstyle module mult(a,b,c,r,en); input [7:0] a,b; output [15:0] r; input [15:0] c; input en; wire [15:0] temp /* synthesis syn_multstyle="logic" */; assign temp = a*b; assign r = en ? temp : c; endmodule
Synplify Pro 使用指导
Synplify Pro简介
用户界面(1)
用户界面(经典视图)
视图设置
设计流程
新建工程
文件添加
黑盒设置
综合选项设置(1)
综合选项设置(2)
综合选项设置(3)
综合选项设置(4)
综合选项设置(5)
综合选项设置(6)
Retiming设置
约束设置
约束选项
TCL脚本快速设置
项目文件解析
文本文档
批处理方式(batch mode)
文本文档
综合(Project –run synthesis)
输出文件
告警处理
时序分析
日志文件解析
SRR 文件
多周期路径约束
RTL视图及层次分析
工艺视图及关键路径
状态机分析
SynplifyPro的属性和指示(1)
SynplifyPro的属性和指示(2)
SynplifyPro属性和指示(3)
attribute应用实例(1)
1. altera_auto_use_eab module top (z, a) /* synthesis altera_auto_use_eab = 0 */; output [3:0] z; input [4:0] a; rom2 myrom (.z(z) , .a(a)); endmodule 2. altera_chip_pin_lc Stratix Example output [7:0] DATA0 /* synthesis altera_chip_pin_lc = "14,12,11,5,21,18,16,15" */;
4. syn_allow_retiming reg [7:0] app_reg /* synthesis syn_allow_retiming=0 */
attribute应用实例(3)
3. syn_encoding module prep3 (CLK, RST, IN, OUT); input CLK, RST; input [7:0] IN; output [7:0] OUT; reg [7:0] OUT; reg [7:0] current_state /* synthesis syn_encoding="gray" */; 4.syn_global_buffers module top (clk1, clk2, clk3, clk4, clk5, clk6, clk7,clk8,clk9, clk10, clk11, clk12, clk13, clk14, clk15, clk16, clk17, clk18, clk19, clk20, d1, d2, d3, d4, d5, d6, d7, d8, q1, q2, q3, q4, q5, q6, q7, q8, reset) /* synthesis syn_global_buffers = 10 */;
attributes control mapping optimizations and attributes can be entered either in an .sdc constraint file or in HDL source code directives control compiler optimizations. directives must be entered in the HDL source code
attribute应用实例(2)
3. altera_io_opendrain module alu (..., aluop, alua, alub, alu_cout, aluz, aluout); input [3:0] aluop; // Apply to a bi-directional bus port inout [7:0] alua /* synthesis altera_io_opendrain=0 */, alub; // Apply to a bit port output alu_cout /* synthesis altera_io_opendrain=1 */, aluz;
attribute应用实例(6)
syn_ramstyle module ram4 (datain,dataout,clk); output dataout[31:0]; input clk; input datain[31:0]; reg [7:0] dataout[31:0] /* synthesis syn_ramstyle="M4K" */; xc_fast output [5:0] DATA0 /* synthesis xc_fast = 1 */;
XILINX增量综合布线(3)
SRR 文件
XILINX增量综合布线(4)
XILINX增量综合布线(4)
XILINX增量综合布线(4)
多点综合应用文章
Adobe Acrobat 7.0 Document
attribute应用实例(4)
syn_noclockbuf module my_design(out, in, clk_in); output out; input in; input clk_in /* synthesis syn_noclockbuf = 1 */; syn_probe module alu(out1, opcode, clk, a, b, sel, clk); output [7:0] out1; input [2:0] opcode; input [7:0] a, b; input clk, sel; reg [7:0] alu_tmp /* synthesis syn_probe=probe1 xc_loc="P20,P21,P22,P23,P24,P25,P26,P27" */;
directive应用实例(1)
syn_keep
directive应用实例(2)
syn_noprune
directive应用实例(3) syn_preserve
增量综合
步骤一
步骤二
ALTERA 增量INX增量综合布线(1)
XILINX增量综合布线(2)
attribute应用实例(5)
syn_pipeline `define lefta 7 `define leftb 7 module mult(r, a, b, preset, clk); output [`lefta+`leftb +1:0] r; input [`lefta:0] a; input [`leftb:0] b; input clk; input preset; reg [`lefta:0] a_aux; reg [`leftb:0] b_aux; reg [`lefta+`leftb+1:0] res /* synthesis syn_pipeline = 1 */; reg [`lefta+`leftb+1:0] res1 ; wire [`lefta+`leftb+1:0] res_out1 = a_aux * b_aux; wire [`lefta+`leftb+1:0] res_out2 = res ;