KAIST Signal integrity of TSV-based 3DIC
ASIC新思维:从2D到3D——TSV的挑战与未来
ASIC新思维：从2D到3D——TSV的挑战与未来
林崇铭
【期刊名称】《集成电路应用》
【年(卷),期】2012(000)007
【摘要】随着集成电路工艺从微米向纳米迈进，将平面IC往立体或三维发展的硅穿孔（TSV）技术应运而生。
在向3D发展进程中，2．5D技术以优越的性能和更低的成本可以满足当前设计要求。
【总页数】3页(P24-25,35)
【作者】林崇铭
【作者单位】SiP/3D IC专案处
【正文语种】中文
【相关文献】
1.关于Diophantine方程nx(x+d)(x+2d)(x+3d)=y(y+d)(y+2d)(Y+3d) 的一点注记 [J], 乐茂华
2.3D TSV测试的挑战和潜在解决方案 [J], Ben;Scott;Karen;Andy;Robert;Erik
3.关于不定方程x（x＋d）（x＋2d）（x＋3d）=P^2ky（y＋d）（y＋2d）（y ＋3d） [J], 郑惠
4.衣领纸型设计3D-2D转换的原理与方法——衣领结构数学模型和3D-2D转换的原理研究 [J], 张文斌;吴宇
5.《征途Ⅱ》年内推出2D力作挑战3D网游 [J], 无
因版权原因，仅展示原文概要，查看原文内容请购买。
0Through Silicon Via (TSV) Shielding Structures
Through Silicon Via (TSV) Shielding StructuresJonghyun Cho, Joohee Kim, Taigon Song, Jun So Pak,and Joungho KimDepartment of Electrical Engineering,KAISTDaejeon, South Koreajonghyun@eeinfo.kaist.ac.kr Hyungdong Lee, Junho Lee and Kunwoo ParkAdvanced Design TeamHynix Semiconductor Inc.Icheon-si, Gyeonggi-do, South KoreaAbstract— Three different shielding structures for noise coupling suppression between through silicon vias (TSVs) are proposed in this manuscript. These structures are modeled using the 3-dimensional transmission line matrix (3D-TLM) method, and the model is verified using EM-simulation. The shielding structures are analyzed with regard to consumption area, manufacturing process compatibility, and noise isolation levels in low, mid, and high frequency ranges. Each shielding structure has unique advantages and disadvantages, and selection of an appropriate shielding structure is needed for effective noise isolation.Keywords-through silicon via (TSV); noise coupling; TSV-TSV coupling;coupling suppression; shielding structure; guard ring; shielding TSVI.I NTRODUCTIONIn recent years, the use of through silicon via (TSV)-based 3-dimensional integrated circuits (3D-IC) has become an inevitable technical trend to simultaneously achieve low cost, high performance, and small form factor [1]. Although TSVs have several advantages over conventional bonding wire, such as increased I/O and short interconnection delays, they suffer from some drawbacks that are mainly due to the loss of the silicon substrate. TSV is a simple conductor via immersed in silicon substrate and an isolation layer is placed between conductor via and silicon substrate. The TSV isolation layer prevents TSV to be directly connected to the silicon substrate, which causes high DC loss through silicon substrate. However at high frequency, thin isolation layer has no effect, and TSV signal experiences high loss through a lossy silicon substrate. High loss in TSVs refers to a high noise coupling coefficient among signal TSVs through the lossy silicon substrate, which becomes a problem in TSV system. Normally, noise coupling through the silicon substrate causes several harmful effects in a system. It increases jitter and phase noise of clock signals, power ground noise, and the bit-error-rate of the RF system [2]. To prevent performance degradation due to substrate noise coupling, several shielding structures can be used as a solution. Guard rings and deep n-wells (DNW) are two well-known solutions in 2D-IC. However analysis of shielding structures for TSV-TSV noise coupling suppression has not been performed. The characteristics of different TSV shielding structures should be analyzed for the optimum choice of shielding structures.In this paper, we propose three types of shielding structures for TSV-TSV noise coupling suppression and model them using a 3-dimensional transmission line matrix (3D-TLM). The shielding structures are analyzed with regard to consumption area, isolation levels at different frequency ranges, and the compatibility of the manufacturing process. Additionally, the effects of TSV dimensions on each shielding structure are studied and a guideline for the appropriate choice of a shielding structure is proposed.II.M ODELING OF TSV S HIELDING S TRUCTURES We propose three types of TSV shielding structures for TSV-TSV coupling suppression – p+ guard ring, DNW guard ring, and shielding TSVs. The three structures are illustrated in Fig. 1.(a) (b) (c)Figure 1. Top view of the three shielding structures for TSV-TSV coupling suppression proposed in this paper (a) p+ guard ring (b) DNW guard ring (c)Shieldeding TSVsThe shielding structures are analyzed using modeling based on 3D-TLM, which uses lumped circuits. Using 3D-TLM, it is possible to model the depletion capacitor of the DNW, which cannot be modeled using EM-simulation. Also, the model facilitates the control of the effects of interconnections between ground TSVs, although this aspect is not of primary interest in our study. For the modeling using 3D-TLM methods, the entire TSVs and shielding structures are divided into several unit cells with equivalent lumped circuits as illustrated in Fig. 2 - TSV, silicon substrate, p+ contact, and DNW unit cells. A combination of these unit cells is used to model the structures in Fig. 1. Any arbitrary structure can be modeled using a combination of these unit cells if the structure is composed of these unit cells. It is the most powerful advantage of modeling using 3D-TLM. For TSV unit cells, the skin effect, which has a minor effect on TSV-TSV coupling, has been neglected but mutual inductance between TSVs has been considered. The DNW unit cell depletion capacitance, which is generated between the DNW and the p-silicon substrate, is represented as C dep in Fig. 2. Some of the equations for the lumped circuitsare listed below, and some are listed in the reference [3,4]. Here, r TSV , h TSV , N a , N d , n i , V well , and t DNW stand for the radius, height of TSV, doping concentration of substrate, DNW, and intrinsic silicon, DNW bias voltage, and DNW thickness,respectively.(a) (b)(c) (d)Figure 2. Equivalent circuit model of 3D-TLM unit cells for shielding structures. (a) TSV unit cell (b) silicon substrate unit cell (c) p+/pwell unit cell(d) DNW unit cellTSVh unith )TSV L(r 2πTSVμh 21TSV L =(1a)TSVh unit h )TSV L(p 2πTSVμh 21TSV M =(1b)Where 1hx h x 1x h x h ln L(x)2TSVTSV 2TSV TSV+÷÷øöççèæ-+÷÷÷øöçççèæ+÷÷øöççèæ+÷÷øöççèæ= ()()DNW unit well bi d a da si dep1t l V V N N 2N N qεC +×+=(2)Where ÷÷øöççèæ=2i da bi n N N ln q kT V The noise coupling coefficient between signal TSVs without any shielding structures are illustrated in Fig. 3. The proposed model and the 3D EM-simulation show excellent correlation, which verifies the model. The difference between near-end crosstalk (NEXT) and far-end crosstalk (FEXT) is due to mutual inductance between TSVs. NEXT is larger thanFEXT and the noise coupling coefficient used in the following sections is the NEXT.Figure 3. Noise coupling coefficient between signal TSVs of the proposed model and the 3D EM-simulation without any shielding structure. Here, the TSV diameter is 10 um, the TSV isolation layer thickness is 0.5 um, height is50 um, and the pitch between TSVs is 40 um.III. A NALYSIS OF TSV S HIEDLING S TRUCTURESAn analysis of the shielding structures for TSV-TSV noise-coupling suppression is described below using the 3D-TLM equivalent circuit model of the TSV, silicon substrate, p+ contact, and the DNW unit cell.A. The Principles of Shielding StructuresTo demonstrate the principles of shielding structures, three types of simplified circuits for each shielding structure are illustrated in Fig. 4 [5]. Here, the p+ guard ring and the shielding TSV are connected to ground, whereas the DNW guard ring is connected to power. The coupling noise is captured by these shielding structures and directly sent to ground, which decreases the noise coupling between signal TSVs. Shielding and coupling paths exist in this model, and the noise isolation level is determined as the ratio of impedance of these two paths.(a)(b)(c)Figure 4. Simplified circuit showing the principles of (a) p+ guard ring and(b) DNW guard ring (c) shielding TSVAt low frequency, the impedance of both shielding and coupling paths is determined by the TSV isolation capacitance. However, as the frequency increases, the effects of the TSV capacitance decrease and the effects of the silicon substrate impedance between the signal TSV and the shielding structure become more important. The effects are determined primarily by the shape and dimensions of the shielding structures. The noise coupling coefficient between signal TSVs with and without shielding structures is shown in Fig. 5.Figure 5. Noise coupling coefficient between signal TSVs with and withoutshielding structures.The p+ guard ring shows high noise isolation levels at low frequency, because it experiences only one TSV isolation capacitance at shielding path, but two TSV isolation capacitances at coupling path. However it shows almost no noise isolation at frequencies over 1 GHz because the p+ contact has a shallow depth (0.5 um in this case) compared to the TSV height of 50 um. The DNW guard ring has low noise isolation levels at low frequency and higher levels at high frequency due to its thickness. DNW is assumed to have a thickness of 5 um and a junction depth of 0.5 um between the DNW and the p-silicon substrate. At low frequency, the junction capacitance prevents the noise from being captured by the DNW guard ring, but as frequency increases, the effect of the junction capacitance is reduced, and the advantage of the thickness is visible in the noise isolation level. The junction depth between DNW and silicon substrate is dependent on doping profile, bias voltage, and temperature as listed in Eq. 2. The higher noise isolation of DNW guard ring over that of p+ guard ring can be shown from the lower frequency or higher frequency regarding these values. On the other hand, the noise isolation level increases with frequency for shielding TSVs. This is because the impedance of shielding path becomes low as frequency goes up due to TSV isolation capacitance. The consumption area and noise isolation level at 50 MHz, 1 GHz, and 10 GHz for different shielding structures are summarized in Table 1. Here, the consumption area is calculated by the surface area of shielding structures, and additional keep-away zone is not considered. The case of three shielding TSVs shows the highest noise isolation level, but it consumes the largest area among all the shielding structures.TABLE I. C OMPARISON OF D IFFERENT S HIELDING S TRUCTURES FORTSV-TSV N OISE C OUPLING S UPPRESSIONShielding StructuresGuard ringDNWguard ring1 ShieldingTSV3 ShieldingTSVs Isolationat 50MHz(dB)-5.22 -1.73 -2.74 -6.09 Isolationat 1GHz (dB)-0.72 -1.88 -3.17 -7.70 Isolationat 10GHz (dB)-0.26 -1.05 -5.45 -12.76 Consumptionarea (㎛2)52 52 95.0 285.1The time-domain coupled noise waveform is illustrated in Fig. 6. Even though the noise coupling coefficient is fixed, the coupling noise varies with the aggressor signal frequency, rise/fall time, and the termination scheme. In this case, a 1-GHz, 1-V pk-to-pk clock signal with a rise/fall time of 100 ps is inserted at the lower side of the TSV with source impedance of 500 Ω. The upper side of the TSV is terminated with a capacitance of 5 fF. The other port on the lower side of the TSV is terminated with a 500-Ω resistor and the port at the upper side of the TSV is terminated with a 5-fF capacitor, which represent the input and output drivers, respectively.Figure 6. TSV coupling noise with several shielding structures. A 1 V pk-to-pk,1 GHz clock signal with 100 ps rise/fall time is injected as the aggressor signal. The source impedance is 500 Ω and the output is terminated by a 5-fFcapacitor.With the help of three shielding TSVs, the peak-to-peak coupling noise is dramatically reduced from 132.8 mV to 32.4 mV. The p+ and the DNW guard ring show low coupling suppression effects due to the high frequency of the aggressor signal and the low noise-isolation level of the guard rings at high frequencies. Shielding TSVs has limited application dueto the minimum TSV space design rule while guard ring cannot be used for the package or interposer without active circuits. In practical situations, noise is coupled from several signal TSVs that are closely located to the victim TSV, and the coupling noise can be much larger. Therefore, more powerful and area-effective shielding structures are necessary.B.The Effects of TSV Dimensions on Shielding StrucutesDevelopments in the TSV manufacturing process tend to shrink TSV dimensions, which affects the noise isolation level and consumption area of each shielding structure. The effects of varying TSV heights on the noise isolation level are shown in Fig. 7.Figure 7. Noise isolation level of shielding structures at 1GHz with varyingTSV heights.Despite the developments in the TSV manufacturing process, the thickness of the p+ contact, the thickness of the DNW, and the depletion depth between the DNW and the p-silicon substrate remain unchanged, and the guard ring shows higher noise isolation levels with decreasing TSV height. On the other hand, the shielded TSV shows almost constant noise isolation levels despite variations in the TSV height. The noise isolation level is determined by the impedance ratio of the coupling and shielding paths shown in Fig. 4, and all of these values are proportional to the TSV height. Consequently, there is no difference in the noise isolation level with varying TSV heights.Figure 8. Noise isolation level per consumption area of shielding structures at 1 GHz when the TSV diameter and pitch vary and the TSV height is fixedat 50 umDevelopments in the TSV manufacturing process lead to decreases in the TSV diameter and pitch, which changes the noise isolation effects of each shielding structure. The noise isolation level per area is illustrated in Fig. 8. The noise isolation level itself is almost constant for shielding TSVs, but the consumption area per TSV decreases with decreasing TSV diameter. On the other hand, the noise isolation of the guard ring is not sensitive to variations in the TSV diameter and pitch and is mainly affected by TSV height as shown in Fig. 7. Therefore, it shows almost constant noise isolation level per unit area regardless of variations in the TSV diameter and pitch. Developments in the TSV manufacturing process have shrunk not only the TSV diameter and pitch, but also the TSV height, which increases noise isolation of guard ring. Therefore, appropriate choice of a shielding structure is needed for area-efficient shielding.IV.C ONCLUSIONTSVs are essential structures for a 3D integration system, but, noise coupling between signal TSVs through silicon substrate becomes a problem. For the suppression of noise coupling, three types of shielding structures are proposed in this manuscript. The p+ guard ring has high noise isolation levels at low frequency but almost no effect over 1 GHz. Because of its thick thickness, the DNW guard ring has a better isolation effect at high frequency than the p+ guard ring. Shielding TSVs show higher noise isolation levels with increases in frequency, making them a powerful solution for noise isolation at high frequency. However, the noise isolation level and the consumption area vary with the TSV dimensions. Selection of an appropriate shielding structure between the DNW guard ring and the shielding TSV is needed for effective noise isolation at high frequency.A CKNOWLEDGMENTThis work was supported by the IT R&D program of MKE/KEIT. [KI002134, Wafer Level 3D IC Design and Integration ]R EFERENCES[1]J. S. Pak, et.al., “Electrical Characterization of Through Silicon Via(TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation”, IEEE Electromagnetic Electronic Materials and Packaging, 2008.[2] A. Helmy, et.al., “The chip-A design guide for reducing substrate noisecoupling in RF Applications," IEEE Circuits and Devices Magazine, vol.22, no.5, pp.7-21, Sept.-Oct. 2006[3]J. Cho, et.al., " Active circuit to through silicon via (TSV) noisecoupling", IEEE Electrical Performance of Electronic Packaging and Systems, 2009.[4] D. A. Neamen, Semiconductor Physics and Devices Basic Principles.McGraw-Hill, 2003[5]J. S. Pak, et.al., "Slow wave and dielectric quasi-TEM modes of Metal-Insulator-Semiconductor (MIS) structure Through Silicon Via (TSV) in signal propagation and power delivery in 3D chip package," IEEE Electronic Components and Technology Conference, 2010。
一种基于机器学习的3D芯片信号耦合性分析系统及方法[发明专利]
![一种基于机器学习的3D芯片信号耦合性分析系统及方法[发明专利]](https://img.taocdn.com/s3/m/55a76516910ef12d2bf9e70b.png)
专利名称：一种基于机器学习的3D芯片信号耦合性分析系统及方法
专利类型：发明专利
发明人：张力,唐思瑶,施叶昕,李原
申请号：CN202010511973.7
申请日：20200608
公开号：CN111783376A
公开日：
20201016
专利内容由知识产权出版社提供
摘要：本发明公开了一种基于机器学习的3D芯片信号耦合性分析系统及方法，通过TSV通孔3D模型得到在不同的TSV通孔的半径、高度以及通孔之间的距离参数下的TSV通孔的S参数，并分别存入S2P文件；建立TSV通孔RLGC等效电路模型并根据S2P文件得到对应尺寸下的RLGC等效电路的电路参数；将TSV通孔的半径、高度以及通孔之间的距离参数作为BP神经网络的输入，RLGC等效电路的电路参数作为BP神经网络的输出，对BP神经网络进行训练，根据训练后的网络输出进行S参数仿真分析，分析结果即为对应尺寸下TSV通孔3D模型的传输特性。
本发明中的神经网络是采用实际模型仿真和优化结果作为训练集，对于不同情况电路性能的分析更为灵活，具有更高的准确性。
申请人：浙江大学
地址：310058 浙江省杭州市西湖区余杭塘路866号
国籍：CN
代理机构：杭州求是专利事务所有限公司
代理人：刘静
更多信息请下载全文后查看。
一种基于半圆形开口谐振环结构的太赫兹环偶极子超表面设计
一种基于半圆形开口谐振环结构的太赫兹环偶极子超表面设计王晨;王爽
【期刊名称】《应用物理》
【年(卷),期】2022(12)6
【摘要】设计了一种基于半圆形开口谐振环结构太赫兹环偶极子谐振的超表面,超表面的单元结构由金属结构层及基底介质组成。
金属结构层由一对对称半圆形开口谐振环和一个矩形金属条构成。
利用电磁仿真软件研究了半圆形半径r及开口距离d对超表面谐振频率、品质因子Q值等电磁特性的影响;通过计算超材料多极子的散射功率研究内部机理。
发现超表面的谐振响应随着半径和开口间距的改变而发生变化;该设计实现了一种新型太赫兹波段的平面环偶极子超表面,为太赫兹功能器件的开发和应用提供了更多的可能性。
【总页数】8页(P343-350)
【作者】王晨;王爽
【作者单位】天津职业技术师范大学电子工程学院
【正文语种】中文
【中图分类】G63
【相关文献】
1.矩形开口环结构的太赫兹环偶极子超材料设计
2.矩形开口环结构的太赫兹环偶极子超材料设计
3.基于双开口谐振环超表面的宽带太赫兹涡旋光束产生
4.太赫兹多
谐振环偶极子超表面中的类EIT效应5.太赫兹多谐振环偶极子超表面中的类EIT效应
因版权原因，仅展示原文概要，查看原文内容请购买。
TSV等效电路模型建立及分析
47科技资讯 SCIENCE & TECHNOLOGY INFORMATIONDOI：10.16661/ki.1672-3791.2104-5042-2226TSV等效电路模型建立及分析①付颜龙 王圆 赵晓宇(鄂尔多斯应用技术学院 内蒙古鄂尔多斯 017000)摘 要：硅通孔技术(TSV)是一种实现三维集成电路的方法。
为了加快三维集成电路的制造测试速度，必须对TSV结构精确建模。
该文提出了一种利用CAD工具提取TSV电路模型的方法。
通过三维全波模拟，可揭示常见的 TSV参数和故障对TSV电路模型的影响。
该文方法所提取的模型表明，衬底电导率对TSV故障的表征有较大的影响，相对较大的针洞不会改变TSV特征参数。
关键词：三维集成电路 参数提取 TSV分析 TSV故障中图分类号：TN40 文献标识码：A文章编号：1672-3791(2021)04(a)-0047-04Establishment and Analysis of TSV Equivalent Circuit ModelFU Yanlong WANG Yuan ZHAO Xiaoyu(Ordos Institute of Applied Technology, Ordos, Inner Mongolia Autonomous Region, 017000 China)Abstract : Through Silicon Via (TSV) is a technology for realizing three-dimensional integrated circuits. In order to speed up the manufacturing and testing speed of 3D integrated circuits, TSV must be accurately modeled. This paper presents a method to extract TSV circuit model using CAD tools. Through the three-dimensional full-wave simulation, the inf luence of common TSV parameters and faults on the TSV circuit model is revealed. The extracted model shows that the substrate conductivity has a greater impact on the characterization of TSV faults, and relatively large pinholes will not change the TSV characteristic parameters.Key Words : 3D integrated Circuit; Parameter Extraction; TSV Analysis; TSV Fault①基金项目：鄂尔多斯应用技术学院科研项目（项目编号：KyyB2017006）；鄂尔多斯应用技术学院教改项目资 助（项目编号：20190403）。
基于一维特异材料的微带漏波空间扫描天线
基于一维特异材料的微带漏波空间扫描天线
张冶文;李贵泉;赫丽;李宏强
【期刊名称】《同济大学学报（自然科学版）》
【年(卷),期】2007(035)006
【摘要】介绍了一种工作在基模状态下的微带漏波天线.这种天线基于传输线结构,其传播常数由负值增加到正值,显现出一种随频率增加而具有的由后向辐射变为前向辐射的特性.通过实验,验证了基于一维特异材料的微带漏波天线的这种特性.【总页数】4页(P811-814)
【作者】张冶文;李贵泉;赫丽;李宏强
【作者单位】同济大学,波耳固体物理研究所,上海,200092;同济大学,波耳固体物理研究所,上海,200092;同济大学,波耳固体物理研究所,上海,200092;同济大学,波耳固体物理研究所,上海,200092
【正文语种】中文
【中图分类】TN822
【相关文献】
1.毫米波宽带低旁瓣一维扫描相控阵天线分析设计 [J], 李成国;牟善祥;张忠传
2.基于LTCC超材料基板的小型化V波段毫米波微带天线设计 [J], 刘振哲;汪澎
3.复合左右手微带有源漏波阵列天线 [J], 李磊;张安学;魏晓勇
4.基于微带传输线的由特异材料构成的一维光子晶体 [J], 张利伟;张冶文;李海洋;赫丽;王治国
5.AT89S52多路电压控制器实现特异材料天线电扫描 [J], 刘西阁;樊元成;李宏强
因版权原因，仅展示原文概要，查看原文内容请购买。
硅通孔技术TSV研究ppt课件
GaAs 基TSV 20/03/2020
10μm 引脚间距
8μm厚 1.6μm
3.3μm
5
TSV的研究动态
概述
TSV应用市场预测
发展 状况
TSV的 应用
据法国调查公司Yole Development提供，到2015年，逻辑 和存储器方面的应用占TSV应用的比 例将大于30%，接触式图像传感器、 微机电系统，传感器占30%的市场， 存储器堆叠形成的动态随机存取存储
技术(电镀、化学气相沉积、高分子涂布等)； ➢ 工艺流程——先通孔(via first)或后通孔(via 1ast)技术； ➢ 堆叠形式——晶圆到晶圆、芯片到晶圆或芯片到芯片； ➢ 键合方式——直接Cu-Cu键合、粘接、直接熔合、焊接和
混合等； ➢ 超薄晶圆的处理——是否使用载体。
GaAs 基TSV 20/03/2020
TSV的 应用
GaAs 基TSV 20/03/2020
Samsung’s 32-memory stacking (each chip is 20μm thick)
17
概述
发展 状况
TSV的研究动态
2011年10月，意法半导体宣布将TSV技术引入MEMS 芯片量产，在其多款MEMS产品（智能传感器、多轴惯性 模块）内，TSV以垂直短线方式取代传统的芯片互连方法， 在尺寸更小的产品内实现更高的集成度和性能。
TSV技术的发展
ＴＳＶ技术的发展、挑战和展望，3D IC 技术的一体化、3D硅技术的一体化摘要：3D集成技术包括3D IC集成，3D IC封装和3D 硅集成技术。
这三者是不同的技术，并且硅通孔技术将3D IC封装技术与3D IC集成技术、3D IC硅集成技术区分开来，因为后二者使用了该技术而3D IC封装没有。
硅通孔技术（TSV）是3D IC集成技术、3D 硅集成技术的核心。
也是研究的热点。
3D集成技术起源于当代，当然，3D IC/硅集成技术的革新、挑战与展望已是讨论的热点，还有它的蓝图。
最后，通用的、更低能耗的、加强热控制的3D IC集成封装系统相继被提出。
关键词：硅通孔技术，3D IC集成技术，3D 硅集成技术，活泼的、消极的互边导电物，C2W和W2W。
说明：电子产业自从1996年以来已成为世界上最大的产业。
截止2011年底已经创造了一万五千亿美元的价值。
其中电子工业最大的发明便是电子管（1947年），这也使得John Bardeen,Walter Brattain 和William赢得了1956年的诺贝尔物理学奖。
1958年Jack Kilby发明了集成电路（也使他获得了诺贝尔奖），六个月后Robert Noyce(他因在1990年去世而未能与Jack kilby分享诺贝尔奖)首创IC集成技术。
由戈登·摩尔在1965年提出的每二年便要在电路板上将晶体管的数量翻一倍的理论（也叫摩尔定律，为了更低的能耗），在过去的46年中已成为发展微电子产业最有力的指导。
这条定律强调可以通过单片集成系统（SOC）将平面技术和所有功能的集成（在2D层面）放到单片芯片中。
另一方面，这里所有功能的集成能通过3D集成技术例如3D IC封装,3D IC 集成［1］，［2］，［4］-［143］，［168］-［201］和3D 硅集成［1］，［2］，［144］－［167］，［168］－［201］得到实现，这些都会在1、2小节中提及。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Density
Æ Achieving the highest capacity / volume ratio
Source: “3D 3D IC & TSV Report” Report , Yole Development
Terahertz Interconnection and Package Laboratory
Electrical performance
Æ Interconnect speed and reduced parasitic power consumption
Logic
3D vs. “More Moore”
Æ Can 3D be cheaper than going to the next lithography node?
Signal Integrity II: Crosstalk & Jitter 3D IC using g TSV (Through Silicon Via)
0 S21(Phase) [Degree] -10 -20 -30 -40
()
Cvia_ox Cvia_ox Csil Cox
Solid line = model Symbol line = measurement 0.1 1 Frequency [GHz] 10 20
2000
Time
2010
Relative comparison of I/O densities for 3D silicon, 3D die stacking, and silicon packaging, for both ceramic and organic packaging
Terahertz Interconnection and Package Laboratory
• Bonding Wire located in Chip Perimeter
Æ Low Density Chip Wiring Æ Limited Number of I/O Æ Limited I/O Pitch Æ Large Area Package
3D Stacked Chip Package with Wire Bonding
Terahertz Interconnection and Package Laboratory
TERA
Terahertz Interconnection and Package Laboratory
1
Contents
1) 2) 3) 4) 5)
Driving Forces of 3D Package and IC Signal Integrity Design N i C Noise Coupling li Issues I Noise Isolations Summary
3rd Chip (Thinned Substrate) Under fill Dielectric 2nd Chip (Thinned Substrate) Dielectric Under fill Multi-level On-chip On chip Interconnect 1st Chip SiO2 Si-Substrate
* ref: f IBM J J. RES RES. & DEV. DEV VOL. VOL 52 NO.6 NO 6 NOVEMBER 2008, 2008 p555
3D-IC integration
I/O: 0.4 - 10.0μm pitch 105 – 108 I/O per cm2 Wiring pitch: 45nm
• Complex Interposer
Æ Long Redistribution Interconnection Æ Bonding Wire located in Interposer Periphery
Terahertz Interconnection and Package Laboratory
TERA
- Vertical Die-to-Die Die to Die EMI Coupling - RF Sensitivity Reduction by EMI - EM Radiation Increase
- Simultaneous Switching Noise caused by Insufficient Power - High freq Noise Coupling & Transfer
TERA
Terahertz Interconnection and Package Laboratory
4
16GB Samsung NAND Flash, 8Gbx16
Terahertz Interconnection and Package Laboratory
TERA
Terahertz Interconnection and Package 5 Sharp, Laboratory Morihiro Kada
TERA
Terahertz Interconnection and Package Laboratory
7
Technology Trend of 3D IC
Relati ive wiring p pitch, I/O pitch, and I/O in nterconnect tion density ranges (I/O O per cm2)
DRAM MEMS
3D IC
Optimum Market Access Conditions
RFSiP
Flash Cost Æ “Long Long term term” driven
driver: > 2012
CIS
(NAND & NOR)
Form factor driven
Æ “Short term” driver: > 2008
TERA
Terahertz Interconnection and Package Laboratory
3
3D Housings
Sk L Sky Lounge
Apartment
Medical care center Restaurant Fitness & Spa Parking
Terahertz Interconnection and Package Laboratory
CIS Logic Analog DRAM RF - Crosstalk Between TSVs - Die-to-Die Vertical Coupling - Jitter by Inter-Symbol-Interference
- Limitation of High Speed Signaling by Capacitive Loading - Impedance Mismatching, Reflection
TERA
Terahertz Interconnection and Package Laboratory 11
11
Key Technology : TSV (Through Silicon Via)
• Short Interconnection
Æ Reduced RC Delays Æ Low Impedance for Power Distribution Network Æ Low Power Consumption Æ Heat Dissipation Through Via
Terahertz Interconnection and Package Laboratory
TERA
Terahertz Interconnection and Package Laboratory
2
3D Movie
Terahertz Interconnection and Package Laboratory
IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC
July 21, 21 2010 Joungho Kim at KAIST joungho@ee.kaist.ac.kr joungho@ee kaist ac kr http://tera.kaist.ac.kr
3D Hamburger
SDRAM
Di it l Core Digital C
RF
Analog
Terahertz Interconnection and Package Laboratory
TERA
Terahertz Interconnection and Package Laboratory 6
TERA
Terahertz Interconnection and Package Laboratory
8
Core Technologies of 3D IC
Substrate Via Ball PCB Attachment TSV
Unified Design/CAD Environment and Test 3D Thermal & Reliability Analysis And Design Methodologies Chip & SoC Architecture and Design Methodologies
Si-on-Si package p stacking g and chip
I/O: 10-50μm pitch 103 - 106 I/O per cm2 Wiring pitch: 0.5μm
Organic and cerami00 200-μm pitch 102 - 103 I/O per cm2 Wiring pitch: 25 - 200μm