SIA519EDJ-T1-GE3;中文规格书,Datasheet资料
SUD19P06-60-GE3;SUD19P06-60-E3;中文规格书,Datasheet资料
VDS - Drain-to-Source Voltage (V)
Qg - Total Gate Charge (nC)
Capacitance
Gate Charge
Document Number: 69253 S11-2132 Rev. B, 31-Oct-11 This document is subject to change without notice.
SUD19P06-60
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
30 VGS = 10 thru 5 V 25 ID - Drain Current (A) 4V ID - Drain Current (A) 25 30
3
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?91000 /
• High Side Switch for Full Bridge Converter • DC/DC Converter for LCD Display
TO-252
S
G Drain Connected to Tab G D S D P-Channel MOSFET
Top View Ordering Information: SUD19P06-60-E3 (Lead (Pb)-free) SUD19P06-60-GE3 (Lead (Pb)-free and Halogen free)
FEATURES
• Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % UIS Tested
SI2301CDS-T1-GE3中文资料
Vishay SiliconixSi2301CDSP-Channel 20-V (D-S) MOSFET FEATURES•Halogen-free Option Available•TrenchFET ® Power MOSFETAPPLICATIONS •Load SwitchMOSFET PRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)a Q g (Typ.)- 200.112 at V GS = - 4.5 V - 3.1 3.3 nC0.142 at V GS = - 2.5 V- 2.7Notes:a. Based on T C = 25 °C.b. Surface Mounted on 1" x 1" FR4 board.c. t = 5 s.d. Maximum under Steady State conditions is 175 °C/W.ABSOLUTE MAXIMUM RATINGS T A = 25°C, unless otherwise notedParameter Symbol Limit U nitDrain-Source Voltage V DS - 20VGate-Source Voltage V GS ± 8Continuous Drain Current (T J = 150 °C)T C = 25 °C I D- 3.1A T C = 70 °C - 2.5T A = 25 °C - 2.3b, c T A = 70 °C - 1.8b, cPulsed Drain Current I DM - 10Continuous Source-Drain Diode CurrentT C = 25 °C I S - 1.3T A = 25 °C - 0.72b, c Maximum Power Dissipation T C = 25 °C P D 1.6WT C = 70 °C 1.0T A = 25 °C 0.86b, c T A = 70 °C 0.55b, cOperating Junction and Storage T emperature Range T J , T stg - 55 to 150°C THERMAL RESISTANCE RATINGSParameter Symbol Typical Maximum UnitMaximum Junction-to-Ambient b, d ≤ 5 s R thJA 120145°C/WMaximum Junction-to-Foot (Drain)Steady State R thJF 6278Vishay SiliconixSi2301CDSNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.MOSFET SPECIFICATIONS T J = 25°C, unless otherwise notedParameter Symbol Test Conditions Min.Typ.Max.U nit StaticDrain-Source Breakdown Voltage V DS V DS = 0 V, I D = - 250 µA- 20VV DS Temperature Coefficient ΔV DS /T J I D = - 250 µA - 18mV/°C V GS(th) T emperature Coefficient ΔV GS(th)/T J 2.2Gate-Source Threshold Voltage V GS(th) V DS = V GS , I D = - 250 µA - 0.4- 1V Gate-Source LeakageI GSS V DS = 0 V , V GS = ± 8 V ± 100nA Zero Gate Voltage Drain Current I DSS V DS = - 20 V , V GS = 0 V - 1µA V DS = - 20 V, V GS = 0 V , T J = 55 °C- 10On-State Drain Current aI D(on) V DS ≤ - 5 V , V GS = - 4.5 V - 6A Drain-Source On-State Resistance aR DS(on) V GS = - 4.5 V, I D = - 2.8 A 0.0900.112ΩV GS = - 2.5 V, I D = - 2.0 A 0.1100.142Forward T ransconductance a g fsV DS = - 5 V , I D = - 2.8 A2.0SDynamic bInput Capacitance C iss V DS = - 10 V , V GS = 0 V , f = 1 MHz405pFOutput CapacitanceC oss 75Reverse Transfer Capacitance C rss 55Total Gate Charge Q g V DS = - 10 V , V GS = - 4.5 V , ID = - 3 A 5.510nC V DS = - 10 V , V GS = - 2.5 V , I D = - 3 A 3.36Gate-Source Charge Q gs 0.7Gate-Drain Charge Q gd 1.3Gate Resistance R g f = 1 MHz6.0ΩTurn-On Delay Time t d(on) V DD = - 10 V, R L = 10 ΩI D = - 1 A, V GEN = - 4.5 V , R G = 1 Ω1120ns Rise Timet r 3560Turn-Off Delay Time t d(off) 3050Fall Timet f1020Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 °C- 1.3A Pulse Diode Forward Current a I SM - 10Body Diode VoltageV SD I S = - 0.7 A- 0.8- 1.2V Body Diode Reverse Recovery Time t rr I F = - 3.0 A, dI/dt = 100 A/µs, T J = 25 °C3050ns Body Diode Reverse Recovery Charge Q rr 2550nC Reverse Recovery Fall Time t a 15nsReverse Recovery Rise Timet b15Output CharacteristicsOn-Resistance vs. Drain Current and Gate VoltageTransfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureThreshold VoltageSingle Pulse PowerVishay SiliconixSi2301CDSTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?68741.Normalized Thermal Transient Impedance, Junction-to-FootDisclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。
SIC762CD-T1-GE3;中文规格书,Datasheet资料
Integrated DrMOS Power StageDESCRIPTIONThe SiC762CD is an integrated solution that contains PWM optimized n-channel MOSFETs (high side and low side) and a full featured MOSFET driver IC. The device complies with the Intel DrMOS standard for desktop and server V core power stages. The SiC762CD delivers up to 35 A continuous output current and operates from an input voltage range of 3 V to 27 V. The integrated MOSFETs are optimized for output voltages in the ranges of 0.8 V to 2.0 V with a nominal input voltage of 24 V. The device can also deliver very high power at 5 V output for ASIC applications.The SiC762CD incorporates an advanced MOSFET gate driver IC. This IC accepts a single PWM input from the V R controller and converts it into the high side and low side MOSFET gate drive signals. The driver IC is designed to implement the skip mode (SMOD) function for light load efficiency improvement. Adaptive dead time control also works to improve efficiency at all load points. The SiC762CD has a thermal warning (THDN) that alerts the system of excessive junction temperature. The driver IC includes an enable pin, UVLO and shoot through protection.The SiC762CD is optimized for high frequency buck applications. Operating frequencies in excess of 1 MHz can easily be achieved.The SiC762CD is packaged in Vishay Siliconix high performance PowerP AK MLP6 x 6 package. Compact co-packaging of components helps to reduce stray inductance, and hence increases efficiency. •FEATURES•Integrated Gen III MOSFETs and DrMOScompliant gate driver IC•Enables V core switching at 1 MHz•Easily achieve > 90 % efficiency in multi-phase, low output voltage solutions•Low ringing on the VSWH pin reduces EMI•Pin compatible with DrMOS 6 x 6 version 3.0•Tri-state PWM input function prevents negative output voltage swing• 5 V logic levels on PWM•MOSFET threshold voltage optimized for 5 V driver bias supply•Automatic skip mode operation (SMOD) for light load efficiency•Under-voltage lockout•Built-in bootstrap schottky diode•Adaptive deadtime and shoot through protection •Thermal shutdown warning flag•Low profile, thermally enhanced PowerPAK® MLP 6 x 640 pin package•Halogen-free according to IEC 61249-2-21 definition •Compliant to RoHS directive 2002/95/ECAPPLICATIONS•CPU and GPU core voltage regulation•Server, computer, workstation, game console, graphics boards, PCSIC762CD APPLICATION DIAGRAMMa.T A = 25 °C and all voltages referenced to P GND = C GND unless otherwise noted.Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.Note:a.Recommended operating conditions are specified over the entire temperature range, and all voltages referenced to P GND = C GND unless otherwise noted.ORDERING INFORMATIONPart Number Package SiC762CD-T1-GE3PowerPAK MLP66-40SiC762DBReference boardRECOMMENDED OPERATING CONDITIONSParameter Symbol Min.Typ.Max.UnitInput Voltage V IN 3.01224VControl Input Voltage V CIN 4.5 5.5Drive Input Voltage V DRV 4.55.5Switch NodeV SW_DC1224THERMAL RESISTANCE RATINGSParameterSymbol Typ.Max.Unit Maximum Power Dissipation at T PCB = 25 °C P D_25C 25W Maximum Power Dissipation at T PCB = 100 °C P D_100C 10Thermal Resistance from Junction to T op R th_J_TOP 15°C/WThermal Resistance from Junction to PCBR th_J_PCB5Notes:a.Typical limits are established by characterization and are not production tested.b.Guaranteed by design.ELECTRICAL SPECIFICATIONSParameter Symbol Test Conditions Unless SpecifiedV DSBL# = V SMOD = 5 V ,V IN = 12 V , V VDRV = V VCIN = 5 V ,T A = 25 °C Min.Typ.a Max.UnitPower SuppliesV CIN Control Input Current I VCIN V DSBL# = 0 V , no switching21µAV DSBL# = 5 V , no switching 350V DSBL# = 5 V , f s = 300 kHz, D = 0.1500Drive Input Current (Dynamic)I VDRV f s = 300 kHz, D = 0.11418mAf s = 1000 kHz, D = 0.14054Bootstrap SupplyBootstrap Switch Forward Voltage V BS Diode V VCIN = 5 V, forward bias current 2 mA0.600.75VControl Inputs (PWM, DSBL#, SMOD)PWM Rising Threshold V th_pwm_r 3.5 3.9 4.2VPWM Falling Threshold V th_pwm_f 0.8 1.0 1.2PWM T ristate Rising Threshold V th_tri_r 0.9 1.3 1.8PWM T ristate Falling ThresholdV th_tri_f 3.43.74.0PWM T ristate Rising Threshold Hysteresis V hys_tri_r 280mV PWM T ristate Falling Threshold Hysteresis V hys_tri_f 180T ristate Hold-Off Time b t TSHO 150ns PWM Input CurrentI PWM V PWM = 5 V 250µA V PWM = 0 V - 250SMOD, DSBL# Logic Input Voltage V LOGIC_LH Rising (low to high) 2.0V V LOGIC_LH Falling (high to low)0.8Pull Down Impedance R THDN 5 k Ω resistor pull-up to V CIN40ΩTHDN Output Low V THDNL0.04V ProtectionThermal Warning Flag Set 150°CThermal Warning Flag Clear 135Thermal Warning Flag Hysteresis 15Under Voltage Lockout V CIN V UVLO Rising, on threshold 3.3 3.9V Under Voltage Lockout V CINFalling, off threshold 2.32.95Under Voltage Lockout Hysteresis V CIN V UVLO_HYST 400mV High Side Gate Discharge ResistorbR HS_DSCRGV VDRV = V VCIN = 0 V; V IN = 12 V20.2k ΩNote:a. Min. and Max. are not 100 % production tested.TIMING DEFINITIONSNote:GH is referenced to the high side source. GL is referenced to the low side source.TIMING SPECIFICATIONSParameter Symbol Test Conditions Unless Specified V VDRV = V VCIN = V DSBL# = 5 V ,V VIN = 12 V , T A = 25 °C Min. Typ.Max.UnitTurn Off Propagation DelayHigh Side at d_off_HS 25 % of PWM to 90 % of GH102035nsRise Time High Side t r_HS 10 % to 90 % of GH 10Fall Time High Side t f_HS 90 % to 10 % of GH 8Turn Off Propagation Delay Low Side at d_off_LS 75 % of PWM to 90 % of GL103745Rise Time Low Side t r_LS 10 % to 90 % of GL 6Fall Time Low Side t f_LS 90 % to 10 % of GL 5Dead Time Rising t dead_on 10 % of GL to 10 % of GH 27Dead Time Fallingt dead_off10 % of GH to 10 % of GL19Region DefinitionSymbol 1T urn off propagation delay LSt d_off_LS 2Fall time LS t f_LS 3Dead time rising t dead_on 4Rise time HSt r_HS 5T urn off propagation delay HSt d_off_HS 6Fall time HS t f_HS 7Dead time falling t dead_off 8Rise time LSt r_LSP W MGHGLS W1234 567810%90%10%90%75%25%SIC762CD BLOCK DIAGRAMDETAILED OPERATIONAL DESCRIPTIONPWM Input with Tristate FunctionThe PWM input receives the PWM control signal from the V R controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate Tristate logic (H, L and Tristate) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above V th_pwm_r the low side is turned off and the high side is turned on. When PWM input is driven below V th_pwm_f the high side turns off and the Low side turns on. For Tristate logic, the PWM input operates as above for driving the MOSFETs.However, there is an third state that is entered into as the PWM output of Tristate compatible controller enters its high impedance state during shut-down. The high impedance state of the controller's PWM output allows the SiC762CD to pull the PWM input into the Tristate region (see the Tristate Voltage Threshold Diagram below). If the PWM input stays in this region for the Tristate Hold-Off Period, t TSHO , both high side and low side MOSFETs are turned off. This function allows the V R phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and Tristate regions are separated by hysteresis to prevent false triggering. The SiC762CD incorporates PWM voltage thresholds that are compatible with 5 V logic.Disable (DSBL#)In the low state, the DSBL# pin shuts down the driver IC and disables both high-side and low-side MOSFET. In this state,the standby current is minimized. If DSBL# is left unconnected an internal pull-down resistor will pull the pin Diode Emulation Mode (SMOD) Skip ModeWhen SMOD pin is low the diode emulation mode is enabled.This is a non-synchronous conversion mode that improves light load efficiency by reducing switching losses. Conducted losses that occur in synchronous buck regulators when inductor current is negative are also reduced. Circuitry in the gate drive IC detects when inductor current crosses zero and automatically stops switching the low side MOSFET. See SMOD Operation Diagram for additional details. This function can also be used for a pre-biased output voltage. If SMOD is left unconnected, an internal pull up resistor will pull the pin up to V CIN (Logic High) to disable the diode emulation function.Thermal Shutdown Warning (THDN)The THDN pin is an open drain signal that flags the presence of excessive junction temperature. Connect a maximum of 20 k Ω to pull this pin up to V CIN . An internal temperature sensor detects the junction temperature. The temperature threshold is 150 °C. When this junction temperature is exceeded the THDN flag is set. When the junction temperature drops below 135 °C the device will clear the THDN signal. The SiC762CD does not stop operation when the flag is set. The decision to shutdown must be made by an external thermal control function.Voltage Input (V IN )This is the power input to the drain of the high-side Power MOSFET. This pin is connected to the high power intermediate BUS rail.Switch Node (V SWH and PHASE)The Switch node V SWH is the circuit PWM regulated output.Figure 2U V LOV DR VGHGLC G N DP G N DV S W HBOOTV I N V CI NP W MDSBL#THD NSMOD Thermal W arningT ristate P W MAST C N TL DCM DETECTPHASEregulated high output for the buck converter. The PHASE pin is internally connected to the switch node V SWH . This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20.2 k Ω resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that V CIN goes to zero while V IN is still applied.Ground connections (C GND and P GND )P GND (power ground) should be externally connected to C GND (control signal ground). The layout of the Printed Circuit Board should be such that the inductance separating the C GND and P GND should be a minimum. Transient differences due to inductance effects between these two pins should not exceed 0.5 V.Control and Drive Supply Voltage Input (V DRV ,V CIN )V CIN is the bias supply for the gate drive control IC. V DRV is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC.Bootstrap Circuit (BOOT)The internal bootstrap switch and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin.Shoot-Through Protection and Adaptive Dead Time (AST)The SiC762CD has an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFET are not turned on the same time. The adaptive dead time control operates as follows. When PWM input goes high the LS gate starts to go low after a few ns. When this signal crosses through 1.7 V the logic to switch the HS gate on is activated. When PWM goes low the HS gate goes low. When the HS gate-to-source drive signal crosses through 1.7 V the logic to turn on the LS gate is activated.This feature helps to adjust dead time as gate transitions change with respect to output current and temperature.Under Voltage Lockout (UVLO)During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC762CD also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20.2 k Ω resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET.TRISTATE PWM VOLTAGE THRESHOLD DIAGRAMDEVICE TRUTH TABLEDSBL#SMOD PWM GH GL Open X X L L L X X L L H L L L H (I L > 0), L (I L ≤ 0)H L H H L H H H H L HHLLHFigure 3V th_tri_f V th_p w m_r V th_tri_rV th_p w m_fP W MGHGL t TSHOt TSHOSMOD OPERATION DIAGRAMPIN CONFIGURATIONFigure 4DSBLSMODP W MGHGLV S WI L > 0I L = 0t d(O N)t d(OFF)Figure 5 - PowerPAK MLP 6 x 6 40P Pin Out - Top ViewV I NP2A G N DP1V S W HP330V S W H29V S W H28 P G N D27 P G N D26 P G N D25 P G N D24 P G N D23 P G N D22 P G N D21 P G N D4PWM39DSBL#38THDN37CGND36GL35VSWH34VSWH33VSWH32VSWH31VSWHSMOD 1V CI N 2V DR V 3BOOT 4C G ND 5GH 6PHASE 7V I N8V I N 9V I N 1020 PGND19 PGND18PGND17 PGND16 PGND15VSWH14VIN13VIN12VIN11VINPIN DESCRIPTIONPin Number Symbol Description1SMOD Disable low side gate operation. Active low.2V CIN This will be the bias supply input for control IC (5 V).3V DRV IC bias supply and gate drive supply voltage (5 V).4BOOT High side driver bootstrap voltage pin for external bootstrap capacitor.5, 37, PAD1C GND Control signal ground. It should be connected to P GND externally. All pins internally connected.6GH Gate signal output pin for high side MOSFET. Pin for monitoring.7PHASE Return pin for the HS bootstrap capacitor. Connect a 0.1 µF ceramic capacitor from this pin to the boot pin (4).8 to 14, PAD2V IN Input voltage for power stage. It is the drain of the high-side MOSFET.15, 29 to 35,PAD3VSWHIt is the phase node between high side MOSFET source and low side MOSFET drain. It should be connected to an output inductor. All pins internally connected.16 to 28P GND Power ground.36GL Gate signal output pin for low side MOSFET. Pin for monitoring.38THDN Thermal shutdown open drain output. Use a 10K pull up resistor to V CIN.39DSBL#Disable pin. Active low.ELECTRICAL CHARACTERISTICSI CIN (mA) vs. Temperature at Frequency = 300 kHzD = 10 %, V CIN = V DRV = 5 VPWM Falling Threshold (V) vs. Temperature (°C)V CIN = V DRV = 5 VDSBL Falling Threshold (V) vs. Temperature (°C)I DRV (mA) vs. Temperature at Frequency = 300 kHzD = 10 %, V CIN = V DRV = 5 VPWM Rising Threshold (V) vs. Temperature (°C)V CIN = V DRV = 5 VDSBL Rising Threshold (V) vs. Temperature (°C)ELECTRICAL CHARACTERISTICSSMOD Falling Threshold (V) vs. Temperature (°C)V CIN = V DRV = 5 VI CIN + I DRV (mA) vs. Temperature at Frequency = 1 MHzD = 10 %, V CIN = V DRV = 5 VPWM Falling Tristate (V) vs. Temperature (°C)SMOD Rising Threshold (V) vs. Temperature (°C)V CIN = V DRV = 5 VI DRV (mA) vs. Temperature at Frequency = 1 MHzD = 10 %, V CIN = V DRV = 5 VPWM Rising Tristate Threshold (V) vs. Temperature (°C)ELECTRICAL CHARACTERISTICSCINSMOD Falling Threshold vs. V CINPWM Falling Threshold vs. VCINSMOD Rising Threshold vs. V CINPWM Rising Threshold vs. V分销商库存信息: VISHAYSIC762CD-T1-GE3。
SI7116DN-T1-GE3;中文规格书,Datasheet资料
Vishay SiliconixSi7116DNN-Channel 40-V (D-S) Fast Switching MOSFETFEATURES•Halogen-free Option Available •TrenchFET ® Power MOSFET•New Low Thermal Resistance PowerPAK ®Package with Low 1.07 mm Profile •PWM Optimized •100 % R g TestedAPPLICATIONS•Synchronous Rectification •Intermediate Switch •Synchronous BuckPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)Q g (Typ.)400.0078 at V GS = 10 V 16.415 nC0.010 at V GS = 4.5 V14.5Notes:a.Surface Mounted on 1" x 1" FR4 board.b.See Solder Profile (/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.c.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameterSymbol 10 sSteady StateUnit Drain-Source Voltage V DS 40VGate-Source VoltageV GS ± 20Continuous Drain Current (T J = 150 °C)a T A = 25 °C I D16.410.5AT A = 70 °C13.18.4Pulsed Drain CurrentI DM 60Continuous Source Current (Diode Conduction)a I S 3.21.3Avalanche Current L = 0 1 mH I AS 15Avalanche EnergyE AS 11mJ Maximum Power Dissipation aT A = 25 °C P D 3.8 1.5W T A = 70 °C 2.00.8Operating Junction and Storage T emperature Range T J , T stg- 55 to 150°CSoldering Recommendations (Peak Temperature)b, c260THERMAL RESISTANCE RATINGSParameter Symbol T ypical Maximum UnitMaximum Junction-to-Ambient a t ≤ 10 s R thJA 2433°C/WSteady State 6581Maximum Junction-to-Case (Drain)Steady StateR thJC1.92.4Vishay SiliconixSi7116DNNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.MOSFET SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol T est Conditions Min.T yp.Max.UnitStaticGate Threshold Voltage V GS(th) V DS = V GS , I D = 250 µA 1.52.5VGate-Body LeakageI GSS V DS = 0 V , V GS = ± 20 V ± 100 nAZero Gate Voltage Drain Current I DSS V DS = 40 V , V GS = 0 V 1µA V DS = 40 V, V GS = 0 V , T J = 55 °C5On-State Drain Current aI D(on) V DS ≥ 5 V , V GS = 10 V 40A Drain-Source On-State Resistance a R DS(on) V GS = 10 V , I D = 16.4 A 0.00650.0078ΩV GS = 4.5 V, I D = 14.5 A 0.00830.010Forward T ransconductance a g fs V DS = 15 V , I D = 16.4 A 68S Diode Forward Voltage a V SDI S = 3.2 A, V GS = 0 V0.81.2VDynamic bTotal Gate Charge Q g V DS = 20 V , V GS = 4.5 V , I D = 16.4 A1523nCGate-Source Charge Q gs 6.7Gate-Drain Charge Q gd 5.1Gate Resistance R g f = 1 MHz0.71.42.1ΩTurn-On Delay Time t d(on) V DD = 20 V , R L = 20 ΩI D ≅ 1 A, V GEN = 10 V , R g = 6 Ω1015ns Rise Timet r 1015Turn-Off Delay Time t d(off) 3655Fall Timet f 1015Source-Drain Reverse Recovery Time t rr I F = 3.2 A, di/dt = 100 A/µs 3060Body Diode Reverse Recovery ChargeQ rrI F = 3.2 A, di/dt = 100 A/µs 2652nc Output Characteristics Transfer CharacteristicsVishay SiliconixSi7116DNTYPICAL CHARACTERISTICS 25°C, unless otherwise notedGate ChargeSource-Drain Diode Forward VoltageCapacitanceOn-Resistance vs. Gate-to-Source VoltageSafe Operating AreaVishay SiliconixSi7116DNTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Sil iconix maintains worl dwide manufacturing capabil ity. Products may be manufactured at one of several qual ified l ocations. Rel iabil ity data for Sil icon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?73139.Normalized Thermal Transient Impedance, Junction-to-CaseVishay SiliconixAN822PowerPAK ® 1212 Mounting and Thermal ConsiderationsJohnson ZhaoMOSFETs for switching applications are now available with die on resistances around 1 m Ω and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this,mounting information is presented. Finally, thermal and electrical performance is discussed.THE PowerPAK PACKAGEThe PowerPAK 1212-8 package (Figure 1) is a deriva-tive of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resis-tance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance.(Please refer to application note “PowerPAK SO-8Mounting and Thermal Considerations.”)The PowerPAK 1212-8 has a footprint area compara-ble to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger pack-ages are typically required solely for thermal consider-ation, the PowerPAK 1212-8 is a good option.Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8.The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints.PowerPAK 1212 SINGLE MOUNTINGTo take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document.In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack,experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve-ment in thermal performance.Figure 1.PowerPAK 1212 DevicesVishay SiliconixAN822PowerPAK 1212 DUALTo take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK 1212-8 dual in the index of this doc-ument.The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the Pow-erPAK 1212-8 dual package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack,experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve-ment in thermal performance.REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humid-ity, HAST, or pressure pot. The solder reflow tempera-ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see /doc?73257.Ramp-Up Rate+ 6°C /Second Maximum Temperature at 155 ± 15 °C 120 Seconds Maximum Temperature Above 180 °C 70 - 180 Seconds Maximum T emperature240 + 5/- 0 °CTime at Maximum T emperature 20 - 40 Seconds Ramp-Down Rate+ 6 °C/Second MaximumFigure 2. Solder Reflow Temperature ProfileFigure 3.Solder Reflow Temperatures and Time DurationsVishay SiliconixAN822THERMAL PERFORMANCE IntroductionA basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R θjc, or the junction to- foot thermal resistance, R θjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8,standard TSSOP-8 and SO-8 equivalent steady state performance.By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the tempera-ture of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junc-tion-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the Pow-erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the Power-PAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on r DS(ON) whereas a rise of over 40 °C will cause an increase in r DS(ON) as high as 20 %.Spreading CopperDesigners add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper.Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-nal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many appli-cations. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement.A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No signif-icant effect was observed.TABLE 1: EQIVALENT STEADY STATE PERFORMANCEPackage SO-8TSSOP-8TSOP-8PPAK 1212PPAK SO-8ConfigurationSingleDual Single Dual Single Dual Single Dual Single Dual Thermal Resiatance R thJC (C/W)2040528340902.45.51.85.5Figure 4. Temperature of Devices on a PC BoardVishay SiliconixAN822CONCLUSIONSAs a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal perfor-mance while having a footprint that is more than 40 %smaller than the standard TSSOP-8.Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package.The PowerPAK 1212-8 combines small size with attrac-tive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps r DS(ON) low, and permits the device to handle more current than a same- or larger-size MOS-FET die in the standard TSSOP-8 or SO-8 packages.Figure 5. Spreading Copper - Si7401DNFigure 6. Spreading Copper - Junction-to-Ambient Performance分销商库存信息: VISHAYSI7116DN-T1-GE3。
SI4459ADY-T1-GE3;中文规格书,Datasheet资料
3600
1800 Crss
Coss
0.003 0 14 28 42 ID - Drain Current (A) 56 70
0 0 6 12 18 24 VDS - Drain-to-Source Voltage (V) 30
A
mJ
Maximum Power Dissipation
PD
W
Operating Junction and Storage Temperature Range
TJ, Tstg
°C
THERMAL RESISTANCE RATINGS
Parameter Maximum Junction-to-Ambienta, c Maximum Junction-to-Foot Notes: a. Surface mounted on 1" x 1" FR4 board. b. t = 10 s. c. Maximum under steady state conditions is 80 °C/W. d. Based on TC = 25 °C. Document Number: 69979 S11-1813-Rev. B, 12-Sep-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?91000 / 1 t 10 s Steady State Symbol RthJA RthJF Typical 29 13 Maximum 35 16 Unit °C/W
SI7485DP-T1-GE3;中文规格书,Datasheet资料
Vishay SiliconixSi7485DPP-Channel 20-V (D-S) MOSFETFEATURES•Halogen-free According to IEC 61249-2-21Available•TrenchFET ® Power MOSFETs•New Low Thermal Resistance PowerPAK ®Package with Low 1.07 mm ProfileAPPLICATIONS•Battery Switch for Portable DevicesPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)- 200.0073 at V GS = - 4.5 V- 200.0090 at V GS = - 2.5 V - 180.013 at V GS = - 1.8 V- 15Notes:a.Surface Mounted on 1" x 1" FR4 board.b.See Solder Profile (/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.c.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameterSymbol 10 sSteady StateUnit Drain-Source Voltage V DS - 20VGate-Source VoltageV GS± 8Continuous Drain Current (T J = 150 °C)a T A = 25 °C I D - 20- 12.5AT A = 70 °C- 16.5- 9.5Pulsed Drain CurrentI DM - 50Continuous Source Current (Diode Conduction)a I S - 4.5- 1.6Maximum Power Dissipation aT A = 25 °C P D 5 1.8W T A = 70 °C 3.21.1Operating Junction and Storage T emperature Range T J , T stg- 55 to 150°CSoldering Recommendations (Peak Temperature)b,c260THERMAL RESISTANCE RATINGSParameter S ymbol Typical Maximum UnitMaximum Junction-to-Ambient at ≤ 10 s R thJA 2025°C/WSteady State 5468Maximum Junction-to-Case (Drain)Steady State R thJC 1.7 2.2Vishay SiliconixSi7485DPNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter S ymbol Test Condition Min. Typ.Max.UnitStaticGate Threshold Voltage V GS(th) V DS = V GS , I D = - 1 mA - 0.4- 0.9VGate-Body LeakageI GSS V DS = 0 V , V GS = ± 8 V± 100 nAZero Gate Voltage Drain Current I DSS V DS = - 20 V, V GS = 0 V - 1µA V DS = - 20 V , V GS = 0 V, T J = 70 °C- 10On-State Drain Current aI D(on) V DS ≥ - 5 V , V GS = - 4.5 V - 40ADrain-Source On-State Resistance a R DS(on) V GS = - 4.5 V, I D = - 20 A 0.0060.0073ΩV GS = - 2.5 V, I D = - 18 A 0.00740.0090V GS = - 1.8 V, I D = - 15 A 0.01060.013Forward T ransconductance a g fs V DS = - 15 V , I D = - 20 A 80S Diode Forward Voltage a V SDI S = - 4.5 A, V GS = 0 V- 0.62- 1.1V Dynamic bTotal Gate Charge Q g V DS = - 10 V , V GS = - 5 V , I D = - 20 A99150nCGate-Source Charge Q gs 11.5Gate-Drain Charge Q gd 29Gate Resistance R g 2.4ΩTurn-On Delay Time t d(on) V DD = - 10 V , R L = 10 Ω I D ≅ - 1 A, V GEN = - 4.5 V , R g = 6 Ω80120ns Rise Timet r 140210Turn-Off Delay Time t d(off) 360540Fall Timet f 170260Source-Drain Reverse Recovery Timet rrI F = - 2.9 A, dI/dt = 100 A/µs 5580Vishay SiliconixSi7485DPTYPICAL CHARACTERISTICS 25Vishay SiliconixSi7485DPTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Silico nix maintains wo rldwide manufacturing capability. Pro ducts may be manufactured at o ne o f several qualified lo catio ns. Reliability data fo r Silico n Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?72275.Normalized Thermal Transient Impedance, Junction-to-CasePackage InformationVishay Siliconix PowerPAK® SO-8, (SINGLE/DUAL)MILLIMETERS INCHES DIM.MIN.NOM.MAX.MIN.NOM.MAX.A0.97 1.04 1.120.0380.0410.044A10.00-0.050.000-0.002b0.330.410.510.0130.0160.020c0.230.280.330.0090.0110.013D 5.05 5.15 5.260.1990.2030.207D1 4.80 4.90 5.000.1890.1930.197D2 3.56 3.76 3.910.1400.1480.154D3 1.32 1.50 1.680.0520.0590.066D40.57 TYP.0.0225 TYP.D5 3.98 TYP.0.157 TYP.E 6.05 6.15 6.250.2380.2420.246E1 5.79 5.89 5.990.2280.2320.236E2 3.48 3.66 3.840.1370.1440.151E3 3.68 3.78 3.910.1450.1490.154E40.75 TYP.0.030 TYP.e 1.27 BSC0.050 BSCK 1.27 TYP.0.050 TYP.K10.56--0.022--H0.510.610.710.0200.0240.028L0.510.610.710.0200.0240.028L10.060.130.200.0020.0050.008θ0°-12°0°-12°W0.150.250.360.0060.0100.014M0.125 TYP.0.005 TYP.ECN: T10-0055-Rev. J, 15-Feb-10DWG: 5881Vishay SiliconixAN821PowerPAK ® SO-8 Mounting and Thermal ConsiderationsWharton McDanielMOSFETs for switching applications are now available with die on resistances around 1 m Ω and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. In this appli-cation note, PowerPAK’s construction is described.Following this mounting information is presented including land patterns and soldering profiles for max-imum reliability. Finally, thermal and electrical perfor-mance is discussed.THE PowerPAK PACKAGEThe PowerPAK package was developed around the SO-8 package (Figure 1). The PowerPAK SO-8 uti-lizes the same footprint and the same pin-outs as the standard SO-8. This allows PowerPAK to be substi-tuted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8 utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly larger than a full sized DPAK die. The bottom of the die attach pad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the device is mounted on. Finally, the package height is lower than the standard SO-8, making it an excellent choice for applications with space constraints.PowerPAK SO-8 SINGLE MOUNTINGThe PowerPAK single is simple to use. The pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard SO-8 devices (see Figure 2). Therefore, the PowerPAK connection pads match directly to those of the SO-8. The only dif-ference is the extended drain connection area. To take immediate advantage of the PowerPAK SO-8 single devices, they can be mounted to existing SO-8 land patterns.The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Sili-conix MOSFETs . Click on the PowerPAK SO-8 single in the index of this document.In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight and layer stack,experiments have found that more than about 0.25 to 0.5 in 2 of additional copper (in addition to the drain land) will yield little improvement in thermal perfor-mance.Figure 1.PowerPAK 1212 DevicesFigure 2.Standard SO-8Pow erPAK SO-8Vishay SiliconixAN821PowerPAK SO-8 DUALThe pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8. As in the single-channel package,the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns.To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK 1212-8 dual in the index of this doc-ument.The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the Pow-erPAK SO-8 dual package.REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humid-ity, HAST, or pressure pot. The solder reflow tempera-ture profile used, and the temperatures and time duration, are shown in Figures 3 and 4.For the lead (Pb)-free solder profile, see /doc?73257.Ramp-Up Rate+ 6 °C /Second Maximum Temperature at 155 ± 15 °C 120 Seconds Maximum Temperature Above 180 °C 70 - 180 Seconds Maximum T emperature 240 + 5/- 0 °CTime at Maximum T emperature 20 - 40 SecondsRamp-Down Rate+ 6 °C/Second MaximumFigure 3. Solder Reflow Temperature ProfileFigure 3.Solder Reflow Temperatures and Time DurationsVishay SiliconixAN821THERMAL PERFORMANCE IntroductionA basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R θjc , or the junction-to-foot thermal resistance, R θjf . This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and stan-dard SO-8. The PowerPAK has thermal performance equivalent to the DPAK, while having an order of magni-tude better thermal performance over the SO-8. Thermal Performance on Standard SO-8 Pad Pattern Because of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pat-tern. The question then arises as to the thermal perfor-mance of the PowerPAK device under these conditions.A characterization was made comparing a standard SO-8and a PowerPAK device on a board with a trough cut out underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in Figure 5.Because of the presence of the trough, this result sug-gests a minimum performance improvement of 10 °C/W by using a PowerPAK SO-8 in a standard SO-8 PC board mount.The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is that there should be no traces running between the body of the MOSFET.Where the standard SO-8 body is spaced away from the pc board, allowing traces to run underneath, the Power-PAK sits directly on the pc board.Thermal Performance - Spreading CopperDesigners may add additional copper, spreading cop-per, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading cop-per.Figure 6 shows the thermal resistance of a PowerPAK SO-8 device mounted on a 2-in. 2-in., four-layer FR-4PC board. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken.The results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces,and then totally removed. No significant effect was observed.TABLE 1.DPAK and PowerPAK SO-8Equivalent Steady State PerformanceDPAKPowerPAKSO-8 Standard SO-8 Thermal Resistance R θjc1.2 °C/W1.0 °C/W16 °C/WFigure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal PathFigure 6. Spreading Copper Junction-to-Ambient PerformanceR th v s. Spreading Copper (0 %, 50 %, 100 % Back Copper))s t t a w /C ( e c n a d e p m I 0.0056514641360.250.500.751.001.251.501.752.000 %50 %100 %Vishay Siliconix AN821SYSTEM AND ELECTRICAL IMPACT OF PowerPAK SO-8In any design, one must take into account the change in MOSFET r DS(on) with temperature (Figure 7).A MOSFET generates internal heat due to the current passing through the channel. This self-heating raises the junction temperature of the device above that of the PC board to which it is mounted, causing increased power dissipation in the device. A major source of this problem lies in the large values of the junction-to-foot thermal resistance of the SO-8 package.PowerPAK SO-8 minimizes the junction-to-board ther-mal resistance to where the MOSFET die temperature is very close to the temperature of the PC board. Consider two devices mounted on a PC board heated to 105 °C by other components on the board (Figure 8).Suppose each device is dissipating 2.7 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK SO-8 and the standard SO-8, the die tem-perature is determined to be 107 °C for the PowerPAK (and for DPAK) and 148 °C for the standard SO-8. This is a 2 °C rise above the board temperature for the Pow-erPAK and a 43 °C rise for the standard SO-8. Referring to Figure 7, a 2 °C difference has minimal effect on r DS(on) whereas a 43C difference has a significant effect on r DS(on).Minimizing the thermal rise above the board tempera-ture by using PowerPAK has not only eased the thermal design but it has allowed the device to run cooler, keep r DS(on) low, and permits the device to handle more cur-rent than the same MOSFET die in the standard SO-8 package.CONCLUSIONSPowerPAK SO-8 has been shown to have the same thermal performance as the DPAK package while hav-ing the same footprint as the standard SO-8 package. The PowerPAK SO-8 can hold larger die approximately equal in size to the maximum that the DPAK can accom-modate implying no sacrifice in performance because of package limitations.Recommended PowerPAK SO-8 land patterns are pro-vided to aid in PC board layout for designs using this new package.Thermal considerations have indicated that significant advantages can be gained by using PowerPAK SO-8 devices in designs where the PC board was laid out for the standard SO-8. Applications experimental data gave thermal performance data showing minimum and typical thermal performance in a SO-8 environment, plus infor-mation on the optimum thermal performance obtainable including spreading copper. This further emphasized the DPAK equivalency.PowerPAK SO-8 therefore has the desired small size characteristics of the SO-8 combined with the attractive thermal characteristics of the DPAK package.DS(on)Figure 8. Temperature of Devices on a PC Board分销商库存信息: VISHAYSI7485DP-T1-GE3。
SI7439DP-T1-GE3;中文规格书,Datasheet资料
Min. - 2.0
Typ.
Max. - 4.0 ± 100 -1 - 10
Unit V nA µA A
- 30 0.073 0.077 19 - 0.78 88 - 1.2 135 0.090 0.095
S V
Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time
FEATURES
• Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFETs • Ultra-Low On-Resistance Critical for Application • Low Thermal Resistance PowerPAK®Package with Low 1.07 mm Profile • 100 % Rg and Avalanche Tested • Compliant to RoHS Directive 2002/95/EC
Notes: a. Surface mounted on 1" x 1" FR4 board. b. See solder profile (/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 73106 S10-2246-Rev. E, 04-Oct-10 1
SIB433EDK-T1-GE3;中文规格书,Datasheet资料
Min. - 20
Typ.
Max.
Unit V
- 13 2.5 - 0.4 -1 ±6 ± 0.5 -1 - 10 - 15 0.047 0.064 0.085 12 0.058 0.077 0.105
mV/°C V
µA
A S
Drain-Source On-State Resistance Forward Transconductancea Dynamic
°C
THERMAL RESISTANCE RATINGS
Parameter Maximum Junction-to-Ambientb, f Maximum Junction-to-Case (Drain) t5s Steady State Symbol RthJA RthJC Typical 41 7.5 Maximum 51 9.5 Unit °C/W
G R
1.60 mm
D
Ordering Information: SiB433EDK-T1-GE3 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
SiB433EDK
Vishay Siliconix
P-Channel 20-V (D-S) MOSFET
FEATURES PRODUCT SUMMARY
VDS (V) - 20 RDS(on) () 0.058 at VGS = - 4.5 V 0.077 at VGS = - 2.5 V 0.105 at VGS = - 1.8 V ID (A) - 9a - 9a -5 7.6 nC Qg (Typ.)
DG611AEQ-T1-E3中文资料
1 pC Charge Injection, 100 pA Leakage, Quad SPST SwitchesFEATURES•Low charge injection (1 pC typ.) •Leakage current < 0.25 nA at 85 °C•Low switch capacitance (C soff 2 pF typ.)•Low r DS(on) - 115 Ω maximum•Fully specified with single supply operation at 3 V, 5 V and dual supplies at ± 5 V•Low voltage, 2.5 V CMOS/TTL compatible •720 MHz, 3 dB bandwidth•Excellent isolation performance (62 dB at 10 MHz) •Excellent crosstalk performance (90 dB at 10 MHz)•Fully specified from - 40 °C to + 85 °C and - 40 °C to + 125 °C•16 lead SOIC, TSSOP and miniQFN package (1.8 x 2.6 mm)APPLICATIONS•Precision instrumentation •Medical instrumentation •Automated test equipment•High speed communications applications •High-end data acquisition •Sample and hold applications •Sample and hold systemsDESCRIPTIONThe DG611A, DG612A and DG613A contain four independently selectable SPST switches. They offer improved performance over the industry standard DG611series. The DG611A and DG612A have all switches normally closed and normally open respectively, while the DG613A has 2 normally open and 2 normally closed switches.They are designed to operate from a 2.7 V to 12 V single supply or from ± 2.7 V to ± 5 V dual supplies and are fully specified at + 3 V , + 5 V and ± 5 V . All control logic inputs have guaranteed 2 V logic high limits when operating from + 5 V or ± 5 V supplies and 1.4 V when operating from a + 3 V supply.The DG611A, DG612A and DG613A switches conduct equally well in both directions and offer rail to rail analog signal handling.1 pC low charge injection, coupled with very low switch capacitance:2 pF , fast switching speed: t on /t off 27 ns/16 ns and excellent3 dB bandwidth: 720 MH z, make these products ideal for precision instrumentation, high-end data acquisition, automated test equipment and high speed communication applications.Operation temperature is specified from - 40 °C to + 125 °C.The DG611A, DG612A and DG613A are available in 16 lead SOIC, TSSOP and the space saving 1.8 x 2.6 mm miniQFN packages.FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATIONTRUTH TABLELogic DG611A DG612A 0ON OFF 1OFFONFUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATIONNotes:a. - 40 °C to 85 °C datasheet limits apply.TRUTH TABLELogic SW 1, SW 4SW 2, SW 30OFF ON 1ONOFFORDERING INFORMATIONTemp. Range PackagePart NumberDG611A/612A/613A- 40 °C to 125 °Ca16-Pin TSSOPDG611AEQ-T1-E3DG612AEQ-T1-E3DG613AEQ-T1-E316-Pin Narrow SOICDG611AEY -T1-E3DG612AEY -T1-E3DG613AEY -T1-E316-Pin miniQFNDG611AEN-T1-E4DG612AEN-T1-E4DG613AEN-T1-E4Notes:a.Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.b.All leads welded or soldered to PC Board.c.Derate 5.6 mW/°C above 70 °C.d.Derate 6.6 mW/°C above 70 °C.e.Derate 8.0 mW/°C above 70 °C.f.Manual soldering with iron is not recommended for leadless components. The miniQFN-16 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameter Limit UnitV+ to V- 14V GND to V-7Digital Inputs a , V S , V D(V-) - 0.3 V to (V+) + 0.3 V or 30 mA, whichever occurs firstContinuous Current (Any T erminal)30mA Peak Current, S or D (Pulsed 1 ms, 10 % Duty Cycle)100Storage Temperature- 65 to 150°CPower Dissipation (Package)b16-Pin TSSOP c450mW 16-Pin miniQFN d 52516-Pin Narrow SOIC e 640Thermal Resistance (Package)b16-Pin TSSOP178°C/W 16-Pin miniQFN 15216-Pin Narrow SOIC125SPECIFICATIONS FOR DUAL SUPPLIES V+ = + 5 V, V- = - 5 VParameter Symbol Test Conditions Unless Specified V+ = + 5 V , V- = - 5 V V IN = 2.0 V , 0.8 V a Temp.b Typ.c - 40 to 125 °C- 40 to 85 °CUnitMin.d Max.d Min.d Max.dAnalog Switch Analog Signal Range e V ANALOGFull -55-55VOn-Resistance r ON I S = 1 mA, V D = - 3 V, 0 V , + 3 VRoom Full 72115160115140ΩOn-Resistance Match Δr ON I S = 1 mA, V D = ± 3 V Room Full 0.746.545.5On-Resistance Flatness r FLATNESS I S = 1 mA, V D = - 3 V, 0 V , + 3 VRoom Full 2540604055Switch OffLeakage Current I S(off)V+ = 5.5 V , V- = - 5.5 V V D = + 4.5 V/- 4.5 V V S = - 4.5 V/+ 4.5 V Room Full ± 0.02- 0.1- 20.12- 0.1- 0.250.10.25nA I D(off)Room Full ± 0.02- 0.1- 20.12- 0.1- 0.250.10.25Switch OnLeakage Current I D(on)V+ = 5.5 V , V- = - 5.5 V V D = V S = ± 4.5 VRoom Full± 0.02- 0.1- 60.16- 0.1- 0.250.10.25Digital Control Input Current, V IN Low I IL V IN Under T est = 0.8 V Full 0.005- 0.10.1- 0.10.1µA Input Current, V IN High I IH V IN Under T est = 2.0 VFull 0.005- 0.10.1- 0.10.1Input Capacitance e C INf = 1 MHzRoom2pFDynamic Characteristics Turn-On Time t ON R L = 300 Ω, C L = 35 pF V S = ± 3 V, see Figure 1Room Full 2755905575nsTurn-Off Time t OFF Room Full 1635503545Break-Before-Make Time Delay t BBM DG613A only, V S = 3 V R L = 300 Ω, C L = 35 pF Room Full 1522Charge Injection e Q V g = 0 V , R g = 0 Ω, C L = 1 nFRoom 1pCOff Isolation eOIRR R L = 50 Ω, C L = 5 pFf = 10 MHz Room - 62dB Channel-to-Channel Crosstalk e X T ALK Room - 903 dB Bandwidth eBW R L = 50 Ω, C L = 5 pF Room 720MHzSource Off Capacitance e C S(off) f = 1 MHz; V S = 0 V Room 2pF Drain Off Capacitance e C D(off)Room 3Drain On Capacitance e C D(on) f = 1 MHz; V S = V D = 0 V Room 9Total Harmonic Distortion e THDSignal = 1 V RMS , 20 Hz to 20 kHz,R L = 600 ΩRoom0.01%Power Supplies Power Supply Current I+V+ = + 5 V , V- = - 5 VV IN = 0 or 5 VRoom Full 0.0010.110.11µANegative Supply Current I- Room Full - 0.001- 0.1- 1- 0.1- 1Ground CurrentI GNDRoom Full- 0.001- 0.1- 1- 0.1- 1SPECIFICATIONS FOR UNIPOLAR SUPPLIES V+ = + 5 V, V- = 0 VParameter Symbol Test Conditions Unless Specified V+ = + 5 V , V- = 0 VV IN = 2.0 V , 0.8 V a Temp.b Typ.c- 40 to 125 °C- 40 to 85 °CUnitMin.d Max.d Min.d Max.dAnalog Switch Analog Signal Range e V ANALOGFull 0505VOn-Resistance r ON V+ = + 5 V, V- = 0 V I S = 1 mA, V D = + 3.5 V Room Full 139180235180215ΩOn-Resistance Match Δr ON V+ = + 5 V , V- = 0 V ,I S = 1 mA, V D = + 3.5 V Room Full 161069On-Resistance Flatness r FLATNESS V+ = + 5 V , V- = 0 V ,I S = 1 mA, V D = 0 V, + 3.5 VRoom Full 568012080110Switch OffLeakage Current I S(off)V+ = 5.5 V , V- = 0 V V D = 4.5 V/1 V V S = 1 V/4.5 V Room Full ± 0.02- 0.1- 20.12- 0.1- 0.250.10.25nA I D(off)Room Full ± 0.02- 0.1- 20.12- 0.1- 0.250.10.25Switch OnLeakage Current I D(on)V+ = 5.5 V , V- = 0 V V D = V S = 1 V/4.5 VRoom Full± 0.02- 0.1- 60.16- 0.1- 0.250.10.25Digital Control Input Current, V IN Low I IL V IN Under T est = 0.8 V Full 0.005- 0.10.1- 0.10.1µA Input Current, V IN High I IH V IN Under T est = 2.0 VFull 0.005- 0.10.1- 0.10.1Input Capacitance e C INf = 1 MHzRoom2pFDynamic Characteristics T urn-On Time e t ON R L = 300 Ω, C L = 35 pF V S = 3 V , see Figure 1Room Full 33601006090nsT urn-Off Time e t OFF Room Full 1635503545Break-Before-Make e Time Delay t BBM DG613A only, V S = 3 V R L = 300 Ω, C L = 35 pF Room Full 1922Charge Injection e Q V g = 0 V , R g = 0 Ω, C L = 1 nFFull 2.3pCOff Isolation eOIRR R L = 50 Ω, C L = 5 pFf = 10 MHz Room - 61dB Channel-to-Channel Crosstalk e X TALK Room - 903 dB Bandwidth eBW R L = 50 Ω, C L = 5 pF Room 675MHzSource Off Capacitance e C S(off) f = 1 MHz; V S = 0 V Room 3pF Drain Off Capacitance e C D(off)Room 5Drain On Capacitance e C D(on)f = 1 MHz; V S = V D = 0 VRoom9Power Supplies Power Supply Current I+V IN = 0 or 5 VRoom Full 0.001 0.110.11µANegative Supply Current I- Room Full - 0.001- 0.1- 1- 0.1- 1Ground CurrentI GNDRoom Full- 0.001- 0.1- 1- 0.1- 1Notes:a. V IN = input voltage to perform proper function.b. Room = 25 °C, Full = as determined by the operating temperature suffix.c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.e. Guaranteed by design, not subject to production test.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS FOR UNIPOLAR SUPPLIES V+ = + 3 V, V- = 0 VParameter Symbol Test Conditions Unless Specified V+ = + 3 V , V- = 0 V V IN = 1.4 V, 0.6 V a Temp.b Typ.c- 40 to 125 °C- 40 to 85 °C UnitMin.dMax.dMin.dMax.dAnalog Switch Analog Signal Range e V ANALOGFull 0303V On-Resistance r ON I S = 1 mA, V D = + 1.5 V Room Full 195235300235280ΩSwitch OffLeakage Current I S(off)V+ = 3.3 V, V- = 0 V V D = 3 V/0.3 V V S = 0.3 V/3 V Room Full ± 0.02- 0.1- 20.12- 0.1- 0.250.10.25nA I D(off)Room Full ± 0.02- 0.1- 20.12- 0.1- 0.250.10.25Switch OnLeakage Current I D(on)V+ = 3.3 V, V- = 0 V V D = V S = 0.3 V/3 VRoom Full± 0.02- 0.1- 60.16- 0.1- 0.250.10.25Digital Control Input Current, V IN Low I IL V IN Under Test = 0.6 V Full 0.005- 0.10.1- 0.10.1µA Input Current, V IN High I IH V IN Under Test = 1.4 VFull 0.005- 0.10.1- 0.10.1Input Capacitance e C INf = 1 MHzRoom2pFDynamic Characteristics Turn-On Time t ON R L = 300 Ω, C L = 35 pF V S = 2 V, see Figure 1Room Full 87125180125170nsTurn-Off Time t OFF Room Full 3355655560Break-Before-Make Time Delay t BBM DG613 only, V S = 2 V R L = 300 Ω, C L = 35 pF Room Full 601010Charge Injection e Q V g = 0 V , R g = 0 Ω, C L = 1 nFRoom 2.3pCOff Isolation eOIRR R L = 50 Ω, C L = 5 pFf = 10 MHz Room - 60dB Channel-to-Channel Crosstalk e X T ALK Room - 903 dB Bandwidth eBW R L = 50 Ω, C L = 5 pF Room 550MHzSource Off Capacitance e C S(off) f = 1 MHz; V S = 0 V Room 5pF Drain Off Capacitance e C D(off)Room 6Drain On Capacitance e C D(on)f = 1 MHz; V S = V D = 0 VRoom9Power Supplies Power Supply Current I+V IN = 0 or 3 VRoom Full 0.0010.110.11µANegative Supply Current I- Room Full - 0.001- 0.1- 1- 0.1- 1Ground CurrentI GNDRoom Full- 0.001- 0.1- 1- 0.1- 1TYPICAL CHARACTERISTICS 25°C, unless otherwise notedOn-Resistance vs. V D (Dual Supply)Leakage Current vs. TemperatureOn-Resistance vs. V D (Single Supply)TYPICAL CHARACTERISTICS 25°C, unless otherwise notedSwitching Time vs. Temperature (Single Supply)Switching Threshold vs. Supply VoltageInsertion Loss, Off-Isolation, Crosstalkvs. FrequencySupply Current vs. Switching FrequencyTEST CIRCUITSFigure 1. Switching TimeFigure 2. Break-Before-Make (DG613A)Figure 3. Charge InjectionTEST CIRCUITSVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?69904.Figure 4. CrosstalkFigure 5. Off-IsolationFigure 6. Source/Drain CapacitancesDocument Number: 91000 Revision: 18-Jul-081DisclaimerLegal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。
SI4401DDY-T1-GE3;中文规格书,Datasheet资料
0.024 V GS = 4.5 V 0.018 V GS = 10 V 0.012
C - Capacitance (pF)
3600 Ciss 2700
1800
0.006
900
Coss Crss
0 0 10 20 30 40 50
0 0 8 16 24 32 40
ID - Drain Current (A)
0.5
1.0
1.5
2.0
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
0.030 4500
Transfer Characteristics
RDS(on) - On-Resistance (Ω)
50 V GS = 10 V thru 5 V 40
ID - Drain Current (A)
10
V GS = 4 V
ID - Drain Current (A)
8
30
6
20
4 T C = 25 °C 2
10 V GS = 3 V 0 0.0
T C = 125 °C 0 T C = - 55 °C 0 1 2 3 4
• Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • 100 % UIS Tested • Compliant to RoHS Directive 2002/95/EC
Si4401DDY
Vishay Siliconix
DG470EQ-T1-E3中文资料
Vishay SiliconixDG469/470High Voltage, Single and Dual Supply SPDT Analog Switchwith Enable PinFEATURES•Low on resistance (3.6 Ω typical)•On resistance flatness (0.4 Ω typical) •44 V supply maximum rating •± 15 V analog signal range••TTL/CMOS compatible •Break before make switching guaranteed •Total harmonic distortion 0.0145 %APPLICATIONS•Audio and video signal switching •Precision automatic test equipment •Precision data acquisition •Relay replacement•Communications systems •Automotive applications •Sample and hold systems •Power routing applications •Telecom signal switching •Medical equipment•Portable and battery power systemsDESCRIPTIONThe DG469/470 are high voltage SPDT switches, with a typical on resistance of 3.6 Ω and typical flatness of 0.4 Ω.The DG469 and DG470 are identical, except the DG470provides an enable input. When the enable input is activated,both sides of the switch are in a high impedance mode (Off),maintaining a "Safe State" at power up. This function can also be used as a quick "disconnect" in the event of a fault condition. For audio switching, the enable pin provides a mute function. These are high voltage switches that are fully specified with dual supplies at ± 4.5 V and ± 15 V and a single supply of 12 V over an operating temperature range from - 40 °C to + 125 °C. Fast switching speeds coupled with high signal bandwidth makes these parts suitable for video switching applications. All digital inputs have 0.8 V and 2.4 V logic thresholds ensuring low voltage TTL/CMOS compatibility. Each switch conducts equally well in both directions when on and can handle an input signal range that extends to the supply voltage rails. They exhibit break-before-make switching action to prevent momentary shorting when switching between channels. The DG469 and DG470are offered in a MSOP 8 and SOIC 8 package.FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATIONTRUTH TABLE: DG469Logic NC NO 0ON OFF 1OFFONTRUTH TABLE: DG470ENABLELogic NC NO 00ON OFF 01OFF ON 1XOFFOFFVishay SiliconixDG469/470Notes:a. - 40 °C to 85 °C datasheet limits apply.Notes:a. Signals on S X , D X , or IN X exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.b. All leads welded or soldered to PC Board.c. Derate 4.0 mW/°C above 70 °C.d. Derate 5.0 mW/°C above 70 °C.ORDERING INFORMATIONTemp Range PackagePart NumberDG469/470- 40 °C to 125 °C a8-Pin MSOPDG469EQ-T1-E3DG470EQ-T1-E38-Pin Narrow SOICDG469EY -T1-E3DG470EY -T1-E3ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameter Limit Unit V+ to V- 44VGND to V- 25Digital Inputs a, V S , V D(V-) - 2 to (V+) + 2or 30 mA, whichever occurs firstContinuous Current (NO, NC, or COM)120mA Current (Any terminal except NO, NC, or COM)30Peak Current, (Pulsed 1 ms, 10 % Duty Cycle)200Storage T emperature - 65 to 150°C Power Dissipation (Package)b8-Pin MSOP c 320mW8-Pin Narrow SOIC d400SPECIFICATIONS FOR DUAL SUPPLIESParameter Symbol Test Conditions Unless Specified V+ = 15 V , V- = - 15 V V IN = 2.4 V , 0.8 V a Temp b Typ c - 40 to 125 °C- 40 to 85 °CUnitMin d Max d Min d Max dAnalog Switch Analog Signal Range e V ANALOGFull - 1515- 1515VOn-Resistance r ON I S = 50 mA, V D = - 10 V to + 10 VRoom Full 3.66867ΩOn-Resistance Match Δr ON I S = 50 mA, V D = ± 10 V Room Full 0.120.40.90.40.5On-Resistance Flatness r FLATNESS I S = 50 mA, V D = - 5 V, 0 V , + 5 VRoom Full 0.40.50.90.50.8Switch OffLeakage Current I S(off)V D = ± 14 V , V S = ± 14 VRoom Full ± 0.1- 0.5- 200.520- 0.5- 2.50.52.5nA I D(off)Room Full ± 0.1- 0.5- 200.520- 0.5- 2.50.52.5Channel On Leakage Current I D(on)V S = V D = ± 14 VRoom Full± 0.2- 0.5- 200.520- 0.5- 50.55Digital Control Input Current, V IN Low I IL V IN Under T est = 0.8 V Full 0.05- 11- 11µA Input Current, V IN High I IH V IN Under T est = 2.4 VFull 0.05- 11- 11Input Capacitance eC INf = 1 MHzRoom3.7pFVishay SiliconixDG469/470Dynamic Characteristics T urn-On Time t ON R L = 300 Ω, C L = 35 pFV S = ± 10 V Room Full 129166200166185nsT urn-Off Time t OFF Room Full 80108135108120Break-Before-MakeTime Delay t D V S = 10 VR L = 300 Ω, C L = 35 pF Room 15Charge Injection e Q V g = 0 V , R g = 0 Ω, C L = 1 nFRoom 58pCOff Isolation eOIRR R L = 50 Ω, C L = 5 pFf = 1 MHzRoom - 57dB Channel-to-Channel Crosstalk eX T ALK Room - 63Source Off Capacitance e C S(off) f = 1 MHzRoom 37pF Drain Off Capacitance e C D(off)Room 85Channel On Capacitance e C D(on)Room125Power Supplies Power Supply Current I+V+ = 16.5 V, V- = - 16.5 VV IN = 0 or 5 VRoom Full 3.06767µANegative Supply Current I- Room Full - 0.4- 0.5- 4.5- 0.5- 4.5Ground CurrentI GNDRoom Full- 3.0- 6- 7- 6- 7SPECIFICATIONS FOR DUAL SUPPLIESParameter Symbol Test Conditions Unless Specified V+ = 15 V, V- = - 15 V V IN = 2.4 V , 0.8 V a Temp b Typ c - 40 to 125 °C- 40 to 85 °CUnitMin d Max d Min d Max dSPECIFICATIONS FOR DUAL SUPPLIESParameter Symbol Test Conditions Unless Specified V+ = 4.5 V , V- = - 4.5 V V IN = 2.4 V , 0.8 V a Temp b T yp c - 45 to 125 °C- 40 to 85 °CUnitMin d Max d Min d Max dAnalog Switch Analog Signal Range e V ANALOGFull - 4.54.5- 4.54.5V On-Resistance e r ON I S = 50 mA, V D = - 2 V to + 2 VRoom Full 811161115ΩOn-Resistance Match e Δr ONI S = 50 mA, V D = ± 2 VRoom Full0.60.70.90.70.8Dynamic Characteristics T urn-On Time e t ON R L = 300 Ω, C L = 35 pFV S = 2 V Room Full 24526534065310nsT urn-Off Time e t OFF Room Full 145163200163185Break-Before-Make eTime Delay t D V S = 2 VR L = 300 Ω, C L = 35 pF Room Full 15Charge Injection e QV g = 0 V , R g = 0 Ω, C L = 1 nFFull58pCPower Supplies Power Supply Current e I+V IN = 0 or 4.5 VRoom Full 3.06767µANegative Supply Current e I- Room Full - 0.4- 0.5- 4.5- 0.5- 4.5Ground Current eI GNDRoom Full3.0- 6- 7- 6- 7Vishay SiliconixDG469/470Notes: a. V IN = input voltage to perform proper function.b. Room = 25 °C, Full = as determined by the operating temperature suffix.c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.e. Guaranteed by design, not subject to production test.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS FOR UNIPOLAR SUPPLIESParameter Symbol Test Conditions Unless Specified V+ = 12 V , V- = 0 V V IN = 2.4 V, 0.8 V a Temp b T yp c - 40 to 125 °C- 40 to 85 °CUnitMin d Max d Min d Max dAnalog Switch Analog Signal Range e V ANALOGFull 1212VOn-Resistance r ON I S = 25 mA, V D = 0 V to + 10 V Room Full 7.58.5148.511.3ΩOn-Resistance Match Δr ON I S = 25 mA, V D = + 10 V Room Full 0.40.450.90.450.5On-Resistance Flatness r FLATNESSI S = 25 mA,V D = 0 V , + 5 V , + 10 VRoom Full2.52.62.92.62.8Dynamic Characteristics Turn-On Time t ON R L = 300 Ω, C L = 35 pFV S = 10 V Room Full 190200255200240nsTurn-Off Time t OFF Room Full 100110135110120Break-Before-MakeTime Delay t D V S = 10 VR L = 300 Ω, C L = 35 pF Room 50Charge Injection e QV g = 0 V , R g = 0 Ω, C L = 1 nFRoom2.4pCPower Supplies Power Supply Current I+V IN = 0 or 5 VRoom Full 3.06767µANegative Supply Current I- Room Full - 0.4- 0.5- 4.5- 0.5- 4.5Ground CurrentI GNDRoom Full- 3.0- 6- 7- 6- 7Vishay SiliconixDG469/470TYPICAL CHARACTERISTICSDD Leakage Current vs. TemperatureD DVishay SiliconixDG469/470TYPICAL CHARACTERISTICSCharge Injection vs. Analog VoltageCharge Injection vs. Analog VoltageSwitching Time vs. Temperature andDual Supply VoltageSingle Supply VoltageVishay SiliconixDG469/470TYPICAL CHARACTERISTICSTEST CIRCUITSInsertion Loss, Off-Isolation, Crosstalkvs. FrequencySwitching Threshold vs. Dual Supply VoltageSwitching Threshold vs. Signal Supply VoltageDG469, DG470 Total Harmonic DistortionFigure 1. Switching TimeVishay SiliconixDG469/470New ProductTEST CIRCUITSVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for SiliconTechnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?71470.Figure 2. Break-Before-MakeFigure 3. Charge InjectionFigure 4. Off-Isolation Figure 5. Source/Drain Capacitances元器件交易网Legal Disclaimer NoticeVishayNoticeSpecifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.元器件交易网。
SIR426DP-T1-GE3;中文规格书,Datasheet资料
Vishay SiliconixSiR426DPN-Channel 40-V (D-S) MOSFETFEATURES•Halogen-free According to IEC 61249-2-21Definition•TrenchFET ® Power MOSFET •100 % R g Tested •100 % UIS Tested•Compliant to RoHS Directive 2002/95/ECAPPLICATIONS•DC/DC Converters- Synchronous Buck - Synchronous RectifierPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)Q g (Typ.)400.0105 at V GS = 10 V 30a 9.3 nC0.0125 at V GS = 4.5 V30aNotes:a.Based on T C = 25 °C. Package limited.b.Surface Mounted on 1" x 1" FR4 board.c.t = 10 s.d. See Solder Profile (/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.e.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.f.Maximum under Steady State conditions is 70 °C/W.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameter Symbol Limit Unit Drain-Source Voltage V DS 40VGate-Source Voltage V GS ± 20Continuous Drain Current (T J = 150 °C)T C = 25 °C I D 30a AT C = 70 °C 30aT A = 25 °C 15.9b, cT A = 70 °C 12.8b, cPulsed Drain Current I DM 70Avalanche Current L = 0.1 mHI AS 20Avalanche Energy E AS 20mJ Continuous Source-Drain Diode Current T C = 25 °C I S30a A T A = 25 °C 4b, c Maximum Power DissipationT C = 25 °C P D 41.7W T C = 70 °C 26.7T A = 25 °C 4.8b, c T A = 70 °C 3.1b, cOperating Junction and Storage T emperature Range T J , T stg - 55 to 150°C Soldering Recommendations (Peak Temperature)d, e 260THERMAL RESISTANCE RATINGSParameter Symbol Typical MaximumUnitMaximum Junction-to-Ambient b, f t ≤ 10 s R thJA2126°C/WMaximum Junction-to-Case (Drain)Steady StateR thJC 2.4 3.0Vishay SiliconixSiR426DPNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol Test Conditions Min. Typ.Max.UnitStaticDrain-Source Breakdown Voltage V DS V GS = 0 V , I D = 250 µA40V V DS Temperature Coefficient ΔV DS /T J I D = 250 µA47mV/°C V GS(th) T emperature Coefficient ΔV GS(th)/T J - 5.4Gate-Source Threshold Voltage V GS(th)V DS = V GS , I D = 250 µA 1.2 2.5V Gate-Source LeakageI GSS V DS = 0 V , V GS = ± 20 V ± 100nA Zero Gate Voltage Drain Current I DSS V DS = 40 V , V GS = 0 V 1µA V DS = 40 V , V GS = 0 V , T J = 55 °C5On-State Drain Current aI D(on) V DS ≥ 5 V, V GS = 10 V 30A Drain-Source On-State Resistance a R DS(on)V GS = 10 V , I D = 15 A 0.00850.0105ΩV GS = 4.5 V, I D = 10 A 0.01040.0125Forward T ransconductance a g fsV DS = 15 V , I D = 15 A43SDynamic bInput Capacitance C iss V DS = 20 V , V GS = 0 V, f = 1 MHz1160pFOutput CapacitanceC oss 185Reverse Transfer Capacitance C rss 70Total Gate Charge Q g V DS = 20 V , V GS = 10 V , ID = 10 A 20.531nC V DS = 20 V , V GS = 4.5 V , I D = 10 A 9.314Gate-Source Charge Q gs 3.1Gate-Drain Charge Q gd 2.5Gate Resistance R g f = 1 MHz0.20.8 1.6ΩTurn-On Delay Time t d(on) V DD = 20 V , R L = 2 ΩI D ≅ 10 A, V GEN = 4.5 V , R g = 1 Ω1835ns Rise Timet r 1530Turn-Off Delay Time t d(off) 1835Fall Timet f 1020Turn-On Delay Time t d(on) V DD = 20 V , R L = 2 ΩI D ≅ 10 A, V GEN = 10 V , R g = 1 Ω918Rise Timet r 918Turn-Off Delay Time t d(off) 1835Fall Timet f816Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 °C30A Pulse Diode Forward Current I SM 70Body Diode VoltageV SD I S = 4.0 A, V GS = 0 V0.77 1.2V Body Diode Reverse Recovery Time t rr I F = 10 A, dI/dt = 100 A/µs, T J = 25 °C2345ns Body Diode Reverse Recovery Charge Q rr 1938nC Reverse Recovery Fall Time t a 14nsReverse Recovery Rise Timet b9Vishay Siliconix SiR426DPOn-Resistance vs. Drain Current and Gate VoltageGate ChargeThreshold VoltageSingle Pulse Power (Junction-to-Ambient)Vishay SiliconixSiR426DPTYPICAL CHARACTERISTICS 25 °C, unless otherwise noted* The power dissipation P D is based on T J(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.Power, Junction-to-CasePower, Junction-to-AmbientSiR426DPVishay SiliconixTYPICAL CHARACTERISTICS 25 °C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?65162.Package InformationVishay Siliconix PowerPAK® SO-8, (SINGLE/DUAL)MILLIMETERS INCHES DIM.MIN.NOM.MAX.MIN.NOM.MAX.A0.97 1.04 1.120.0380.0410.044A10.00-0.050.000-0.002b0.330.410.510.0130.0160.020c0.230.280.330.0090.0110.013D 5.05 5.15 5.260.1990.2030.207D1 4.80 4.90 5.000.1890.1930.197D2 3.56 3.76 3.910.1400.1480.154D3 1.32 1.50 1.680.0520.0590.066D40.57 TYP.0.0225 TYP.D5 3.98 TYP.0.157 TYP.E 6.05 6.15 6.250.2380.2420.246E1 5.79 5.89 5.990.2280.2320.236E2 3.48 3.66 3.840.1370.1440.151E3 3.68 3.78 3.910.1450.1490.154E40.75 TYP.0.030 TYP.e 1.27 BSC0.050 BSCK 1.27 TYP.0.050 TYP.K10.56--0.022--H0.510.610.710.0200.0240.028L0.510.610.710.0200.0240.028L10.060.130.200.0020.0050.008θ0°-12°0°-12°W0.150.250.360.0060.0100.014M0.125 TYP.0.005 TYP.ECN: T10-0055-Rev. J, 15-Feb-10DWG: 5881Vishay SiliconixAN821PowerPAK ® SO-8 Mounting and Thermal ConsiderationsWharton McDanielMOSFETs for switching applications are now available with die on resistances around 1 m Ω and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. In this appli-cation note, PowerPAK’s construction is described.Following this mounting information is presented including land patterns and soldering profiles for max-imum reliability. Finally, thermal and electrical perfor-mance is discussed.THE PowerPAK PACKAGEThe PowerPAK package was developed around the SO-8 package (Figure 1). The PowerPAK SO-8 uti-lizes the same footprint and the same pin-outs as the standard SO-8. This allows PowerPAK to be substi-tuted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8 utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly larger than a full sized DPAK die. The bottom of the die attach pad is exposed for the purpose of providing a direct,low resistance thermal path to the substrate the device is mounted on. Finally, the package height is lower than the standard SO-8, making it an excellent choice for applications with space constraints.PowerPAK SO-8 SINGLE MOUNTINGThe PowerPAK single is simple to use. The pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard SO-8 devices (see Figure 2). Therefore, the PowerPAK connection pads match directly to those of the SO-8. The only dif-ference is the extended drain connection area. To take immediate advantage of the PowerPAK SO-8 single devices, they can be mounted to existing SO-8 land patterns.The minimum land pattern recommended to take full advantage of the PowerPAK thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Sili-conix MOSFETs . Click on the PowerPAK SO-8 single in the index of this document.In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight and layer stack,experiments have found that more than about 0.25 to 0.5 in 2 of additional copper (in addition to the drain land) will yield little improvement in thermal perfor-mance.Figure 1.PowerPAK 1212 DevicesFigure 2.Standard SO-8Pow erPAK SO-8Vishay SiliconixAN821PowerPAK SO-8 DUALThe pin arrangement (drain, source, gate pins) and the pin dimensions of the PowerPAK SO-8 dual are the same as standard SO-8 dual devices. Therefore, the PowerPAK device connection pads match directly to those of the SO-8. As in the single-channel package,the only exception is the extended drain connection area. Manufacturers can likewise take immediate advantage of the PowerPAK SO-8 dual devices by mounting them to existing SO-8 dual land patterns.To take the advantage of the dual PowerPAK SO-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK 1212-8 dual in the index of this doc-ument.The gap between the two drain pads is 24 mils. This matches the spacing of the two drain pads on the Pow-erPAK SO-8 dual package.REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humid-ity, HAST, or pressure pot. The solder reflow tempera-ture profile used, and the temperatures and time duration, are shown in Figures 3 and 4.For the lead (Pb)-free solder profile, see /doc?73257.Ramp-Up Rate+ 6 °C /Second Maximum Temperature at 155 ± 15 °C 120 Seconds Maximum Temperature Above 180 °C 70 - 180 Seconds Maximum T emperature 240 + 5/- 0 °CTime at Maximum T emperature 20 - 40 SecondsRamp-Down Rate+ 6 °C/Second MaximumFigure 3. Solder Reflow Temperature ProfileFigure 3.Solder Reflow Temperatures and Time DurationsVishay SiliconixAN821THERMAL PERFORMANCE IntroductionA basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R θjc , or the junction-to-foot thermal resistance, R θjf . This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the DPAK, PowerPAK SO-8, and stan-dard SO-8. The PowerPAK has thermal performance equivalent to the DPAK, while having an order of magni-tude better thermal performance over the SO-8. Thermal Performance on Standard SO-8 Pad Pattern Because of the common footprint, a PowerPAK SO-8can be mounted on an existing standard SO-8 pad pat-tern. The question then arises as to the thermal perfor-mance of the PowerPAK device under these conditions.A characterization was made comparing a standard SO-8and a PowerPAK device on a board with a trough cut out underneath the PowerPAK drain pad. This configuration restricted the heat flow to the SO-8 land pads. The results are shown in Figure 5.Because of the presence of the trough, this result sug-gests a minimum performance improvement of 10 °C/W by using a PowerPAK SO-8 in a standard SO-8 PC board mount.The only concern when mounting a PowerPAK on a standard SO-8 pad pattern is that there should be no traces running between the body of the MOSFET.Where the standard SO-8 body is spaced away from the pc board, allowing traces to run underneath, the Power-PAK sits directly on the pc board.Thermal Performance - Spreading CopperDesigners may add additional copper, spreading cop-per, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading cop-per.Figure 6 shows the thermal resistance of a PowerPAK SO-8 device mounted on a 2-in. 2-in., four-layer FR-4PC board. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken.The results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces,and then totally removed. No significant effect was observed.TABLE 1.DPAK and PowerPAK SO-8Equivalent Steady State PerformanceDPAKPowerPAKSO-8 Standard SO-8 Thermal Resistance R θjc1.2 °C/W1.0 °C/W16 °C/WFigure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal PathFigure 6. Spreading Copper Junction-to-Ambient PerformanceR th v s. Spreading Copper (0 %, 50 %, 100 % Back Copper))s t t a w /C ( e c n a d e p m I 0.0056514641360.250.500.751.001.251.501.752.000 %50 %100 %分销商库存信息: VISHAYSIR426DP-T1-GE3。
SI2309CDS-T1-GE3中文资料
Vishay SiliconixSi2309CDSP-Channel 60-V (D-S) MOSFETFEATURES•Halogen-free Option Available •TrenchFET ® Power MOSFETAPPLICATIONS•Load SwitchPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)d Q g (Typ.)- 600.345 at V GS = - 10 V - 1.6 2.7 nC0.450 at V GS = - 4.5 V- 1.4Notes:a. Surface Mounted on 1" x 1" FR4 board.b. t = 5 s.c. Maximum under Steady State conditions is 166 °C/W.d. When T C = 25 °C.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameter Symbol Limit nitDrain-Source Voltage V DS - 60VGate-Source VoltageV GS± 20Continuous Drain Current (T J = 150 °C)a, bT C = 25 °CI D - 1.6A T C = 70 °C - 1.3T A = 25 °C - 1.2a, b T A = 70 °C- 1.0a, bPulsed Drain Current (10 µs Pulse Width)I DM - 8Single Pulse Avalanche Current L = 0.1 mH I AS - 5Continuous Source-Drain Diode CurrentT C = 25 °C I S - 1.4T A = 25 °C - 0.9a, b Maximum Power DissipationT C = 25 °CP D 1.7W T C = 70 °C 1.1T A = 25 °C 1.0a, b T A = 70 °C0.67a, b Operating Junction and Storage T emperature Range T J , T stg - 55 to 150°C Soldering Recommendations (Peak Temperature)c260THERMAL RESISTANCE RATINGSParameter Symbol Typical Maximum UnitMaximum Junction-to-Ambient a, c t ≤ 5 s R thJA 92120°C/WMaximum Junction-to-Foot (Drain)Steady StateR thJF5873Vishay SiliconixSi2309CDSNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol Test Conditions Min.Typ.Max.U nitStaticDrain-Source Breakdown Voltage V DS V GS = 0 V , I D = - 250 µA- 60V V DS Temperature Coefficient ΔV DS /T J I D = - 250 µA - 65mV/°C V GS(th) Temperature Coefficient ΔV GS(th)/T J 4.5Gate-Source Threshold Voltage V GS(th) V DS = V GS , I D = - 250 µA - 1- 3VGate-Source LeakageI GSS V DS = 0 V , V GS = ± 20 V - 100nAZero Gate Voltage Drain Current I DSS V DS = - 60 V , V GS = 0 V - 1µA V DS = - 60 V , V GS = 0 V , T J = 55 °C- 10On-State Drain Current aI D(on) V DS ≤ 5 V , V GS = - 10 V - 6A Drain-Source On-State Resistance a R DS(on) V GS = - 10 V , I D = - 1.25 A 0.2850.345ΩV GS = - 4.5 V , I D = - 1.0 A 0.3600.450Forward T ransconductance a g fsV DS = - 10 V, I D = - 1.0 A2.8SDynamic bInput Capacitance C iss V DS = - 30 V , V GS = 0 V, f = 1 MHz210pFOutput CapacitanceC oss 28Reverse Transfer Capacitance C rss 20Total Gate Charge Q g V DS = - 30 V, V GS = - 4.5 V , ID = - 1.25 A 2.7 4.1nC Gate-Source Charge Q gs 0.8Gate-Drain Charge Q gd 1.2Gate Resistance R g f = 1 MHz7ΩTurn-On Delay Time t d(on) V DD = - 30 V, R L = 30 Ω I D ≅ - 1 A, V GEN = - 4.5 V , R g = 1 Ω4060nsRise Timet r 3555Turn-Off Delay Time t d(off) 1525Fall Timet f 1020Turn-On Delay Time t d(on) V DD = - 30 V, R L = 30 ΩI D ≅ - 1 A, V GEN = - 10 V, R g = 1 Ω510Rise Timet r 1020Turn-Off Delay Time t d(off) 1525Fall Timet f1020Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 °C- 1.4A Pulse Diode Forward Current I SM - 8Body Diode VoltageV SD I S = - 0.75 A, V GS = 0 V- 0.8- 1.2V Body Diode Reverse Recovery Time t rr I F = - 1.25 A, dI/dt = 100 A/µs, T J = 25 °C3060ns Body Diode Reverse Recovery Charge Q rr 3360nC Reverse Recovery Fall Time t a 18nsReverse Recovery Rise Timet b12Gate ChargeOn-Resistance vs. Junction TemperatureSource-Drain Diode Forward VoltageThreshold VoltageSingle Pulse Power, Junction-to-AmbientVishay SiliconixSi2309CDSTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?68980.Normalized Thermal Transient Impedance, Junction-to-AmbientDisclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。
SI2343DS-T1-GE3;中文规格书,Datasheet资料
Vishay SiliconixSi2343DSP-Channel 30-V (D-S) MOSFETFEATURES•Halogen-free According to IEC 61249-2-21Available•TrenchFET ® Power MOSFETAPPLICATIONS•Load Switch •PA SwitchPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)- 300.053 at V GS = - 10 V - 4.00.086 at V GS = - 4.5 V- 3.1Notes:a. Surface Mounted on 1" x 1" FR4 board.b. Pulse width limited by maximum junction temperature.* Pb containing terminations are not RoHS compliant, exemptions may apply ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameterSymbol 5 s Steady State Unit Drain-Source Voltage V DS - 30VGate-Source VoltageV GS± 20Continuous Drain Current (T J = 150 °C)a, b T A = 25 °C I D - 4.0- 3.1AT A = 70 °C- 3.2- 2.5Pulsed Drain CurrentI DM - 15Continuous Source Current (Diode Conduction)a, b I S- 1.0- 0.6Maximum Power Dissipationa, bT A = 25 °C P D 1.250.75W T A = 70 °C0.80.48Operating Junction and Storage T emperature RangeT J , T stg- 55 to 150°C THERMAL RESISTANCE RATINGSParameter Symbol T ypical Maximum UnitMaximum Junction-to-Ambient a t ≤ 5 s R thJA 75100°C/WSteady State 120166Maximum Junction-to-Foot (Drain)Steady StateR thJF4050Vishay SiliconixSi2343DSNotes:a. Pulse test: PW ≤ 300 µs, duty cycle ≤ 2 %.b. For DESIGN AID ONLY, not subject to production testing.c. Switching time is essentially independent of operating temperature.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol T est Conditions LimitsUnitMin.Typ.Max.StaticDrain-Source Breakdown Voltage V (BR)DSS V GS = 0 V , I D = - 250 µA - 30VGate-Threshold Voltage V GS(th) V DS = V GS , I D = - 250 µA - 1- 3Gate-Body LeakageI GSS V DS = 0 V , V GS = ± 20 V ± 100 nAZero Gate Voltage Drain Current I DSS V DS = - 24 V , V GS = 0 V - 1µA V DS = - 24 V, V GS = 0 V , T J = 55 °C- 10On-State Drain Current a I D(on) V DS ≤ - 5 V , V GS = - 10 V - 15A Drain-Source On-Resistance aR DS(on) V GS = - 10 V , I D = - 4.0 A 0.0430.053ΩV GS = - 4.5 V , I D = - 3.1 A 0.0680.086Forward T ransconductance a g fs V DS = - 5 V , I D = - 4.0 A 10S Diode Forward Voltage V SDI S = - 1.0 A, V GS = 0 V- 0.7- 1.2VDynamic bTotal Gate Charge Q g V DS = - 15 V , V GS = - 10 VI D ≅ - 4.0 A1421nCGate-Source Charge Q gs 1.9Gate-Drain Charge Q gd 3.7Input Capacitance C iss V DS = - 15 V, V GS = 0 V , f = 1 MHz540pFOutput CapacitanceC oss 131Reverse Transfer Capacitance C rss105Switching c Turn-On Time t d(on) V DD = - 15 V , R L = 15 ΩI D ≅ - 1.0 A, V GEN = - 10 VR G = 6 Ω1015nst r 1525Turn-Off Timet d(off) 3150t f2030Output CharacteristicsOn-Resistance vs. Drain CurrentGate ChargeCapacitanceOn-Resistance vs. Junction TemperatureSingle Pulse PowerVishay SiliconixSi2343DSTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?72079.Normalized Thermal Transient Impedance, Junction-to-AmbientVishay SiliconixPackage InformationSOT-23 (TO-236): 3-LEADDimMILLIMETERS INCHESMinMaxMinMaxA 0.89 1.120.0350.044A 10.010.100.00040.004A 20.88 1.020.03460.040b 0.350.500.0140.020c 0.0850.180.0030.007D 2.803.040.1100.120E 2.10 2.640.0830.104E 1 1.201.400.0470.055e 0.95 BSC 0.0374 Ref e 1 1.90 BSC0.0748 RefL 0.400.600.0160.024L 10.64 Ref 0.025 Ref S 0.50 Ref0.020 Refq3°8°3°8°ECN: S-03946-Rev. K, 09-Jul-01DWG: 5479AN807Vishay Siliconix Mounting LITTLE FOOT R SOT-23 Power MOSFETsWharton McDanielSurface-mounted LITTLE FOOT power MOSFET s use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFET s, (/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET footprint . In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board.Figure 1 shows the footprint with copper spreading for the SOT-23 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. T o create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the ambient air. This pattern uses all the available area underneath the body for this purpose.FIGURE 1.Footprint With Copper Spreading0.03941.00.0370.95Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically.A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device.Application Note 826Vishay SiliconixA P P L I C A T I O N N O T RECOMMENDED MINIMUM PADS FOR SOT -23Legal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.Material Category PolicyVishay Intertechnology, Inc. hereb y certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.分销商库存信息: VISHAYSI2343DS-T1-GE3。
SIA921EDJ-T1-GE3;中文规格书,Datasheet资料
Vishay SiliconixSiA921EDJDocument Number: Dual P-Channel 20-V (D-S) MOSFETNotes:a.Package limited.b.Surface Mounted on 1" x 1" FR4 board.c.t = 5 s.d.See Solder Profile (/ppg?73257). The PowerPAK SC-70 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.e.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.f.Maximum under Steady State conditions is 110 °C/W.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameter Symbol Limit UnitDrain-Source VoltageV DS - 20VGate-Source VoltageV GS ± 12Continuous Drain Current (T J = 150 °C)T C = 25 °C I D- 4.5a A T C = 70 °C - 4.5aT A = 25 °C - 4.5a, b, c T A = 70 °C - 3.7b, cPulsed Drain CurrentI DM - 15Continuous Source-Drain Diode CurrentT C = 25 °C I S - 4.5aT A = 25 °C - 1.6b, c Maximum Power DissipationT C = 25 °C P D 7.8W T C = 70 °C 5T A = 25 °C 1.9b, c T A = 70 °C 1.2b, cOperating Junction and Storage Temperature RangeT J , T stg - 55 to 150°CSoldering Recommendations (Peak T emperature)d, e260THERMAL RESISTANCE RATINGSParameter Symbol Typical Maximum UnitMaximum Junction-to-Ambient b, f t ≤ 5 s R thJA 5265°C/WMaximum Junction-to-Case (Drain)Steady State R thJC 12.516FEATURES•Halo g en-free Accordin g to IEC 61249-2-21Definition•TrenchFET ® Power MOSFET•New Thermally Enhanced PowerPAK ® SC-70Package- Small Footprint Area - Low On-Resistance•Typical ESD Protection: 1700 V •High Speed Switching•Compliant to RoHS Directive 2002/95/ECAPPLICATIONSPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)Q g (Typ.)- 200.059 at V GS = - 4.5 V - 4.5a 4.9 nC0.098 at V GS = - 2.5 V- 4.5a Document Number: 64734Vishay SiliconixSiA921EDJNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol Test Conditions Min.Typ.Max.UnitStaticDrain-Source Breakdown Voltage V DS V GS = 0 V , I D = - 250 µA- 20V V DS Temperature Coefficient ΔV DS /T J I D = - 250 µA - 14mV/°C V GS(th) Temperature Coefficient ΔV GS(th)/T J 2.5Gate-Source Threshold Voltage V GS(th) V DS = V GS , I D = - 250 µA - 0.5- 1.4VGate-Source LeakageI GSS V DS = 0 V , V GS = ± 4.5 V ± 1 µAV DS = 0 V , V GS = ± 12 V ± 10Zero Gate Voltage Drain Current I DSS V DS = - 20 V , V GS = 0 V - 1V DS = - 20 V , V GS = 0 V , T J = 55 °C- 10On-State Drain Current aI D(on) V DS ≤ - 5 V , V GS = - 4.5 V - 15A Drain-Source On-State Resistance a R DS(on) V GS = - 4.5 V, I D = - 3.6 A 0.0480.059ΩV GS = - 2.5 V, I D = - 1.5 A 0.0800.098Forward T ransconductance a g fsV DS = - 10 V , I D = - 3.6 A11SDynamic bTotal Gate Charge Q g V DS = - 10 V, V GS = - 10 V , I D = - 4.7 A 1523nCV DS = - 10 V, V GS = - 4.5 V , I D = - 4.7 A7.111Gate-Source Charge Q gs 1.3Gate-Drain Charge Q gd 2.1Gate Resistance R g f = 1 MHz6.3ΩTurn-On Delay Time t d(on) V DD = - 10 V , R L = 2.7 ΩI D ≅ - 3.7 A, V GEN = - 4.5 V , R g = 1 Ω2030ns Rise Timet r 2030Turn-Off Delay Time t d(off) 2540Fall Timet f 1015Turn-On Delay Time t d(on) V DD = - 10 V , R L = 2.7 ΩI D ≅ - 3.7 A, V GEN = - 10 V , R g = 1 Ω510Rise Timet r 1220Turn-Off Delay Time t d(off) 2540Fall Timet f1015Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 °C- 4.5A Pulse Diode Forward Current I SM - 15Body Diode VoltageV SD I S = - 3.7 A, V GS = 0 V- 0.9- 1.2V Body Diode Reverse Recovery Time t rr I F = - 3.7 A, dI/dt = 100 A/µs, T J = 25 °C1530ns Body Diode Reverse Recovery Charge Q rr 612nC Reverse Recovery Fall Time t a 8.5nsReverse Recovery Rise Timet b6.5On-Resistance vs. Drain Current and Gate Volta g eDocument Number: Document Number: 64734Vishay SiliconixSiA921EDJTYPICAL CHARACTERISTICS 25°C, unless otherwise notedGate Char g eThreshold Volta g eOn-Resistance vs. Gate-to-Source Volta g eSin g le Pulse Power, Junction-to-AmbientDocument Number: Vishay SiliconixSiA921EDJTYPICAL CHARACTERISTICS 25°C, unless otherwise noted* The power dissipation P D is based on T J(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.Current Deratin g *Power Deratin gSiA921EDJVishay SiliconixTYPICAL CHARACTERISTICS 25°C, unless otherwise notedNormalized Thermal Transient Impedance, Junction-to-AmbientNormalized Thermal Transient Impedance, Junction-to-CaseVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?64734. Document Number: 64734Vishay SiliconixPackage InformationDocument Number: PowerPAK ®DIMSINGLE PADDUAL PADMILLIMETERSINCHES MILLIMETERSINCHESMinNom Max Min Nom Max Min Nom Max Min Nom Max A 0.6750.750.800.0270.0300.0320.6750.750.800.0270.0300.032A10-0.050-0.0020-0.050-0.002b 0.230.300.380.0090.0120.0150.230.300.380.0090.0120.015C 0.150.200.250.0060.0080.0100.150.200.250.0060.0080.010D 1.98 2.05 2.150.0780.0810.085 1.98 2.05 2.150.0780.0810.085D10.850.95 1.050.0330.0370.0410.5130.6130.7130.0200.0240.028D20.1350.2350.3350.0050.0090.013E 1.98 2.05 2.150.0780.0810.085 1.98 2.05 2.150.0780.0810.085E1 1.40 1.50 1.600.0550.0590.0630.850.951.050.0330.0370.041E20.3450.3950.4450.0140.0160.018E30.4250.4750.5250.0170.0190.021e 0.65 BSC 0.026 BSC 0.65 BSC 0.026 BSC K 0.275 TYP 0.011 TYP 0.275 TYP 0.011 TYP K10.400 TYP 0.016 TYP 0.320 TYP 0.013 TYP K20.240 TYP 0.009 TYP 0.252 TYP0.010 TYPK30.225 TYP 0.009 TYP K40.355 TYP 0.014 TYP L 0.1750.2750.3750.0070.0110.0150.1750.2750.3750.0070.0110.015T0.050.100.150.0020.0040.006ECN: C-07431 − Rev. C, 06-Aug-07DWG: 5934Application Note 826Vishay SiliconixA P P L I C A T I O N N O T ERECOMMENDED PAD LAYOUT FOR PowerPAK ®SC70-6L DualReturn to IndexLegal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.Material Category PolicyVishay Intertechnology, Inc. hereb y certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.Revision: 12-Mar-121Document Number: 91000分销商库存信息: VISHAYSIA921EDJ-T1-GE3。
SQJ964EP-T1-GE3;中文规格书,Datasheet资料
Automotive Dual N-Channel 60 V (D-S) 175 °C MOSFETFEATURES•Halogen-free According to IEC 61249-2-21Definition•TrenchFET ® Power MOSFET •AEC-Q101 Qualified d•100 % R g and UIS Tested•Compliant to RoHS Directive 2002/95/ECNotesa.Package limited.b.Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.c.When mounted on 1" square PCB (FR-4 material).d.Parametric verification ongoing.e.See solder profile (/doc?73257). The PowerPAK SO-8L. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.f.Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.PRODUCT SUMMARYV DS (V)60R DS(on) (Ω) at V GS = 10 V 0.028I D (A) per leg 8ConfigurationDualORDERING INFORMATIONPackagePowerPAK SO-8L Lead (Pb)-free and Halogen-freeSQJ964EP-T1-GE3ABSOLUTE MAXIMUM RATINGS (T C = 25 °C, unless otherwise noted)PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS60VGate-Source Voltage V GS ± 20Continuous Drain Current aT C = 25 °C I D 8A T C = 125 °C8Continuous Source Current (Diode Conduction)a I S 8Pulsed Drain Current bI DM 32Single Pulse Avalanche Current L = 0.1 mH I AS 25Single Pulse Avalanche Energy E AS 31mJ Maximum Power Dissipation bT C = 25 °C P D 35W T C = 125 °C 11Operating Junction and Storage Temperature Range T J , T stg- 55 to + 175°C Soldering Recommendations (Peak Temperature)e, f260THERMAL RESISTANCE RATINGSARAMETER SYMBOL LIMIT UNIT Junction-to-Ambient PCB Mount cR thJA 85°C/WJunction-to-Case (Drain)R thJC4.2Notesa.Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.b.Guaranteed by design, not subject to production testing.c.Independent of operating temperature.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS (T C = 25 °C, unless otherwise noted)PARAMETER SYMBOLTEST CONDITIONS MIN.TY P .MAX.UNITStaticDrain-Source Breakdown Voltage V DS V GS = 0, I D = - 250 μA 60--V Gate-Source Threshold Voltage V GS(th)V DS = V GS , I D = - 250 μA 3.4 3.8 4.5Gate-Source LeakageI GSS V DS = 0 V, V GS = ± 20 V--± 100nAZero Gate Voltage Drain Current I DSS V GS = 0 V V DS = 60 V --1μA V GS = 0 V V DS = 60 V, T J = 125 °C --50V GS = 0 V V DS = 60 V, T J = 175 °C--150On-State Drain Current aI D(on) V GS = 10 V V DS ≥ 5 V 30--A Drain-Source On-State Resistance a R DS(on) V GS = 10 V I D = 9.6 A -0.0200.028ΩV GS = 10 V I D = 9.6 A, T J = 125 °C -0.0330.046V GS = 10 VI D = 9.6 A, T J = 175 °C-0.0400.055Forward Transconductance b g fsV DS = 15 V, I D = 9.6 A-30-S Dynamic bInput Capacitance C issV GS = 0 V V DS = 30 V, f = 1 MHz -23602900pFOutput CapacitanceC oss -155190Reverse Transfer Capacitance C rss -7390Total Gate Charge c Q gV GS = 10 VV DS = 30 V, I D = 9.6 A -3857nC Gate-Source Charge c Q gs -12.5-Gate-Drain Charge c Q gd -8-Gate Resistance R g f = 1 MHz123ΩTurn-On Delay Time c t d(on)V DD = 20 V, R L = 20 Ω I D ≅ 1 A, V GEN = 10 V, R g = 6.0 Ω-1725ns Rise Time ct r-1116Turn-Off Delay Time c t d(off) -3745Fall Time c t f -1015Source-Drain Diode Ratings and Characteristics bPulsed Current a I SM --32A Forward VoltageV SDI F = 2.9 A, V GS = 0-0.81.1VTYPICAL CHARACTERISTICS(T A = 25 °C, unless otherwise noted)Output Characteristics TransconductanceCapacitanceTransfer CharacteristicsOn-Resistance vs. Drain CurrentGate ChargeTYPICAL CHARACTERISTICS(T A = 25 °C, unless otherwise noted)On-Resistance vs. Junction Temperature On-Resistance vs. Gate-to-Source VoltageSource Drain Diode Forward VoltageDrain-Source Breakdown vs. Junction Temperature Threshold VoltageTHERMAL RATINGS(T A = 25 °C, unless otherwise noted)Safe Operating AreaNormalized Thermal Transient Impedance, Junction-to-AmbientTHERMAL RATINGS(T A = 25 °C, unless otherwise noted)Normalized Thermal Transient Impedance, Junction-to-CaseNote•The characteristics shown in the two graphs- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)- Normalized Transient Thermal Impedance Junction-to-Case (25 °C)are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities can widely vary depending on actual application parameters and operating conditions.Vishay Silico nix maintains wo rldwide manufacturing capability. Pro ducts may be manufactured at o ne o f several qualified lo catio ns. Reliability data fo r Silico n Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?65167.PowerPAK® SO-8L Case OutlineNote•Millimeters will goverLIMETERSINCHESMIN.NOM.MAX.MIN.NOM.MAX.A 1.00 1.07 1.140.0390.0420.045A10.00-0.1270.00-0.005b 0.330.410.480.0130.0160.019b10.440.510.580.0170.0200.023b2 4.804.905.000.1890.1930.197b30.0940.004b40.470.019c 0.200.250.300.0080.0100.012D 5.00 5.13 5.250.1970.2020.207D1 4.80 4.90 5.000.1890.1930.197D2 3.86 3.96 4.060.1520.1560.160D3 1.63 1.73 1.830.0640.0680.072e 1.27 BSC 0.050 BSC E 6.05 6.15 6.250.2380.2420.246E14.27 4.37 4.470.1680.1720.176E2 (for Al product) 2.75 2.85 2.950.1080.1120.116E2 (for other product)3.18 3.28 3.380.1250.1290.133F --0.15--0.006L 0.620.720.820.0240.0280.032L10.921.07 1.220.0360.0420.048K 0.510.020W 0.230.009W10.410.016W2 2.820.111W3 2.960.1170°-10°0°-10°ECN: C12-0026-Rev. B, 27-Aug-12DWG: 5976Legal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.Material Category PolicyVishay Intertechnology, Inc. hereb y certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.分销商库存信息: VISHAYSQJ964EP-T1-GE3。
总磷 安卓屏 泽天版 操作说明书
Vishay Siliconix S20-0283-Rev. A数据手册说明书
SISS32ADN-T1-GE3SiSS32ADNVishay SiliconixN-Channel 80 V (D-S) MOSFETFEATURES•TrenchFET ® Gen IV power MOSFET •Very low R DS - Q g figure-of-merit (FOM)•Tuned for the lowest R DS - Q oss FOM •100 % R g and UIS tested•Material categorization: for definitions ofcompliance please see /doc?99912APPLICATIONS•Synchronous rectification •Primary side switch •DC/DC converter •Solar micro inverter •Motor drive switch•Battery and load switch •IndustrialNotesa.Package limitedb.Surface mounted on 1" x 1" FR4 boardc.t = 10 sd.See solder profile (/doc?73257). The PowerPAK 1212-8S is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnectione.Rework conditions: manual soldering with a soldering iron is not recommended for leadless componentsf.Maximum under steady state conditions is 63 °C/Wg.T C = 25 °CPRODUCT SUMMARYV DS (V)80R DS(on) max. (Ω) at V GS = 10 V 0.0073R DS(on) max. (Ω) at V GS = 7.5 V 0.0087Q g typ. (nC)18.5I D (A)63ConfigurationSinglePowerPAK ® 1212-8STop View3.3 m m3 1.3mm Bottom ViewD 8D 7D 6D 51S2S3S4GORDERING INFORMATIONPackagePowerPAK 1212-8S Lead (Pb)-free and halogen-freeSiSS32ADN-T1-GE3ABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise noted)PARAME T ERSYMBOL LIMI T UNIT Drain-source voltage V DS 80VGate-source voltageV GS ± 20Continuous drain current (T J = 150 °C)T C = 25 °C I D63AT C = 70 °C 50.3T A = 25 °C 17.4 b, c T A = 70 °C13.9 b, cPulsed drain current (t = 100 μs)I DM 120Continuous source-drain diode current T C = 25 °C I S59.7T A = 25 °C 4.5 b, cSingle pulse avalanche current L = 0.1 mH I AS 20Single pulse avalanche energyE AS20mJ Maximum power dissipationT C = 25 °CP D65.7WT C = 70 °C42T A = 25 °C 5 b, c T A = 70 °C3.2 b, cOperating junction and storage temperature range T J , T stg -55 to +150°CSoldering recommendations (peak temperature) c260THERMAL RESISTANCE RATINGSPARAME T ER SYMBOL T YPICAL MAXIMUM UNI T Maximum junction-to-ambient b t ≤ 10 s R thJA 2025°C/WMaximum junction-to-case (drain)Steady state R thJC1.5 1.9SiSS32ADNVishay SiliconixNotesa.Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %b.Guaranteed by design, not subject to production testingStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS (T J = 25 °C, unless otherwise noted)PARAME T ER SYMBOL T ES T CONDI T IONS MIN.T YP.MAX.UNI T StaticDrain-source breakdown voltage V DS V GS = 0 V, I D = 250 μA80--V V DS temperature coefficient ∆V DS /T J I D = 1 mA -62-mV/°C V GS(th) temperature coefficient ∆V GS(th)/T J I D = 250 μA --7.3-Gate-source threshold voltage V GS(th)V DS = V GS , I D = 250 μA 2- 3.6V Gate-source leakageI GSS V DS = 0 V, V GS = ± 20 V --100nA Zero gate voltage drain current I DSS V DS = 80 V, V GS = 0 V --1μA V DS = 80 V, V GS = 0 V, T J = 70 °C--15On-state drain current aI D(on)V DS ≥ 10 V, V GS = 10 V 40--A Drain-source on-state resistance a R DS(on)V GS = 10 V, I D = 10 A -0.00610.0073ΩV GS = 7.5 V, I D = 10 A -0.00710.0087Forward transconductance a g fs V DS = 15 V, I D = 10 A-65-SDynamic bInput capacitance C iss V DS = 40 V, V GS = 0 V, f = 1 MHz-1520-pF Output capacitanceC oss -252-Reverse transfer capacitance C rss -16-Total gate charge Q gV DS = 40 V, V GS = 10 V, I D = 10 A -2436nC V DS = 40 V, V GS = 7.5 V, I D =10 A -18.528Gate-source charge Q gs -7.2-Gate-drain charge Q gd - 4.3-Output charge Q oss V DS = 40 V, V GS = 0 V-33-Gate resistance R g f = 1 MHz0.30.9 1.6ΩTurn-on delay time t d(on)V DD = 40 V, R L = 4 Ω, I D ≅ 10 A,V GEN = 10 V, R g = 1 Ω-1224ns Rise timet r -612Turn-off delay time t d(off)-2040Fall timet f -612Turn-on delay time t d(on)V DD = 40 V, R L = 4 Ω, I D ≅ 10 A,V GEN = 7.5 V, R g = 1 Ω-1428Rise timet r -612Turn-off delay time t d(off)-1836Fall timet f-612Drain-Source Body Diode Characteristics Continuous source-drain diode current I S T C = 25 °C --59.7A Pulse diode forward current I SM --120Body diode voltageV SD I S = 5 A, V GS = 0 V -0.75 1.1V Body diode reverse recovery time t rr I F = 10 A, di/dt = 100 A/μs,T J = 25 °C-3774ns Body diode reverse recovery charge Q rr -3570nC Reverse recovery fall time t a -23-nsReverse recovery rise timet b-14-SiSS32ADNVishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Output CharacteristicsOn-Resistance vs. Drain CurrentGate Charge Transfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureSiSS32ADNVishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Source-Drain Diode Forward VoltageOn-Resistance vs. Gate-to-Source VoltageThreshold VoltageSingle Pulse Power, Junction-to-AmbientSafe Operating Area, Junction-to-AmbientNotea.V GS > minimum V GS at which R DS(on) is specifiedSiSS32ADNVishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Current Derating aPower, Junction-to-Case Power, Junction-to-AmbientNotea.The power dissipation P D is based on T J max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below thepackage limitSiSS32ADN Vishay SiliconixTYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)Normalized Thermal Transient Impedance, Junction-to-CaseVishay Silico nix maintains wo rldwide manufacturing capability. Pro ducts may be manufactured at o ne o f several qualified lo catio ns. Reliability data fo r Silico n Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see /ppg?77851.Legal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.© 2019 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVEDSISS32ADN-T1-GE3。
OM5193资料
• 3-phase output motor driver • 1.9 A maximum available start-up current • Total Rds(on) = 0.6 Ω (typical) at 25 °C • Back ElectroMotive Force (BEMF) processing for sensorless motor commutation • Linear current control • External current sense resistor • External current control loop compensation • Adjustable slew rate control • Short-circuit brake • Adjustable brake-after-park delay time. 1.2.2 VOICE COIL MOTOR DRIVER
Philips Semiconductors
Product specification
Disk drive spindle and VCM with servo controller
CONTENTS 1 1.1 1.2 1.2.1 1.2.2 1.3 2 3 3.1 3.2 3.3 3.4 4 5 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.17.1 8.17.2 8.18 FEATURES Servo control Motor control Spindle motor driver Voice coil motor driver Miscellaneous items APPLICATIONS GENERAL DESCRIPTION Overview Servo controller Spindle and voice coil motor Safety functions QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAMS PINNING FUNCTIONAL DESCRIPTION Serial interface Commutation and sleep mode Commutation control Blanks, Watchdog and Start-up delays Comdelim delay 10-bit ADC with 7 analog inputs Input channels Input ranges Conversion modes Programming register#0 Converter clock frequency values 10-bit VCM DAC Reference voltage Stand-alone op-amps Analog switch Charge pump voltage Spindle driver VCM driver Park the VCM Precharge the VCM Brake the motor Power-on reset Thermal monitor and shutdown Power supply isolation External isolation diode External power FET Thermal behaviour 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 LIMITING VALUES HANDLING
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N- and P-Channel 20-V (D-S) MOSFETFEATURES•Halogen-free According to IEC 61249-2-21Definition•TrenchFET ® Power MOSFETs•Typical ESD Protection: N-Channel 2000 VP-Channel 1900 V •100 % R g Tested•Compliant to RoHS Directive 2002/95/ECPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)Q g (Typ.)N-Channel 200.040 at V GS = 4.5 V 4.5a 3.7 nC 0.065 at V GS = 2.5 V 4.5a P-Channel- 200.090 at V GS = - 4.5 V - 4.5a 5.3 nC0.137 at V GS = - 2.5 V- 4.5aNotes:a.Package Limited.b.Surface Mounted on 1" x 1" FR4 board.c.t = 5 s.d.See Solder Profile (/ppg?73257). The PowerPAK SC-70 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.e.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.f.Maximum under Steady State conditions is 110 °C/W.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameter Symbol N-Channel P-Channel UnitDrain-Source VoltageV DS 20- 20VGate-Source VoltageV GS ± 12Continuous Drain Current (T J = 150 °C)T C = 25 °C I D 4.5a - 4.5a A T C = 70 °C 4.5a- 4.5a T A = 25 °C 4.5a, b, c - 3.7b, c T A = 70 °C 4.4b, c- 3b, c Pulsed Drain Current I DM 15- 15Source Drain Current Diode CurrentT C = 25 °C I S 4.5a - 4.5aT A = 25 °C 1.6b, c - 1.6b, c Maximum Power Dissipation T C = 25 °C P D 7.87.8W T C = 70 °C 55T A = 25 °C 1.9b, c 1.9b, c T A = 70 °C 1.2b, c1.2b, c Operating Junction and Storage T emperature Range T J , T stg - 55 to 150°C Soldering Recommendations (Peak Temperature)d, e260THERMAL RESISTANCE RATINGSParameter Symbol N-ChannelP-ChannelUnitTyp.Max.Typ.Max.Maximum Junction-to-Ambient b, f t ≤ 5 s R thJA 52655265°C/WMaximum Junction-to-Case (Drain)Steady State R thJC 12.51612.516Notes:a. Guaranteed by design, not subject to production testing.b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol Test Conditions Min. Typ.Max.UnitStaticDrain-Source Breakdown Voltage V DS V GS = 0 V, I D = 250 µA N-Ch 20VV GS = 0 V , I D = - 250 µAP-Ch - 20V DS Temperature Coefficient ΔV DS /T J I D = 250 µA N-Ch 23mV/°CI D = - 250 µA P-Ch - 11V GS(th) Temperature Coefficient ΔV GS(th)/T J I D = 250 µA N-Ch - 3.3I D = - 250 µA P-Ch 2.6Gate Threshold VoltageV GS(th)V DS = V GS , I D = 250 µA N-Ch 0.6 1.4V V DS = V GS , I D = - 250 µA P-Ch - 0.5- 1.3Gate-Body LeakageI GSSV DS = 0 V , V GS = ± 4.5 VN-Ch ± 0.5 µA P-Ch ± 0.5 V DS = 0 V , V GS = ± 12 V N-Ch ± 90P-Ch ± 8Zero Gate Voltage Drain CurrentI DSSV DS = 20 V , V GS = 0 VN-Ch 1V DS = - 20 V, V GS = 0 V P-Ch - 1V DS = 20 V , V GS = 0 V , T J = 55 °C N-Ch 10V DS = - 20 V , V GS = 0 V , T J = 55 °CP-Ch - 10On-State Drain CurrentbI D(on)V DS ≥ 5 V , V GS = 4.5 V N-Ch 10AV DS ≤ - 5 V , V GS = - 4.5 V P-Ch - 10Drain-Source On-State Resistance b R DS(on)V GS = 4.5 V , I D = 4.2 A N-Ch 0.0320.040ΩV GS = - 4.5 V , I D = - 2.9 A P-Ch 0.0740.090V GS = 2.5 V , I D = 3.3 A N-Ch 0.0530.065V GS = - 2.5 V , I D = - 2.3 A P-Ch 0.1130.137Forward T ransconductance b g fsV DS = 10 V , I D = 4.2 A N-Ch 12S V DS = - 10 V , I D = - 2.9 AP-Ch 7Dynamic aInput Capacitance C iss N-ChannelV DS = 10 V , V GS = 0 V , f = 1 MHz P-ChannelV DS = - 10 V, V GS = 0 V , f = 1 MHz N-Ch350pFP-Ch 340Output CapacitanceC oss N-Ch 82P-Ch 105Reverse Transfer CapacitanceC rssN-Ch 50P-Ch 95Total Gate ChargeQ gV DS = 10 V , V GS = 10 V , I D = 5.5 AN-Ch 7.712nC V DS = - 10 V , V GS = - 10 V, I D = - 3.7 A P-Ch 10.516N-ChannelV DS = 10 V, V GS = 4.5 V , I D = 5.5 AP-ChannelV DS = - 10 V , V GS = - 4.5 V , I D = - 3.7 AN-Ch 3.76P-Ch 5.38Gate-Source Charge Q gs N-Ch 0.85P-Ch 0.75Gate-Drain Charge Q gd N-Ch 0.95P-Ch 2Gate ResistanceR gf = 1 MHzN-Ch 0.7 3.57ΩP-Ch0.21020Notes:a. Guaranteed by design, not subject to production testing.b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol Test Conditions Min. Typ.Max.UnitDynamic aT urn-On Delay Time t d(on) N-ChannelV DD = 10 V , R L = 2.3 Ω I D ≅ 4.4 A, V GEN = 4.5 V , R g = 1 ΩP-ChannelV DD = - 10 V, R L = 3.3 Ω I D ≅ - 3 A, V GEN = - 4.5 V, R g = 1 ΩN-Ch1015nsP-Ch 2030Rise Timet r N-Ch 1220P-Ch 2030T urn-Off Delay Time t d(off) N-Ch 2135P-Ch 2540Fall Timet f N-Ch 1625P-Ch 1015T urn-On Delay Time t d(on) N-ChannelV DD = 10 V , R L = 2.3 Ω I D ≅ 4.4 A, V GEN = 10 V , R g = 1 ΩP-ChannelV DD = - 10 V, R L = 3.3 Ω I D ≅ - 3 A, V GEN = - 10 V , R g = 1 ΩN-Ch510P-Ch 510Rise Timet r N-Ch 1015P-Ch 1015T urn-Off Delay Time t d(off) N-Ch 1525P-Ch 2030Fall Timet fN-Ch 1015P-Ch1015Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 °CN-Ch 4.5AP-Ch - 4.5Pulse Diode Forward Current a I SM N-Ch 15P-Ch - 15Body Diode VoltageV SD I S = 4.4 A, V GS = 0 V N-Ch 0.8 1.2V I S = - 3 A, V GS = 0 VP-Ch - 0.8- 1.2Body Diode Reverse Recovery Time t rr N-ChannelI F = 4.4 A, dI/dt = 100 A/µs, T J = 25 °C P-ChannelI F = - 3 A, dI/dt = - 100 A/µs, T J = 25 °CN-Ch 1530ns P-Ch 2650Body Diode Reverse Recovery Charge Q rr N-Ch 820nC P-Ch 1325Reverse Recovery Fall Time t a N-Ch 8nsP-Ch 14Reverse Recovery Rise Timet bN-Ch 7P-Ch12N-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise notedOn-Resistance vs. Drain Current and Gate VoltageCapacitanceN-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise notedGate ChargeSingle Pulse Power (Junction-to-Ambient)N-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted* The power dissipation P D is based on T J(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.N-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise notedNormalized Thermal Transient Impedance, Junction-to-AmbientNormalized Thermal Transient Impedance, Junction-to-CaseOn-Resistance vs. Drain Current and Gate VoltageTransfer CharacteristicsCapacitanceP-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise notedGate ChargeP-CHANNEL TYPICAL CHARACTERISTICS 25°C, unless otherwise noted* The power dissipation P D is based on T J(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.Current Derating*Power Derating分销商库存信息: VISHAYSIA519EDJ-T1-GE3。