iMX23 25 28 区别

Freescale Semiconductor
Application Note
1Introduction
This application note describes the key architectural differences between the i.MX23, i.MX25, and i.MX28 ARM® based 32-bit applications processors. This application note provides an overview on several aspects of these processors which includes core, security, peripherals, and connectivity. It compares the different features of the processors.
2Overview
The i.MX23 is a System on Chip (SoC) designed for applications such as portable media players, portable navigation devices and other handheld multimedia devices that require low-power, high performance and integration, and quality audio and video playback. The 90 nm SoC is based on the ARM926EJ-S TM core, coupled with the
on-chip audio and power management functions. This highly integrated SoC eliminates the use of discrete ICs(more than 10 in number) found in the portable navigation devices. Unlike the other ICs based on the ARM9TM core, the
i.MX23 integrates the analog functions on the same silicon die as that of the processor. For more information, refer to the
Document Number:AN4198
Rev. 0, 09/2010
Contents
1.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3.System Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.External Memory and Storage . . . . . . . . . . . . . . . . . 12
6.Audio Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.Display and Video . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 29
work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
munications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Architectural Differences between the i.MX23, i.MX25, and i.MX28
by Multimedia Applications Division
Freescale Semiconductor, Inc.
Austin, TX
Overview
i.MX23 Applications Processor Reference Manual (IMX23RM) and i.MX23 Applications Processor Data Sheet (IMX23EC).
The i.MX25 multimedia applications processor includes several key features that allow the user to reduce the overall system bill of materials cost such as Double Data Rate 2 (DDR2) support, two embedded USB PHYs, 3.3 V I/O support, general purpose 12-bit Analog to Digital Converters (ADCs), and Touch Screen Controller (TSC). In addition, the i.MX25 makes the industrial and general embedded market a key focus, with the integration of 10/100 Ethernet Media Access Control (MAC), Secure Digital Input/Output (SDIO) connectivity, resolution up to Super Video Graphics Array (SVGA) (800 × 600) Thin Film Transistor (TFT) Liquid Crystal Display (LCD) support, camera sensor interface, and 400 MHz CPU speed grade. The i.MX25 processor provides an additional tamper detection security that monitors and helps to prevent against system integrity attacks from hackers. Therefore, the i.MX25 processor is recommended for any type of secure device (wired or wireless payment terminal, Point-of-Scale (POS)), or any other type of product that requires secure system boot and tamper detection. The i.MX25 also complements the i.MX ARM11TM portfolio by maintaining a large share of peripheral commonality with the i.MX35 multimedia applications processor family. For more information, refer to the i.MX25 Multimedia Applications Processor Reference Manual (IMX25RM), i.MX25 Applications Processor for Consumer and Industrial Products (IMX25CEC), and i.MX25 Applications Processor for Automotive Products (IMX25AEC).
The i.MX28 is a low-power, high performance applications processor optimized for the general embedded industrial and consumer markets. The i.MX28 is based on the ARM926EJ-S core with speed up to
454MHz coupled with the Power Management Unit (PMU). The i.MX28 can be connected to the devices such as high speed USB, Controller Area Network (CAN), Secured Digital (SD)/SDIO/Multi Media Card (MMC) and 10M/100M Ethernet. The i.MX28 is suitable for a wide range of applications including Human Machine Interface (HMI) panels, industrial drive, Programmable Logic Controller (PLC), I/O control display, factory robotics display, handle scanners and printers, POS terminals, patient monitoring devices, and smart energy meters.For more information, refer to the i.MX28 Applications Processor Reference Manual (IMX28RM), i.MX28 Applications Processor Data Sheet for Consumer and Industrial Products (IMX28CEC), and i.MX28 Applications Processor Data Sheet for Automotive Products (IMX28AEC).
Table1 provides the features of the i.MX23, i.MX25, and i.MX28 processors.
Table1. Features of the i.MX23, i.MX25, and i.MX28 Processors
Feature i.MX23i.MX25i.MX28
System Core
Micro Controller Unit (MCU) core ARM926EJ-S, 454 MHz ARM926EJ-S, 400 MHz ARM926EJ-S, 454 MHz
Caches16-Kbyte data and
16-Kbyte instruction 16-Kbyte data and
16-Kbyte instruction
32-Kbyte data and
16-Kbyte instruction
On-chip RAM32 Kbyte128 Kbyte128 Kbyte On-chip ROM64 Kbyte32 Kbyte128 Kbyte On-chip Secure RAM N/A 2 Kbyte N/A
On-Chip One-Time-Progammable (OCOTP)1 Kbit IC Identification Module
(IIM)
1280 bit
Overview
Embedded T race Macrocell (ETM)Y es
Y es
Y es
Joint T est Action Group (JT AG) Interface 1-wire serial/6-wire parallel
Secure JT AG (parallel only)6-wire parallel
Security Features Security hardware
Data Co-Processor (DCP):
•Advanced Encryption Standard (AES) •Hashing
Runtime Integrity Checker v3 (RTICv3)
Secure RAM Module and Security Monitor (SCCv3)DryIce
Random Number Generator (RNGB)DCP: •AES •Hashing
One-Time programmable storage 1-Kbit OCOTP ROM IIM 1280-bit OCOTP ROM Secure RAM N/A 2 Kbyte N/A Secure JT AG N/A
Y es
N/A
Secure Boot
128-bit AES hardware decryption
High Assurance Boot (HAB) with SHA-256
128-bit AES hardware decryption
HAB with SHA-256
External Memory and Storage Memory and storage hardware interface
External Memory Interface (EMI)
General Purpose Media Interface (GPMI) •NAND Flash
Synchronous Serial Port (SSP)
EMI
•Multi-Master Memory Interface (M3IF) •Enhanced SDRAM Controller (ESDRAMC) •NAND Flash Controller (NFC)
•Wireless Extension Interface Module (WEIM)
Advanced T echnology Attachment (AT A)Enhanced SD Host Interface (eSDHC)EMI GPMI
•NAND Flash SSP
SDRAM
2.5V DDR1
1.8V Mobile DDR (mDDR)
3.3V SDRAM 1.8V DDR21.8V mDDR
1.8V DDR21.8V mDDR
1.5V Low Power DDR2 (LP-DDR2)
NAND Flash
Four 8-bit/16-bit NAND Single Level Cell
(SLC)/Multiple Level Cell (MLC) NAND
8-bit Reed-Solomon Error Correction Code (ECC)20-bit BCH ECC Four 8-bit/16-bit NAND SLC/MLC NAND
8-bit Reed Solomon ECC Internal RAM Buffer
Eight 8-bit/16-bit NAND SLC/MLC NAND 20-bit BCH ECC
NOR Flash N/A
Y es N/A
Table 1. Features of the i.MX23, i.MX25, and i.MX28 Processors (continued)
Feature
i.MX23
i.MX25
i.MX28
Overview
AT A N/A UDMA-5N/A
SD/MMC eMMC 4.2, eMMC 4.3
(limited)
eMMC 4.3eMMC 4.3, eMMC 4.4 Audio Features
Serial audio interface Dual Serial Audio
Interface (SAIF)
half-duplex Enhanced Serial Audio
Interface (ESAI)
full-duplex
Dual SAIF
half-duplex
Sony-Philips Digital Interface Format
(SPDIF) digital audio out
Y es N/A Y es
Digital audio multiplexer N/A Y es N/A
Analog audio outputs Stereo headphone
amplifier
Mono speaker amplifier
N/A N/A
Analog audio inputs Mono microphone input
T wo stereo line inputs
N/A N/A
Display and Video
LCD Interface (LCDIF)Y es Y es Y es
Resolution Up to 640 × 480Up to 800 × 600Up to 800 × 480
Bit/Pixel8, 16, 18, 24 (color)1, 2, 4 (mono)
4, 8, 12, 16, 18, 24 (color)
8, 16, 18, 24 (color) TV-Out Y es N/A N/A
Display processing Pixel Processing Pipeline
(PXP)
8 Overlays
Color key/Alpha blend
Color space conversion
and scaling
Rotation 1 Overlay (Graphic window)
Color key/Alpha blend
Panning
PXP
8 Overlays
Color key/Alpha blend
Color space conversion
and scaling
Rotation
CMOS Sensor Interface (CSI)N/A Y es N/A
Linear image scanner interface N/A N/A High Speed Analog to
Digital Conversion
(HSADC)
Power Management
Internal power supply DC-DC switched
converter
Four linear regulators
• 3.3 V
• 1.2 V
• 1.8 V
• 2.5 V N/A DC-DC switched
converter
Four linear regulators
• 3.3 V
• 1.2 V
• 1.8 V
• 1.5 V
Table1. Features of the i.MX23, i.MX25, and i.MX28 Processors (continued) Feature i.MX23i.MX25i.MX28
Overview
Power management
Adaptive Voltage Control (AVC)
CLK_H auto-slow Clock gating
Silicon speed sensor Multiple peripheral clock (domains)Dynamic Voltage and
Frequency Scaling (DVFS)Clock gating
Active Well Bias (AWB)
AVC
CLK_H auto-slow Clock gating
Silicon speed sensor Multiple peripheral clock (domains)Low-power mode
Standby Deep-sleep
Wait Doze Stop Sleep
Standby Deep-sleep
Network Ethernet
N/A One Fast Ethernet
Controller (FEC) 10/100T wo Ethernet Controller (ENET) 10/100IEEE1588 Hardware Timestamp N/A N/A Y es 3-port L2 switch N/A N/A
Y es
CAN
N/A
Dual CAN (FlexCAN)
Dual CAN (FlexCAN)
Communications
Universal Asynchronous Receiver/Transmitter (UART)Three
Five
Six
UART speed
Up to 3.25 mega bits per second (Mbps)Up to 4 Mbps
Up to 3.25 Mbps Infrared Data Association (IrDA)N/A UART IrDA compatible N/A I 2C interface
One Three
T wo
Serial Peripheral Interface (SPI)
SSP
Configurable Serial
Peripheral Interface (CSPI)Synchronous Serial Interface (SSI)SSP Subscriber Identification Module (SIM)N/A Y es N/A 1-wire module N/A Y es N/A SDIO Rev. 2.0Y es
Y es
Y es
I/O Modules USB 2.0 High Speed
1 HS port (Host) with HS PHY (does not support
LS)
1 HS port (On-The-Go
(OTG)) with HS PHY and 1 HS port (Host) with FS PHY 1 HS port (OTG) with HS PHY and 1 HS port (Host) with HS PHY Pulse Width Modulator (PWM)Five channels Four channels Eight channels General Purpose I/O (GPIO)Y es
Y es Y es
Input/Output Multiplexer (IOMUX)
Pin multiplexing scheme
Y es
Pin multiplexing
scheme
Table 1. Features of the i.MX23, i.MX25, and i.MX28 Processors (continued)
Feature
i.MX23
i.MX25
i.MX28
System Core
3System Core
The core of the i.MX23, i.MX25, and i.MX28 is fast, proven, power efficient implementation of the ARM926EJ-S core. These processors include a stand-alone ARM CoreSight Embedded Trace Marcocell, ETM9CSSingle that provides instruction trace and data trace for the ARM9 microprocessor.
Low Resolution ADC (LRADC)Y es (12-bit resolution)Y es (12-bit resolution)Y es (12-bit resolution)TSC
Y es (4-wire resistive)Y es (4-wire or 5-wire resistive)Y es (4-wire or 5-wire resistive)Keypad Port (KPP)N/A
Y es
N/A
Boot Modes I 2C Y es Y es Y es SPI Y es Y es Y es SD/MMC Y es Y es Y es NAND Y es Y es Y es JT AG Y es Y es Y es NOR Flash N/A Y es N/A USB Y es N/A Y es UART N/A Y es N/A WEIM
N/A
Y es
N/A
Table 1. Features of the i.MX23, i.MX25, and i.MX28 Processors (continued)
Feature
i.MX23
i.MX25
i.MX28
System Core Figure1 shows the ARM926 RISC processor core.
Figure1. ARM926 RISC Processor Core
Table2 shows the comparison of the system core features of the i.MX23, i.MX25, and i.MX28.
Table2. Comparison of System Core Features
Feature i.MX23i.MX25i.MX28
MCU core ARM926EJ-S, 454 MHz ARM926EJ-S, 400 MHz ARM926EJ-S, 454 MHz
Cache16-Kbyte data and 16-Kbyte
instruction 16-Kbyte data and 16-Kbyte
instruction
32-Kbyte data and
16-Kbyte instruction
On-chip RAM32 Kbyte128 Kbyte128 Kbyte
On-chip ROM64 Kbyte32 Kbyte128 Kbyte
On-chip Secure RAM N/A 2 Kbyte N/A
OCOTP 1 Kbit IIM1280 bit ETM Y es Y es Y es
JTAG Interface1-wire serial/6-wire parallel Secure JTAG (parallel only)6-wire parallel
System Core
3.1i.MX23 System Core
The i.MX23 can run up to 454 MHz. The i.MX23 includes a 16-Kbyte data cache, 16-Kbyte instruction cache, 32-Kbyte on-chip RAM, and 64-Kbyte on-chip ROM. The i.MX23 includes a serial JTAG module that maps 1-wire protocol to 6-wire JTAG interface. The HW_DIGCTL_USE_SERIAL_JTAG bit in the digital control block selects the serial or parallel JTAG to be used. The default configuration is set by the USE_PARALLEL_JTAG bit in HW_OCOTP_ROM0 in the OCOTP ROM. It is loaded by the ROM code during the boot up. If the bit is not blown, the serial JTAG is used by default.
The i.MX23 includes a 1-Kbit OCOTP ROM to store the hardware and software capability bits, ROM configuration bits, processor operations, and unique-ID fields. The OCOTP ROM can also be used to store customer programmable cryptography key. Four words storage is also available for general use. In addition, a 32-bit word is dedicated to control the read and write locking of several
One-Time-Programmable (OTP) regions that are copied into the shadow register.
3.2i.MX25 System Core
The i.MX25 can run up to 400 MHz. The i.MX25 includes a 16-Kbyte data cache, 16-Kbyte instruction cache, 128-Kbyte on-chip RAM, 32-Kbyte on-chip ROM, and 2-Kbyte on-chip secure RAM to store sensitive information. The i.MX25 includes a secure JTAG port which protects the debug port from system integrity attack by regulating or blocking the access to the system debug features.
The i.MX25 has an IIM which provides the primary user visible mechanism for interfacing with the
on-chip fuse elements. The fuses are used for unique chip identifiers, mask version numbers, cryptographic keys, and several control signals that require permanent non-volatility. The IIM can also provide up to 28 volatile control signals and can generate a second 168-bit SCC key.
3.3i.MX28 System Core
The i.MX28 can run up to 454 MHz. The i.MX28 includes 32-Kbyte data cache, 16-Kbyte instruction cache, 128-Kbyte on-chip RAM, and 128-Kbyte on-chip ROM. The i.MX28 includes a 6-wire parallel JTAG interface for debugging.
The i.MX28 includes 1280 bits of OCOTP ROM to store hardware and software capability bits, ROM configuration bits, processor operations, and unique-ID fields. The OCOTP ROM can also be used to store customer programmable cryptography key. Four words storage is also available for general purpose. In addition, a 32-bit word is dedicated to control the read and write locking of several OTP regions, which are copied into the shadow register.
Security Features
4Security Features
Table 3 shows a comparison of the security features of the i.MX23, i.MX25, and i.MX28.
4.1Security Hardware
The security hardware features of the i.MX23, i.MX25, and i.MX28 processors are described in the following sections.
4.1.1DCP
The i.MX23 and i.MX28 have a DCP module that includes an AES block for general encryption and a hashing block for security functions. The AES block implements a 128-bit key/data encryption/decryption block as defined by the National Institute of Standards and Technology (NIST) as US FIPS PUB 197. For more information, see /publications/PubsFIPS.html .
The DCP implements four SRAM based keys that can be used by the software to securely store the keys on a temporary basis. Keys are written using the programmed I/O (PIO) interface by specifying a key index. This key index specifies the key that should be loaded, and a subword pointer which indicates the word that should be written within the key. After a subword is written, the subword pointer is automatically incremented so that the higher order words of the key can be programmed without rewriting the key index. The keys written to the storage are not readable.
After a system reset, the OTP controller reads the e-fuse devices, provides the OTP key information over a parallel 128-bit interface and captures the key into the key RAM.
The DCP supports two forms of encryption:
•Electronic Code Book (ECB) mode—this is the basic mode where the output is a function of the key and plain text.
•Cipher Block Chaining (CBC) mode—this mode can be implemented around ECB to provide additional security. CBC takes the previously encrypted data and logically XORs it with the next incoming plain text before performing the encryption. During decryption, the process is reversed
Table 3. Comparison of Security Features
Feature
i.MX23
i.MX25
i.MX28
Security hardware
DCP: •AES •Hashing
RTICv3SCCv3DRYICE RNGB DCP: •AES •Hashing
One-time programmable storage 1-Kbit OCOTP ROM IIM 1280-bit OCOTP ROM Secure RAM N/A 2 Kbyte N/A Secure JTAG N/A
Y es
N/A
Secure Boot
128-bit AES hardware decryption
HAB with SHA-256
128-bit AES hardware decryption
HAB with SHA-256
Security Features
and previously encrypted data is XORed with the decrypted ECB data and the plain text is
retrieved.
The hashing module on the i.MX23 and i.MX28 DCP implements the SHA-1 hashing algorithm and the modified CRC-32 checksum algorithm. In addition to the SHA-1 hashing algorithm, the i.MX28 also implements the SHA-256 hashing algorithm. These algorithms produce a signature for a block of data that can be used to determine if the data is intact.
The CRC-32 algorithm implements a 32-bit CRC algorithm similar to the one used by the Ethernet and other protocols. The SHA-1 block implements a 160-bit hashing algorithm that operates on 512-bit (64-byte) blocks, defined by US FIPS PUB 180-1. The SHA-256 block implements a 256-bit hashing that operates on 512-bit (64-byte) blocks, defined by US FIPS PUB 180-2 (For more information, see /publications/PubsFIPS.html). The module can be used to generate a unique signature for a block of data to validate the integrity of the data by comparing the resulting digest with the original digest.
4.1.2RNGB
The i.MX25 contains a true hardware based RNGB. RNGB can be used for generating true random numbers for security keys and random challenges for software applications. Unlike the software driven pseudo random number generators, the hardware RNGB is not predictable and therefore, less vulnerable to prediction attacks.
4.1.3SCCv3
The i.MX25 contains SSCv3 that provides 2 Kbyte of secure storage for sensitive information on both on-chip RAM and off-chip non-volatile memory. When used with the on-chip memory, the data is stored in RAM, which can be cleared (if required) to prevent unauthorized access. When used with the off-chip memory, the data is stored in encrypted form using an encryption key that is unique to each device and is accessible only to the Secure RAM module.
4.1.4DryIce
The i.MX25 has a DryIce module that provides volatile storage of encryptions keys with robust tamper detection and secure key erase for POS terminals. The DryIce module also provides a trusted time source for the Digital Rights Management (DRM) schemes. The trusted time source consists of a 47-bit secure time counter that uses a 32.768 kHz clock source and a 32-bit monotonic counter. The DryIce is powered by the SoC power supply and the backup power source to maintain the secure counter and key storage in the event of power loss.
4.1.5RTICv3
The i.MX25 contains RTICv3 and HASH accelerator that includes SHA-1 and SHA-256 message authentication to ensure the integrity of the peripheral memory contents. The RTICv3 is used to assist the boot authentication process by verifying the memory contents during the system boot. The RTICv3 can also verify the memory contents during the run-time execution.
Security Features 4.2Secure Boot
The encrypted boot and HAB features are described in the following sections.
4.2.1Encrypted Boot
The i.MX23 and i.MX28 support encrypted boot with the secure bootloader in the ROM and DCP. At the reset, the ARM core starts the operation on the on-chip ROM instead of directly performing the operation on the user code.The boot mode is sampled from the boot pins on the ROM startup, and then the ROM loader takes the control. The ROM loader first calls the initialization function for the selected boot driver, which initializes the corresponding hardware port and external device. The loader then requests the boot image data from the driver.
The encrypted boot images are encrypted using a randomly selected session key by elftosb application. The key is symmetric and based on the AES-128 algorithm. The session key is encrypted by the OTP key and determined by the ROM during the authentication process. The bootloader authenticates and decrypts the boot image on reset. Based on the Cipher Block Chaining Message Authentication Code (CBC-MAC) signature calculated using the DCP and OTP key, a proprietary authentication scheme (not HAB) is used by the bootloader to authenticate the boot images. Only authenticated images are booted by the bootloader and loaded into the SDRAM.
4.2.2HAB
HAB ensures trusted execution of the firmware by validating the code image stored in the external memory originated from a trusted authority. It also verifies if the code is in the original form. The HAB uses digital signatures to validate the external code images, and therefore establishes the security level of the system. The digital signatures are created by encrypting the hash values of the code blocks with a RSA private key crypto system. The signature is then added to the code and stored in the Flash. Verification by the HAB uses a public key stored in the on-chip non-volatile memory. The private key is not stored in the end device. The signature extracted from the code block and public key is used to decrypt it into the original hash value. A new hash value of the code block is recalculated and compared with the decrypted hash value for verification.
The secure boot of the i.MX25 shown in Figure2 is supported by HAB3 with SHA-256. The HAB component of ROM protects against potential threat from attackers by modifying the areas of code or data in programmable memory. The HAB also prevents attempts to gain access to unavailable features.
External Memory and Storage
Figure 2 shows the secure boot of the i.MX25 processor supported by HAB3 with SHA-256.Figure
2. i.MX25 Secure Boot Components
The i.MX28 supports HAB4. On the i.MX28, the ROM loader loads the boot image into memory and calls the HAB authenticate image function to verify the image. The boot image is not executed unless the image authentication is successful. The public key is stored in the CRYPTO_KEY_OTP fuse bits on OCOTP. Encryption is turned ON/OFF by the ENABLE_UNENCRYPTED_BOOT fuse (unencrypted image is booted if the fuse is blown). Similarly, the HAB can be turned ON/OFF by the HAB_DISABLE fuse (HAB is disabled if the fuse is blown). The HAB_CONFIG fuse controls the HAB security type. Users have control over the HAB super root key hash through the HW_OTP_SRK fuses, which are used to compare the DCP SHA-256 generated super root key (public key) hash from the boot image. The Boot images are created by elftosb application, which handles both encryption and HAB signature binding. In addition, the HAB boot can be combined with the encrypted boot on the i.MX28.
5External Memory and Storage
The i.MX23, i.MX25, and i.MX28 can interface efficiently with several external memories and storage devices such as Flash memory and Secure Digital (SD). Table 4 shows a comparison of the external memory and storage features of the i.MX23, i.MX25, and i.MX28.
Table 4. Comparison of External Memory and Storage
Feature i.MX23i.MX25
i.MX28Memory and storage hardware interface EMI GPMI •NAND Flash SSP EMI
•M3I F
•ESDRAMC
•NFC
•WEI M
A TA
eSDHC
EMI GPMI •NAND Flash SSP SDRAM 2.5 V DDR11.8 V mDDR 3.3 V SDRAM
1.8 V DDR2
1.8 V mDDR
1.8 V DDR21.8 V mDDR 1.5 V LP-DDR2NAND Flash
Four 8-bit/16-bit NAND SLC/MLC NAND 8-bit Reed-Solomon ECC 20-bit BCH ECC Four 8-bit/16-bit NAND
SLC/MLC NAND
8-bit Reed Solomon ECC
Internal RAM Buffer Eight 8-bit/16-bit NAND SLC/MLC NAND 20-bit BCH ECC
External Memory and Storage Table4. Comparison of External Memory and Storage (continued)
Feature i.MX23i.MX25i.MX28
NOR Flash N/A Y es N/A
A TA N/A UDMA-5N/A
SD/MMC eMMC 4.2, eMMC 4.3 (limited)eMMC 4.3eMMC 4.3, eMMC 4.4
5.1i.MX23 Memory Interfaces
The i.MX23 supports off-chip DRAM storage through the EMI controller. The EMI supports 2.5 V DDR1 and 1.8 V mDDR.
The EMI consists of two major components:
•DRAM controller
•Delay Compensation Circuitry (DCC)
The DRAM controller supports up to two external chip-selects and a maximum of 128 Mbytes of DRAM storage. The 128-pin LQFP has one chip select pin and supports a maximum of 64 Mbytes of DRAM. The 169-pin BGA has two chip select pins and supports a maximum of 128 Mbytes of DRAM. The programmable registers within the DRAM controller allow flexibility for device timings, low-power operation, and performance tuning.
The i.MX23 GPMI is a flexible interface that supports up to four NAND Flash devices. The GPMI has configurable address and command behavior, and it provides support for future devices.
The GPMI has the following features, which efficiently supports NAND Flash:
•Individual chip select and ready/busy pins for four NAND Flashes
•Individual state machine and Direct Memory Access (DMA) channel for each chip select
•Special command modes work with the DMA controller to perform all normal NAND Flash functions without the intervention of the CPU
•Configurable timing based on a dedicated clock that allows optimal balance of high NAND Flash performance and low system power
The i.MX23 has hardware ECC accelerators to provide forward error correction to interface with the MLC NAND Flashes. The ECC engine on the i.MX23 implements Bose Ray-Choudhury Hocquenghem (BCH-ECC) engine and provides up to 20 bits of correction. For backward compatibility, Reed-Solomon (RS-ECC8) engine is used, which provides 4 or 8 bits of correction. Both engines are tightly coupled to the GPMI and are for mutually exclusive use, with separate programming modules and DMA structures. External media like SD or MMC can be supported by the i.MX23 SSP. eMMC version 4.2 and 4.3 is supported. However, the ROM cannot boot an eMMC 4.3 device with the CSD_STRUCTURE version in the EXT_CSD register. To support SD, SDIO, MMC, and high speed (4-bit and 8-bit) MMC cards, SSP is configured in the SD/SDIO/MMC mode. In this mode, the SSP supports simultaneous command and data transfers. Commands are sent to the card and responses are returned to the host on the CMD line. Register data is sent as a command response. Block data read from or written to the card Flash is transferred on the DA T line(s). The SSP also supports the SDIO Interrupt Request (IRQ).
External Memory and Storage
5.2i.MX25 Memory Interfaces
The i.MX25 EMI handles the external memory access. The EMI manages the following external memory controllers to support different memory devices:
•M3IF
•ESDRAM/LP-DDR memory controller (ESDRAMC/mDDR controller)
•NFC
•SRAM/Pseudo SRAM (PSRAM)/FLASH memory controller (WEIM)
The M3IF supports multiple requests up to eight masters through the input port interfaces. The M3IF supports memory snooping that monitors a region (from 2 Kbytes to 16 Mbytes) in the external memory for the write access. Some versions of M3IF also support memory watermark protection up to eight chip selects for hardware preselected masters.
The ESDRAMC/mDDR controller provides interface and control for synchronous Single Data Rate (SDR), LP-DDR, and DDR1 devices. It also provides support for 4-bank DDR2 devices and can be connected to 8-bank DDR2 devices (though it can access only 4 banks without the On Device Termination (ODT) control signal). The controller supports 64-Mbit, 128-Mbit, 256-Mbit, 512-Mbit, and 1-Gbit
(4banks) synchronous DRAM with two independent chip selects and up to 128-Mbyte addressable memory per chip select. Only 16-bit SDRAM is supported by the controller. The controller has a PC133 compliant interface that supports SDR at 133 MHz and DDR at 266 MHz, with JEDEC standard pin-out and operations (For more information, see /). Consecutive memory accesses are optimized through memory command anticipation or latency hiding. The controller also has a built-in auto-refresh timer and state machine with self-refresh entry and exit support to keep the data in SDRAM valid during the system reset and low-power modes.
The NFC provides a glueless interface to both 8-bit and 16-bit NAND Flash with page sizes of 512bytes, 2Kbytes, or 4Kbytes. The NFC has an internal RAM buffer (4 Kbytes + 512 bytes), which can be configured as a boot RAM, or operated as a buffer during normal operation. The NFC supports both SLC and MLC NAND Flashes. MLC NAND Flash uses two Reed Solomon RS (511,503) ECCs, which corrects 4/8 error bits in 528/538 bytes (512 bytes main + 16/26 bytes spare). The i.MX25 includes an internal bootcode loader to provide advanced data protection during power-up when booted from the external NAND Flash.
The WEIM interfaces with the external devices and includes generation of chip selects, clocks, and control for the external peripherals and memory. The WEIM provides asynchronous and synchronous access to 16-bit or 32-bit devices with SRAM-like interface. The WEIM has six chip selects for the external devices with selectable protection for each chip select. The WEIM includes a programmable data port size
wait-state generator for each chip select. The WEIM supports asynchronous accesses with programmable setup and hold time for control signals. For synchronous accesses, the WEIM supports burst read mode for AMD, Intel, and Micron burst Flash memory, and burst write mode for PSRAM (CellularRAM TM from Micron, Infineon, Cypress). The WEIM also supports multiplexed address/data bus operation, external cycle termination/postpone with DTACK signal, and big/little-endian modes operation per access.。