VCS_VERDI仿真脚本

VCS编译脚本：将以下代码保存为**.sh（shell脚本）即可
#!/bin/csh -f
##############################################################
set TEST_TOP_NAME = "test_spi_interface.v"
set RTL_TOP_NAME = "spi_interface.v"
# include search path for modules
set INC_DIRS="+incdir+/home/project/project2018/digital_ic/AI4018/RTL/source"
# library search path for modules
set LIB_DIRS="-y /home/project/project2018/digital_ic/AI4018/RTL/lib"
# top rtl verilog file
set RTL_TOP_FILE="/home/project/project2018/digital_ic/AI4018/RTL/source/$RTL_TOP_NAME"
#set SEG_CTRL_FILE="../code/rtl/disp/sdh_seg_ctrl.v"
# test top verilog file
set
TEST_TOP_FILE="/home/project/project2018/digital_ic/AI4018/RTL/simulation/$TEST_TOP_NA ME"
echo "simulation top file = $TEST_TOP_FILE"
echo "RTL top file = $RTL_TOP_FILE"
# define vcs compile flags
set VCS_FLAGS="\
-sverilog \
-debug_all \
-timescale=1ns/10ps \
+libext+.v \
-P $LD_LIBRARY_PATH/novas.tab $LD_LIBRARY_PATH/pli.a \
-notice -l vcs_information.log \
+nospecify \
+notimingcheck \
+lint=TFIPC-L \
+define+FSDB"
#define code coverage metrics
set CM_COMPILE_FLAGS="\
-cm line+cond+fsm+tgl \
-cm_tgl mda"
#set coverage test
set CM_SIM_FLAGS="\
-cm line+tgl+fsm+cond"
# excute VCS sim at my_vcs directory
cd /home/project/project2018/digital_ic/AI4018/VCS/my_vcs
# compile using the HDL simulator to produce an executable
vcs $VCS_FLAGS $INC_DIRS $LIB_DIRS $CM_COMPILE_FLAGS $RTL_TOP_FILE $TEST_TOP_FILE
#./simv -ucli $CM_SIM_FLAGS -i ../script/vcs_ucli.tcl
#./simv -gui
./simv -ucli -i ../script/vcs_ucli.tcl
#DVE GUI converage analysis
#dve -cov -dir simv.vdb
#genarate html converage analysis results
#urg -dir simv.vdb -report both -full64
Verdi波形仿真脚本：将以下代码保存为**.tcl（tcl脚本）即可
#!/bin/csh -f
# excute VCS sim at my_vcs directory
cd /home/project/project2018/digital_ic/AI4018/VCS/my_vcs
# set verdi top and FSDB
set VERDI_TOP="test_spi_interface"
set MY_FSDB = "test_spi_interface"
verdi -sv -f ../script/verilog_file_list.f \
-top $VERDI_TOP \
-nologo \
-ssf ./my_fsdb/$MY_FSDB.fsdb &。