K9G8G08U0M-W
K9F1G08UOM数据手册
m A 5 5 15 15 1 10 10 20 20 1 µA 10 50 10 50
页 编 ICC2 程 擦除 ICC3 ISB1 等待状态电流 （TTL） 等待状态电流 （CMOS） 输入开漏电流 输出开漏电流
ISB2
IL1 IL0
-
-
±10 ±10
-
-
±10 ±10 VCC V +0.3 0.8 -
6． 命令/地址/ 数据复用端口： 7. 硬件数据保护：编程/擦除操作在电源转换时关闭。 8. 可靠的 CMOS 浮置门技术： --保证：100K 编程/ 擦除次数。 --数据保持时间: 10 年。 9. 命令寄存器操作 10. 为高速编程设置的缓冲编程操作。 11. 通电自动读操作。 12. 智能复制拷贝操作。 13．为防盗版而设置的唯一的 ID 保护。 14. 封装。 - K9F1GXXX0M-YCB0/YIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F1G08U0M-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm)
器件描述
三星 K9F1GXXX0M 提供了 128M*8Bit/64M*16Bit 的存储容量，另外还有 32 M 的空闲存储器，它是采用 NAND 技术的大容量、高可靠的 Flash 存储器。 它对 2112 字节一页（*8device ）或者 1056 字（*16device）一页的写操作。典型 时间是 300 微秒。对 128 字节／64K 字一块的擦除时间是 50 纳秒。输出引脚可 以作为数据／地址／命令复用。每一页的数据读出时间也很快，平均每个字节只 需 50 纳秒。片内的写控制器，可以自动执行写操作和擦除功能，包括必要的脉 冲产生器，内部校验和冗余数据。 K9F1G08 提供了实时映像算法的纠错码，写 操作系统可以利用 K9F1G08U0M 扩展的 100K 编程/ 擦除。K9F1G08U0M 为大 容量存储，新型电可擦写的非易失性半导体存储器，提供了最优方案。
K9K8G08U0A
K9WAG08U1A K9K8G08U0A K9NBG08U5A
FLASH MEMORY
K9XXG08UXA
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
使用的NandFlash为三星的K9F2G08U0M
使用的Nand Flash为三星的K9F2G08U0M，存储为256M，数据宽度为8bit.具体的资料可以参考datasheet.由于S3C2440里面包括了Nand FLash 控制器，所以，我们的工作就是根据芯片手册配置一下寄存器。
包括的寄存器如下：NFCONF; NFCONT;NFCMD;NFADDR;NFDATA; NFMECCD0; NFMECCD1;NFSECCD; N FSTAT; NFESTAT0; NFESTAT1;NFMECC0；NFMECC1;NFSECC;NFSBLK;NFEBLK;(1) 对于每个寄存器的地址，每一位的功能可以参考S3C2440芯片手册！对于目前的编程主要涉及到如下五个寄存器：NFCONT;NFCMD;NFADDR;NFDATA；NFSTAT；使用宏定义：#define rNFCONF (*(volatile unsigned *)0x4E000000)#define rNFCONT (*(volatile unsigned *)0x4E000004)#define rNFCMD (*(volatile unsigned *)0x4E000008) #define rNFADDR (*(volatile unsigned char*)0x4E00000C)#define rNFDATA8 (*(volatile unsigned char*)0x4E000010)#define rNFSTAT (*(volatile unsigned *)0x4E000020)特别注明：对于NFCONF寄存器，特别要说明的是TACLS，TWRPH0，TWRPH1，这三个参数。
如何设置这三个参数，主要得看K9F2G08U0M 手册上的时序表，参数表，上面已经写好了CLE ，ＡＬＥsetup时间，WE_N的Pulse WiDth,WE_N HIGH HOLD TIME .根据这些参数，设置个合适的TACLS，TWRPH0，TWRPH1值！(2) 命令！ Nand Flash编程时涉及到很多命令，其实这些命令帮助我们完成了很多的工作，我们现在只需做发送命令的工作。
INCOM369CC CD主控FLASH支持表1.8.xls(09-06-08)
HY27UF082G2B
Hynix
HY27UG082G2M HY27UF081G2A HY27UF081G2M JS29F64G08CAMD1 JS29F64G08FAMC1 JS29F32G08AAMD1 JS29F32G08CAMC1 JS29F32G08FAMB1 JS29F32G08FAMB2 JS29F32G08FANC1 JS29F16G08AAMC1 JS29F16G08CAMB1 JS29F16G08CAMB2 JS29F16G08FANC1 JS29F16G08CANC1 JS29F16G08FANB1 JS29F16G08FANB2 JS29F08G08AAMC1 JS29F08G08AAMB2 JS29F08G08AANC1 JS29F08G08CANC1 JS29F08G08CANB1 JS29F08G08CANB2 JS29F08G08BANB1 JS29F08G08FANB3 JS29F08G08FANA2 JS29F04G08AANC1
FLASH厂商
容量
2Gb 2Gb 1Gb 1Gb 64Gb 64Gb 32Gb 32Gb 32Gb 32Gb 32Gb 16Gb 16Gb 16Gb 16Gb 16Gb 16Gb 16Gb 8Gb 8Gb 8Gb 8Gb 8Gb 8Gb 8Gb 8Gb 8Gb 4Gb
FLASH类型
SLC SLC SLC SLC MLC MLC MLC MLC MLC MLC SLC MLC MLC MLC SLC SLC SLC SLC MLC MLC SLC SLC SLC SLC SLC SLC SLC SLC
MICRON
MT29F4G08AAB MT29F4G08AAA MT29F2G08AAD MT29F2G08AAB MT29F2G08AAC MT29F2G08AAA K9HCG08U1M K9HCG08U5M K9LBG08U0M K9LBG08U1M K9HBG08U1M K9WBG08U1M K9GAG08U0M K9GAG08U0D K9LAG08U0M
U盘 维修
U盘（优盘）的故障表现及数据恢复1、U盘毫无反应：有可能U盘插口针脚断裂，晶震坏，稳压三极管电路不能工作，数据全部可以恢复。
2。
有盘符，提示请插入磁盘：<1>U盘主控内部系统文件损坏,数据全部可以恢复。
一般更换相同的主控即可，可是找一个相同的U 盘，主控相同，U盘容量相同，实在不易，为此我公司引进世界先进技术，直接读取FLASH芯片内的数据，达到快速恢复文件，欢迎咨询<2>U盘ＦＬＡＳＨ芯片存在坏块区，数据恢复可以完全恢复或部份恢复，视具体损坏情况来定！3。
有盘符但提示未格式化：U盘存在坏扇区或引导扇区有问题，如无重要数据格式化之后便可使用。
可做数据恢复，而且数据恢复的结果十分完整，这种情况一般都是使用不当造成的故障，如热插拔之类的误操作，USB接口电压等，尽量使用时正常使用。
4。
无盘符提示无法识别的USB设备：晶震或稳压三极管损坏，这种情况数据全部可以恢复。
5。
逻辑类的问题：无盘符，但能检到U盘，提示格式化等，数据可以恢复。
常见flash芯片类型列表H27UCG8VFM HY27UG088G5M HY27SA161G1M HY27SS08121MH27U2G8T2M HY27UH08AG5M HY27UF081G2A HY27SS16121MH27U2G8T2M HY27UH08AG5B HY27UF161G2A HY27US08121MHN29V2G74W30 HY27UK08BGFM HY27UF081G2M HY27US16121MH27UBG8H5M HY27UH08BGFB HY27UF161G2M HY27US08561AH27U8G8F2M HY27UT084G2A HY27SF081G2M HY27US16561AH27UAG8G5M HY27UT084G2M HY27SF161G2M HY27SS08561AH27UBG8T5M HY27UU088G5M HY27UF082G2A HY27SS16561AHY27US08281A HY27UT088G2M HY27UF162G2A HY27US08561MHY27US08561A HY27UT088G2A HY27UF082G2B HY27US16561MHY27US08561M HY27UV08AG5M HY27UF162G2B HY27SS08561MHY27US08121A HY27UV08BG5M HY27UF084G2B HY27SS16561MHY27US08121M HY27UV08BGFM HY27UF164G2B HY27US08281AHY27UA081G1M HY27UV08BGFA HY27UF082G2M HY27US16281AHY27UA081G4M HY27UU08AG5M HY27UF162G2M HN29W12811T-60HY27UB082G4M HY27UU08AG5A HY27UH088G2M HN29V25691BTHY27UF081G2A HY27UW08BGFM HY27UH088GDM HN29V51211T-50HY27UF081G2M HY27UW08CGFM HY27UG088G5B HN29V1G91T-30HY27UF082G2A Hynix InkDie HY27UG088G5M HY27UF164G2B（x16）HY27UF082G2M H27UAG8T2M HY27UH08AG5M HYF33DS512804（5）BTC HY27UF082G2B H27UCG8V5M HY27UK08BGFM HYF33DS512804（5）BTC HY27UF084G2B HY27SF082G2B HY27US081G1M HYF33DS512804（5）BTC HY27UG088G5B HY27SF162G2B HY27US161G1M HYF33DS512804（5）BTC HY27UF084G2M HY27SF081G2A HY27US08121A HYF33DS1G800CTIHY27UG084G2M HY27SF161G2A HY27US16121A HYF33DS1G800CTIHY27UH084G2M HY27U（s）A081G1M HY27SS08121A HY27US16562AHY27UH088G2M HY27UA161G1M HY27SS16121A HY27SS081G1XI29F04G08AAA I29F32G08CAMCI FTGM40A2GK3WG FTNL41B8GK3PGI29F08G08AAMB2 I29F64G08FAMC1 FBNL41B32K3P4 FTNL41B8GK3PGI29F08G08AAMBI PF79BL1208BSG FBNL41B8GK3P2 FTNL41B8GK3PGI29F16G08AAMCI PF79AL1208BS FTNL41BHGK3W4 R1FV04G13RSA-3I29F16G08MAA DFT512W08B-P1 FBNL41B8GK3W3 R1FV04G13RSA-3_2ASU4GA30GT K9F2G08U0M K9WBG08U1M K9L8G08U0MASU2GA30GT K9F2G08U0M K9NBG08U5A K9LAG08U0MK9F2808U0B K9K2G08U0M K9NCG08U5M K9LAG08U0A_BK9F5608U0B K9GAG08U0A K9G2G08U0M K9HBG08U1AK9F1208U0A K9GAG08U0D K9G4G08U0A K9LBG08U0MK9F1208U0B K9K4G08U0M K9G8G08U0A K9HAG08U1MK9F1208U0C K9F4G08U0A K9G8G08U0M K9HBG08U1MK9K1G08U0M K9F8G08U0M K9L8G08U1M K9HCG08U1MK9E2G08U1M K9K8G08U0A K9LBG08U0D K9MDG08U5MK9F1G16U0M K9KAG08U0M K9HCG08U1M K9MBG08U5MK9F1G08U0A K9W8G08U1M K9HCG08U1D K9MCG08U5MK9F1G08U0B K9WAG08U1A K9LAG08U1M K9GAG08U0MK9F1G08U0M K9LBG08U1M K9HCG08U5M K9F5616U0C（x16）K9F2G08U0A K9F1208U0M K9F5616U0C K9K4G16Q0MK9F1G16Q0M K9F2808U0 K9G8G08U0M K9XXG08UXMK9F1G08 K9F5608U0B K9LAG08U0M K9K4G16U0MK9F1G16U0M K9F5616U0B K9HBG08U1M K9K8G08U0MK9F2G08U0A K9F5608D0C K9MCG08U5M K9WAG08U1MK9F2G16U0M K9F5616D0C K9K1G08U0M K9K2G08Q0MK9F2G08U0M K9F5608U0C K9K4G08Q0M K9K2G16Q0MK9XXG08UXM K9XXG16UXM K9K2G08U0M K9F1G08Q0MNAND128W3A2BN6E NAND08GW3C2B NAND512R3A NAND04GW4B2DNAND256W3A2BN6E NAND16GW3C4B NAND512W3A NAND08GW3B2CNAND512W3A0AN6 NAND01GW3B2B NAND512R4A NAND08GR4B2CNAND01GW3A0AN6 NAND01GR4B2B NAND512W4A NAND08GW4B2CNAND01GW3B2AN6 NAND01GW4B2B NAND01GR3A NAND08GW3C2ANAND01GW3B2BN6 NAND02GW3B2C NAND01GW3A NAND16GW3C4ANAND02GW3B2AN6 NAND02GR4B2C NAND01GR4A NAND08GW3C2BNAND02GW3B2D NAND02GW4B2C NAND01GW4A NAND08GW3D2ANAND02GW3B2CN6 NAND01GW3B2C NAND02GW3B2D NAND512R3A2DNAND04GW3B2DN6 NAND01GR4B2C NAND02GR4B2D NAND512W3A2DNAND04GW3B2BN6 NAND01GW4B2C NAND02GW4B2D NAND512R4A2DNAND08GW3B2CN6 NAND128R3A NAND04GW3C2A NAND512W4A2DNAND08GW3B2AN6 NAND128W3A NAND04GA3C2A NAND01GR3A2CNAND04GW3C2AN1 NAND256R3A NAND04GW3B2B NAND01GW3A2CNAND08GW3C2AN1 NAND256W3A NAND08GW3B2A NAND01GR4A2CNAND08GW3B2CN6 NAND256R4A NAND04GW3B2D NAND01GW4A2CNAND04GW3C2B NAND256W4A NAND04GR4B2D NAND04GW3C2BNAND08GW3F2A NAND16GW3F2A NAND08GW3C2BMT29F8G08MAA MT29F64G08TAA MT29F4G08ABC MT29F4G08BABMT29F8G16MAA MT29F32G08BAAA MT29F32G08FAA MT29F8G08FABMT29F16G08QAA MT29F64G08CFAAA MT29F8G08BAA MT29F4G16BABMT29F2G08AAC MT29F4G08ABC MT29F8G08DAA MT29F16G08QAA（DUAL） MT29F32G08TAA MT29F2G08AAA MT29F16G08FAA MT29F2G08ABCMT29F2G16AAC MT29F2G16ABD MT29F4G08MAA MT29F32G08TAA-BMT29F2G16ABC MT29F2G08AAB_C MT29F4G08MAA_2 MT29F128G08CJAAA MT29F4G08BBC MT29F4G08AAA_C MT29F8G08MAD MT29F4G08BACMT29F8G08MBD MT29F4G08BAB_C MT29F8G08MAD MT29F8G08FACMT29F4G08AAA MT29F8G08FAB_C MT29F2G08AAD MT29F16G08CBABAMT29F8G08DAA MT29F8G08MAD MT29F2G08AAB MT29F32G08CBABAMT29F16G08MAA MT29F8G08AAA MT29F2G08ABB MT29F8G08BAAMT29F16G08MAA MT29F16G08DAA MT29F2G16AAB MT29F16G08FAAMT29F32G08QAA MT29F2G08ABC MT29F2G16ABBSDTNFCH-512 SDTNKGHSM-8192 SDMLC-1GB-I SDUNIHHSM-8192（16bit）SDTNFCH-1024 SDMLC-16384-I SDTNLLBHSM-32768 SDTNIHHSM-4096（16Bit）SDTNKGHSM-1024 SDTNKHHSM-16384 SANDISK-16384（43nm） SDTNKGHSM-4096（16bit） SDTNGBHE0-2048-I SDTNKHHSM-32768 SDTNIGHE0-4096 SDTNKHHSM-32768（16bit）SDTNGFHE0-2048 SDTNLJCHSM-2048 Sandisk-4GB（43nm） SDTNLLAHSM-1024（16bit） SDTNKGHSM-2048 SDTNLJCHSM-4096 SDTNLMBHSM-4096 SDTNKGHSM-2048（16bit）SDMLC-4GB-I SM90-256MB SDTNKLBHSM-2048 SDTNKJBHSM-8192（16bit）SDTNKGHSM-4096 SM90-256MB SDTNLLCHSM-1024 SDTNKGHSM-8192（16bit）SDTNLJCHSM-1024 SDTNIGHSM-2048 SDTNLLBHSM-4096 SDTNIGHSM-4096（16bit）SDUNIHHSM-8192 SDTNIGHSM-2048（16bit） SDMLC-1GB-I SDTNKHHSM-16384（16bit） SDTNIHHSM-4096 SDMLC-2GB-I SDTNKHHSM-16384（16bit）TC58NVG4D1DTG00 TC58NVG3D4CTG00 TC58DVG14B1FT00 TC58DVG02ATC58NVG4D2ETA00 TC58DVM72A1FT00 TC58NVG1D4BTG00 TC58DVM92ATH58NVG4D6CTG00 TC58DVM82A1FT00 TH58DVG24B1FT00 TC58NVG0S3CTA00TH58NVG6D1DTG20 TC58DVM92A1FT00 TC58NVG2D4BFT00 TC58NVM9S3BTG00TH58NVG5D2ETA20 TC58DVG02A1FT00 TH58NVG3D4BTG00 TC58NVG3D1DTG00（S）TH58NVG6D2ETA20 TC58NVG02A2FT00 TC58NVG3D4CTG10 TC58NVG6D1DTG00TH58NVG4T2DTG00 TC58NVG0S3BTG00 TH58NVG4D4CTG00 TC58NVG7D1DTG20TH58NVG6T2DTG20 TC58NVG1S3BTG00 TH58NVG5D4CTG20 TC58NVG2D1DTG00TH58NVG5D2ETA00 TH58NVG2S3BFT00 TC58NVG3D1DTG00 TC58NVG2D1DTG00TH58NVG5D1DTG00 TC58DVM94B1FT00 TH58NVG6D1DTG80 TC58NVG5D1DTG20TC58512FT TC58DVG04B1FT00 TC58NVG4D1DTG00工厂级U盘维修很多人打电话咨询U盘故障及数据恢复问题,现在把U盘的一些故障及排除方法归类一、硬件故障故障现象：U盘插在电脑里面什么反应都没有或是插上去在设备管理器的“通用串行总线控制器”里面能看到有新设备，但是我的电脑里面没有出现新盘符此类故障必须要懂电子的人才能搞定，至少要懂得焊接故障排除：重新焊好FLASH和主控，如果有新晶振也可以换掉试下，如果还不行就只有换主控IC了，总之，至少插在电脑里面要有新的盘符显示才算硬件基本正常（不是完全正常哦）。
闪存型号容量对照
Toshiba
TC58512(A)FT
Toshiba
TC58DVM92A1FT
Toshiba
SLC SLC SLC MLC MLC MLC MLC SLC MLC SLC MLC MLC MLC MLC MLC MLC MLC SLC MLC MLC MLC SLC MLC MLC MLC MLC MLC MLC SLC MLC MLC MLC MLC MLC MLC MLC MLC SLC SLC SLC SLC SLC
HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX HYNIX Micron Micron Micron Micron Micron Micron Micron
容量 16MB 16MB 32MB 32MB 64MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 1GB 1GB 1GB 1GB 1GB 1GB 2GB 2GB 1GB 1GB 4GB 4GB 2GB 2GB 2GB 2GB 4GB 4GB 4GB 4GB 8GB 16GB 16MB 32MB
MLC SLC MLC SLC SLC MLC MLC MLC SLC SLC MLC MLC MLC MLC MLC MLC MLC MLC MLC MLC MLC
K9K8G08U0B-PCBO
K9K8G08U0BK9WAG08U1BINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title1G x 8 / 2G x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.1RemarkAdvance AdvanceHistory 1. Initial issue1. K9K8G08U0B-P is added.Draft DateJun. 11, 2008Jul. 10, 2008GENERAL DESCRIPTIONFEATURES• Voltage Supply- 3.3V (2.70V ~ 3.60V)• Organization- Memory Cell Array :- K9K8G08U0B : (1G + 32M) x 8bit - K9WAG08U1B : (2G + 64M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.)1G x 8 / 2G x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology- Endurance : 100K Program/Erase Cycles (with 1bit/528Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Unique ID for Copyright Protection • Package :- K9K8G08U0B-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1B-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1B-ICB0/IIB052 - Pin ULGA (12 x 17 / 1.0 mm pitch)Offered in 1G x 8bit, the K9K8G08U0B is a 8G-bit NAND Flash Memory with spare 256M-bit. And the K9WAG08U1B is a 16G-bit NAND Flash Memory with spare 512M-bit. Its NAND cell provides the most cost-effective solution for the solid state application mar-ket. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K8G08U0B/K9WAG08U1B ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K8G08U0B/K9WAG08U1B is an optimum solution for large nonvola-tile storage applications such as solid state file storage and other portable applications requiring non-volatility.PRODUCT LISTPart Number Vcc RangeOrganizationPKG Type K9K8G08U0B-P 2.70 ~ 3.60VX8TSOP1K9WA G08U1B-P K9WA G08U1B-I52ULGA1.001.001.001.002.007 6 5 4 3 2 11.001.001.0012.00±0.10#A117.00±0.1017.00±0.10BA12.00±0.10(Datum B)(Datum A)12.0010.002.502.502.000.501.30A B C DEF GHJ K L M N12-∅1.00±0.0541-∅0.70±0.05Side View1.0(M a x .)0.10 C17.00±0.10Top ViewBottom ViewABC D EF G H J KL M N7654321K9WAG08U1B-ICB0/IIB052ULGA (measured in millimeters)NCNCNCNCNCNCNCNCNC NCNCNCNCNCNC NCVccVcc VssVssVss /RE1/RE2/CE1/CE2CLE1CLE2ALE1ALE2/WE1/WE2/WP1/WP2R/B1R/B2VssIO0-1IO0-2IO1-1IO1-2IO2-1IO3-1IO2-2IO3-2IO4-1IO4-2IO5-1IO5-2IO6-1IO6-2IO7-1IO7-2∅ABC M 0.1∅ABC M 0.1PACKAGE DIMENSIONSPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CE / CE1CHIP ENABLEThe CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation.Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation. CE2CHIP ENABLEThe CE2 input enables the second of K9WAG08U1B.REREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/B / R/B1READY/BUSY OUTPUTThe R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9K8G08U0B has a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0B. The K9K8G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1,056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K8G08U0B.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.The K9WAG08U1B is composed of two K9K8G08U0B chips which are selected separately by each CE1 and CE2.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hTwo-Plane Page Program(3)80h---11h81h---10hCopy-Back Program85h10hTwo-Plane Copy-Back Program(3)85h---11h81h---10hBlock Erase60h D0hTwo-Plane Block Erase60h---60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h OChip1 Status(2)F1h OChip2 Status(2)F2h ONOTE : 1. Random Data Input/Output can be executed in a page.2. Interleave-operation between two chips is allowed.It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.3.Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .Caution : Any undefined command inputs are prohibited except for above command set of Table 1.DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.3. The maximum value of K9K8G08U0B -P’s I LI and I LO is ±40µA , the maximum value of K9K8G08U0B -I’s I LI and I LO is ±20µA .ParameterSymbol Test ConditionsMinTypMaxUnitOperating CurrentPage Read withSerial Access I CC 1tRC=25nsCE=V IL, I OUT =0mA-2535mAProgramI CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -40200µAInput Leakage Current I LI V IN =0 to Vcc(max)--±40Output Leakage Current I LO V OUT =0 to Vcc(max)--±40Input High VoltageV IH (1)-0.8xVcc -Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH I OH =-400µA 2.4--Output Low Voltage Level V OL I OL =2.1mA --0.4Output Low Current(R/B)I OL (R/B)V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9XXG08UXB-XCB0 :T A =0 to 70°C, K9XXG08UXB-XIB0:T A =-40 to 85°C)ParameterSymbol Min Typ.Max Unit Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit Voltage on any pin relative to VSSV CC -0.6 to +4.6VV IN -0.6 to +4.6V I/O-0.6 to Vcc+0.3 (<4.6V)Temperature Under Bias K9XXG08UXB-XCB0T BIAS -10 to +125°C K9XXG08UXB-XIB0-40 to +125Storage Temperature K9XXG08UXB-XCB0T STG-65 to +150°CK9XXG08UXB-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested. K9WAG08U1B-IXB0’s capacitance(I/O, Input) is 20pF.ItemSymbol Test ConditionMin MaxUnitK9K8G08U0BK9WAG08U1B*Input/Output Capacitance C I/O V IL =0V -2040pF Input CapacitanceC INV IN =0V-2040pF VALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.* : Each K9K8G08U0B chip in the K9WAG08U1B has Maximun 160 invalid blocks.Parameter Symbol Min Typ.Max Unit K9K8G08U0B N VB8,028-8,192BlocksK9WAG08U1B16,064*-16,384*AC TEST CONDITION(K9XXG08UXB-XCB0: T A =0 to 70°C, K9XXG08UXB-XIB0:T A =-40 to 85°C ,K9XXG08UXB: Vcc=2.7V~3.6V unless otherwise noted)ParameterK9WAG08U1B Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF (K9K8G08U0B-P/K9WAG08U1B-I)1 TTL GATE and CL=30pF (K9WAG08U1B-P)MODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byProgram / Erase CharacteristicsParameter Symbol Min Typ Max Unit Program Time t PROG-200700µs Dummy Busy Time for Two-Plane Page Program t DBSY-0.51µs Number of Partial Program Cycles Nop--4cycles Block Erase Time t BERS- 1.52msNOTE : 1. Typical value is measured at Vcc=3.3V, T A=25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C tempera-ture.AC Timing Characteristics for Command / Address / Data InputParameter Symbol Min Max UnitCLE Setup Time t CLS(1)12-nsCLE Hold Time t CLH5-nsCE Setup Time t CS(1)20-nsCE Hold Time t CH5-nsWE Pulse Width t WP12-nsALE Setup Time t ALS(1)12-nsALE Hold Time t ALH5-nsData Setup Time t DS(1)12-nsData Hold Time t DH5-nsWrite Cycle Time t WC25-nsWE High Hold Time t WH10-nsAddress to Data Loading Time t ADL(2)70-nsNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.AC Characteristics for OperationParameter Symbol Min Max Unit Data Transfer from Cell to Register t R-25µs ALE to RE Delay t AR10-ns CLE to RE Delay t CLR10-ns Ready to RE Low t RR20-ns RE Pulse Width t RP12-ns WE High to Busy t WB-100ns Read Cycle Time t RC25-ns RE Access Time t REA-20ns CE Access Time t CEA-25ns RE High to Output Hi-Z t RHZ-100ns CE High to Output Hi-Z t CHZ-30ns RE High to Output hold t RHOH15-ns RE Low to Output hold t RLOH5-ns CE High to Output hold t COH15-ns RE High Hold Time t REH10-ns Output Hi-Z to RE Low t IR0-ns RE High to WE Low t RHW100-ns WE High to RE Low t WHR60-ns Device Resetting Time(Read/Program/Erase)t RST-5/10/500(1)µs NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.NAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /528Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2,048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2,048 Figure 3. Flow chart to create initial invalid block table.StartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionInterleave Page ProgramK9WAG08U1B is composed of two K9K8G08U0Bs. And K9K8G08U0B also is composed of two K9F4G08U0Bs. K9K8G08U0B pro-vides interleaving operation between two K9F4G08U0Bs.This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.At first, the host issues page program command to one of the K9F4G08U0B chips, say K9F4G08U0B(chip #1). Due to this K9K8G08U0B goes into busy state. During this time, K9F4G08U0B(chip #2) is in ready state. So it can execute the page program command issued by the host.After the execution of page program by K9F4G08U0B(chip #1), it can execute another page program regardless of the K9F4G08U0B(chip #2). Before that the host needs to check the status of K9F4G08U0B(chip #1) by issuing F1h command. Only when the status of K9F4G08U0B(chip #1) becomes ready status, host can issue another page program command. If the K9F4G08U0B(chip #1) is in busy state, the host has to wait for the K9F4G08U0B(chip #1) to get into ready state.Similarly, K9F4G08U0B chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F4G08U0B(chip #2) by issuing F2h command. When the K9F4G08U0B(chip #2) shows ready state, host can issue another page program command to K9F4G08U0B(chip #2).This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation.NOTES : During interleave operations, 70h command is prohibited.R / B (#1)b u s y o f C h i p #1I /O X80h10h C o m m a n d A 30 : L o w A d d & D a t a80h 10h A 30 : H i g h A d d & D a t ab u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e P a g e P r o g r a m≈≈≈F 1h o r F 2h A B CDa n o t h e r p a g e p r o g r a m o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a p a g e p r o g r a m o p e r a t i o n a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a p a g e p r o g r a m c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g p a g e p r o g r a m o p e r a t i o n .S t a t e C : P a g e p r o g r a m o n c h i p #1 i s t e r m i n a t e d , b u t p a g e p r o g r a m o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r p a g e p r o g r a m c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e p a g e p r o g r a m o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x hR / B (#1)b u s y o f C h i p #1I /O X60hD 0h C o m m a n d A 30 : L o w A d d60h D 0h A 30 : H i g h A d db u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e B l o c k E r a s e≈≈≈F 1h o r F 2h A B CDa n o t h e r B l o c k E r a s e o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a b l o c k e r a s e o p e r a t i o n , a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a b l o c k e r a s e c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g b l o c k e r a s e o p e r a t i o n .S t a t e C : B l o c k e r a s e o n c h i p #1 i s t e r m i n a t e d , b u t b l o c k e r a s e o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r b l o c k e r a s e c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e b l o c k e r a s e o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x hR /B (#1)I /O XC o m m a n dt B E R S o f c h i p #1i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /B60h D 0h A 30 :L o w A d d 60hA 30 : L o wA d d F 1h o r F 2h *60h D 0hA 30 :H i g h A d d60h A 30 : H i g h A d d t B E R S o f c h i p #2t B E R S o f c h i p #211I n t e r l e a v e T w o -P l a n e B l o c k E r a s eR /B (#1)I /O Xi n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /B≈≈≈ABCS t a t e A : C h i p #1 i s e x e c u t i n g a b l o c k e r a s e o p e r a t i o n , a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a b l o c k e r a s e c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g b l o c k e r a s e o p e r a t i o n .S t a t e C : B l o c k e r a s e o n c h i p #1 i s c o m p l e t e d a n d c h i p #1 i s r e a d y f o r t h e n e x t o p e r a t i o n . C h i p #2 i s s t i l l e x e c u t i n g b l o c k e r a s e o p e r a t i o n .S t a t e D : B o t h c h i p #1 a n d c h i p #2 a r e r e a d y .N o t e : *F 1h c o m m a n d i s r e q u i r e d t o c h e c k t h e s t a t u s o f c h i p #1 t o i s s u e t h e n e x t b l o c k e r a s e c o m m a n d t o c h i p #1. F 2h c o m m a n d i s r e q u i r e d t o c h e c k t h e s t a t u s o f c h i p #2 t o i s s u e t h e n e x t b l o c k e r a s e c o m m a n d t o c h i p #2.A s t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e t w o -p l a n e b l o c k e r a s e o n c h i p #1 a n d c h i p #2 a l t e r n a t i v e l y .DRead ID OperationCECLEWEALERE90hRead ID CommandMaker Code Device Code00h ECht REAAddress 1cycleI/Oxt ARDevice Device Code(2nd Cycle)3rd Cycle 4th Cycle 5th Cycle K9K8G08U0B DCh51h95h58hK9WAG08U1BSame as K9K8G08U0BDevice 4th cyc.Code3rd cyc.5th cyc.。
大容量闪存K9WAG08U0A的硬软件接口设计方法
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K9F4G08U0M中文资料
NC
NC
NC
NC
NC
NC
7
NC
/RE1 R/B2 IO7-2 IO6-2 IO5-2
NC
6
Vcc
/RE2 Vss
IO7-1 IO5-1
Vcc
5
4
/CE1 /CE2
R/B1 /WP2 IO6-1
IO4-1 IO4-2
3
CLE1 CLE2 /WE1
IO0-1 IO2-1
A B
0.65(Max.)
12-∅1.00±0.05
∅0.1 M C AB
Side View
17.00±0.10
41-∅0.70±0.05
∅0.1 M C AB
0.10 C
4
元器件交易网
K9K8G08U1M K9F4G08U0M
Advance FLASH MEMORY
K9K8G08U1M-ICB0/IIB0
12.00±0.10
#A1
17.00±0.10
(Datum A)
A B C D (Datum B) E F G H J K L M N
Bottom View
12.00±0.10
2.00
10.00
1.00
1.00
7 6 54 3 2 1
1.00
1.00
1.00
0.50
1.00
1.00
1.30
2.00 2.50 2.50
1
元器件交易网
K9K8G08U1M K9F4G08U0M
512M x 8 Bit / 1G x 8 Bits NAND Flash Memory
SMI主控FLASH支持列表
64Gbit 128Gbit 32Gbit 64Gbit
32Gbit
8G bit
32G bit 16G bit 16G bit 32Gbit 64Gbit 32Gbit 64Gbit 128Gbit 32G bit 64G bit 128G bit 32GB 128G bit 64G bit 128G bit 64G bit 64G bit 64G bit 64G bit 32G bit 32G bit 32G bit 32G bit 32G bit 32G bit 16G bit 16G bit 16G bit 16G bit 16G bit 16G bit 16G bit 8G bit 8G bit 8G bit 8G bit 8G bit 4G bit 4G bit 4G bit 2G bit 64G bit 32G bit 32G bit 32G bit 16G bit 16G bit 16G bit
Y
Y
Y
1CE 4b/512B
60nm
Y
Y
Y
2CE 4b/512B
90nm
Y
Y
Y
M 1CE 4b/512B
59nm
Y
Y
Y
S1CE 4b/512B
51nm
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
Y
N
Y
N
Y
N
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
K9WAG08U1M中文资料
K9XXG08UXMINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title1G x 8 Bit / 2G x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.10.2RemarkAdvance Advance PreliminaryHistory1. Initial issue1. Technical note is changedDraft DateMar. 1st. 2005Apr. 1st. 2005May 3rd. 2005GENERAL DESCRIPTIONFEATURES• Voltage Supply - 2.70V ~ 3.60V • Organization- Memory Cell Array : (1G + 32M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 20µs(Max.) - Serial Access : 25ns(Min.)1G x 8 Bit / 2G x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology- Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9K8G08U0M-YCB0/YIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- K9K8G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1M-YCB0/YIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- K9WAG08U1M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1M-ICB0/IIB052 - Pin TLGA (12 x 17 / 1.0 mm pitch)Offered in 1G x 8bit, the K9K8G08U0M is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K8G08U0M ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K8G08U0M is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. An ultra high density solution having two 8Gb stacked with two chip selects is also available in standard TSOPI package.PRODUCT LISTPart NumberVcc RangeOrganizationPKG Type K9K8G08U0M-Y ,P 2.70 ~ 3.60VX8TSOP1 K9WA G08U1M-Y ,P K9WA G08U1M-I52TLGA1.001.001.001.002.007 6 5 4 3 2 11.001.001.0012.00±0.10#A117.00±0.1017.00±0.10BA12.00±0.10(Datum B)(Datum A)12.0010.002.502.502.000.501.30A B C DEF GHJ K L M N12-∅1.00±0.0541-∅0.70±0.05Side View1.0(M a x .)0.10 C17.00±0.10Top ViewBottom ViewABC D EF G H J KL M N7654321K9WAG08U1M - ICB0 / IIB052-TLGA (measured in millimeters)NCNCNCNCNCNCNCNCNC NCNCNCNCNCNC NCVccVcc VssVssVss /RE1/RE2/CE1/CE2CLE1CLE2ALE1ALE2/WE1/WE2/WP1/WP2R/B1R/B2VssIO0-1IO0-2IO1-1IO1-2IO2-1IO3-1IO2-2IO3-2IO4-1IO4-2IO5-1IO5-2IO6-1IO6-2IO7-1IO7-2∅ABC M 0.1∅ABC M 0.1PACKAGE DIMENSIONSPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CE / CE1CHIP ENABLEThe CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation.Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation. CE2CHIP ENABLEThe CE2 input enables the second K9K8G08U0MREREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/B / R/B1READY/BUSY OUTPUTThe R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9K8G08U0M is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0M. The K9K8G08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K8G08U0M.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.The K9WAG08U1M is composed of two K9K8G08U0M chips which are selected separately by each CE1 and CE2. Therefore, in terms of each CE, the basic operation of K9WAG08U1M is same with K9K8G08U0M except some AC/DC charateristics.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hTwo-Plane Page Program(4)80h---11h81h---10hCopy-Back Program85h10hTwo-Plane Copy-Back Program(4)85h---11h81h---10hBlock Erase60h D0hTwo-Plane Block Erase60h---60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h ORead EDC Status(2)7Bh OChip1 Status(3)F1h OChip2 Status(3)F2h ONOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.3. Interleave-operation between two chips is allowed.It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.4.Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .Caution : Any undefined command inputs are prohibited except for above command set of Table 1.DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.3. The typical value of the K9WAG08U1M’s I SB 2 is 40µA and the maximum value is 200µA.4. The maximum value of K9WAG08U1M-Y ,P’s I LI and I LO is ±40µA , the maximum value of K9WAG08U1M-I’s I LI and I LO is ±20µA .ParameterSymbol Test ConditionsMinTypMaxUnitOperating CurrentPage Read withSerial Access I CC 1tRC=25nsCE=V IL, I OUT =0mA-1530mAProgramI CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -20100µAInput Leakage Current I LI V IN =0 to Vcc(max)--±20Output Leakage Current I LO V OUT =0 to Vcc(max)--±20Input High VoltageV IH (1)-0.8xVcc -Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH I OH =-400µA 2.4--Output Low Voltage Level V OL I OL =2.1mA --0.4Output Low Current(R/B)I OL (R/B)V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9XXG08UXM-XCB0 :T A =0 to 70°C, K9XXG08UXM-XIB0:T A =-40 to 85°C)ParameterSymbol Min Typ.Max Unit Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit Voltage on any pin relative to VSSV CC -0.6 to +4.6VV IN -0.6 to +4.6V I/O-0.6 to Vcc+0.3 (<4.6V)Temperature Under Bias K9XXG08UXM-XCB0T BIAS -10 to +125°C K9XXG08UXM-XIB0-40 to +125Storage Temperature K9XXG08UXM-XCB0T STG-65 to +150°CK9XXG08UXM-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested. K9WAG08U1M-IXB0’s capacitance(I/O, Input) is 20pF.ItemSymbol Test ConditionMin MaxUnit K9K8G08U0MK9WAG08U1M*Input/Output Capacitance C I/O V IL =0V -2040pF Input CapacitanceC INV IN =0V-2040pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.* : Each K9K8G08U0M chip in the K9WAG08U1M has Maximun 160 invalid blocks.ParameterSymbol Min Typ.Max Unit K9K8G08U0M N VB 8,032-8,192Blocks K9WAG08U1MN VB16,064*-16,384*BlocksAC TEST CONDITION(K9XXG08UXM-XCB0: T A =0 to 70°C, K9XXG08UXM-XIB0:T A =-40 to 85°C ,K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise noted)ParameterK9XXG08UXM Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF (K9K8G08U0M-Y ,P/K9WAG08U1M-I) 1 TTL GATE and CL=30pF (K9WAG08U1M-Y ,P)MODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byProgram / Erase CharacteristicsParameter Symbol Min Typ Max Unit Program Time t PROG-200700µs Dummy Busy Time for Two-Plane Page Program t DBSY-0.51µs Number of Partial Program Cycles Nop--4cycles Block Erase Time t BERS- 1.52msNOTE : 1. Typical value is measured at Vcc=3.3V, T A=25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C tempera-ture.AC Timing Characteristics for Command / Address / Data InputParameter Symbol Min Max UnitCLE Setup Time t CLS(1)12-nsCLE Hold Time t CLH5-nsCE Setup Time t CS(1)20-nsCE Hold Time t CH5-nsWE Pulse Width t WP12-nsALE Setup Time t ALS(1)12-nsALE Hold Time t ALH5-nsData Setup Time t DS(1)12-nsData Hold Time t DH5-nsWrite Cycle Time t WC25-nsWE High Hold Time t WH10-nsAddress to Data Loading Time t ADL(2)70-nsNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleAC Characteristics for OperationParameter Symbol Min Max Unit Data Transfer from Cell to Register t R-20µs ALE to RE Delay t AR10-ns CLE to RE Delay t CLR10-ns Ready to RE Low t RR20-ns RE Pulse Width t RP12-ns WE High to Busy t WB-100ns Read Cycle Time t RC25-ns RE Access Time t REA-20ns CE Access Time t CEA-25ns RE High to Output Hi-Z t RHZ-100ns CE High to Output Hi-Z t CHZ-30ns RE High to Output hold t RHOH15-ns RE Low to Output hold t RLOH5-ns CE High to Output hold t COH15-ns RE High Hold Time t REH10-ns Output Hi-Z to RE Low t IR0-ns RE High to WE Low t RHW100-ns WE High to RE Low t WHR60-ns Device Resetting Time(Read/Program/Erase)t RST-5/10/500(1)µs NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.NAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block table.StartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionNAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9K8G08U0M supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). EDC status bits are not available for sectors within which some bits or bytes are modified by Random Data Input operation. However, in case of the one time 528 byte sector unit modification at the same address, EDC status bits are available.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-nificant bit) pages of the block. Random page address programming is prohibited.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::Interleave Page ProgramK9K8G08U0M is composed of two K9F4G08U0Ms. K9K8G08U0M provides interleaving operation between two K9F4G08U0Ms. This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.At first, the host issues page program command to one of the K9F4G08U0M chips, say K9F4G08U0M(chip #1). Due to this K9K8G08U0M goes into busy state. During this time, K9F4G08U0M(chip #2) is in ready state. So it can execute the page program command issued by the host.After the execution of page program by K9F4G08U0M(chip #1), it can execute another page program regardless of the K9F4G08U0M(chip #2). Before that the host needs to check the status of K9F4G08U0M(chip #1) by issuing F1h command. Only when the status of K9F4G08U0M(chip #1) becomes ready status, host can issue another page program command. If the K9F4G08U0M(chip #1) is in busy state, the host has to wait for the K9F4G08U0M(chip #1) to get into ready state.Similarly, K9F4G08U0M chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F4G08U0M(chip #2) by issuing F2h command. When the K9F4G08U0M(chip #2) shows ready state, host can issue another page program command to K9F4G08U0M(chip #2).This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation.NOTES : During interleave operations, 70h command is prohibited.R / B (#1)b u s y o f C h i p #1I /O X80h10h C o m m a n d A 30 : L o w A d d & D a t a80h 10h A 30 : H i g h A d d & D a t ab u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e P a g e P r o g r a m≈≈≈F 1h o r F 2h A B CDa n o t h e r p a g e p r o g r a m o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a p a g e p r o g r a m o p e r a t i o n a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a p a g e p r o g r a m c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g p a g e p r o g r a m o p e r a t i o n .S t a t e C : P a g e p r o g r a m o n c h i p #1 i s t e r m i n a t e d , b u t p a g e p r o g r a m o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r p a g e p r o g r a m c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e p a g e p r o g r a m o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x hR / B (#1)b u s y o f C h i p #1I /O X60hD 0h C o m m a n d A 30 : L o w A d d60h D 0h A 30 : H i g h A d db u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e B l o c k E r a s e≈≈≈F 1h o r F 2h A B CDa n o t h e r B l o c k E r a s e o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a b l o c k e r a s e o p e r a t i o n , a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a b l o c k e r a s e c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g b l o c k e r a s e o p e r a t i o n .S t a t e C : B l o c k e r a s e o n c h i p #1 i s t e r m i n a t e d , b u t b l o c k e r a s e o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r b l o c k e r a s e c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e b l o c k e r a s e o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x h。
K9W8G08U1M 512内存
1
K9W8G08U1M K9K4G08Q0M K9K4G08U0M
K9K4G16Q0M K9K4G16U0M
FLASH MEMORY
512M x 8 Bit / 256M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part Number K9K4G08Q0M-Y K9K4G16Q0M-Y K9XXG08UXM-Y K9K4G16U0M-Y 2.7 ~ 3.6V Vcc Range 1.70 ~ 1.95V Organization X8 X16 X8 X16 TSOP1 PKG Type
K9W8G08U1M K9K4G08Q0M K9K4G08U0M
K9K4G16Q0M K9K4G16U0M
FLASH MEMORY
Document Title
512M x 8 Bit / 256M x 16 Bit NAND Flash Memory
Revision History
Revision No
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
K9WAG08U1A-PCB0中文资料
K9XXG08UXAINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.00.11.01.1RemarkAdvance PreliminaryFinal History1. Initial issue1. Leaded part is eliminated2. tRHW is definedment of "Addressing for program operation" is added (p.17)1. 4GB DSP is addedDraft DateNov. 09. 2005Jan. 10. 2006Mar. 7. 2006July 18th 2006GENERAL DESCRIPTIONFEATURES• Voltage Supply - 2.70V ~ 3.60V • Organization- Memory Cell Array : (1G + 32M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.) * K9NBG08U5A : 50ns(Min.)1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology- Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9K8G08U0A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9WAG08U1A-ICB0/IIB052 - Pin TLGA (12 x 17 / 1.0 mm pitch) - K9NBG08U5A-PCB0/PIB048 - Pin TSOP I (12 x 20 / 0.5 mm pitch)Offered in 1G x 8bit, the K9K8G08U0A is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns(K9NBG08U5A : 50ns) cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as com-mand input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K8G08U0A ′s extended reli-ability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. TheK9K8G08U0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.An ultra high density solution having two 8Gb stacked with two chip selects is also available in standard TSOPI package and another ultra high density solution having two 16Gb TSOPI package stacked with four chip selects is also available in TSOPI-DSP .PRODUCT LISTPart Number Vcc RangeOrganizationPKG Type K9K8G08U0A-Y 2.70 ~ 3.60VX8TSOP1K9WA G08U1A-Y K9WA G08U1A-I 52TLGA K9NBG08U5A-PTSOP1-DSP1.001.001.001.002.007 6 5 4 3 2 11.001.001.0012.00±0.10#A117.00±0.1017.00±0.10BA12.00±0.10(Datum B)(Datum A)12.0010.002.502.502.000.501.30A B C DEF GHJ K L M N12-∅1.00±0.0541-∅0.70±0.05Side View1.0(M a x .)0.10 C17.00±0.10Top ViewBottom ViewABC D EF G H J KL M N7654321K9WAG08U1A - ICB0 / IIB052-TLGA (measured in millimeters)NCNCNCNCNCNCNCNCNC NCNCNCNCNCNC NCVccVcc VssVssVss /RE1/RE2/CE1/CE2CLE1CLE2ALE1ALE2/WE1/WE2/WP1/WP2R/B1R/B2VssIO0-1IO0-2IO1-1IO1-2IO2-1IO3-1IO2-2IO3-2IO4-1IO4-2IO5-1IO5-2IO6-1IO6-2IO7-1IO7-2∅ABC M 0.1∅ABC M 0.1PACKAGE DIMENSIONSPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.There are two CE pins (CE 1 & CE 2) in the K9WAG08U1A and four CE pins (CE 1 & CE 2 & CE 3 & CE 4) in the K9NBG08U5A.There are two R/B pins (R/B1 & R/B2) in the K9WAG08U1A and four R/B pins (R/B1 & R/B2 & R/B3 & R/B4) in the K9NBG08U5A.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CE / CE1CHIP ENABLEThe CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is ignored, and the device does not return to standby mode in program or erase operation.Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation. CE2CHIP ENABLEThe CE2 input enables the second K9K8G08U0AREREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/B / R/B1READY/BUSY OUTPUTThe R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9K8G08U0A is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0A. The K9K8G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K8G08U0A.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.The K9WAG08U1A is composed of two K9K8G08U0A chips which are selected separately by each CE1 and CE2 and the K9NBG08U5A is composed of four K9K8G08U0A chips which are selected seperately by each CE1, CE2, CE3 and CE4. Therefore, in terms of each CE, the basic operations of K9WAG08U0A and K9NBG08U5A are same with K9K8G08U0A except some AC/DC charateristics.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hTwo-Plane Page Program(4)80h---11h81h---10hCopy-Back Program85h10hTwo-Plane Copy-Back Program(4)85h---11h81h---10hBlock Erase60h D0hTwo-Plane Block Erase60h---60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h ORead EDC Status(2)7Bh OChip1 Status(3)F1h OChip2 Status(3)F2h ONOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.3. Interleave-operation between two chips is allowed.It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.4.Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .Caution : Any undefined command inputs are prohibited except for above command set of Table 1.DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.3. The typical value of the K9WAG08U1A’s I SB 2 is 40µA and the maximum value is 200µA.4. The typical value of the K9NBG08U5A’s I SB 2 is 80µA and the maximum value is 400µA.5. The maximum value of K9WAG08U1A-P’s I LI and I LO is ±40µA , the maximum value of K9WAG08U1A-I’s I LI and I LO is ±20µA .6. The maximum value of K9NBG08U5A’s I LI and I LO is ±80µA.ParameterSymbol Test ConditionsMinTypMaxUnitOperating CurrentPage Read withSerial Access I CC 1tRC=25ns(K9NBG08U5A: 50ns)CE=V IL, I OUT =0mA-2535mAProgramI CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -20100µAInput Leakage Current I LI V IN =0 to Vcc(max)--±20Output Leakage Current I LO V OUT =0 to Vcc(max)--±20Input High VoltageV IH (1)-0.8xVcc -Vcc+0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH I OH =-400µA 2.4--Output Low Voltage Level V OL I OL =2.1mA --0.4Output Low Current(R/B)I OL (R/B)V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9XXG08UXA-XCB0 :T A =0 to 70°C, K9XXG08UXA-XIB0:T A =-40 to 85°C)ParameterSymbol Min Typ.Max Unit Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSVABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit Voltage on any pin relative to VSSV CC -0.6 to +4.6VV IN -0.6 to +4.6V I/O-0.6 to Vcc+0.3 (<4.6V)Temperature Under Bias K9XXG08UXA-XCB0T BIAS -10 to +125°C K9XXG08UXA-XIB0-40 to +125Storage Temperature K9XXG08UXA-XCB0T STG-65 to +150°CK9XXG08UXA-XIB0Short Circuit CurrentI OS5mACAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested. K9WAG08U1A-IXB0’s capacitance(I/O, Input) is 20pF.ItemSymbol Test Condition Min MaxUnit K9K8G08U0AK9WAG08U1A*K9NBG08U5AInput/Output Capaci-C I/O V IL =0V -204080pF Input CapacitanceC INV IN =0V-204080pFVALID BLOCKNOTE :1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.* : Each K9K8G08U0A chip in the K9WAG08U1A and K9NBG08U5A has Maximun 160 invalid blocks.Parameter Symbol Min Typ.Max Unit K9K8G08U0A N VB 8,032-8,192Blocks K9WAG08U1A N VB 16,064*-16,384*Blocks K9NBG08U5AN VB32,128*32,768*BlocksAC TEST CONDITION(K9XXG08UXA-XCB0: T A =0 to 70°C, K9XXG08UXA-XIB0:T A =-40 to 85°C ,K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise noted)ParameterK9XXG08UXA Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pF (K9K8G08U0A-P/K9WAG08U1A-I) 1 TTL GATE and CL=30pF (K9WAG08U1A-P) 1 TTL GATE and CL=30pF (K9NBG08U5A-P)MODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(5clock)H L L H H Write Mode Command Input L H L H H Address Input(5clock)L L L HH Data Input L L L H X Data Output X X X X H X During Read(Busy)X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-byProgram / Erase CharacteristicsNOTE : 1. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C tempera-ture .ParameterSymbol Min Typ Max Unit Program Time t PROG -200700µs Dummy Busy Time for Two-Plane Page Program t DBSY -0.51µs Number of Partial Program Cycles Nop --4cycles Block Erase Timet BERS- 1.52msAC Timing Characteristics for Command / Address / Data InputNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleParameterSymbol MinMaxUnitK9NBG08U5AK9K8G08U0A K9NBG08U5AK9K8G08U0A K9WAG08U1AK9WAG08U1ACLE Setup Time t CLS (1)2512--ns CLE Hold Time t CLH 105--ns CE Setup Time t CS (1)3520--ns CE Hold Time t CH 105--ns WE Pulse Width t WP 2512--ns ALE Setup Time t ALS (1)2512--ns ALE Hold Time t ALH 105--ns Data Setup Time t DS (1)2012--ns Data Hold Time t DH 105--ns Write Cycle Time t WC 4525--ns WE High Hold Timet WH 1510--ns Address to Data Loading Timet ADL (2)7070--nsAC Characteristics for OperationNOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.ParameterSymbol MinMaxUnitK9NBG08U5AK9K8G08U0A K9NBG08U5AK9K8G08U0A K9WAG08U1AK9WAG08U1AData Transfer from Cell to Register t R -2020µs ALE to RE Delay t AR 1010-ns CLE to RE Delay t CLR 1010-ns Ready to RE Low t RR 2020-ns RE Pulse Width t RP 2512-ns WE High to Busy t WB --100100ns Read Cycle Time t RC 5025--ns RE Access Time t REA --3020ns CE Access Time t CEA --4525ns RE High to Output Hi-Z t RHZ --100100ns CE High to Output Hi-Z t CHZ --3030ns RE High to Output hold t RHOH 1515--ns RE Low to Output hold t RLOH -5--ns CE High to Output hold t COH 1515--ns RE High Hold Time t REH 1510--ns Output Hi-Z to RE Low t IR 00--ns RE High to WE Low t RHW 100100--ns WE High to RE Lowt WHR 6060--ns Device Resetting Time(Read/Program/Erase)t RST--5/10/500(1)5/10/500(1)µsNAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block table.StartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionNAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9K8G08U0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-nificant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn’t need to be page 0.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::Interleave Page ProgramK9K8G08U0A is composed of two K9F4G08U0As. K9K8G08U0A provides interleaving operation between two K9F4G08U0As.This interleaving page program improves the system throughput almost twice compared to non-interleaving page program.At first, the host issues page program command to one of the K9F4G08U0A chips, say K9F4G08U0A(chip #1). Due to this K9K8G08U0A goes into busy state. During this time, K9F4G08U0A(chip #2) is in ready state. So it can execute the page program command issued by the host.After the execution of page program by K9F4G08U0A(chip #1), it can execute another page program regardless of the K9F4G08U0A(chip #2). Before that the host needs to check the status of K9F4G08U0A(chip #1) by issuing F1h command. Only when the status of K9F4G08U0A(chip #1) becomes ready status, host can issue another page program command. If the K9F4G08U0A(chip #1) is in busy state, the host has to wait for the K9F4G08U0A(chip #1) to get into ready state.Similarly, K9F4G08U0A chip(chip #2) can execute another page program after the completion of the previous program. The host can monitor the status of K9F4G08U0A(chip #2) by issuing F2h command. When the K9F4G08U0A(chip #2) shows ready state, host can issue another page program command to K9F4G08U0A(chip #2).This interleaving algorithm improves the system throughput almost twice. The host can issue page program command to each chip individually. This reduces the time lag for the completion of operation.NOTES : During interleave operations, 70h command is prohibited.R / B (#1)b u s y o f C h i p #1I /O X80h10h C o m m a n d A 30 : L o w A d d & D a t a80h 10h A 30 : H i g h A d d & D a t ab u s y o f C h i p #2i n t e r n a l o n l yR /B (#2)i n t e r n a l o n l yR /BI n t e r l e a v e P a g e P r o g r a m≈≈≈F 1h o r F 2h A B CDa n o t h e r p a g e p r o g r a m o n C h i p #1S t a t e A : C h i p #1 i s e x e c u t i n g a p a g e p r o g r a m o p e r a t i o n a n d c h i p #2 i s i n r e a d y s t a t e . S o t h e h o s t c a n i s s u e a p a g e p r o g r a m c o m m a n d t o c h i p #2.S t a t e B : B o t h c h i p #1 a n d c h i p #2 a r e e x e c u t i n g p a g e p r o g r a m o p e r a t i o n .S t a t e C : P a g e p r o g r a m o n c h i p #1 i s t e r m i n a t e d , b u t p a g e p r o g r a m o n c h i p #2 i s s t i l l o p e r a t i n g . A n d t h e s y s t e m s h o u l d i s s u e F 1h c o m m a n d t o d e t e c t t h e s t a t u s o f c h i p #1. I f c h i p #1 i s r e a d y , s t a t u s I /O 6 i s "1" a n d t h e s y s t e m c a n i s s u e a n o t h e r p a g e p r o g r a m c o m m a n d t o c h i p #1.S t a t e D : C h i p #1 a n d C h i p #2 a r e r e a d y .A c c o r d i n g t o t h e a b o v e p r o c e s s , t h e s y s t e m c a n o p e r a t e p a g e p r o g r a m o n c h i p #1 a n d c h i p #2 a l t e r n a t e l y .S t a t u sO p e r a t i o nS t a t u s C o m m a n d / D a t aF 1hF 2hAC h i p 1 : B u s y , C h i p 2 : R e a d y8x hC x hBC h i p 1 : B u s y , C h i p 2 : B u s y8x h8x hCC h i p 1 : R e a d y , C h i p 2 : B u s yC x h8x hDC h i p 1 : R e a d y , C h i p 2 : R e a d yC x hC x h。
K9G8G08U0M
52 - Pin ULGA (12 x 17 / 1.00 mm pitch) - K9LAG08U1M-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
2
K9LAG08U1M K9G8G08U0M
1G x 8 Bit / 2G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number K9G8G08U0M-P K9G8G08U0M-I K9LAG08U1M-I
Vcc Range 2.7V ~ 3.6V
Apr. 1st 2005 Advance
2. Technical note is changed.
0.2
1. AC Para. tRHW deleted
Sept. 1. 2005 Advance
2. the power recovery time of minmum is changed from 10µs to 100µs(p38)
GENERAL DESCRIPTION
Offered in 1Gx8bit, the K9G8G08U0M is a 8G-bit NAND Flash Memory with spare 256M-bit. Its NAND cell provides the most costeffective solution for the solid state mass storage market. A program operation can be performed in typical 800µs on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (256K+8K)byte block. Data in the data register can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9G8G08U0M′s extended reliability of 5K program/ erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9G8G08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
从闪存芯片编号识容量
从闪存芯片编号识容量根据芯片编号识容量三星的闪存芯片均以K9打头，与容量相关的字段是从第4位到第7位。
第4～5位表示闪存密度，12代表512M、16代表16M、28代表128M、32代表32M、40代表4M、56代表256M、64代表64M、80代表8M、1G代表1G 、2G代表2G、4G代表4G、8G代表8G、00代表没有。
第6～7位表示闪存结构，00代表没有、08代表×8.16代表×16. 32代表×32。
闪存芯片的容量=闪存密度×闪存结构÷8通过上述公式就可以计算出闪存芯片的真实容量了编号为K9K1G08U0M-YC80的SUMSUNG闪存芯片。
这块闪存芯片的规格为：128M×8bit、50ns 速度，单颗容量 128MB。
工作电压2.4～2.9V。
芯片编号K9F5608U0A，32M×8bit规格50ns速度，单颗容量32MB。
工作电压2.7～3.6V，内部分成块写区域大小（16K＋512）。
三星型号详解K9×××××：Nand FlashK8×××××：Nor FlashK7×××××：Sync SRAM(同步SRAM，带clock，速度快，网络产品，6个晶体管)K6×××××：Aync SRAM(异步SRAM，不带clock，速度快，手机产品，6个晶体管)K5×××××：MCP（相当于K1+K8+K9）K4×××××：DRAMK3×××××：Mask RomK2×××××：FRAMK1×××××：utRAM(使用SRAM技术，但只有2个晶体管跟1个电容，所以比SRAM功耗大，但成本低)samsung 编号：K9LAG08U0M，容量为2G，以K9L为开头的三星闪存一般都为MLC闪存，使用MLC闪存是大势所趋* K9K8G(1GB)、K9W8G(1GB)、K9WAG(2GB)* K9x1Gxxxxx = 1Gb (GigaBit) = 128MB (MegaByte)* K9x2Gxxxxx = 2Gb (GigaBit) = 256MB (MegaByte)* K9x4Gxxxxx = 4Gb (GigaBit) = 512MB (MegaByte)* K9x8Gxxxxx = 8Gb (GigaBit) = 1024MB (MegaByte)* (1 Byte = 8 bits)SAMSUNG K9F2808U0B-YCB0 32MBK9F2808U0C-VCB0 32MBK9F5608U0B-YCB0 16MBK9F5608U0C-YCB0 16MBK9F1208U0M-YCB0 64MBK9F1208U0A-YCB0 64MBK9F1208U0A-YIB0 64MBK9F1208U0A-VCB0 64MBK9K1G08U0A-YCB0 128MBK9K1G08U0M-YCB0 128MBK9K1G08U0M-VIB0 128MBK9F1G08U0M-YCB0 128MBK9F1G08U0A-YCB0 128MBK9F1G08U0M-VCB0 128MBK9F1G08U0M-VIB0 128MBK9F1G08U0M-FIB0 128MBK9K2G08U0M-YCB0 256MBK9K2G08U0A-FIB0 (90nm) 256MBK9K2G08U0M-VCB0 256MBK9K2G08U0M-VIB0 256MBK9K2G08U0A-VIB0 (90nm) 256MBK9F2G08U0M-YCB0 (90nm) 256MBK9K4G08U0M-YCB0 (90nm) 512MBK9K4G08U0M-YCBO(90nm) 512MBK9K4G08U0M-PIB0(90nm) 512MBK9W8G08U1M-YCB0(90nm) 1GBK9W8G08U1M-YIB0(90nm) 1GBK9WAG08U1M 2GMNAND闪存芯片, 一般都是Samsung 或Hynix 芯片. SAMSUNG闪存的型号及对应容量:K9x1Gxxxxx = 1Gb (GigaBit) = 128MB (MegaByte) K9x2Gxxxxx = 2Gb (GigaBit) = 256MB (MegaByte)K9x4Gxxxxx = 4Gb (GigaBit) = 512MB (MegaByte)K9x8Gxxxxx = 8Gb (GigaBit) = 1024MB (MegaByte) (1 Byte = 8 bits)Hynix闪存的型号及对应容量:HY27UH081G2M = 1Gb (GigaBit) = 128MB (MegaByte) HY27UH082G2M = 2Gb (GigaBit) = 256MB (MegaByte) HY27UH084G2M = 4Gb (GigaBit) = 512MB (MegaByte) HY27UH088G2M = 8Gb (GigaBit) = 1024MB (MegaByte) (1 Byte = 8 bits)Part No Description MfgNANDFLASHHY27US08281A-T(P)CB 16Mx8 HYNIXHY27US08561A-T(P)CB 32Mx8 HYNIXHY27US08121A-T(P)CB 64Mx8 HYNIXHY27UF081G2M-T(P)CB 128Mx8 HYNIXHY27UF082G2M-T(P)CB 256Mx8 HYNIXHY27UF082G2A-TPCB 256Mx8 HYNIXHY27UG084G2M-TPCB 512Mx8 HYNIXHY27UF084G2M-TPCB 512Mx8 HYNIXHY27UT084G2M-TPCB 512Mx8 HYNIXHY27UH088G2M-TPCB 1Gx8 HYNIXHY27UU085G2M-TPCB 1Gx8 HYNIXHynix闪存的型号及对应容量:HY27UH081G2M = 1Gb (GigaBit) = 128MB (MegaByte); HY27UH082G2M = 2Gb (GigaBit) = 256MB (MegaByte); HY27UH084G2M = 4Gb (GigaBit) = 512MB (MegaByte); HY27UH088G2M = 8Gb (GigaBit) = 1024MB (MegaByte) ATJ2051/ATJ2085主控支持的闪存FLASH型号列表品牌型号内存ATJ2085(2051) samsung K9K4G08U0M 512M ysamsung K9W4G08U1M 512M ysamsung K9W8G08U1M 1GB ysamsung K9F4G08U0M 512M ysamsung K9F4G08U0A 512M ysamsung K9K8G08U0M 1G ysamsung K9K8G08U0A 1G nsamsung K9WAG08U1M 2G ysamsung K9G4G08U0M 512M nsamsung K9L8G08U0M 1G nsamsung K9HAG08U1M 2G nHynix HY27UG084G1M 512M yHynix HY27UG084G2M 512M yHynix HY27UH084G1M 512M nHynix HY27UH084G2M 512M yHynix HY27UG088G2M 1G y Hynix HY27UG088G5M 1G n Hynix HY27UG088GDM 1G n Hynix HY27UH088G2M 1G y Hynix HY27UH088GDM 1G n Hynix HY27UH08AG5M 2G n Hynix HY27UH08AGDM 2G n Hynix HY27UF084G2M 512M y Hynix HY27UG088G5M 1GB n Hynix HY27UU088G5M 1G n Hynix HY27UV08AG5M 2G n Hynix HY27UT084G2A, 512M n Hynix HY27UT084G2M 512M n Hynix HY27UU088G 1GB nHynix HY27UU8G5M(MLC) 1GB n Hynix HY27UT4G2M(MLC) 512M n Hynix HY27UVAG5M(MLC) 2GB n Hynix HY27US08561M VPCB 428A 32MB HY27US08561M TPIB 427A 32MBHY27US08121M TCB 64MBHY27US08121M TPIB 407T 64MBHY27US08121M TCB 416A 64MBHY27US08121M TCB 422A 64MB HY27US08121M TCB 426A 64MB HY27US08121M TPCB 427B 64MB HY27US08121M VPCB 429A 64MB HY27UA081G1M TCB 128MBHY27UA081G1M TPCB 128MBHY27UA081G1M TCB 423A 128MB HY27UG082G2M 256MBHY27UH084G2M 512MBHY27UG088G5M 1GBHY27UH088G2M 1GBHY27UH08AG5M 2GBTOSHIBA TC58128AFT 16MBTC58128AFTI 16MBTC58DVM72A1FT00/05 16MBTC58256AFT 32MBTC58NVM8S0AFTI0 32MBTC58DVM82A1FT00/05 32MBTC58DVM82A1FTI0 32MBTC58512FT 64MBTC58DVM92A1FT00/05 64MBTH58100FT 128MBTC58DVG02A1FT00/05 128MBTC58NVG0S3AFT00/05 128MBTC58NVG0S3AFTI5 128MBTH58NVG1S3AFT00/05 256MBTH58NVG1S3AFTI0 256MBTC58NVG1S3BFT00 256MBTC58005FT 64MBTC58DVM94B1FT00/05 64MBTC58010FT 128MBTC58DVG04B1FT00/05 128MBTC58DVG14B1FT00/05 256MBTC58DVG14B1FTI0 256MBTH58DVG24B1FT00/05 512MBTC58NVG1D4BFT00 256MBTC58NVG1D4BFT00 256MBTC58NVG2D4BFT00 512MBTH58NVG3D4BFT00 1GBTH58NVG3D4BFTI0 1GBTC58NVG3D4CTG10 1GBTH58NVG4D4BTG20 2GBSANDISK SDTNFAH-128, SDTNGAHE0-128 16M SDTNFAH-256, SDTNGAHE0-256 32MSDTNFAH-512, SDTNGAHE0-512 64M SDTNFCH-512, SDTNGCHE0-512 64M SDTNFBH-1024, SDTNGBHE0-1024 128M SDTNFCH-1024, SDTNGCHE0-1024 128M SDTNFDH-2048, SDTNGDHE0-2048 256M Micron MT29F2G08A 256MBMT29F4G08B 256MBMT29F4G08BAB 512MMT29F8G08FAB 1G。
闪存芯片型号容量表
SLC闪存芯片型号容量表品牌类型容量型号Samsung SLC16M K9F2808U0M/A/B/C Samsung SLC16M K9F2816Q0C(x16) Samsung SLC32M K9F5608U0M/A/B/C Samsung SLC32M K9F5616U0C(x16) Samsung SLC32M K9F5616U0B(x16) Samsung SLC64M K9F1208U0M/A/B/C Samsung SLC64M K9F1208Q0CSamsung SLC64M K9K1216U0C(x16) Samsung SLC64M K9k1216Q0C(x16) Samsung SLC128M K9K1G08Q0ASamsung SLC128M K9K1G08U0M/A/B Samsung SLC128M K9K1G16U0A(x16) Samsung SLC128M K9F1G16U0M(x16) Samsung SLC128M K9F1G08U0ASamsung SLC128M K9F1G08R0ASamsung SLC128M K9F1G08U0M/A Samsung SLC128M K9F1G08R0M/A Samsung SLC128M K9F1G08U0BSamsung SLC128M K9F1G16Q0B(x16) Samsung SLC128M K9F1G16Q0M(x16) Samsung SLC256M K9E2G08U0MSamsung SLC256M K9E2G08U1MSamsung SLC256M K9K2G08U1ASamsung SLC256M K9K2G08Q0M/A Samsung SLC256M K9K2G08U0M/A Samsung SLC256M K9K2G16Q0M/A(x16) Samsung SLC256M K9K2G16U0M/A(x16) Samsung SLC256M K9F2G08U0MSamsung SLC256M K9F2G16U0M(x16) Samsung SLC256M K9F2G08U0ASamsung SLC256M K9F2G08R0ASamsung SLC512M K9W4G08U1MSamsung SLC512M K9W4G16U1M(x16) Samsung SLC512M K9K4G08U0M Samsung SLC512M K9F4G08U0M Samsung SLC1G K9W8G08U1M Samsung SLC1G K9K8G08U1M Samsung SLC1G K9K8G08U0M/A Samsung SLC1G K9F8G08U0M Samsung SLC2G K9WAG08U1M/A Samsung SLC2G K9KAG08U0M Samsung SLC4G K9NBG08U5M/A Samsung SLC4G K9WBG08U1M Samsung SLC8G K9NCG08U5MMicron SLC128M MT29F1G08ABBMicron SLC128M MT29F1G16ABB(x16) Micron SLC128M MT29F1G08ABCMicron SLC128M MT29F1G16ABC(x16) Micron SLC128M MT29F1G08AACMicron SLC128M MT29F1G16AAC(x16) Micron SLC128M MT29F1G08AACMicron SLC256M MT29F2G08AAAMicron SLC256M MT29F2G08AABMicron SLC256M MT29F2G16AAB(x16) Micron SLC256M MT29F2G08ABDMicron SLC256M MT29F2G16ABD(x16) Micron SLC256M MT29F2G08AADMicron SLC256M MT29F2G16AAD(x16) Micron SLC256M MT29F2G08ABBEA Micron SLC256M MT29F2G16ABBEA(x16) Micron SLC256M MT29F2G08ABAEA Micron SLC256M MT29F2G16ABAEA(x16) Micron SLC256M MT29F2G16AAA(x16) Micron SLC512M MT29F4G08BBCMicron SLC512M MT29F4G16BBC(x16) Micron SLC512M MT29F4G08BABMicron SLC512M MT29F4G16BAB(x16) Micron SLC512M MT29F4G08ABA/CMicron SLC512M MT29F4G16ABA/C(x16) Micron SLC512M MT29F4G08AAA/CMicron SLC512M MT29F4G08ABBDAMicron SLC512M MT29F4G16ABBDA(x16) Micron SLC512M MT29F4G08ABADAMicron SLC512M MT29F4G16ABADA(x16) Micron SLC512M MT29F4G16AAA/C(x16) Micron SLC1G MT29F8G08FABMicron SLC1G MT29F8G08DAAMicron SLC1G MT29F8G08BAAMicron SLC1G MT29F8G16BAA(x16) Micron SLC1G MT29F8G08ADBDAH4 Micron SLC1G MT29F8G16ADBDAH4(x16) Micron SLC1G MT29F8G08ADADAH4 Micron SLC1G MT29F8G16ADADAH4(x16) Micron SLC1G MT29H8G08ACAH1Micron SLC1G MT29F8G08ABABAMicron SLC1G MT29F8G08AAAMicron SLC2G MT29F16G08FAAMicron SLC2G MT29F16G16FAA(x16) Micron SLC2G MT29F16G08ABABA Micron SLC2G MT29H16G08ECAH1 Micron SLC2G MT29F16G08DAAMicron SLC4G MT29F32G08FAAMicron SLC4G MT29H32G08GCAH2 Micron SLC4G MT29F32G08AFABA Micron SLC8G MT29F64G08AJABAIntel SLC512M JS29F04G08AANB1Intel SLC1G JS29F08G08CANB1Intel SLC1G JS29F08G08BANB1Intel SLC1G JS29F08G08AANC1Intel SLC1G JS29F08G08AAND1/2Intel SLC2G JS29F16G08FANB1Intel SLC2G JS29F16G08AAND1/2Intel SLC2G JS29F16G08CANC1Intel SLC4G JS29F32G08FANC1Intel SLC4G JS29F32G08CAND1/2Intel SLC8G JS29F64G08JAND1/2 Spectek SLC128M FxxMx9xxxK3WGSpectek SLC512M FxxM40AxxK3xGSpectek SLC512M FxxMx9xxxK3W2Spectek SLC1G FxxM40AxxK3x2Spectek SLC1G FxxMx9xxxK3W4Spectek SLC1G FxxM51AxxK3xGSpectek SLC1G FxxM61AxxK3xGSpectek SLC2G FxxM40AxxK3x4Spectek SLC2G FxxM51AxxK3x2Spectek SLC2G FxxM62BxxK3xGSpectek SLC4G FxxM51AxxK3x4Spectek SLC4G FxxM62BxxK3x2Spectek SLC8G FxxM62BxxK3x4 PowerFlash SLC64M PF79AL1208 PowerFlash SLC64M PF79BL1208 PowerFlash SLC256M ASU2GA30GT PowerFlash SLC512M ASU4GA30GT Hynix SLC16M HY27US08281AHynix SLC16M HY27US16281A(x16)Hynix SLC32M HY27US08561M/AHynix SLC32M HY27US16562M/A(x16) Hynix SLC32M HY27SS08561M/AHynix SLC32M HY27SS16561M/A(x16) Hynix SLC64M HY27US08121M/AHynix SLC64M HY27US16121M/A(x16) Hynix SLC64M HY27SS08121M/AHynix SLC64M HY27SS16121M/A(x16) Hynix SLC128M H27U1G8F2BHynix SLC128M HY27UA081G4MHynix SLC128M HY27(U/S)A081G1M Hynix SLC128M HY27(U/S)A161G1M(x16) Hynix SLC128M HY27SS081G1XHynix SLC128M HY27UF081G2MHynix SLC128M HY27UF081G2AHynix SLC128M HY27SF081G2M(x16) Hynix SLC256M HY27(U/S)B082G4M Hynix SLC256M HY27(U/S)B162G4M(x16) Hynix SLC256M HY27UF082G2MHynix SLC256M HY27SF082G2MHynix SLC256M HY27UF162G2M(x16) Hynix SLC256M HY27SF162G2M(x16) Hynix SLC256M HY27UF082G2AHynix SLC256M HY27UF162G2A(x16) Hynix SLC256M HY27SF162G2A(x16) Hynix SLC256M HY27UF082G2BHynix SLC256M HY27SF082G2B(x16) Hynix SLC512M HY27UG084G2MHynix SLC512M HY27SG084G2MHynix SLC512M HY27UG164G2M(x16) Hynix SLC512M HY27SG164G2M(x16) Hynix SLC512M HY27UF084G2MHynix SLC512M HY27UF084G2BHynix SLC512M HY27UF164G2B(x16) Hynix SLC512M HY27SF084G2BHynix SLC512M HY27SF164G2B(x16) Hynix SLC1G HY27UH088G2MHynix SLC1G HY27UG088G5MHynix SLC1G HY27UG088G5BHynix SLC1G HY27UG088G2MHynix SLC1G H27U8G8F2MHynix SLC2G HY27UH08AG5MHynix SLC2G HY27UH08AG5BHynix SLC2G H27UAG8G5MHynix SLC4G HY27UK08BGFMHynix SLC4G HY27UK08BGFBHynix SLC4GB H27UBG8H5MHynix SLC8GB H27UCG8KFMST SLC16M NAND128R3AST SLC16M NAND128W3AST SLC16M NAND128R4A(x16)ST SLC16M NAND128W4A(x16) ST SLC32M NAND256R3AST SLC32M NAND256W3AST SLC32M NAND256R4A(x16)ST SLC32M NAND256W4A(x16) ST SLC64M NAND512R3AST SLC64M NAND512W3AST SLC64M NAND512R4A(x16)ST SLC64M NAND512W4A(x16) ST SLC64M NAND512W3BST SLC128M NAND01GR3AST SLC128M NAND01GW3AST SLC128M NAND01GR4A(x16) ST SLC128M NAND01GW4A(x16) ST SLC128M NAND01GW3B2AST SLC128M NAND01GR3B2BST SLC128M NAND01GW3B2BST SLC128M NAND01GR4B2B(x16) ST SLC128M NAND01GW4B2B(x16) ST SLC128M NAND01GR3B2CST SLC128M NAND01GW3B2CST SLC128M NAND01GR4B2C(x16) ST SLC128M NAND01GW4B2C(x16) ST SLC256M NAND02GR3B2CST SLC256M NAND02GW3B2CST SLC256M NAND02GR4B2C(x16)ST SLC256M NAND02GW4B2C(x16)ST SLC256M NAND02GR3B2DST SLC256M NAND02GW3B2DST SLC256M NAND02GR4B2D(x16)ST SLC256M NAND02GW3B2AST SLC256M NAND02GW4B2D(x16)ST SLC512M NAND04GW3B2BST SLC512M NAND04GR3B2DST SLC512M NAND04GW3B2DST SLC512M NAND04GR4B2D(x16)ST SLC512M NAND04GW4B2D(x16)ST SLC1G NAND08GW3B2AST SLC1G NAND08GR3B4CST SLC1G NAND08GW3B4CST SLC1G NAND08GR3B2CST SLC1G NAND08GW3B2CST SLC1G NAND08GR4B2C(x16)ST SLC1G NAND08GW4B2C(x16)ST SLC1G NAND08GW3F2AST SLC2G NAND16GW3B4DST SLC2G NAND16GW3F4AST SLC2G NAND16GW3F2AST SLC4G NAND32GW3F4A Toshiba SLC16M TC58DVM72A1FT00 Toshiba SLC32M TC58DVM82A1FT00 Toshiba SLC64M TC58NVM9S3BTG00 Toshiba SLC64M TC58NVM9S8CTA00(x16) Toshiba SLC64M TC58DVM92A1FT00 Toshiba SLC128M TC58DVG02A1FT00 Toshiba SLC128M TC58NVG0S3ETA00 Toshiba SLC128M TC58NVG0S3AFT05 Toshiba SLC128M TC58NVG0S3BTGI0 Toshiba SLC128M TC58NVG0S3BTG00 Toshiba SLC256M TC58DVG12A1FT00Toshiba SLC256M TH58NVG1S3AFT05 Toshiba SLC256M TC58NVG1S3BFT00 Toshiba SLC256M TC58NVG1S3BFT00 Toshiba SLC256M TC58NVG1S8BFT00(x16) Toshiba SLC256M TC58NVG1S8BFT00(x16) Toshiba SLC256M TC58NVG1S3ETA00 Toshiba SLC512M TH58NVG2S3BFT00 Toshiba SLC1G TC58NVG3S0DTG00 Toshiba SLC2G TH58NVG4S0DTG20 Toshiba SLC4G TC58NVG5S0DTG20 SanDisk SLC64M SDTNFCH-512SanDisk SLC128M SDTNKGHSM-1024 SanDisk SLC256M SDTNGBHE0-2048 SanDisk SLC256M SDTNGFHE0-2048 SanDisk SLC512M SDTNIHHSM-4096 SanDisk SLC512M SDTNIHHSM-4096(x16) SanDisk SLC512M SDTNKEHSM-4096 SanDisk SLC512M SDTNKEHSM-4096(x16) SanDisk SLC1G SDTNKFHSM-8192 SanDisk SLC1G SDTNLJAHSM-1024 SanDisk SLC1G SDTNKFHSM-8192(x16) SanDisk SLC2G SDTNKGHSM-16384 SanDisk SLC2G SDTNKGHSM-16384(x16) SanDisk SLC2G SDTNLJBHSM-2048 SanDisk SLC4G SDTNLJCHSM-4096 Infineon SLC64M HYF33DS512800ATC Infineon SLC64M HYF33DS512800BTC Infineon SLC64M HYF33DS512804(5)BTC/I Infineon SLC128M HYF33DS1G800CTI Spansion SLC64M S30MS512RSpansion SLC64M S39MS512RSpansion SLC128M S30MS01GRSpansion SLC128M S39MS01GRSpansion SLC256M S39MS02GRSpansion SLC256M S30MS02GR Spansion SLC512M S30MS04GR表制程CE Pin1111111111111111111112211111111211221 50nm12 50nm14 50nm2 50nm411111111111111 M69A1 M69A1 M69A1 M69A11111111 M60A1 M60A1 M60A1 M60A112211 M60A1 M60A1 M60A1 M60A1 50nm1 34nm1 50nm122 34nm1 50nm2 50nm2 50nm2 50nm2 34nm2 34nm2112 50nm1 34nm134nm1 50nm2 50nm2 34nm2 34nm411122 50nm1 34nm12 50nm2 34nm1 50nm2 34nm2 34nm211111111111111 41nm1111111221111111111111111111221 48nm12248nm244 48nm2 48nm4111111111111111111111111111111111111111122111112212111111 43nm111111111 43nm11 56nm1 56nm2 56nm21111111111111111111 65nm1 65nm1 65nm1 65nm1 65nm165nm1 65nm1。
NAND FLASH芯片种娄及规格
NAND FLASH芯片种娄及NAND FLASH芯片规格及NAND FLASH芯片数量专业IC烧录工厂 张工：yingming421@ qq:88037025芯片容量芯片编号芯片PIN数芯片封装芯片规格NAND512Mx 8HY27UF084G2B(PXA)48TSOP12mmx 20mmx 1.2mm NAND256Mx 16H8BXXX0MCP(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND256Mx 16K524G2GACB(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND256Mx 16KA100O015(QFIT)NAND256Mx 8H27U2G8F2C_(Y45H)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8TC58NVG1S3E(Y45H)48TSOP12mmx 20mmx 1.2mm NAND128Mx 16TYAB0A11125x(F31e)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8H27U1G8F2BT(OR01)48TSOP12mmx 20mmNAND128Mx 8MT29F1G08ABA(2027)63FBGA9mmx 11mmx 1.0mm NAND256Mx 8TC58NVG1S3E(SMP)48TSOP12.4mmx 20mmx 1.2mm NAND256Mx 8TC58NVG1S3E(SMPe)48TSOP12.4mmx 20mmx 1.2mm NAND256Mx 8H27U2G8F2C_(Y4502)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8TC58NVG1S3E(Y4502)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8MT29F2G08AAH4(PTS)63FBGA9mmx 11mmx 1.0mm NAND256Mx 8NAND02GW3B2D(PTS)63FBGA9mmx 11mmx 1.0mm NAND128Mx 8H8ACS0EJ0MCP(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND256Mx 8H8BCS0RJ0M46(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8NAND01GR3B2x(QFIT)63VFBGA9mmx 11mmx 1.05mm NAND128Mx 8H9DA1GG51HA3(MBF)107FBGA13mmx 10.5mmx 1.1mm NAND128Mx 8K9F1G08U0C/D(IJP)48TSOP12mmx 20mmx 1.2mm NAND64Mx 16H8BCS0QI0AAR(F53)149FBGA10mmx 14mmx 1.2mm NAND64Mx 16H8BCS0QI0AAR(F53e)149FBGA10mmx 14mmx 1.2mm NAND256Mx 8HY27UF082G2B(MBF1)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8HY27UF082G2B(MBF1e)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8NAND512R3A2D(SKCJC)63VFBGA9mmx 11mmx 1.05mm NAND64Mx 8NAND512R3A2D(SKCJN)63VFBGA9mmx 11mmx 1.05mm NAND128Mx 8H27S1G8F2BF(5551)63FBGA9mmx 11mmx 1.0mm NAND128Mx 8H27S1G8F2BF(5551e)63FBGA9mmx 11mmx 1.0mm NAND128Mx 8H9DA1GG1GJM(5551)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8H9DA1GG1GJM(5551e)130FBGA8mmx 9mmx 1.0mm NAND512Mx 16KF98G16Q4X(QFIT4et)63FBGA11mmx 11mmx 1.0mm NAND256Mx 8HY27UF082G2B(NB1)48TSOP12mmx 20mmNAND256Mx 8K9F2G08U0x__(NB1)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8TC58NVG1S3ET(NB1)48TSOP12mmx 20mmx 1.2mm NAND16Mx 8HY27US08281A(MBF1)48TSOP12mmx 20mmNAND16Mx 8HY27US08281A(MBFP)48TSOP12mmx 20mmNAND32Mx 8HY27US08561A(MBF1)48TSOP12mmx 20mmNAND32Mx 8HY27US08561A(MBFP)48TSOP12mmx 20mmNAND16Mx 8NAND128W3A2B(MBF1)48TSOP12mmx 20mmNAND16Mx 8NAND128W3A2B(MBFP)48TSOP12mmx 20mmNAND64Mx 8NAND512W3A(MBF1)48TSOP12mmx 20mmNAND64Mx 8NAND512W3A(MBFP)48TSOP12mmx 20mmNAND512Mx 16TY0D000114(QFIT4et)63TFBGA11mmx 10mmx 1.0mm NAND64Mx 16H8BCS0QIOAA(Q464e)149FBGA10mmx 14mmx 1.2mmNAND128Mx 16H9DA2GH1GHA(Q464e)107FBGA13mmx 10.5mmx 1.1mm NAND512Mx 16KAT008015M(NAv3)168FBGA12mmx 12mmx 1.0mm NAND32Mx 16TC58RYM9S8E(MV03)48FBGA7mmx 9mmx 1.0mm NAND64Mx 16TC58RYG0S8E(MV03)48FBGA7mmx 9mmx 1.0mm NAND128Mx 8K521F1GACA(MV02e)130FBGA8mmx 9mmx 1.0mm NAND512Mx 8TC58NVG2S3E(NAND)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8TC58NVG0S3ET(BT1)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8TC58NVG1S3ET(BT12G48TSOP12mmx 20mmx 1.2mm NAND16Mx 8HY27US08281M(PIX1)48TSOP12mmx 20mmNAND32Mx 8HY27US08561A(PIX1)48TSOP12mmx 20mmNAND16Mx 8NAND128W3A2B(PIX1)48TSOP12mmx 20mmNAND128Mx 8H9LA1GG51JM(5551e)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8K511F13ACC(5551e)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8K521F1GACA(5551e)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8KA100Z018M(5551e)215FBGA14mmx 14mmx 1.07mm NAND512Mx 8H8BES0UP0(Q464e)4G107FBGA13mmx 10.5mmx 1.1mm NAND64Mx 16H8ACS0QJ0MC(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16KAT008015M(NAv2)168FBGA12mmx 12mmx 1.0mm NAND128Mx 8H27U1G8F2BT(JV1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8H27U1G8F2BT(JV2)48TSOP12mmx 20mmx 1.2mm NAND512Mx 8K9F4G08U0D(MBF1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8H27U1G8F2BTR(HUM)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0C__(HUM)48TSOP12mmx 20mmx 1.2mm NAND64Mx 16H8ACS0QJ0MC(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8K9F1G08U0D__(PNX3)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8HY27UF082G2B(SOC3)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8K9F2G08U0C__(SOC3)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8TC58NVG0S3ET(MAV1)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8TC58DVM92A5(IJP)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8TC58NVG0S3ET(IJP)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8H27U2G8F2CTR(NAND)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8EHE01C021PB(5551e)215FBGA14mmx 14mmx 1.07mm NAND64Mx 8H8ACS0CF0AMR(5551e)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8KAL00R018A(5551e)215FBGA14mmx 14mmx 1.07mm NAND256Mx 16TYMCDD23124(E85)225BGA14mmx 11mmx 1.2mm NAND1Gx 8KFM8G16Q5M(NAv2)152FBGA14mmx 14mmx 1.07mm NAND128Mx 8H27U1G8F2BTR(PNX3)48TSOP12mmx 20mmx 1.2mm NAND512Mx 8K9F4G08U0D(NAND)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8TC58NVG1S3E(NAND)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8TC58NVG1S3E(NANDe)48TSOP12mmx 20mmx 1.2mm NAND256Mx 16KA100O0xD(Q400e)4G153FBGA9mmx 10mmx 1.2mm NAND512Mx 16KF98G16Q4X(Q4K2e)63FBGA11mmx 11mmx 1.0mm NAND512Mx 16KF98G16Q4X(Q4K3e)63FBGA11mmx 11mmx 1.0mm NAND128Mx 16TYLB0A21123x(F13)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 16TYLB0A21123x(F13e)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8NAND01GW3B2C(MDP9)48TSOP12mmx 20mmx 1.2mm NAND1Gx 8TC58DVG3S0E(NAND)48TSOP12mmx 20mmNAND1Gx 8TC58DVG3S0E(PXA)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8H9LA1GG51JM(5551)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8K511F13ACC(5551)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8K521F1GACA(5551)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8KA100Z018M(5551)215FBGA14mmx 14mmx 1.07mm NAND128Mx 8TY9A0A111311(5551)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8TYAA0A111376(5551)130FBGA8mmx 9mmx 1.0mm NAND1Gx16KAV00N002M/POP(MBF)201BGA13.0mm x13.0mmNAND512Mx 16K5W8G13ACM/POP(MBF)201BGA13.0mm x13.0mmNAND1Gx16KAV00N002M(MBF)136FBGA13mm x13mmNAND512Mx 16K5W8G13ACM(MBF)136FBGA13mm x13mmNAND128Mx 8K511F57ACD(NAv1)128FBGA12mmx 12mmx 1.0mm NAND128Mx 8K521F1GACA(MV02)130FBGA8mmx 9mmx 1.0mm NAND512Mx 16KBY00UxVA(Q400e)4G137FBGA13mmx 10.5mmx 0.9mm NAND128Mx 8H27U1G8F2BTR(IJP)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0C__(IJP)48TSOP12mmx 20mmx 1.2mm NAND512Mx 16KAT008015M(NAv1)168FBGA12mmx 12mmx 1.0mm NAND512Mx 16KFM8G16Q5M(NAv1)152FBGA14mmx 14mmx 1.07mm NAND128Mx 8H27U1G8F2BT(MBF1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8H27U1G8F2BT(MBF1e)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8TC58NVG0S3E(MBF1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8TC58NVG0S3E(MBF1e)48TSOP12mmx 20mmx 1.2mm NAND32Mx 8K9F5608U0D(NAND)48TSOP12mmx 20mmx 1.2mm NAND64Mx 16H8BCS0QIOMA(Q464e)149FBGA10mmx 14mmx 1.2mm NAND64Mx 16H8BCS0QIOMA(QFIT)149FBGA10mmx 14mmx 1.2mm NAND64Mx 8TC58DVM92A5(NAND)48TSOP12mmx 20mmNAND384Mx16KBN00X00XM(NAv5)152FBGA14mmx 14mmx 1.07mm NAND512Mx 8NAND04GW3B2x(MBF)48TSOP12mmx 20mmx 1.2mm NAND512Mx 8NAND04GW3B2x(MBFe)48TSOP12mmx 20mmx 1.2mm NAND128Mx 16PF58F0026M0Y1B2105S-CSP13mmx 11mmx 1.4mm NAND128Mx 16TYLB0A21123x(E82)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 16TYLB0A21123x(E82e)137FBGA13mmx 10.5mmx 1.0mm NAND256Mx 8K9F2G08U0B(MBF1)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8K9F2G08U0B(MBF1e)48TSOP12mmx 20mmx 1.2mm NAND512Mx 16MT29C8GxA(Q464e)4G137FBGA13mmx 10.5mmx 0.9mm NAND512Mx 16KBY00UxVM(Q464e)4G137FBGA13mmx 10.5mmx 0.9mm NAND128Mx 8CT48248NS(PI27e)119FBGA13.0mmx 10.0mmx 1.2mm NAND512Mx 8K9F4G08U0B(NA4G)48TSOP12mmx 20mmx 1.2mm NAND16Mx 8NAND128W3A2(QFIT)48TSOP12mmx 20mmNAND16Mx 8NAND128W3A2(QFITe)48TSOP12mmx 20mmNAND256Mx 8TC58NVG1S3E(2381)63TFBGA10mmx 13mmx 1.0mm NAND256Mx 8TC58NVG1S3E(2381e)63TFBGA10mmx 13mmx 1.0mm NAND512Mx 16NN5081K0H22(Q464e)137FBGA13mmx 10.5mmx 0.9mm NAND32Mx 8HY27US08561A(PIX)48TSOP12mmx 20mmNAND128Mx 8NAND01GW3B2C(MDP6)48TSOP12mmx 20mmx 1.2mm NAND384Mx16KBN00X00XM(NAv4)152FBGA14mmx 14mmx 1.07mm NAND1Gx 8K9F8G08U0M(NAND)48TSOP12mmx 20mmNAND384Mx16KBN00X00XM(NAv3)152FBGA14mmx 14mmx 1.07mm NAND256Mx 8NAND02GW3B2D(SMP)48TSOP12mmx 20mmNAND256Mx 8NAND02GW3B2D(SMPe)48TSOP12mmx 20mmNAND64Mx 8K5D1213ACK(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8K5E1213ACE(5551)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8TC58NVG0S3ET(NAND)48TSOP12mmx 20mmx 1.2mm NAND128Mx 16TYAB0A11125x(E81)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8CT48248NS(PI27)119FBGA13.0mmx 10.0mmx 1.2mm NAND64Mx 8H8ACS0CF0ACR(NAND)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8H8ACS0CF0ACR(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND32Mx 16TC58EVM9S8E(MV01)48FBGA7mmx 9mmx 1.0mm NAND64Mx 8NAND512W3A(IJP)48TSOP12mmx 20mmNAND128Mx 8TC58NYG0S3E(IJP)63TFBGA9mm倶 11mmNAND384Mx16KBN00X00XM(NAv1)152FBGA14mmx 14mmx 1.07mm NAND384Mx16KBN00X00XM(NAv2)152FBGA14mmx 14mmx 1.07mm NAND64Mx 8H27U518S2(IJP)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8MT29F1G08ABC(IJP)63VFBGA10.5mmx 13mmx 1mm NAND64Mx 8H27U518S2(NAND)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8MT29F1G08ABC(NAND)63VFBGA10.5mmx 13mmx 1mm NAND256Mx 16K5W4G2GACD(NAv1)152FBGA14mmx 14mmx 1.07mm NAND64Mx 8H27U518S2C(MDP7e)48TSOP12mmx 20mmx 1.2mm NAND128Mx 16KFM2G16Q2A(NAv2)63FBGA13mmx 10mmx 1.1mm NAND32Mx 16TY890A11122(Q464e)130FBGA8mmx 9mmx 1.0mm NAND32Mx 16TY890A11122(QFIT)130FBGA8mmx 9mmx 1.0mm NAND32Mx 16TY890A11122(QFITe)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8H27U1G8F2BTR(PNX2)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0C__(PNX2)48TSOP12mmx 20mmx 1.2mm NAND128Mx 16TYAB0A11125(Q464e)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8K9F1G08U0x(NAND)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0x(NANDe)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8MT29F1G08ABC(PI27)63VFBGA10.5mmx 13mmx 1mm NAND64Mx 8EHE01C021PB(5551)215FBGA14mmx 14mmx 1.07mm NAND64Mx 8EHE01C031PB(5551)215FBGA14mmx 14mmx 1.07mm NAND64Mx 8EHE01C041PB(5551)215FBGA14mmx 14mmx 1.07mm NAND64Mx 8KAL00R018A(5551)215FBGA14mmx 14mmx 1.07mm NAND128Mx 16TYLB0A21123x(E67)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 16TYLB0A21123x(E67e)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8K9F1G08U0C(MBF1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0C(MBF1e)48TSOP12mmx 20mmx 1.2mm NAND2Gx 8H27UAG8T2A__(P2e3)48TSOP12mmx 20mmNAND384Mx16KCD00D00BA(NAv1)152FBGA14mmx 14mmx 1.07mm NAND384Mx16KCD00D00BA(NAv2)152FBGA14mmx 14mmx 1.07mm NAND256Mx 16TYMCDD23124(QF4G)225BGA14mmx 11mmx 1.2mm NAND256Mx 16TYMCDD23124(QF4Ge)225BGA14mmx 11mmx 1.2mm NAND256Mx 8HY27UF082G2B(SOC1)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8HY27UF082G2B(SOC2)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8K9F2G08U0B__(SOC2)48TSOP12mmx 20mmx 1.2mmNAND256Mx 8K9F2G08U0x__(SOC1)48TSOP12mmx 20mmx 1.2mm NAND2Gx 8H27UAG8T2A__(P2)48TSOP12mmx 20mmNAND2Gx 8H27UAG8T2A__(P2e)48TSOP12mmx 20mmNAND128Mx 8H27U1G8F2BTR(SOC1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8H27U1G8F2BTR(SOC2)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0C__(SOC1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0C__(SOC2)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8H8BCS0CH0MMR(555e)130FBGA8mmx 9mmx 1.0mm NAND2Gx 8SDIN2C-2G169BGA16mmx 12mmx 0.85mm NAND512Mx 16KFM8GH6Q4M(MBF)101FBGA11mmx 9mmNAND512Mx 16KFM8GH6Q4M(MSG)101FBGA11mmx 9mmNAND256Mx 8HY27UF082G2B(B40)48TSOP12mmx 20mmNAND256Mx 8HY27UF082G2B(B40e)48TSOP12mmx 20mmNAND512Mx 16K558G13ACM/POP(MBF)201BGA13.0mm x13.0mm NAND512Mx 16K558G13ACM/POP(MSG)201BGA13.0mm x13.0mm NAND512Mx 16K558G13ACM(MSG)136FBGA13mm x13mmNAND32Mx 16TC58EVM9S8E(MV02)48FBGA7mmx 9mmx 1.0mm NAND64Mx 16TC58EVG0S8E(MV02)48FBGA7mmx 9mmx 1.0mm NAND128Mx 8HY27UF081G2A(MAV1)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8EHE01E031MA(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8EHF01C031MA(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8H8ACS0CF0AMR(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8H8ACS0CH0AMR(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8H8BCS0CH0AMR(5551)130FBGA8mmx 9mmx 1.0mm NAND128Mx 8K9F1G08U0C(MAV1)48TSOP12mmx 20mmx 1.2mm Nand2Gx 8THGVN1G4D1E52LGA18mm x14mmNAND2Gx 8THGVN1G4D1E(MDP)52LGA18mm x14mmNAND2Gx 8THGVN1G4D1E(PNP)52LGA18mm x14mmNAND2Gx 8THGVN1G4D1E(VFP)52LGA18mm x14mmNAND128Mx 8EHE01E051MA(NAND)130FBGA8mmx 9mmx 1.0mm NAND256Mx 16EHD013151MA(NAND)137FBGA13mmx 10.5mmx 1.0mm NAND384Mx16KFT6G16Q2A(NAv3)63FBGA11mmx 9mmx 1.4mm NAND64Mx 8HYC0SEF0MF3(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8HYC0SEF0MF3(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8HYC0SEH0AF3(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8H8ACS0EH0ACR(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8H8ACS0EH0ACR(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8HYG0SGH0MF3(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8HYG0SGH0MF3(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8K5D1258ACB(QFITe)137FBGA13mmx 10.5mmx 0.9mm NAND128Mx 8K5D1G13ACH(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8K5D1G13ACH(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8KAL00X00UM(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8KAL00X00UM(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8H8BCZ0CH0MMR(MDP1)130FBGA8mmx 9mmx 1.0mm NAND1Gx 8K9G8G08U0A(MDP5e)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8NAND02GW3B2D(MDP4)48TSOP12mmx 20mmx 1.2mmNAND256Mx 8HY27UF082G2B(BT12G48TSOP12mmx 20mmx 1.2mm NAND256Mx 8K9F2G08U0B__(BT12G48TSOP12mmx 20mmx 1.2mm NAND256Mx 8NAND02GW3B2D(BT12G48TSOP12mmx 20mmx 1.2mm NAND128Mx 8HY27UF081G2A(MDP2)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8HY27UF081G2A(PI27)63VFBGA9mmx 11mmx 1.05mm NAND128Mx 8NAND01GW3B2x(PI27)63VFBGA9mmx 11mmx 1.05mm NAND16Mx 8NAND128W3A2B(PIX)48TSOP12mmx 20mmNAND64Mx 8HYC0SEH0AF3(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8K5D1258ACB(QFIT)137FBGA13mmx 10.5mmx 0.9mm NAND32Mx 16KFG1216U2B(MV02)48FBGA7mmx 9mmx 1.0mm NAND128Mx 8NAND01GW3B2C(MV02)63VFBGA9mmx 11mmx 1.05mm NAND128Mx 8TC58NVG0S3CT(MV02)48TSOP12mmx 20mmx 1.2mm NAND64Mx 16KFG1G16U2C(MV02)48FBGA7mmx 9mmx 1.0mm NAND256Mx 16NANDC3R4N5A(NAND)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16NANDD3R4N5A(NAND)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8HY27US08121B(B3)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8K9F1208U0x(B3)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8NAND512W3A(B3)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8H27U1G8F2B__(BT1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8HY27UF081G2A(BT1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0B__(BT1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8NAND01GW3B2B(BT1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8NAND01GW3B2C(BT1)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8HY27UF081G2A(2027)63FBGA9mmx 11mmx 1.0mm NAND128Mx 8NAND01GW3B2B(2027)63VFBGA9mmx 11mmx 1.05mm NAND128Mx 8NAND01GW3B2C(2027)63VFBGA9mmx 11mmx 1.05mm NAND128Mx 8NAND01GW3B2xN48TSOP12mmx 20mmNAND384Mx16KFT6G16Q2A(NAv1)63FBGA11mmx 9mmx 1.4mm NAND16Mx 8HY27US08281M(PIX)48TSOP12mmx 20mmNAND128Mx 16TYA000B000Ax(D74)149FBGA10mmx 13.5mmx 1.4mm NAND128Mx 16TYA000B000Ax(D74e)149FBGA10mmx 13.5mmx 1.4mm NAND384Mx16KFT6G16Q2A(NAv2)63FBGA11mmx 9mmx 1.4mm NAND2Gx 8H27UAG8T2M__(P2)48TSOP12mmx 20mmNAND2Gx 8H27UAG8T2M__(P2e)48TSOP12mmx 20mmNAND2Gx 8HY27UU08AG5A(P2)48TSOP12mmx 20mmNAND2Gx 8HY27UU08AG5A(P2e)48TSOP12mmx 20mmNAND64Mx 8EHF01C022MA(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8TY990A111132(5551)130FBGA8mmx 9mmx 1.0mm NAND256Mx 16TYCC0A22111(QFIT)224FBGA12mmx 18mmx 1.2mm NAND256Mx 16TYCC0A22111(QFITe)224FBGA12mmx 18mmx 1.2mm NAND256Mx 16KAV00Q013M(NAv1)152FBGA14mmx 14mmx 1.07mm NAND128Mx 16TYA000B000Ax(D74B)149FBGA10mmx 13.5mmx 1.4mm NAND256Mx 8NAND02GW3B2D(S2P)48TSOP12mmx 20mmNAND256Mx 8NAND02GW3B2D(S2Pe)48TSOP12mmx 20mmNAND512Mx 16KFN8GH6Q4M(MBF)63FBGA13mmx 10mmx 1.1mm NAND128Mx 16TYA000B810Cx(E30e)225BGA14mmx 11mmx 1.2mm NAND512Mx 16K558G13ACM(MBF)136FBGA13mm x13mmNAND256Mx 16TYT7DT0000B(NAND)224FBGA12mmx 18mmx 1.2mm NAND256Mx 16TYT7DT0000B(QFIT)224FBGA12mmx 18mmx 1.2mm NAND256Mx 16TYT7DT0000B(QFITe)224FBGA12mmx 18mmx 1.2mm NAND256Mx 8NAND02GW3B2D(NAe)48TSOPNAND256Mx 8NAND02GW3B2D(NAND)48TSOPNAND256Mx 16NANDCBR4N3A(NAND)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16NANDCBR4N3A(QFIT)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16NANDCBR4N3A(QFITe)137FBGA13mmx 10.5mmx 0.9mm NAND512Mx 16NANDDBR4N5B(NAND)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16NANDDBR4N5B(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16NANDDBR4N5B(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 8HY27UF081G2A(B21G)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8K9F1G08U0B__(B21G)48TSOP12mmx 20mmx 1.2mm NAND128Mx 8NAND01GW3B2C(B21G)48TSOP12mmx 20mmx 1.2mm NAND256Mx 8NAND02GW3B2D(NAe)48TSOPNAND256Mx 8NAND02GW3B2D(NAND)48TSOPNAND128Mx 16TYL000BC00B(NL15e)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 16TYL000BC00B(NS15e)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 16TYL000BC00BFGP137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8K9F1208R0C(SKCJ_C)63FBGA8.5mmx 13mmx 1.0mm NAND64Mx 8K9F1208R0C(SKCJ_N)63FBGA8.5mmx 13mmx 1.0mm NAND2Gx 8K9GAG08U0M(B16)48TSOP12mmx 20mmx 1.2mm NAND2Gx 8K9GAG08U0M(B16e)48TSOP12mmx 20mmx 1.2mm NAND2Gx 8K9LAG08U0A(B16)48TSOP12mmx 20mmx 1.2mm NAND2Gx 8K9LAG08U0A(B16e)48TSOP12mmx 20mmx 1.2mm NAND512Mx 16NANDDBR4N5B(NAND)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16NANDDBR4N5B(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16NANDDBR4N5B(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16TYB000DCX1A(NAND)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16TYB000DCX1A(QFIT)137FBGA13mmx 10.5mmx 1.0mm NAND512Mx 16TYB000DCX1A(QFITe)137FBGA13mmx 10.5mmx 1.0mm NAND2Gx 8H27UAG8T2M(B40)48TSOP12mmx 20mmNAND2Gx 8H27UAG8T2M(B40e)48TSOP12mmx 20mmNAND2Gx 8HY27UU08AG5M(B40)48TSOP12mmx 20mmNAND2Gx 8HY27UU08AG5M(B40e)48TSOP12mmx 20mmNAND128Mx 8HY27UF081G2A(B40)48TSOP12mmx 20mmNAND128Mx 8HY27UF081G2A(B40e)48TSOP12mmx 20mmNAND512Mx 8HY27UT084G2A(B40)48TSOP12mmx 20mmNAND512Mx 8HY27UT084G2A(B40e)48TSOP12mmx 20mmNAND1Gx 8HY27UT088G2A(B40)48TSOP12mmx 20mmNAND1Gx 8HY27UT088G2A(B40e)48TSOP12mmx 20mmNAND1Gx 8HY27UT088G2M(B40)48TSOP12mmx 20mmNAND1Gx 8HY27UT088G2M(B40e)48TSOP12mmx 20mmNAND1Gx 8MT29F8G08MAD(B40)48TSOP12mmx 20mmNAND1Gx 8MT29F8G08MAD(B40e)48TSOP12mmx 20mmNAND128Mx 16K522H1HACA(Q464e)107FBGA13mmx 10.5mmx 1.1mm NAND64Mx 16TYA000A000A(Q464e)149FBGA10mmx 13.5mmx 1.4mmNAND256Mx 16KFN4G16Q2A(NAv3)63FBGA13mmx 10mmx 1.1mm NAND128Mx 16TYA000B810Cx(E30)225BGA14mmx 11mmx 1.2mm NAND128Mx 16K522H1HACA(NAND)107FBGA13mmx 10.5mmx 1.1mm NAND128Mx 16K522H1HACA(NANDe)107FBGA13mmx 10.5mmx 1.1mm NAND128Mx 16K522H1HACA(QFIT)107FBGA13mmx 10.5mmx 1.1mm NAND128Mx 16K522H1HACA(QFITe)107FBGA13mmx 10.5mmx 1.1mm NAND128Mx 16TYA000B810Cx(D69e)225BGA14mmx 11mmx 1.2mm NAND64Mx 8EHE01C011MA(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8EHF01C021MA(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8TY90009800B(5551)130FBGA8mmx 9mmx 1.0mm NAND256Mx 16KBY00N00HA(QFIT)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16KBY00N00HA(QFITe)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16NANDCBR4N3A(QFIT)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16NANDCBR4N3A(QFITe)137FBGA13mmx 10.5mmx 0.9mm NAND64Mx 16TYA000A000A(QFIT)149FBGA10mmx 13.5mmx 1.4mm NAND64Mx 16TYA000A000A(QFITe)149FBGA10mmx 13.5mmx 1.4mm NAND128Mx 8HY27UF081G2A(NAND)48TSOP12mmx 20mmNAND64Mx 8H8ACS0CF0MMR(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8H8ACS0CH0MMR(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8H8BCS0CH0MMR(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8HY27US08121B(B2)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8K9F1208U0x(B2)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8NAND512W3A(B2)48TSOP12mmx 20mmx 1.2mm NAND256Mx 16KFN4G16Q2A(NAv2)63FBGA13mmx 10mmx 1.1mm NAND256Mx 16TYT7DJ4000B(QFIT)224FBGA12mmx 18mmx 1.2mm NAND32Mx 8NAND256W3A(PNX)48TSOP12mmx 20mmNAND64Mx 8EHF01C011MA(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8K5D1213ACG(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8K5D1258ACC(5551)130FBGA8mmx 9mmx 1.0mm NAND64Mx 8K5E1213ACC(5551)130FBGA8mmx 9mmx 1.0mm NAND256Mx 8HY27UF082G2A48TSOPNAND128Mx 16TYBD00BC00AOGG225BGA14mmx 11mmx 1.2mm NAND128Mx 16KFM2G16Q2A(NAv1)63FBGA13mmx 10mmx 1.1mm NAND64Mx 8K9F1208R0C(NAND)63FBGA8.5mmx 13mmx 1.0mm NAND64Mx 8K9F1208R0C(QFIT)63FBGA8.5mmx 13mmx 1.0mm NAND64Mx 8HY27US08121B(F)48TSOP12mmx 20mmx 1.2mm NAND256Mx 16KBY00N00HA(NAND)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16NANDCBR4N3A(NAND)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16TYB000CC10A(NAND)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16TYB000CC10A(QFIT)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16TYB000CC10A(QFITe)137FBGA13mmx 10.5mmx 0.9mm NAND256Mx 16TYMC0A311136(NAND)137FBGA10.5mmx 13mmx 1.4mm NAND256Mx 16TYMC0A311136(QFIT)137FBGA10.5mmx 13mmx 1.4mm NAND256Mx 16TYMC0A311136(QFITe)137FBGA10.5mmx 13mmx 1.4mm NAND128Mx 16TYA000B810Cx(D70)225BGA14mmx 11mmx 1.2mm NAND128Mx 16TYA000B810Cx(D69)225BGA14mmx 11mmx 1.2mm NAND256Mx 16KFN4G16Q2A(NAv1)63FBGA13mmx 10mmx 1.1mmNAND64Mx 8NAND512R3A(NPBC)63VFBGA9mmx 11mmx 1.0mm NAND64Mx 8EHF0020A1x(5551)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8EHF0030A1x(5551)137FBGA13mmx 10.5mmx 1.0mm NAND64Mx 8K5D1213ACF(5551)137FBGA13mmx 10.5mmx 0.9mm NAND64Mx 8NAND512W3A48TSOP12mmx 20mmNAND128Mx 16TYB000BC00A(QFITe)225BGA14mmx 11mmx 1.2mm NAND128Mx 16TYB000BC00A(QFIT)225BGA14mmx 11mmx 1.2mm NAND256Mx 8K9F2G08U0x(NAND)48TSOPNAND64Mx 8TY90009000D(D71)149FBGA10mmx 13.5mmx 1.4mm NAND64Mx 8NAND512R3A(QFIT)63VFBGA9mmx 11mmx 1.0mm NAND128Mx 16KAF00F900M(NAv4)109FBGA13mm x13mm x1.09mm NAND128Mx 16KAF00F900M(NAv5)109FBGA13mm x13mm x1.09mm NAND64Mx 16TY000AC00G(QFIT)225BGA14mmx 11mmx 1.2mm NAND64Mx 16TYK000AC00G(NAND)225BGA14mmx 11mmx 1.2mm NAND64Mx 8NAND512R3A(NABC)63VFBGA9mmx 11mmx 1.0mm NAND128Mx 16KAF00F900M(NAv3)109FBGA13mm x13mm x1.09mm NAND64Mx 8TY90009000D(D55v2)149FBGA10mmx 13.5mmx 1.4mm NAND32Mx 16TY90009000L(NAND)149FBGA10mmx 13.5mmx 1.4mm NAND64Mx 16TYK000AC00F(NAND)225BGA14mmx 11mmx 1.2mm NAND32Mx 8NAND256R3A(NABZ)55VFBGA10mm x 8mmNAND256Mx 8HY27UF082G2A(NAND)48TSOPNAND64Mx 8HYC0SEF0MF3(5551)137FBGA13mmx 10.5mmx 1.0mm NAND128Mx 16KAF00F900M(NAv1)109FBGA13mm x13mm x1.09mm NAND128Mx 16KAF00F900M(NAv2)109FBGA13mm x13mm x1.09mm NAND128Mx 8K9F1G08R0A(QFIT)63FBGA12mm x9.5mm x1.2mm NAND128Mx 16TYBD00BC00BTGK224FBGA12mmx 18mmx 1.2mm NAND128Mx 8NAND01GW3B2xN48TSOP12mmx 20mmNAND64Mx 8HY27US08121B(NAND)48TSOPNAND128Mx 16TYA000BC10Cx(D60)225BGA14mmx 11mmx 1.2mm NAND64Mx 8K5D1258ACB(5551)137FBGA13mmx 10.5mmx 0.9mm NAND64Mx 8K5D1213ACE137FBGA13mmx 11.5mmx 1.1mm NAND256Mx 16TYB000CC10BOGG225BGA14mmx 11mmx 1.2mm NAND64Mx 8K9F1208U0x(F)48TSOP12mmx 20mmx 1.2mm NAND64Mx 8NAND512W3A(F)48TSOP12mmx 20mmx 1.2mm NAND64Mx 16TY9000A000E(QFIT)149FBGA10mmx 13.5mmx 1.4mm NAND128Mx 16TYL000BC00B0GG10225BGA14mmx 11mmx 1.2mm NAND128Mx 16TYL000BC10(100)225BGA14mmx 11mmx 1.2mm NAND128Mx 16TYL000BC10B(105)225BGA14mmx 11mmx 1.2mm NAND128Mx 16TC58NVG1S8CTG0548TSOPNAND32Mx 8NAND256R3A55VFBGA10mm x 8mmNAND16Mx 16KFG5616Q1A(MV01)48FBGA7mmx 9mmx 1.0mm NAND16Mx 16KFG5616U1A(MV01)48FBGA7mmx 9mmx 1.0mm NAND32Mx 16KFG1216Q2B(MV01)48FBGA7mmx 9mmx 1.0mm NAND32Mx 16KFG1216U2B(MV01)48FBGA7mmx 9mmx 1.0mm NAND128Mx 16TYA000BC00C(QF20)225BGA14mmx 11mmx 1.2mm NAND256Mx 8KMZGE0A0AM(NAND)199FBGA16mmx 12mmNAND256Mx 8KMZGE0A0AM(QF20)199FBGA16mmx 12mmNAND64Mx 16TYK000AC00E(QF20)225BGA14mmx 11mmx 1.2mm NAND128Mx 16TYT7TD9000B(QF20)224FBGA12mmx 18mmx 1.2mm NAND64Mx 16TYK000AC00E(NAND)225BGA14mmx 11mmx 1.2mm NAND128Mx 8KAL00M00WM-AJ55137FBGA10.5mmx 13mmx 1.4mm NAND1Gx 8K9K8G08U0A(NA4G)48TSOPNAND1Gx 8K9K8G08U0A(NA8G)48TSOPNAND128Mx 16TYT5ZW9000BTGK224FBGA12mmx 18mmx 1.2mm NAND32Mx 8HY27US08561x(5551)63TBGA9mmx 11mmNAND32Mx 8K9F5608U0x__(5551)63TBGA9mmx 11mmNAND256Mx 8TYA000B410(D42)149FBGA10mmx 13.5mmx 1.4mm NAND256Mx 8TYA000B410(D42WS)149FBGA10mmx 13.5mmx 1.4mm NAND64Mx 8HYC0SEH0MF3(NAND)137FBGA10.5mmx 13mmx 1.4mm NAND64Mx 8D422863VFBGA9mmx 11mmx 1.0mm NAND16Mx 16KFG5616U1A-DIB548FBGA7mmx 9mmx 1.0mm NAND256Mx 8KBE00S003M(NAND)107FBGA14mmx 12mmx 1.3mm NAND256Mx 8KBE00S00AM(NAND)137FBGA14mmx 12mmx 1.33mm NAND256Mx 16KCCB0CB00M(NAND)109FBGA11.5mmx 13mmx 1.4mm NAND64Mx 8NAND512R3A2BZA6E63VFBGA9mmx 11mmx 1.0mm NAND128Mx 8K9K1G08R0B(NAND)63FBGA8.5mmx 13mmx 1.0mm NAND64Mx 8K9F1208R0B(NAND)63FBGA8.5mmx 13mmx 1.0mm NAND32Mx 16K9K1216Q0C(NAND)63TBGA9mmx 11mmNAND32Mx 16KAU26N000M(NAND/0)109FBGA11.5mmx 13mmx 1.4mm NAND32Mx 16KAU26N000M(NAND/1)109FBGA11.5mmx 13mmx 1.4mm NAND64Mx 16KAU26N000M109FBGA11.5mmx 13mmx 1.4mm NAND64Mx 16KAU26W000M(NAND/0)109FBGA11.5mmx 13mmx 1.4mm NAND64Mx 16KAU26W000M(NAND/1)109FBGA11.5mmx 13mmx 1.4mm NAND101.2Mx 16K AU26W000M109FBGA11.5mmx 13mmx 1.4mm NAND8Gx 8SDIN2B2-8G169BGA18mmx 12mmx 0.85mm NAND2Gx 8SDIN2C2-2G169BGA16mmx 12mmx 0.85mm.0mm .5mmx 1.0mm 20mmx 1.2mm 20mmx 1.2mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.1mm.5mmx 1.1mm mmx 1.07mm .5mmx 1.1mm .5mmx 1.0mm .5mmx 1.0mmmmx 1.07mm mmx 1.07mm mmx 1.07mm.5mmx 1.0mm .5mmx 1.0mm7mm.5mmx 0.9mm mmx 1.07mmmmx 1.07mm.5mmx 1.0mm .5mmx 1.0mm .5mmx 0.9mm .5mmx 0.9mm 10.0mmx 1.2mm.5mmx 0.9mm mmx 1.07mmmmx 1.07mm 10.0mmx 1.2mm .5mmx 1.0mm .5mmx 1.0mm mmx 1.07mm mmx 1.07mmmmx 1.07mm mmx 1.07mm mmx 1.07mm mmx 1.07mm mmx 1.07mm.5mmx 1.0mm .5mmx 1.0mm mmx 1.07mm mmx 1.07mm5mm.5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 0.9mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm.0mm .5mmx 0.9mm .5mmx 1.0mm .5mmx 1.0mm.5mmx 1.4mm .5mmx 1.4mm mmx 1.07mm .5mmx 1.4mm.9mm .5mmx 0.9mm .5mmx 0.9mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm 3mmx 1.0mm 3mmx 1.0mm.5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.0mm .5mmx 1.1mm .5mmx 1.4mm.1mm .5mmx 1.1mm .5mmx 1.1mm .5mmx 1.1mm .5mmx 0.9mm .5mmx 0.9mm .5mmx 0.9mm .5mmx 0.9mm .5mmx 1.4mm .5mmx 1.4mm3mmx 1.0mm 3mmx 1.0mm .5mmx 0.9mm .5mmx 0.9mm .5mmx 0.9mm .5mmx 0.9mm .5mmx 0.9mm 13mmx 1.4mm 13mmx 1.4mm 13mmx 1.4mm.0mm .5mmx 1.0mm .5mmx 0.9mm .5mmx 1.4mm mm x1.09mm mm x1.09mmmm x1.09mm .5mmx 1.4mm .5mmx 1.4mm .5mmx 1.0mm mm x1.09mm mm x1.09mm 5mm x1.2mm.5mmx 0.9mm .5mmx 1.1mm .5mmx 1.4mm.4mm .5mmx 1.4mm .5mmx 1.4mm 13mmx 1.4mm mmx 1.33mm 13mmx 1.4mm 3mmx 1.0mm 3mmx 1.0mm 13mmx 1.4mm 13mmx 1.4mm 13mmx 1.4mm 13mmx 1.4mm 13mmx 1.4mm 13mmx 1.4mm mmx 0.85mm mmx 0.85mm。
K9F1G08U0B
K9XXG08UXBINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document Title128M x 8 Bit NAND Flash Memory Revision HistoryThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the rightto change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.Revision No0.01.0RemarkAdvance FinalHistory1. Initial issue1. 1.8V device is eliminatedDraft DateMay 26. 2006Sep. 27. 2006GENERAL DESCRIPTIONFEATURES• Voltage Supply- 3.3V Device(K9F1G08U0B) : 2.70V ~ 3.60V • Organization- Memory Cell Array : (128M + 4M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation- Page Size : (2K + 64)Byte - Random Read : 25µs(Max.) - Serial Access : 25ns(Min.)128M x 8 Bit NAND Flash Memory• Fast Write Cycle Time- Page Program time : 200µs(Typ.) - Block Erase Time : 1.5ms(Typ.)• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection- Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology-Endurance : 100K Program/Erase Cycles with 1bit/512Byte ECC)- Data Retention : 10 Years • Command Driven Operation• Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package :- K9F1G08U0B-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)Offered in 128Mx8bit, the K9F1G08U0B is a 1G-bit NAND Flash Memory with spare 32M-bit. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1G08U0B ′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08U0B is an optimum solu-tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.PRODUCT LISTPart Number Vcc Range OrganizationPKG Type K9F1G08U0B-P2.70 ~3.60Vx8TSOP1PIN CONFIGURATION (TSOP1)K9F1G08U0B-PCB0/PIB0PACKAGE DIMENSIONS48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220FUnit :mm/Inch0.787±0.00820.00±0.20#1#240.20+0.07-0.030.008+0.003-0.0010.500.0197#48#250.48812.40M A X12.000.4720.10 0.004M A X 0.250.010()0.039±0.0021.00±0.050.0020.05MIN0.0471.20MAX0.45~0.750.018~0.0300.724±0.00418.40±0.100~8°0.0100.25T Y P0.125+0.0750.0350.005+0.003-0.0010.500.020()48-pin TSOP1Standard Type 12mm x 20mm123456789101112131415161718192021222324484746454443424140393837363534333231302928272625N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.CN.C N.C N.C N.C I/O7I/O6I/O5I/O4N.C N.C N.C Vcc Vss N.C N.C N.C I/O3I/O2I/O1I/O0N.C N.C N.C N.CPIN DESCRIPTIONNOTE : Connect all V CC and V SS pins of each device to common power supply outputs. Do not leave V CC or V SS disconnected.Pin Name Pin FunctionI/O 0 ~ I/O 7DATA INPUTS/OUTPUTSThe I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.CLECOMMAND LATCH ENABLEThe CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ALEADDRESS LATCH ENABLEThe ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.CECHIP ENABLEThe CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation.REREAD ENABLEThe RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WEWRITE ENABLEThe WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.WPWRITE PROTECTThe WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low.R/BREADY/BUSY OUTPUTThe R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.Vcc POWERV CC is the power supply for device. Vss GROUNDN.CNO CONNECTIONLead is not internally connected.Product IntroductionThe K9F1G08U0B is a 1,056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2,112x8 columns. Spare 64x8 col-umns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodat-ing data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08U0B.The K9F1G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 132M byte physical space requires 28 addresses, thereby requiring four cycles for addressing : 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com-mand register. Table 1 defines the specific commands of the K9F1G08U0B.In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.Table 1. Command SetsFunction1st Cycle2nd Cycle Acceptable Command during Busy Read 00h30hRead for Copy Back00h35hRead ID90h-Reset FFh-OPage Program80h10hCopy-Back Program85h10hBlock Erase60h D0hRandom Data Input(1)85h-Random Data Output(1)05h E0hRead Status70h ORead EDC Status(2)7Bh ONOTE : 1. Random Data Input/Output can be executed in a page.2. Read EDC Status is only available on Copy Back operation.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.FLASH MEMORYK9F1G08U0BDC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)NOTE : 1. V IL can undershoot to -0.4V and V IH can overshoot to V CC +0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.ParameterSymbol Test ConditionsK9F1G08U0B(3.3V)UnitMinTypMaxOperating CurrentPage Read with Serial Access I CC 1tRC=25nsCE=V IL, I OUT =0mA-1530mAProgram I CC 2-EraseI CC 3-Stand-by Current(TTL)I SB 1CE=V IH , WP=0V/V CC --1Stand-by Current(CMOS)I SB 2CE=V CC -0.2, WP=0V/V CC -1050µAInput Leakage Current I LI V IN =0 to Vcc(max)--±10Output Leakage Current I LO V OUT =0 to Vcc(max)--±10Input High VoltageV IH (1)-0.8xVcc -V CC +0.3V Input Low Voltage, All inputs V IL (1)--0.3-0.2xVccOutput High Voltage Level V OH K9F1G08U0A :I OH =-400µA 2.4--Output Low Voltage Level V OLK9F1G08U0A :I OL =2.1mA--0.4Output Low Current(R/B)I OL (R/B)K9F1G08U0A :V OL =0.4V810-mA RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, K9F1G08U0B-XCB0 :T A =0 to 70°C, K9F1G0808B-XIB0:T A =-40 to 85°C)ParameterSymbol K9F1G08U0B(3.3V)UnitMin Typ.Max Supply Voltage V CC 2.7 3.3 3.6V Supply VoltageV SSV ABSOLUTE MAXIMUM RATINGSNOTE :1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.ParameterSymbol Rating Unit3.3V Device Voltage on any pin relative to VSSV CC-0.6 to + 4.6VV IN -0.6 to + 4.6V I/O-0.6 to Vcc + 0.3 (< 4.6V)Temperature Under BiasK9XXG08XXB-XCB0T BIAS -10 to +125°C K9XXG08XXB-XIB0-40 to +125Storage Tempera-tureK9XXG08XXB-XCB0T STG-65 to +150°CK9XXG08XXB-XIB0Short Circuit CurrentI OS5mAw w w .DFLASH MEMORYK9F1G08U0BCAPACITANCE (T A =25°C, V CC =3.3V, f=1.0MHz)NOTE : Capacitance is periodically sampled and not 100% tested.ItemSymbol Test ConditionMin Max Unit Input/Output Capacitance C I/O V IL =0V -10pF Input CapacitanceC INV IN =0V-10pFVALID BLOCKNOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.ParameterSymbol Min Typ.Max Unit K9F1G08U0BN VB1,004-1,024BlocksMODE SELECTIONNOTE : 1. X can be V IL or V IH.2. WP should be biased to CMOS high or CMOS low for standby.CLE ALE CE WERE WP ModeH L L H X Read Mode Command Input L H L H X Address Input(4clock)H L L H H Write ModeCommand Input L H L H H Address Input(4clock)L L L HH Data Input L L L H X Data Output X X X X H X DuringRead(Busy)X X X X X H DuringProgram(Busy)X X X X X H DuringErase(Busy)X X (1)X X X L Write Protect XXHXX0V/V CC (2)Stand-by AC TEST CONDITION(K9F1G08U0B-XCB0 :TA=0 to 70°C, K9F1G08U0B-XIB0:TA=-40 to 85°C, K9F1G08U0B : Vcc=2.7V~3.6V unless otherwise noted)ParameterK9F1G08U0B Input Pulse Levels 0V to Vcc Input Rise and Fall Times 5ns Input and Output Timing Levels Vcc/2Output Load1 TTL GATE and CL=50pFFLASH MEMORYK9F1G08U0BAC Timing Characteristics for Command / Address / Data InputNOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycleParameterSymbol Min Max Unit CLE Setup Time t CLS (1)12-ns CLE Hold Time t CLH 5-ns CE Setup Time t CS (1)20-ns CE Hold Time t CH 5-ns WE Pulse Width t WP 12-ns ALE Setup Time t ALS (1)12-ns ALE Hold Time t ALH 5-ns Data Setup Time t DS (1)12-ns Data Hold Time t DH 5-ns Write Cycle Time t WC 25-ns WE High Hold Timet WH 10-ns Address to Data Loading Timet ADL (2)100-nsProgram / Erase CharacteristicsNOTE : 1. Typical value is measured at Vcc=3.3V, T A =25°C. Not 100% tested.2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at3.3V Vcc and 25°C temperature .ParameterSymbol Min Typ Max Unit Program Time t PROG -200700µs Dummy Busy Time for Two-Plane Page Program t DBSY -0.51µs Number of Partial Program Cycles Nop --4cycles Block Erase Timet BERS- 1.52msw w w .D a t a S h eAC Characteristics for OperationParameter Symbol Min Max Unit Data Transfer from Cell to Register t R-25µs ALE to RE Delay t AR10-ns CLE to RE Delay t CLR10-ns Ready to RE Low t RR20-ns RE Pulse Width t RP12-ns WE High to Busy t WB-100ns Read Cycle Time t RC25-ns RE Access Time t REA-20ns CE Access Time t CEA-25ns RE High to Output Hi-Z t RHZ-100ns CE High to Output Hi-Z t CHZ-30ns CE High to ALE or CLE Don’t Care t CSD10-ns RE High to Output Hold t RHOH15-ns RE Low to Output Hold t RLOH5-ns CE High to Output Hold t COH15-ns RE High Hold Time t REH10-ns Output Hi-Z to RE Low t IR0-ns RE High to WE Low t RHW100-ns WE High to RE Low t WHR60-ns Device Resetting Time(Read/Program/Erase)t RST-5/10/500(1)µs NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.NAND Flash Technical NotesIdentifying Initial Invalid Block(s)Initial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select tran-sistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit /512Byte ECC.All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The ini-tial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original initial invalid block information is prohibited.*Check "FFh" at the column address 2048 Figure 3. Flow chart to create initial invalid block tableStartSet Block Address = 0Check "FFh"Increment Block AddressLast Block ?EndNoYesYesCreate (or update)NoInitialof the 1st and 2nd page in the blockInvalid Block(s) TableNAND Flash Technical Notes (Continued)Program Flow ChartStartI/O 6 = 1 ?I/O 0 = 0 ?No*Write 80hWrite AddressWrite DataWrite 10hRead Status RegisterProgram Completedor R/B = 1 ?Program ErrorYesNoYes: If program operation results in an error, map out the block including the page in error and copy thetarget data to another block.*Error in write or read operationWithin its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.Failure ModeDetection and Countermeasure sequenceWrite Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement ReadSingle Bit FailureVerify ECC -> ECC CorrectionECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detectionNAND Flash Technical Notes (Continued)Copy-Back Operation with EDC & Sector Definition for EDCGenerally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors.K9F1G08U0B supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.A 2,112-byte page is composed of 4 sectors of 528-byte and each 528-byte sector is composed of 512-byte main area and 16-byte spare area."A" area 512 Byte(1’st sector)"H" area (4’th sector)Main Field (2,048 Byte)16 Byte"G" area (3’rd sector)16 Byte "F" area (2’nd sector)16 Byte "E" area (1’st sector)16 Byte "B" area 512 Byte(2’nd sector)"C" area 512 Byte(3’rd sector)"D" area 512 Byte(4’th sector)Spare Field (64 Byte)Table 2. Definition of the 528-Byte SectorSector Main Field (Column 0~2,047)Spare Field (Column 2,048~2,111)Area NameColumn AddressArea NameColumn Address 1’st 528-Byte Sector "A"0 ~ 511"E"2,048 ~ 2,0632’nd 528-Byte Sector "B"512 ~ 1,023"F"2,064 ~ 2,0793’rd 528-Byte Sector "C"1,024 ~ 1,535"G"2,080 ~ 2,0954’th 528-Byte Sector"D"1,536 ~ 2,047"H"2,096 ~ 2,111Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0.From the LSB page to MSB page DATA IN: Data (1)Data (64)(1)(2)(3)(32)(64)Data register Page 0Page 1Page 2Page 31Page 63Ex.) Random page program (Prohibition)DATA IN: Data (1)Data (64)(2)(32)(3)(1)(64)Data registerPage 0Page 1Page 2Page 31Page 63Addressing for program operation::::Read ID OperationCECLEWEALERE90hRead ID CommandMaker Code Device Code00h ECht REAAddress 1cycleI/Oxt ARDevice Device Code (2nd Cycle)3rd Cycle 4th Cycle 5th Cycle K9F1G08U0BF1h00h95h40hDevice 4th cyc.Code3rd cyc.5th cyc.4th ID DataDescription I/O7 I/O6I/O5 I/O4 I/O3I/O2I/O1 I/O0Page Size(w/o redundant area ) 1KB2KB4KB8KB0 00 11 01 1Block Size(w/o redundant area ) 64KB128KB256KB512KB0 00 11 01 1Redundant Area Size ( byte/512byte) 8161Organization x8x161Serial Access Minimum 50ns/30ns25nsReservedReserved1111ID Definition Table90 ID : Access command = 90HDescription1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker CodeDevice CodeInternal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size3rd ID DataDescription I/O7 I/O6I/O5 I/O4I/O3 I/O2I/O1 I/O0Internal Chip Number 12480 00 11 01 1Cell Type 2 Level Cell4 Level Cell8 Level Cell16 Level Cell0 00 11 01 1Number ofSimultaneouslyProgrammed Pages 12480 00 11 01 1Interleave Program Between multiple chips Not SupportSupport1Cache Program Not SupportSupport15th ID DataDescription I/O7I/O6 I/O5 I/O4I/O3 I/O2 I/O1I/O0Plane Number 12480 00 11 01 1Plane Size(w/o redundant Area) 64Mb128Mb256Mb512Mb1Gb2Gb4Gb8Gb0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Reserved 0 0 0Figure 7. Random Data Output In a PageAddress 00hData OutputR/B RE t R30hAddress 05hE0h4Cycles2Cycles Data OutputData Field Spare Field Data Field Spare FieldI/OxCol. Add.1,2 & Row Add.1,2PAGE PROGRAMThe device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector. Any partial modification smaller than a sector corrupts the on-chip EDC codes.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.Figure 8. Program & Read Status Operation80hR/B Address & Data Input I/O0PassData10h70hFailt PROGI/OxCol. Add.1,2 & Row Add.1,2"0""1"Col. Add.1,2Figure 9. Random Data Input In a Page80hR/B Address & Data Input I/O0Pass10h70hFailt PROG85hAddress & Data InputI/OxCol. Add.1,2 & Row Add1,2Col. Add.1,2 DataData"0""1"Copy-Back ProgramThe Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory.Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben-efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copy-ing-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input com-mand (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. During tPROG, the device executes EDC of itself. Once the program process starts, the Read Status Register command (70h) or Read EDC Status command (7Bh) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register.When the Copy-Back Program is complete, the Write Status Bit(I/O 0) and EDC Status Bits (I/O 1 ~ I/O 2) may be checked(Figure 10& Figure 11& Figure 12). The internal write verification detects only errors for "1"s that are not successfully programmed to "0"s and the internal EDC checks whether there is only 1-bit error for each 528-byte sector of the source page. More than 2-bit error detection is not available for each 528-byte sector. The command register remains in Read Status command mode or Read EDC Status com-mand mode until another valid command is written to the command register.During copy-back program, data modification is possible using random data input command (85h) as shown in Figure11. But EDC status bits are not available during copy back for some bits or bytes modified by Random Data Input operation. However, in case of the 528 byte sector unit modification, EDC status bits are available.Figure 10. Page Copy-Back Program Operation00hR/B Add.(4Cycles)I/O0Pass85h 70h/7Bh Failt PROGAdd.(4Cycles) t R Source Address Destination Address35h10h I/OxCol. Add.1,2 & Row Add.1,2Col. Add.1,2 & Row Add.1,2Figure 11. Page Copy-Back Program Operation with Random Data Input00hR/B Add.(4Cycles)85h 70ht PROGAdd.(4Cycles) t RSource AddressDestination AddressData 35h10h 85hData Add.(2Cycles) There is no limitation for the number of repetition.I/OxCol. Add.1,2 & Row Add.1,2Col. Add.1,2 & Row Add.1,2Col. Add.1,2Note: 1. For EDC operation, only one time random data input is possible at the same address.Note : 1. Copy-Back Program operation is allowed only within the same memory plane.2. On the same plane, It’s prohibited to operate copy-back program from an odd address page(source page) to an even address page(target page) or from an even address page(source page) to an odd address page(target page). Therefore, the copy-back program is permitted just between odd address pages or even address pages."0""1"Note: 1. For EDC operation, only one time random data input is possible at the same address.。
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K9G8G08U0MINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or sim-ilar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Document TitleSAMSUNG 8Gb(1G x8 Bit) NAND FLASH M-DIERevision HistoryRemarkAdvancedHistoryInitial DraftDateApr. 25, 2006Revision No0.0• Power Supply Voltage : 2.7V ~ 3.6V • Organization : (1G+32M) x 8bit• May contain up to 100 invalid blocks • Functionally Tested Only• 256KB Block Erase operation• 2KB Page Program/ Read Operation• Tray Packing for Chip or Jar Packing for Wafer1.0 Product Introduction1.1 Features• Backside die surface of polished bare silicon• Die Thickness = 725±10um(Bare Wafer) or 200um (Back Lap)• Typical top-level metalization • Single barrier metal : - 6.0K Angstroms Al- 0.2% Si + 0.5% Cu composition • Top side passivation : - 1.0K Angstroms PEOX - 7K Angstroms HDP OX - 3K Angstroms SiN - 10um Polyimide• Typical Pad Size : 90.0um x 90.0um• Die Size : 10380um x 12980um including scribe line (X : 10280um Y : 12880um scribe line)1.2 General Physical SpecificationsDIE OUTLINE (Top View)Wafer Flat ZoneFigure 1. Pad Diagram8Gb NAND FLASH M-DIE10280um x 12880umincluding X:10380um Y:12980um scribe linePad Size : 90.0um x 90.0umPAD Diagram15141312111098765432129282726252423223736353433323130201918171621Y-AxisX-Axis(0,0)381.3 Functional SpecificationsA bare die is tested for only DC parameters and functional items. Please refer to the packaged product data sheet for functional and parametric specifications. For bare die, these specifications are provided for reference only and SAMSUNG makes no guarantees or warranties on bare die.1.4 Standard Probe TestingWafer probe consists of various functional and parametric tests of each die. Test patterns, timing, voltage margins, limits, and test sequence are determined by individual product yields and reliability data.SAMSUNG retains a wafer map of each wafer as part of the probe records along with a lot summary of wafer yields for each lot probed. SAMSUNG reserves the right to change the probe program at any time to improve the reliability, packaged device yield, or performance of the product.1.5 Bonding InstructionsThe 8Gb NAND Flash M-die has total 38pads. Refer to the bond pad location and identification table for a complete list of bond pads and X, Y coordinates. SAMSUNG recommends using a bond wire on each Vcc and Vss bond pad for improved noise immunity. Table 1. Bond Pad Location and IdentificationPAD FUNCTION X Y PAD FUNCTION X Y 1NC62312420IO67835124 2NC87812421IO78413124 3NC112512422NC9052124 4NC1347.7612423NC9307124 5IO0174612424NC9562124 6IO1228212425WP130812754 7IO2259812426WE1685.512754 8IO3316412427ALE234212754 9NC374512428CLE292912754 10NC401512429V SS422212754 11NC428512430NC458512754 12V SS455512431NC492912754 13NC482512432V DD526512754 14V DD502312433NC560112754 15NC524312434NC605312754 16NC585012435CE742312754 17NC6151.3412436RE780012754 18IO4694112437RnB817812754 19IO5751912438NC853412754NOTE:1. Referenced to the center of each pad from the corner of left bottom.2. All units are in um3. NC stands for No Connection.1.6 Packing• Tray Packing for ChipA 2-inch square waffle style carrier for die with separate compartments for each die. Each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic discharge.The chip carriers will be labeled with the following information :- SAMSUNG wafer lot number- SAMSUNG part number- Quantity• Jar Packing for WaferJar Packing is made by Samsung Electronics and used by many customers that we deliver the requested die as wafer.The pack consists of clean paper to wrap the wafer, high cushioned sponge between wafer and hardly fragile plastic box with sponge. Each pack has typically 25 wafers and then several packs are put into larger box depending on amounts of wafers.1.7 Storage and HandlingSAMSUNG recommends the die should be stored in a controlled environment with filtered nitrogen. The carrier must be opened at ESD safe environment at inspection and assembly.。