04-Day1-Persistence-1.5h
nVent ERICO PlusCU 2L 6V 电源控制器操作指南说明书
C o u n t -u p I g n i t i o n I n d i c a t o rT r i g g e r G u a r dT r i g g e rB a t t e r y D o o rB a t t e r y I n d i c a t o rC a d w e l d P l u s C u p C o n n e c t o rP L U S C U 2L 6P L U S C U 2L 15P L U S C U 2L 6N B P B P L U S C U 2L 6P B P L U S C U 2L 15P L U S C U 2R L D 6P L U S C U 2R L D 15L e a d C o n n e c t o rIndicator lights are flashing:The PlusCU uses an internal charging mechanism that sends an electric current to the Cadweld Plus cup. If the trigger on the control unit is pulled before the internal charging mechanism resets, the lights will flash. Wait 5 seconds and try again.If the error message persists, contact your nVent ERICO representative.PlusCU does not respond when trigger is pulled:If the unit does not respond, check battery status to determine if new batteries are needed.Cadweld Plus cup does not ignite:Disconnect the PlusCU lead from the PlusCU then re-examine your mold, weldmetal cup, ignition strip, and other Cadweld equipment to verify proper setup.If this issue persists, contact your nVent ERICO representative.PlusCU does not function properly at temperatures below 0° F [-18°C]:Alkaline batteries are not intended for extreme cold temperatures. nVent ERICOrecommends the use of lithium-ion batteries at temperatures below 0° F [-18°C].WARNING:nVent products shall be installed and used only as indicated in nVent product instruction sheets and training materials. Instruction sheets are available at and from your nVent customer service representative. nVent products must never be used for a purpose other than the purpose for which they were designed or in a manner that exceeds specified load ratings.2.All instructions must be completely followed to ensure proper and safe installation and performance.3.Improper installation, misuse, misapplication or other failure to completely follow nVent's instructions and warnings may cause product malfunction, property4.damage, serious bodily injury and/or death, and void your warranty.SAFETY INSTRUCTIONS:All governing codes and regulations and those required by the job site must be observed.Always use appropriate safety equipment such as eye protection, hard hat, and gloves as appropriate to the application.nVent, nVent CADDY, nVent ERICO Cadweld, nVent ERICO Critec, nVent ERICO, nVent ERIFLEX, and nVent LENTON are owned byHigh voltage electrical shock hazard. Keep hands and body clear of the cord(leads) while operating. Failure to do so can result in death or serious injury.Safety First!Personal SafetyWhen working with nVent ERICO Cadweld Plus, always use appropriate safety equipment suchas eye protection, heat-resistant gloves, and other PPE as appropriate to the application and required by local safety codes.Avoid contact with hot materials. Maintain safe working distance and secure footing whilewelding or working with hot materials.Welding material is a mixture of oxides and metal which react to produce hot molten materialwith temperatures in excess of 1400° C [2500° F] and a localized release of smoke. Thesereactions are not explosive and not known to be toxic. Ignition temperatures of weldingmaterial are in excess of 900° C [1650° F] and will not ignite under ambient conditions.For reduced or eliminated smoke options, contact nVent ERICO.。
JUMO 温度传感器说明书
Page 1/11Data Sheet 702040Blocks tructureFeature sk S tructured operating and programming layout k S elf-optimi s ation k Ramp functionk Timer functionk Digital input filter withprogrammable filter time con s tant k 1 limit comparator k limit s witchJUMO iTRON 04/08/16/32Compact microproce ss or controller sHou s ing for flu s h-panel mounting to DIN IEC 61554Brief de s criptionThe JUMO iTRON controller s erie s compri s e s univer s al and freely programmable com-pact in s trument s for a variety of control ta sks . It con s i s t s of five model s , with the bezel s ize s 96mm x 96mm, 96mm x 48mm in portrait and land s cape format, 48mm x 48mm and 48mm x 24mm.The controller s feature a clearly readable 7-s egment di s play which, depending on the ver-s ion, i s 10 or 20 mm high, for proce ss value and s etpoint indication or for dialog s . Only three k ey s are needed for configuration. Parameter s etting i s arranged dynamically, and after two operation-free s econd s the value i s accepted automatically. S elf-optimi s ation,which i s provided a s s tandard, e s tabli s he s the optimum controller parameter s by a k ey s tro k e. The ba s ic ver s ion al s o include s a ramp function with adju s table gradient s . A timer function ha s been integrated a s an extra.All controller s can be employed a s s ingle-s etpoint controller s with a limit comparator, or as double-s etpoint controller s . The lineari s ation s of the u s ual tran s ducer s are stored. Pro-tection i s IP66 at the front and IP20 at the bac k . The electrical connection i s by a plug-in connector with s crew terminal s .The input s and output s are s hown in the bloc k s tructure below.JUMO iTRON 08Type 702042JUMO iTRON 04Type 702044JUMO iTRON 08Type 702043JUMO iTRON 32Type 702040JUMO iTRON 16Type 702041Approval s /approval mark s (s ee "Technical data")Data Sheet 702040Page 2/11Technical dataThermocouple inputRe s i s tance thermometer inputStandard s ignal inputMea s urement circuit monitoring 1De s ignation Range 1Mea s urement accuracy Ambienttemperature error Fe-Con L Fe-Con J EN 60584Cu-Con U Cu-Con T EN 60584NiCr-Ni K EN 60584NiCr S i-Ni S i N EN 60584Pt10Rh-Pt S EN 60584Pt13Rh-Pt R EN 60584Pt30Rh-Pt6Rh BEN 60584-200to +900°C -200to +1200°C -200to +600°C -200to +400°C -200to +1372°C -100to +1300°C0— 1768°C 0—1768°C +300— 1820°C≤0.4%≤0.4%≤0.4%≤0.4%≤0.4%≤0.4%≤0.4%≤0.4%≤0.4%100 ppm/°C 100 ppm/°C 100 ppm/°C 100 ppm/°C 100 ppm/°C 100 ppm/°C 100 ppm/°C 100 ppm/°C 100 ppm/°CCold junctionPt 100 internal1. The s e range s refer to the ambient temperature of 20°CDe s ignation Connection type RangeMea s urement accuracy Ambienttemperature error Pt 100 EN 607512-/3-wire -200to +850°C ≤0.1%50 ppm/°C Pt 1000 EN 607512-/3-wire -200to +850°C ≤0.1%50 ppm/°C K TY11-62-wire-50to +150°C≤1.0%50 ppm/°CS en s or lead re s i s tance 20Ω max. per lead for 2- and 3-wire circuitMea s urement current 250µALead compen s ationNot required for 3-wire circuit. For 2-wire circuit, lead compen s ation can be implemented in s oftware through proce ss value correction.De s ignation RangeMea s urement accuracy Ambienttemperature error Voltage0—10V , input re s i s tance R E > 100k Ω2—10V , input re s i s tance R E > 100k Ω0—1V , input re s i s tance R E > 10M Ω10,2—1V , input re s i s tance R E > 10M Ω1≤0.1%≤0.1%≤0.1%≤0.1%100 ppm/°C 100 ppm/°C 100 ppm/°C 100 ppm/°C Current4—20mA, voltage drop 3V max.0—20mA, voltage drop 3V max.≤0.1%≤0.1%100 ppm/°C 100 ppm/°C1. for Type 702040/41 with 2 relay output s (option)Tran s ducer Overrange/underrangeProbe /lead s hort-circuit 1Probe/lead breakThermocouple•-•Re s i s tance thermometer •••Voltage 2—10V / 0.2—1V0—10V/ 0—1V •••-•-Current4—20mA 0—20mA•••-•-1. In the event of a fault, the output s move to a defined s tatu s (configurable).= factory s etting •recogni s ed-not recogni s edData Sheet 702040Page 3/11Output sControllerTimerElectrical dataHou s ingA ss ignment Type 702040/41Type 702042/43/44Output 1relayrelay Output 2logic 0/5V or logic input logic 0/5V Output 2 (option)logic 0/12V or logic input logic 0/12V Output 2 (option)relay not po ss ible Output 3not availablerelayTechnical data Relay ratingcontact life n.o. (ma k e) contact 3A at 250VAC re s i s tive load 150 000 operation s at rated loadLogiccurrent limiting load re s i s tance 0/5V 20mAR load 250Ω min .Logiccurrent limiting load re s i s tance 0/12V 20mAR load 600Ω min.= factory s ettingController types ingle-s etpoint controller with limit comparator, double-s etpoint controllerController s tructure s P/PD/PI/PIDA/D converter re s olution better than 15 bitS ampling time210m s ec/250m s ec with activated timer functionAccuracy0.7% ± 10ppm/°CS upply (s witch-mode power s upply)110—240V -15/+10%AC 48—63Hz, or 20—30V AC/DC 48—63Hz, or10—18V DC (Connection to S ELV or PELV)Te s t voltage s (type te s t)to EN 61010, Part 1, March 1994,overvoltage category II, pollution degree 2, for Type 702040/41overvoltage category III, pollution degree 2, for Type 702042/43/44Power con s umption max. 7VA Data bac k upEEPROMElectrical connectionat the rear, via plug-in s crew terminal s ,conductor cro ss -s ection up to 1.5mm 2 (1.0mm 2 for Type 702040/41) or2x 1.5mm 2 (1.0mm 2 for Type 702040/41) with ferrule sElectromagnetic compatibility interference emi ss ion interference immunity EN 61 326Cla ss Bto indu s trial requirement sS afety regulationto EN 61010-1In s tallation height maximum 2000 m above s ea levelCa s e typePla s tic ca s e for panel mounting acc to. IEC 61554 (indoor u s e)Dimen s ion s in mm (for Type)702040702041702042702043702044Bezel s ize48x 2448x 4848x 96(portrait)96x 48(land s cape)96x 96Depth behind panel100100707070Panel cut-out45+0.6x 22.2+0.345+0.6x 45+0.645+0.6x 92+0.892+0.8x 45+0.692+0.8x 92+0.8Ambient/s torage temperature range 0—55°C /-40 to +70°CData Sheet 702040Page 4/11Approval s /approval mark sDi s play and control sSelf-optimi s ation (SO)The s tandard s elf-optimi s ation facility produce s an automatic adju s tment of the controller to the proce ss .S elf-optimi s ation determine s the controller parameter s for PI and PID controller s (proportional band, re s et time, derivative time), a s well a s the cycle time and the filter time con s tant of the digital input filter.Ramp functionClimatic condition s not exceeding 75% rel. humidity, no conden s ationOperating po s ition unre s tricted Protection to EN 60529,IP66 at the front, IP20 at the bac kWeight75g approx.95g approx.145g approx.160g approx.200g approx.Approval mark Te s ting agencyCertificate/certification numberIn s pection ba s i sValid forUL Underwriter Laboratorie s E201387UL 61010-1all device s C S A C S A-Approval232831CAN/C S A-C22.2No. 61010.1-04all device sData Sheet 702040Page 5/11Limit comparatorLimit s witch (extra code)If the limit comparator function i s active, then the s witched s tate will have to be re s et by hand.Precondition: the condition that cau s ed the alarm i s no longer pre s ent (for l k 8: proce ss value < AL). The di s play s how s the alarm s tatu s .The alarm s tatu s will be retained after a power failure.Timer function (extra code)U s ing the timer function, the control action can be influenced by mean s of the adju s table time t i 0. After the timer ha s been s tarted by power ON, by pre ss ing the k ey or via the logic input, the timer s tart value t i 0 i s counted down to 0, either in s tantly or after the proce ss value ha s gone above or below a programmable tolerance limit. When the timer ha s run down, s everal event s are triggered, s uch a s control s witch-off (output 0%) and s etpoint s witching. Furthermore, it i s po ss ible to implement timer s ignalling during or after the timer count, via an output.The timer function can be u s ed in conjunction with the ramp function and s etpoint s witching.Table: Timer function s (u s ing the example of a rever s ed s ingle-s etpoint controller)Data Sheet 702040Page 6/11Tolerance limitThe po s ition of the tolerance limit depend s on the controller type:- S ingle-s etpoint controller (rever s ed, heating): Tolerance limit i s below the s etpoint - S ingle-s etpoint controller (direct, cooling): Tolerance limit i s above the s etpoint - Double-s etpoint controller: Tolerance limit i s below the s etpointIf, during the control proce ss , the proce ss value goe s above/below the tolerance limit, then the timer will be s topped for the duration of the infringement.Di s play and operationThe timer value i s di s played at the operating level and remain s s o permanently (no time-out).Operation i s from the k eypad, when the timer value i s vi s ible in the di s play, or via the logic input. The operating option s compri s e s tart,s top, continue and cancel timer function, and are s hown differently in the di s play.The current timer value and the timer s tart value are acce ss ible and adju s table at any time at a s eparate timer level.Data Sheet 702040Page 7/11Parameter and configurationOperating levelParameter levelConfiguration levelDe s ignation Di s play Factory s ettingValue range S etpointSP /SP1/SP20S PL—S PH Ramp s etpointSPr 0S PL—S PH Timer value/timer s tart valuet i /t i 00 —999.9hDe s ignation Di s play Factory s ettingValue range S etpoint 1SP 10S PL—S PH S etpoint 2SP 20S PL—S PH Limit value for limit comparator AL 0-1999to +9999digit Proportional band 1Pb:100—9999digit Proportional band 2Pb:200—9999digit Derivative time dt 80s ec 0—9999s ec Re s et time rt 350s ec 0—9999s ec Cycle time 1CY 120.0s ec 1.0—999.9s ec Cycle time 2CY 220.0s ec1.0—999.9s ec Contact s pacingdb 00—1000digit Differential (hy s tere s i s ) 1HYS.110—9999digit Differential (hy s tere s i s ) 2HYS.210—9999digit Wor k ing point Y:00%-100to +100%Maximum output Y:1100%0to 100%Minimum output Y:2-100%-100to +100%Filter time con s tant dF 0.6s ec 0.0—100.0s ec Ramp s loperASd—999digitDe s ignation Di s play Factory s etting Value range/s electionTran s ducerC111Pt100Pt100, Pt1000, K TY11-6, T, J, U, L, K , S ,R, B, N, 0 (4)—20mA, 0 (2)—10VDecimal place/unitC112none/°C none, one, two/°C, FController type/output s C113s ee table on next pageLimit comparator function C114no function no function, l k 1—8Ramp functionC115no function no function, °C/min, °C/h Output s ignal on overrange/ underrange C1160% output limit comparator off 0%, 100%, -100% limit comparator on/offLogic inputC117no function k ey / level inhibit,ramp s top, s etpoint s witchingOutput s 1, 2 and 3(only Type 702042/43/44)C118function s a s defined under C113freely configurable(s ee table on next page)Timer functionC120no function s ee de s cription “Timer function”S tart condition for timerC121from k eypad/logic input - power ON - k eypad/logic input- tolerance limitTimer s ignalling C122no function - timer s tart to timer run-down- after run-down for 10s ec - after run-down for 1 min.- after run-down until ac k nowledgementUnit of time (timer)C123mm.ss - mm.ss- hh.mm - hhh.hS tart value of value range SCL0-1999 to +9999 digitData Sheet 702040Page 8/11Controller type/output s (C 113)Expanded configuration option s for the output s on Type 702043/44 (C118)End value of value range SCH 100-1999 to +9999 digit Lower s etpoint limit SPL -200-1999 to +9999 digit Upper s epoint limitSPH 850-1999 to +9999 digit Proce ss value correction OFFS 0-1999 to +9999 digit Differential (hy s tere s i s )HySt 1 0—9999 digitController typeOutput 1Output 2 + 3S ingle s etpoint rever s ed controller limit comparator/timer s ignalling S ingle s etpoint direct controllerlimit comparator/timer s ignallingDouble s etpointcontroller rever s edcontroller direct S ingle s etpoint rever s ed limit comparator/timer s ignalling controller S ingle s etpoint direct limit comparator/timer s ignallingcontrollerDouble s etpoint controller directcontroller rever s ed= factory s ettingOutput 1: Relay (K1)Output 2: Logic (K2)Output 3: Relay 1-s e t p o i n t c o n t r o l l e rFunction s of the output s a s defined under C 113controller output limit comparator timer s ignalling controller output timer s ignalling limit comparator limit comparator controller output timer s ignalling limit comparator timer s ignalling controller output timer s ignalling controller output limit comparator timer s ignalling limit comparator controller output 2-s e t p t .c o n t r o l l e rcontroller output 1controller output 2limit comparator/timer controller output 1limit comparator/timer controller output 2controller output 2controller output 1limit comparator/timer controller output 2limit comparator/timer controller output 1limit comparator/timer controller output 1controller output 2limit comparator/timercontroller output 2controller output 1Data Sheet 702040Page 9/11Dimen s ion sType 702040 / …Type 702043/...Type 702041 / …Type 702044/...Type 702042 / …Typehorizontal vertical 70.2040/418mm min.8mm min.70.2042/43/4410mm min.10mm min.Edge-to-edge mounting(minimum s pacing s of the panel cut-out s)Data Sheet 702040Page 10/11Connection diagram sJUMO iTRON 32, Type 702040, 48mm x 24mm format JUMO iTRON 16, Type 702041, 48mm x 48mm formatJUMO iTRON 08, Type 702042, 48mm x 96mm format (portrait)JUMO iTRON 08, Type 702043. 96mm x 48mm format (land s cape)JUMO iTRON 04, Type 702044, 96mm x 96mm formatStandard ver s ion / Ver s ion with 12V logic outputVer s ion with 2 relay outputs2014-09-01/00357838Data Sheet 702040Page 11/11Order detail sExtra order code s for cu s tomized configuration(2)Ba s ic type exten s ion(3)Input s(1)(2)(3)(4)(5)(6)Type de s ignation 7020../..-...-...-../...,...** Li s t extra code s in s equence, s eparated by comma s(1)Ba s ic type(bezel s ize in mm)40=48x 24, 41 = 48x 48, 42 = 48x 96 (portrait), 43 = 96x 48 (land s cape), 44 = 96x 96(2)Ba s ic typeexten s ion 8899==controller type configurable 1controller type configured to cu s tomer s pecification 2(3)Input s 888999==input s configurable 1input s configured to cu s tomer s pecification 2(4)Output s000=S tandardType 702040/41Type 702042/43/44Output 1relay (n.o. ma k e)relay (n.o. ma k e)Output 2logic 0/5V , optionally configurable a s logic input logic 0/5V Output 3not available relay (n.o. ma k e)Option sType 702040/41Type 702042/43/44113=Output 2(output s 1+3 a s for S tandard)logic 0/12V , optionally configurable a s logic input logic 0/12V 101=Output 2(output 1 a s for S tandard)relay (n.o. ma k e)(logic input i s alway s available)not po ss ible(5)Supply162523===10—18V DC20—30V AC/DC 48—63Hz110—240V AC -15/+10% 48—63Hz (6)Extra code069=UL and C S A approval 210=Timer function220=Timer function + limit s witch 3Delivery package ex-factory for Type 702040/41Type 702042/43/441 mounting frame2 mounting brac k et s1 s eal, 1 Operating In s truction s 70.20401. s ingle-s etpoint with limit comparator, s ee factory s etting s under configuration and parameter level2. s ee extra order code s (below) or factory s etting s under configuration and parameter level3. The linearization s for K TY11-6 and thermocouple B have been deletedController typeOutput 1Output 2 and 310=s ingle s etpoint rever s ed 1controller limit comparator/timer s ignalling 11=s ingle s etpoint direct 2controllerlimit comparator/timer s ignalling 30=double s etpoint controller rever s edcontroller direct 20=s ingle s etpoint rever s ed 1limit comparator/timer s ignalling controller 21=s ingle s etpoint direct 2limit comparator/timer s ignalling controller33=double s etpointcontroller directcontroller rever s ed1. controller output i s active when proce ss value i s below s etpoint, e. g. heating2. controller output i s active when proce ss value i s above s etpoint, e. g. cooling001=Pt1003-wire 040=Fe-Con J 045=Pt13 Rh-Pt R 063=0—10V 003=Pt1002-wire041=Cu-Con U 046=Pt30 Rh-PtRh B 071=2—10V 005=Pt1000 2-wire 042=Fe-Con L 048=NiCr S i-Ni S i N601=K TY11-6 (PTC)006=Pt1000 3-wire 043=NiCr-Ni K 052=0—20mA 039=Cu-Con T044=Pt10Rh-PtS053=4—20mA= factory-s et。
ecl-学习
⨯⨯,块中心网格NX=20,NY=20,NZ=5,dx=dy=20,dz=2 40040010Top=1000E和F为什么是这样的？1、用Schedule建立一个基本的Project1.建立一个基本工程(Project)并保存生产数据：后缀为*.VOL or *.vol井的参数：后缀为*.EV or *.ev，包括射孔(perforation)、堵孔(well squeeze)、酸化(acidise)等。
井的几何参数：后缀为*.TRJ or *.trj；*.CNT or *.cnt；*.NET or *.net；*.LYR or *.lyr；网格参数：后缀为*.*GR* or *.*gr*地层特性：后缀为*.*IN* or *.*in*2.输入井的生产历史(Production History)加载后缀为*.vol的数据文件3.输入井的事件数据(Events Data)加载后缀为*.ev数据文件，包括射孔(perforation)、堵孔(well squeeze)、酸化(acidise)等。
4.输入控制网络数据(Control Network)加载后缀为*.net的数据文件5.输入网格参数(Importing a Grid)加载后缀为*.*gr*即.fgrid的数据文件6.定义井的轨迹(Trajectories)(1) 通过输入井的井斜检测(Deviation Survey)数据计算井的轨迹Schedule加载的这些网格特性数据是由INIT文件提供的，INIT数据文件是通过Eclipse非模拟(NOSIM)数据设置运行而产生的，有两种方式：一种是在GRID部分用INIT关键字运行而产生的；另一种是在RUNSPEC部分运用NOSIM关键字运行而产生的。
在加载数据以前，必须有以下资料：•加载的网格文件（这些网格文件由Eclipse或者GRID软件或其它相关软件运行产生的）；•读入的网格特性文件（Eclipse INIT文件）；•所要输入的井斜检测数据（由Eclipse 产生的后缀为*.cnt的文件）。
USB Mass Storage Class Bulk Only Transport
Universal Serial Bus Mass Storage Class Bulk-Only TransportRevision 1.0September 31, 1999Change HistoryRevision Issue Date Comments0.7September 23, 1998Initial draft, pre-release0.8October 6, 1998Revisions made at the Mass Storage DWG review – Irvine, CA0.9October 21, 1998Revisions made at the Mass Storage DWG review – Plano, TX0.9a January 5, 1999Revisions made at the Mass Storage DWG review – Tigard, OR0.9b February 1, 1999Additions of LUN support - Milpitas, CA1.0[RC1]March 5, 1999RR review - Midway, UT1.0[RC2]March 23, 1999Revisions from reflector review comments1.0[RC3]March 29, 1999Specification line by line review – Milpitas, CA1.0[RC4]June 21, 1999Specification line by line review – RR21 – Milpitas, CA1.0September 31, 1999Final Revision edits for Released Document – SLC, UTUSB Device Class Definition for Mass Storage DevicesCopyright © 1998, 1999, USB Implementers Forum.All rights reserved.INTELLECTUAL PROPERTY DISCLAIMERTHIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE.A LICENSE IS HEREBY GRANTED TO REPRODUCE AND DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY.AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. AUTHORS OF THIS SPECIFICATION ALSO DO NOT WARRANT OR REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE SUCH RIGHTS.ContributorsAl Rickey, Phoenix TechnologiesAlan Haffner, Lexar MediaBill Stanley, AdaptecCalaimany Bhoopathi, Shuttle TechnologyCurtis E. Stevens, Phoenix TechnologiesDarrell Redford , Iomega CorporationDave Gilbert, In-System DesignDavid G. Lawrence, Global Technology Development David L. Jolley, Iomega CorporationDavid Luke, In-System DesignEric Luttman, In-System DesignGlen Slick, Microsoft CorporationHiromichi Oribe, Hagiwara Sys-ComCoJan Matejica, PIMC/PhilipsJim Blackson, Y-E Data, IncJim Quigley, Iomega CorporationJohan Craeybeckk, PIMC/PhilipsJordan Brown, Sun MicrosystemsKenny Chu, Hagiwara Sys-ComCoKenichi Hamada, Y-E Data, IncMark Williams, Microsoft CorporationMasayuki Kitagawa, MitsumiMike Chen, CMD Technology Mike Glass, Microsoft Corporation Mike Liebow, eTEK LabsMike Nguyen, TEACMike Poulsen, Iomega Corporation Moto Watanabe, HagiwaraN.R. Devanathan, Shuttle Technology Paramita Das, Sun MicrosystemsPat LaVarre, Iomega Corporation Peter S'Heeren, PIMC/PhilipsRyota Okazaki, NEC Corporation Sadao Yabuki, TEACShigeyoshi Hashi, NEC Corporation Shing F. Lin, AdaptecSteve Bayless, Hewlett-Packard Steve Kolokowsky, Anchor Chips Steven Smith, eTEK LabsTerry Moore, MCCITim Bradshaw, Iomega Corp Toyoko Shimizu, Y-E Data, Inc Trenton Henry, SMSCTroy Davidson, Iomega Corporation Tsuyoshi Osawa, TEACYuji Oishi, Hagiwara Sys-Com Co LtdTable of Contents1Specification Overview and Scope (5)1.1Scope (5)2Terms and Abbreviations (6)2.1Conventions (6)2.2Definitions (6)3Functional Characteristics (7)3.1Bulk-Only Mass Storage Reset (class-specific request) (7)3.2Get Max LUN (class-specific request) (7)3.3Host/Device Packet Transfer Order (8)3.4Command Queuing (8)3.5Bi-Directional Command Protocol (8)4Standard Descriptors (9)4.1Device Descriptor (9)4.1.1Serial Number (9)4.1.2Valid Serial Number Characters (10)4.2Configuration Descriptor (10)4.3Interface Descriptors (11)4.4Endpoint Descriptors (11)4.4.1Bulk-In Endpoint (11)4.4.2Bulk-Out Endpoint (12)5Command/Data/Status Protocol (13)5.1Command Block Wrapper (CBW) (13)5.2Command Status Wrapper (CSW) (14)5.3Data Transfer Conditions (15)5.3.1Command Transport (15)5.3.2Data Transport (15)5.3.3Status Transport (16)5.3.4Reset Recovery (16)6Host/Device Data Transfers (17)6.1Overview (17)6.2Valid and Meaningful CBW (17)6.2.1Valid CBW (17)6.2.2Meaningful CBW (17)6.3Valid and Meaningful CSW (17)6.3.1Valid CSW (17)6.3.2Meaningful CSW (17)6.4Device Error Handling (17)6.5Host Error Handling (18)6.6Error Classes (18)6.6.1CBW Not Valid (18)6.6.2Internal Device Error (18)6.6.3Host/Device Disagreements (18)6.6.4Command Failure (18)6.7The Thirteen Cases (18)6.7.1H n - Host expects no data transfers (19)6.7.2H i - Host expects to receive data from the device (20)6.7.3H o - Host expects to send data to the device (21)List of TablesTable 3.1 – Bulk-Only Mass Storage Reset (7)Table 3.2 –Get Max LUN (7)Table 4.1 - Device Descriptor (9)Table 4.2 - Example Serial Number Format (10)Table 4.3 - Valid Serial Number Characters (10)Table 4.4 - Configuration Descriptor (10)Table 4.5 – Bulk-Only Data Interface Descriptor (11)Table 4.6 - Bulk-In Endpoint Descriptor (11)Table 4.7 – Bulk-Out Endpoint Descriptor (12)Table 5.1 - Command Block Wrapper (13)Table 5.2 - Command Status Wrapper (14)Table 5.3 - Command Block Status Values (15)Table 6.1 - Host/Device Data Transfer Matrix (19)List of FiguresFigure 1 - Command/Data/Status Flow (13)Figure 2 - Status Transport Flow (15)1 Specification Overview and Scope1.1ScopeA familiarity with the USB1.0 and 1.1Specifications and the USB Mass Storage Class Specification Overview is assumed.This specification addresses Bulk-Only Transport, or in other words, transport of command, data, and status occurring solely via Bulk endpoints (not via Interrupt or Control endpoints). This specification only uses the default pipe to clear a STALL condition on the Bulk endpoints and to issue class-specific requests as defined below. This specification does not require the use of an Interrupt endpoint.This specification defines support for logical units that share common device characteristics. Although this feature provides the support necessary to allow like mass storage devices to share a common USB interface descriptor, it is not intended to be used to implement interface bridge devices.2 Terms and Abbreviations2.1ConventionsNumbers without annotation are decimal -----------------------------------------------1, 17, 23Hexadecimal numbers are followed by an ‘h’-------------------------------------------1Fh, FCh, 38hBinary numbers are followed by a ‘b’----------------------------------------------------011b, 101b, 01110010b Words in italics indicate terms defined by USB or by this specification-----------bRequest, dCSWTag2.2DefinitionsCommand Block Wrapper (CBW)A packet containing a command block and associated information.Command Status Wrapper (CSW)A packet containing the status of a command block.Data-InIndicates a transfer of data IN from the device to the host.Data-OutIndicates a transfer of data OUT from the host to the device.Device RequestRequests from the host to the device using the default pipe.Phase ErrorAn error returned by the device indicating that the results of processing further CBWs will beindeterminate until the device is reset.ProcessedData received and controlled internally by the device to the point that the host need no longer beconcerned about it.RelevantThe amount of the data sent to the host by the device that is significant.Reset RecoveryAn error recovery procedure by which the host prepares the device for further CBWs.Thin DiagonalCases where the host and device are in complete agreement about the data transfer. See Chapter 6 -Host/Device Data Transfers, for additional information regarding error cases and the "thin diagonal."3 Functional Characteristics3.1Bulk-Only Mass Storage Reset (class-specific request)This request is used to reset the mass storage device and its associated interface.This class-specific request shall ready the device for the next CBW from the host.The host shall send this request via the default pipe to the device. The device shall preserve the value of its bulk data toggle bits and endpoint STALL conditions despite the Bulk-Only Mass Storage Reset.The device shall NAK the status stage of the device request until the Bulk-Only Mass Storage Reset is complete. To issue the Bulk-Only Mass Storage Reset the host shall issue a device request on the default pipe of:•bmRequestType: Class, Interface, host to device•bRequest field set to 255 (FFh)•wValue field set to 0•wIndex field set to the interface number•wLength field set to 0Table 3.1 – Bulk-Only Mass Storage ResetbmRequestType bRequest wValue wIndex wLength Data00100001b11111111b0000h Interface0000h none3.2Get Max LUN (class-specific request)The device may implement several logical units that share common device characteristics. The host uses bCBWLUN (see 5.1 Command Block Wrapper (CBW)) to designate which logical unit of the device is the destination of the CBW. The Get Max LUN device request is used to determine the number of logical units supported by the device. Logical Unit Numbers on the device shall be numbered contiguously starting from LUN 0 to a maximum LUN of 15 (Fh).To issue a Get Max LUN device request, the host shall issue a device request on the default pipe of:•bmRequestType: Class, Interface, device to host•bRequest field set to 254 (FEh)•wValue field set to 0•wIndex field set to the interface number•wLength field set to 1Table 3.2 –Get Max LUNbmRequestType bRequest wValue wIndex wLength Data10100001b11111110b0000h Interface0001h 1 byteThe device shall return one byte of data that contains the maximum LUN supported by the device. For example, if the device supports four LUNs then the LUNs would be numbered from 0 to 3 and the return value would be 3. If no LUN is associated with the device, the value returned shall be 0. The host shall not send a command block wrapper (CBW) to a non-existing LUN.Devices that do not support multiple LUNs may STALL this command.3.3Host/Device Packet Transfer OrderThe host shall send the CBW before the associated Data-Out, and the device shall send Data-In after the associated CBW and before the associated CSW. The host may request Data-In or CSW before sending the associated CBW.If the dCBWDataTransferLength is zero, the device and the host shall transfer no data between the CBW and the associated CSW.3.4Command QueuingThe host shall not transfer a CBW to the device until the host has received the CSW for any outstanding CBW. If the host issues two consecutive CBWs without an intervening CSW or reset, the device response to the second CBW is indeterminate.3.5Bi-Directional Command ProtocolThis specification does not provide for bi-directional data transfer in a single command.4 Standard DescriptorsThe device shall support the following standard USB descriptors:•Device. Each USB device has one device descriptor (per USB Specification).•Configuration. Each USB device has one default configuration descriptor, which supports at least one interface.•Interface. The device shall support at least one interface, known herein as the Bulk-Only Data Interface. Some devices may support additional interfaces, to provide other capabilities.•Endpoint. The device shall support the following endpoints, in addition to the default pipe that is required of all USB devices:(a)Bulk-In endpoint(b)Bulk-Out endpointSome devices may support additional endpoints, to provide other capabilities. The host shall use thefirst reported Bulk-In and Bulk-Out endpoints for the selected interface.•String. The device shall supply a unique serial number as detailed in 4.1.1 - Serial Number.This specification defines no class-specific descriptors.The rest of this section describes the standard USB device, configuration, interface, endpoint, and string descriptors for the device. For superseding information about these and other standard descriptors, see Chapter 9, “USB Device Framework,” of the USB Specification.4.1Device DescriptorEach USB device has one device descriptor (per USB Specification). The device shall specify the device class and subclass codes in the interface descriptor, and not in the device descriptor.Table 4.1 - Device DescriptorOffset Field Size Value Description0bLength Byte12h Size of this descriptor in bytes.1bDescriptorType Byte01h DEVICE descriptor type.2bcdUSB Word????h USB Specification Release Number in Binary-Coded Decimal(i.e. 2.10 = 210h). This field identifies the release of the USBSpecification with which the device and is descriptors arecompliant.4bDeviceClass Byte00h Class is specified in the interface descriptor.5bDeviceSubClass Byte00h Subclass is specified in the interface descriptor.6bDeviceProtocol Byte00h Protocol is specified in the interface descriptor.7bMaxPacketSize0Byte??h Maximum packet size for endpoint zero. (only 8, 16, 32, or 64are valid (08h, 10h, 20h, 40h)).8idVendor Word????h Vendor ID (assigned by the USB-IF).10idProduct Word????h Product ID (assigned by the manufacturer).12bcdDevice Word????h Device release number in binary-coded decimal.14iManufacturer Byte??h Index of string descriptor describing the manufacturer.15iProduct Byte??h Index of string descriptor describing this product.16iSerialNumber Byte??h Index of string descriptor describing the device’s serial number.(Details in 4.1.1 below)17bNumConfigurations Byte??h Number of possible configurations.NOTE:Information in this table is from the USB Specification version 1.1 table 9-7. Bold text has been added for clarifications when using these descriptors with this specification.4.1.1Serial NumberThe iSerialNumber field shall be set to the index of the string descriptor that contains the serial number. The serial number shall contain at least 12 valid digits, represented as a UNICODE string. The last 12 digits of the serial number shall be unique to each USB idVendor and idProduct pair.The host may generate a globally unique identifier by concatenating the 16 bit idVendor, the 16 bit idProduct and the value represented by the last 12 characters of the string descriptor indexed by iSerialNumber.The field iSerialNumber is an index to a string descriptor and does not contain the string itself. An example format for the String descriptor is shown below.Table 4.2 - Example Serial Number FormatOffset Field Size Value Description0bLength Byte??h Size of this descriptor in bytes - Minimum of 26 (1Ah)1bDescriptorType Byte03h STRING descriptor type2wString1Word00??h Serial number character 14wString2Word00??h Serial number character 26wString3Word00??h Serial number character 3: :Word: :: :Word: :n x 2wStringn Word00??h Serial number character nShall be at least 12 characters long4.1.2Valid Serial Number CharactersThe following table defines the valid characters that the device shall use for the serial number.Table 4.3 - Valid Serial Number CharactersNumeric ASCII0030h through 0039h"0" through "9"0041h through 0046h"A" through "F"4.2Configuration DescriptorTable 4.4 - Configuration DescriptorOffset Field Size Value Description0bLength Byte09h Size of this descriptor in bytes.1bDescriptorType Byte02h CONFIGURATION Descriptor Type.2wTotalLength Word????h Total length of data returned for this configuration. Includesthe combined length of all descriptors (configuration, interface,endpoint, and class- or vendor-specific) returned for thisconfiguration.4bNumInterfaces Byte??h Number of interfaces supported by this configuration. Thedevice shall support at least the Bulk-Only Data Interface.5bConfigurationValue Byte??h Value to use as an argument to the SetConfiguration() requestto select this configuration.6iConfiguration Byte??h Index of string descriptor describing this configuration.7bmAttributes Byte?0h Configuration characteristics:Bit Description7Reserved (set to one)6Self-powered5Remote Wakeup4..0Reserved (reset to zero)Bit 7 is reserved and must be set to one for historical reasons.For a full description of this bmAttributes bitmap, see theUSB 1.1 Specification.8MaxPower Byte??h Maximum power consumption of the USB device from the busin this specific configuration when the device is fullyoperational. Expressed in 2mA units (i.e. 50 = 100mA) NOTE:Information in this table is from the USB Specification version 1.1 table 9-8. Bold text has been added for clarifications when using these descriptors with this specification.4.3Interface DescriptorsThe device shall support at least one interface, known herein as the Bulk-Only Data Interface. The Bulk-Only Data Interface uses three endpoints.Composite mass storage devices may support additional interfaces, to provide other features such as audio or video capabilities. This specification does not define such interfaces.The interface may have multiple alternate settings. The host shall examine each of the alternate settings to look for the bInterfaceProtocol and bInterfaceSubClass it supports optimally.Table 4.5 – Bulk-Only Data Interface DescriptorOffset Field Size Value Description0bLength Byte09h Size of this descriptor in bytes.1bDescriptorType Byte04h INTERFACE Descriptor Type.2bInterfaceNumber Byte0?h Number of interface. Zero-based value identifying the indexin the array of concurrent interfaces supported by thisconfiguration.3bAlternateSetting Byte??h Value used to select alternate setting for the interfaceidentified in the prior field.4bNumEndpoints Byte??h Number of endpoints used by this interface (excludingendpoint zero). This value shall be at least 2.5bInterfaceClass Byte08h MASS STORAGE Class.6bInterfaceSubClass Byte0?h Subclass code (assigned by the USB-IF). Indicates whichindustry standard command block definition to use.Does not specify a type of storage device such as a floppydisk or CD-ROM drive.(See USB Mass Storage Overview Specification) 7bInterfaceProtocol Byte50h BULK-ONLY TRANSPORT.(See USB Mass Storage Overview Specification) 8iInterface Byte??h Index to string descriptor describing this interface.NOTE:Information in this table is from the USB Specification version 1.1 table 9-9. Bold text has been added for clarifications when using these descriptors with this specification.4.4Endpoint DescriptorsThe device shall support at least three endpoints: Control, Bulk-In and Bulk-Out.Each USB device defines a Control endpoint (Endpoint 0). This is the default endpoint and does not require a descriptor.4.4.1Bulk-In EndpointThe Bulk-In endpoint is used for transferring data and status from the device to the host.Table 4.6 - Bulk-In Endpoint DescriptorOffset Field Size Value Description0bLength Byte07h Size of this descriptor in bytes.1bDescriptorType Byte05h ENDPOINT Descriptor Type.2bEndpointAddress Byte8?h The address of this endpoint on the USB device. The address isencoded as follows.Bit Description3..0The endpoint number6..4Reserved, set to 071=In3bmAttributes Byte02h This is a Bulk endpoint.4wMaxPacketSize Word00??h Maximum packet size. Shall be 8, 16, 32 or 64 bytes (08h,10h, 20h, 40h).6bInterval Byte00h Does not apply to Bulk endpoints.4.4.2Bulk-Out EndpointThe Bulk-Out endpoint is used for transferring command and data from the host to the device.Table 4.7 – Bulk-Out Endpoint DescriptorOffset Field Size Value Description0bLength Byte07h Size of this descriptor in bytes.1bDescriptorType Byte05h ENDPOINT descriptor type.2bEndpointAddress Byte0?h The address of this endpoint on the USB device. This address isencoded as follows:Bit Description3..0Endpoint number6..4Reserved, set to 070=Out3bmAttributes Byte02h This is a Bulk endpoint.4wMaxPacketSize Word00??h Maximum packet size. Shall be 8, 16, 32 or 64 bytes (08h,10h, 20h, or 40h).6bInterval Byte00h Does not apply to Bulk endpoints.5 Command/Data/Status ProtocolFigure 1 - Command/Data/Status Flow shows the flow for Command Transport, Data-In, Data-Out and Status Transport.The following sections define Command and Status Transport.Figure 2 - Status Transport Flow shows a detailed diagram of Status Transport. The following sections outline the various conditions for host/device communication, possible errors, and recovery procedures.5.1 Command Block Wrapper (CBW)The CBW shall start on a packet boundary and shall end as a short packet with exactly 31 (1Fh) bytes transferred. Fields appear aligned to byte offsets equal to a multiple of their byte size. All subsequent data and the CSW shall start at a new packet boundary. All CBW transfers shall be ordered with the LSB (byte 0) first (little endian). Refer to the USBSpecification Terms and Abbreviations for clarification.Table 5.1 - Command Block Wrapperbit Byte 76543210-3dCBWSignature 4-7dCBWTag8-11(08h-0Bh)dCBWDataTransferLength12(0Ch)bmCBWFlags13(0Dh)Reserved (0)bCBWLUN14(0Eh)Reserved (0)bCBWCBLength15-30(0Fh-1Eh)CBWCBdCBWSignature:Signature that helps identify this data packet as a CBW. The signature field shall contain the value 43425355h (little endian), indicating a CBW.dCBWTag:A Command Block Tag sent by the host. The device shall echo the contents of this field back to the host in the dCSWTag field of the associated CSW. The dCSWTag positively associates a CSW with the corresponding CBW.dCBWDataTransferLength:The number of bytes of data that the host expects to transfer on the Bulk-In or Bulk-Out endpoint (as indicated by the Direction bit) during the execution of this command. If this field is zero, the device and the host shall transfer no data between the CBW and the associated CSW, and the device shall ignore the value of the Direction bit in bmCBWFlags .Figure 1 - Command/Data/Status FlowReady Command Transport(CBW)Data - Out(from host)Data - In(to host)Status Transport(CSW)bmCBWFlags:The bits of this field are defined as follows:Bit 7Direction - the device shall ignore this bit if the dCBWDataTransferLength field iszero, otherwise:0 = Data-Out from host to the device,1 = Data-In from the device to the host.Bit 6Obsolete. The host shall set this bit to zero.Bits 5..0 Reserved - the host shall set these bits to zero.bCBWLUN:The device Logical Unit Number (LUN) to which the command block is being sent. For devices thatsupport multiple LUNs, the host shall place into this field the LUN to which this command block isaddressed. Otherwise, the host shall set this field to zero.bCBWCBLength:The valid length of the CBWCB in bytes. This defines the valid length of the command block. Theonly legal values are 1 through 16 (01h through 10h). All other values are reserved.CBWCB:The command block to be executed by the device. The device shall interpret the first bCBWCBLength bytes in this field as a command block as defined by the command set identified by bInterfaceSubClass.If the command set supported by the device uses command blocks of fewer than 16 (10h) bytes inlength, the significant bytes shall be transferred first, beginning with the byte at offset 15 (Fh). Thedevice shall ignore the content of the CBWCB field past the byte at offset (15 + bCBWCBLength - 1). 5.2Command Status Wrapper (CSW)The CSW shall start on a packet boundary and shall end as a short packet with exactly 13 (0Dh) bytes transferred. Fields appear aligned to byte offsets equal to a multiple of their byte size. All CSW transfers shall be ordered with the LSB (byte 0) first (little endian). Refer to the USB Specification Terms and Abbreviations for clarification.Table 5.2 - Command Status WrapperbitByte765432100-3dCSWSignature4-7dCSWTag8-11dCSWDataResidue(8-Bh)12bCSWStatus(Ch)dCSWSignature:Signature that helps identify this data packet as a CSW. The signature field shall contain the value53425355h (little endian), indicating CSW.dCSWTag:The device shall set this field to the value received in the dCBWTag of the associated CBW.dCSWDataResidue:For Data-Out the device shall report in the dCSWDataResidue the difference between the amount of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Data-In the device shall report in the dCSWDataResidue the difference between theamount of data expected as stated in the dCBWDataTransferLength and the actual amount of relevant data sent by the device. The dCSWDataResidue shall not exceed the value sent in thedCBWDataTransferLength.bCSWStatus:bCSWStatus indicates the success or failure of the command. The device shall set this byte to zero if the command completed successfully. A non-zero value shall indicate a failure during commandexecution according to the following table:Table 5.3 - Command Block Status ValuesValue Description00h Command Passed ("good status")01h Command Failed02h Phase Error03h and 04h Reserved (Obsolete)05h to FFh Reserved5.3Data Transfer ConditionsThis section describes how the host and device remainsynchronized.The host indicates the expected transfer in the CBW using the Direction bit and the dCBWDataTransferLength field. The device then determines the actual direction and data transfer length. The device responds as defined in 6 - Host/Device Data Transfers by transferring data, STALLing endpoints when specified, and returning the appropriate CSW. 5.3.1Command TransportThe host shall send each CBW, which contains a command block, to the device via the Bulk-Out endpoint. The CBW shall start on a packet boundary and end as a short packet with exactly 31 (1Fh) bytes transferred.The device shall indicate a successful transport of a CBW by accepting (ACKing) the CBW. If the CBW is not valid see 6.6.1 - CBW Not Valid. If the host detects a STALL of the Bulk-Out endpoint during command transport, the host shall respond with a Reset Recovery (see 5.3.4 - Reset Recovery).5.3.2Data TransportAll data transport shall begin on a packet boundary. The host shall attempt to transfer the exact number of bytes to or from the device as specified by the dCBWDataTransferLength and the Direction bit. The device shall respond as specified in 6 - Host/Device Data Transfers.Attempt to read CSWfrom Bulk-In endpointSTALL Bulk-In- OR -Bulk Error?Clear the STALLconditionYesAttempt to read CSWfrom Bulk-In endpointBulk-IN endpointSTALLed?CSW Valid?NoPhase Error Status?Perform Reset RecoveryYesNoYesYesDevice ready toprocess next CBWNoEnterNoFigure 2 - Status Transport FlowTo report an error before data transport completes and to maximize data integrity, the device may terminate the command by STALLing the endpoint in use (the Bulk-In endpoint during data in, the Bulk-Out endpoint during data out).5.3.3 Status TransportThe device shall send each CSW to the host via the Bulk-In endpoint. The CSW shall start on a packet boundary and end as a short packet with exactly 13 (Dh) bytes transferred. Figure 2 - Status Transport Flow defines the algorithm the host shall use for any CSW transfer.The CSW indicates to the host the status of the execution of the command block from the corresponding CBW. The dCSWDataResidue field indicates how much of the data transferred is to be considered processed or relevant. The host shall ignore any data received beyond that which is relevant.5.3.3.1Phase ErrorThe host shall perform a Reset Recovery when Phase Error status is returned in the CSW.5.3.4Reset RecoveryFor Reset Recovery the host shall issue in the following order: :(a) a Bulk-Only Mass Storage Reset(b) a Clear Feature HALT to the Bulk-In endpoint(c) a Clear Feature HALT to the Bulk-Out endpoint。
A8293
DescriptionIntended for analog and digital satellite receivers, this single low noise block converter regulator (LNBR) is a monolithic linear and switching voltage regulator, specifically designed to provide the power and the interface signals to an LNB down converter via coaxial cable. The A8293 requires few external components, with the boost switch and compensation circuitry integrated inside of the device. A high switching frequency is chosen to minimize the size of the passive filtering components, further assisting in cost reduction. The high levels of component integration ensure extremely low noise and ripple figures. The A8293 has been designed for high efficiency, utilizing the Allegro ® advanced BCD process. The integrated boost switch has been optimized to minimize both switching and static losses. To further enhance efficiency, the voltage drop across the tracking regulator has been minimized.For DiSEqC™ communications, several schemes are available for generating tone signals, all the way down to no-load, and using either the internal clock or an external time source.Features and Benefits▪ 2-wire serial I 2C™ -compatible interface: control (write) and status (read)▪ LNB voltages (7 programmable levels) compatible with all common standards▪ Tracking switch-mode power converter for lowest dissipation ▪ Integrated converter switches and current sensing ▪ Provides up to 700 mA load current▪ Static current limit circuit allows full current at startup and 13→18 V output transition; reliably starts wide load range ▪ Push-pull output stage minimizes 13→18 V and 18→13 V output transition times for highly capacitive loads▪ Adjustable rise/fall time via external timing capacitor ▪ Built-in tone oscillator, factory-trimmed to 22 kHz facilitates DiSEqC™ tone encoding, even at no-load ▪ Four methods of 22 kHz tone generation, via I 2C™ data bits and/or external pin ▪ Auxiliary modulation input ▪ LNB overcurrent with timer▪Diagnostics for output voltage level, input supply UVLOSingle LNB Supply and Control V oltage RegulatorContinued on the next page…Functional Block DiagramA8293L1Packages:20-contact, 4 × 4 mmMLP/QFN (suffix ES)28 contact, 5 × 5 mm MLP/QFN (suffix ET)Package Thermal Characteristics*Package R θJA (°C/W)PCB ES 37 (estimated)4-layer ET324-layer* Additional information is available on the Allegro website.Selection GuidePart Number Packing 1DescriptionA8293SESTR-T 27 in. reel, 1500 pieces/reel12 mm carrier tape ES package, MLP/QFN surface mount 4 mm × 4 mm × 0.75 mm nominal height A8293SETTR-T 2,37 in. reel, 1500 pieces/reel12 mm carrier tapeET package, MLP/QFN surface mount 5 mm × 5 mm × 0.90 mm nominal height1Contact Allegro for additional packing options.2Leadframe plating 100% matte tin.3This variant is in production but has been determined to be NOT FOR NEW DESIGN. This classi fi cation indicates that saleof this device is currently restricted to existing customer applications. The variant should not be purchased for new design ap-plications because obsolescence in the near future is probable. Status date change September 21, 2010.A comprehensive set of fault registers are provided, which comply with all the common standards, including: overcurrent, thermal shutdown, undervoltage, and power not good.The device uses a 2-wire bidirectional serial interface, compatible with the I 2C™ standard, that operates up to 400 kHz.The A8293 is supplied in two lead (Pb) free MLP/QFN packages: ES, 20-contact, 4 mm × 4 mm, 0.75 nominal overall height, and ET, 28-contact, 5 mm × 5 mm, 0.90 nominal overall height.Description (continued)Absolute Maximum RatingsCharacteristic SymbolConditionsRating UnitsLoad Supply Voltage, VIN pin V IN 30V Output Current*I OUTInternally Limited A Output Voltage; LNB and BOOST pins –1 to 33 V Output Voltage; LX pin –1 to 30V Output Voltage; VCP pin –1 to 41 V Logic Input Voltage, EXTM pin –0.3 to 5 V Logic Input Voltage, other pins –0.3 to 7 V Logic Output Voltage–0.3 to 7 V Operating Ambient Temperature T A –20 to 85 °C Junction Temperature T J (max) 150°C Storage TemperatureT stg –55 to 150°C*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed thespecified current ratings, or a junction temperature, T J , of 150°C.PAD1514131211123456789102019181716L N BG N DL XV I NN CN CG N DV R E GS D A A D D FLOAT GND NC SCL IRQBOOST VCP TCAP FLOAT EXTMTerminal List TableName Number FunctionES ET ADD 1011Address selectFLOAT 4, 155, 22These pins must not be connected to anything; do not ground these pins BOOST 11Tracking supply voltage to linear regulator EXTM 56External modulation input GND 7, 148, 19Signal ground GNDLX 1927Boost switch ground IRQ 1114Interrupt request LNB 2028Output voltage to LNB LX 1826Inductor drive point NC 6, 13, 164, 7, 13, 15-18, 20, 21, 23, 24No connectionPAD Pad PadExposed pad; connect to the ground plane, for thermal dissipation SCL 1212I 2C™-compatible clock input SDA 910I 2C™-compatible data input/outputTCAP 33Capacitor for setting the rise and fall time of the LNB output VCP 22Gate supply voltage VIN 1725Supply input voltage VREG89Analog supplyDevice Pin-out Diagram(Top View)PAD 21201918171615123456789101112131428272625242322L N BG N D L XL XV I N N C N CF L O A TG N DV R E GS D A A D D S C L N C I R Q NC NC GND NC NC NC NC BOOST VCP TCAP NC FLOAT EXTM NCES PackageET PackageELECTRICAL CHARACTERISTICS at TA= 25°C, V IN = 9 to 16 V, unless noted otherwise1Characteristics Symbol Test Conditions Min.Typ.Max.Units GeneralSet-Point Accuracy, Load and Line Regulation Err Relative to selected V LNB target level,I LOAD = 0 to 450 mA–3.0–+3.0%Supply Current I IN(Off)ENB bit = 0, LNB output disabled, V IN = 12 V––10.0mA I IN(On)ENB bit = 1, LNB output enabled,I LOAD = 0 mA, V IN = 12 V––19.0mABoost Switch On Resistance R DS(on)BOOST I LOAD = 450 mA–300–mΩSwitching Frequency f SW320352384kHz Switch Current Limit I LIMSW V IN = 9 V, V OUT = 19.0 V– 2.7–ALinear Regulator Voltage Drop∆V REG V BOOST – V LNB, no tone signal,I LOAD = 450 mA–800–mVTCAP Pin CurrentI CHG TCAP capacitor (C7) charging–12.5–10–7.5μA I DISCHG TCAP capacitor (C7) discharging7.51012.5μAOutput Voltage Rise Time2t r(VLNB)For V LNB 13 →18 V; C TCAP = 5.6 nF,I LOAD = 450 mA–500–μsOutput Voltage Pull-Down Time2t f(VLNB)For V LNB 18 →13 V; C LOAD = 100 μF,I LOAD = 0 mA–12.5–msOutput Reverse Current I RLNB ENB bit = 0, V LNB = 33 V , BOOST capacitor(C5) fully charged–15mARipple and Noise on LNB Output3V rip,n(pp)20 MHz BWL; reference circuit shown inFunctional Block diagram; contact Allegro foradditional information on application circuitboard design–30–mV PPProtection CircuitryOutput Overcurrent Limit4I LIMLNB V BOOST – V LNB = 800 mV–700800mA Overcurrent Disable Time t DIS–48–ms VIN Undervoltage Lockout Threshold V UVLO V IN falling7.057.357.65V VIN Turn On Threshold V IN(th)V IN rising7.407.708.00V Undervoltage Hysteresis V UVLOHYS–350–mV Thermal Shutdown Threshold2T J–165–°C Thermal Shutdown Hysteresis2∆T J–20–°C Power Not Good Flag Set PNG SET With respect to V LNB778593% Power Not Good Flag Reset PNG RESET With respect to V LNB829098% Power Not Good Hysteresis PNG HYS With respect to V LNB–5–% ToneTone Frequency f TONE202224kHz Tone Amplitude, Peak-to-Peak V TONE(pp)I LOAD = 0 to 450 mA, C LOAD = 750 nF400620800mVContinued on the next page…Tone Duty Cycle DC TONE I LOAD = 0 to 450 mA, C LOAD = 750 nF 405060%Tone Rise Time t rTONE I LOAD = 0 to 450 mA, C LOAD = 750 nF 51015μs Tone Fall Time t fTONE I LOAD = 0 to 450 mA, C LOAD = 750 nF51015μs EXTM Logic Input V EXTM(H) 2.0––VV EXTM(L)––0.8V EXTM Input Leakage I EXTMLKG–1–1μAI 2C™-Compatible Interface Logic Input (SDA,SCL) Low Level V SCL(L)––0.8V Logic Input (SDA,SCL) High Level V SCL(H) 2.0––V Logic Input Hysteresis V I2CIHYS –150–mV Logic Input CurrentI I2CI V I2CI = 0 to 7 V –10<±1.010μA Logic Output Voltage SDA and IRQ V t2COut(L)I LOAD = 3 mA ––0.4V Logic Output Leakage SDA and IRQ V t2CLKG V t2COut = 0 to 7 V––10μA SCL Clock Frequency f CLK ––400kHz Output Fall Timet fI2COut V t2COut(H) to V t2COut(L)––250ns Bus Free Time Between Stop/Start t BUF 1.3––μs Hold Time Start Condition t HD:STA 0.6––μs Setup Time for Start Condition t SU:STA 0.6––μs SCL Low Time t LOW 1.3––μs SCL High Time t HIGH 0.6––μs Data Setup Timet SU:DAT 100––nsData Hold Timet HD:DAT For t HD:DAT (min) , the master device must provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the SCL signal falling edge 0–900ns Setup Time for Stop Condition t SU:STO 0.6––μs I 2C™ Address SettingADD Voltage for Address 0001,000Address10–0.7V ADD Voltage for Address 0001,001Address2 1.3– 1.7V ADD Voltage for Address 0001,010Address3 2.3– 2.7V ADD Voltage for Address 0001,011Address43.3–5.0V1Operation at 16 V may be limited by power loss in the linear regulator.2Guaranteed by worst case process simulations and system characterization. Not production tested.3LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layoutrecommendations. Not production tested.4Current from the LNB output may be limited by the choice of Boost components.ELECTRICAL CHARACTERISTICS (continued) at T A = 25°C, V IN = 9 to 16 V, unless noted otherwise 1CharacteristicsSymbol Test ConditionsMin.Typ.Max.Units I 2C™ Interface Timing DiagramHIGH LOW SDA SCLProtectionThe A8293 has a wide range of protection features and fault diag-nostics which are detailed in the Status Register section.Boost Converter/Linear RegulatorThe A8293 solution contains a tracking current-mode boost converter and linear regulator. The boost converter tracks the requested LNB voltage to within 800 mV, to minimize power dissipation. Under conditions where the input voltage, V BOOST , is greater than the output voltage, V LNB, the linear regulator must drop the differential voltage. When operating in these conditions, care must be taken to ensure that the safe operating temperature range of the A8293 is not exceeded.The boost converter operates at 352 kHz typical: 16 times the internal 22 kHz tone frequency. All the loop compensation, current sensing, and slope compensation functions are provided internally.The A8293 has internal pulse-by-pulse current limiting on the boost converter and DC current limiting on the LNB output to protect the IC against short circuits. When the LNB output is shorted, the LNB output current is limited to 700 mA typical, and the IC will be shut down if the overcurrent condition lasts for more than 48 ms. If this occurs, the A8293 must be reenabled for normal operation. The system should provide sufficient time between successive restarts to limit internal power dissipation; a minimum of 2 s is recommended.At extremely light loads, the boost converter operates in a pulse-skipping mode. Pulse skipping occurs when the BOOST voltage rises to approximately 450 mV above the BOOST target output voltage. Pulse skipping stops when the BOOST voltage drops 200 mV below the pulse skipping level.In the case that two or more set top box LNB outputs are con-nected together by the customer (e.g., with a splitter), it is pos-sible that one output could be programmed at a higher voltage than the other. This would cause a voltage on one output that is higher than its programmed voltage (e.g., 19 V on the output of a 13 V programmed voltage). The output with the highest voltage will effectively turn off the other outputs. As soon as this voltage is reduced below the value of the other outputs, the A8293 output will auto-recover to their programmed levels.Charge Pump.Generates a supply voltage above the internal tracking regulator output to drive the linear regulator control. Slew Rate Control. During either start-up, or when the output voltage at the LNB pin is transitioning, the output voltage rise and fall times can be set by the value of the capacitor connected from the TCAP pin to GND (C TCAP or C7 in the Applications Schematic). Note that during start-up, the BOOST pin is pre-charged to the input voltage minus a voltage drop. As a result, the slew rate control for the BOOST pin occurs from this voltage.The value of C TCAP can be calculated using the following for-mula:C TCAP = (I TCAP × 6) / SR ,where SR is the required slew rate of the LNB output voltage,in V/s, and I TCAP is the TCAP pin current specified in the data sheet. The recommended value for C TCAP, 10 nF, should provide satisfactory operation for most applications. However, in some cases, it may be necessary to increase the value of C TCAP to avoid activating the current limit of the LNB output. One such situa-tion is when two set-top boxes are connected in parallel. If this is the case, the following formula can be used to calculate C TCAP:C TCAP≥ (I TCAP × 6)(2 × C BOOST) / I LIMLNB ,C TCAP≥ (10 μA × 6)(2 × 100 μF) / 500 mA = 24 nF .The minimum value of C TCAP is 2.2 nF. There is no theoretical maximum value of C TCAP however too large a value will prob-ably cause the voltage transition specification to be exceeded. Tone generation is unaffected by the value of C TCAP .Pull-Down Rate Control.In applications that have to operate at very light loads and that require large load capacitances (in the order of tens to hundreds of microfarads), the output linear stage provides approximately 40 mA of pull-down capability. This ensures that the output volts are ramped from 18 V to 13 V in a reasonable amount of time.ODT (Overcurrent Disable Time)If the LNB output current exceeds 700 mA, typical, for more than 48 ms, then the LNB output will be disabled and the OCP bit will be set.Short Circuit HandlingIf the LNB output is shorted to ground, the LNB output current will be clamped to 700 mA, typical. If the short circuit condition lasts for more than 48 ms, the A8293 will be disabled and the OCP bit will be set.Auto-RestartAfter a short circuit condition occurs, the host controller should periodically reenable the A8293 to check if the short circuit hasFunctional Descriptionbeen removed. Consecutive startup attempts should allow at least 2 s of delay between restarts.In-Rush CurrentAt start-up or during an LNB reconfiguration event, a tran-sient surge current above the normal DC operating level can be provided by the A8293. This current increase can be as high as 700 mA, typical, for as long as required, up to a maximum of48 ms.Tone GenerationThe A8293 solution offers four options for tone generation, providing maximum flexibility to cover every application. The EXTM pin (external modulation), in conjunction with the I2C™ control bits: TMODE (tone modulation) and TGATE (tone gate), provide the necessary control. The TMODE bit controls whether the tone source is either internal or external (via the EXTM pin). Both the EXTM pin and TGATE bit determine the 22 kHz con-trol, whether gated or clocked.Four options for tone generation are shown in figure 1. Note that when using option 4, when EXTM stops clocking, the LNB volts park at the LNB voltage, either plus or minus half the tone signal amplitude, depending on the state of EXTM. For example, if the EXTM is held low, the LNB DC voltage is the LNB pro-grammed voltage minus 325 mV (typical).EXTM TMODE TGATE ToneEXTM TMODETGATE ToneEXTM TMODE TGATE ToneEXTM TMODE TGATE ToneOption 1 – Use internal tone, gated by the TGATE bit. Option 2 – Use internal tone, gated by the EXTM pin. Option 3 – Use external tone, gated by the TGATE bit. Figure 1. Options for tone generationI 2C™-Compatible InterfaceThis is a serial interface that uses two bus lines, SCL and SDA,to access the internal Control and Status registers of the A8293.Data is exchanged between a microcontroller (master) and theA8293 (slave). The clock input to SCL is generated by the master,while SDA functions as either an input or an open drain output,depending on the direction of the data.Timing ConsiderationsThe control sequence of the communication through the I 2C™-compatible interface is composed of several steps in sequence: 1. Start Condition. Defined by a negative edge on the SDA line,while SCL is high.2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)or write (0), and an acknowledge bit. The first five bits of the address are fixed as: 00010. The four optional addresses, de-fined by the remaining two bits, are selected by the ADD input. The address is transmitted MSB first.3. Data Cycles. Write – 6 bits of data and 2 bits for addressing four internal control registers, followed by an acknowledge bit. See Control Register section for more information. Read – Two status registers, where register 1 is read first, followed by register 2, then register 1, and so on. At the start of any read sequence, register 1 is always read first. Data is transmitted MSB first.4. Stop Condition. Defined by a positive edge on the SDA line,while SCL is high. Except to indicate a Start or Stop condi-tion, SDA must be stable while the clock is high. SDA canonly be changed while SCL is low. It is possible for the Start or Stop condition to occur at any time during a data transfer. The A8293 always responds by resetting the data transfer sequence. The Read/Write bit is used to determine the data transfer direc-tion. If the Read/Write bit is high, the master reads the contents of 1 2 3 4 5 6 7 8 9SCL1 2 3 4 5 6 7 8 9SCL1 2 3 4 5 6 7 8 9SCL Write to RegisterRead One Byte from RegisterRead Multiple Bytes from RegisterFigure 2. I 2C™ Interface. Read and write sequences.register 1, followed by register 2 if a further read is performed. If the Read/Write bit is low, the master writes data to one of the two Control registers. Note that multiple writes are not permitted. All write operations must be preceded with the address.The Acknowledge bit has two functions. It is used by the mas-ter to determine if the slave device is responding to its address and data, and it is used by the slave when the master is reading data back from the slave. When the A8293 decodes the 7-bit ad-dress field as a valid address, it responds by pulling SDA low during the ninth clock cycle.During a data write from the master, the A8293 also pulls SDA low during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received. In both cas-es, the master device must release the SDA line before the ninth clock cycle, in order to allow this handshaking to occur.During a data read, the A8293 acknowledges the address in the same way as in the data write sequence, and then retains control of the SDA line and send the data from register 1 to the master. On completion of the eight data bits, the A8293 releases the SDA line before the ninth clock cycle, in order to allow the master to acknowledge the data. If the master holds the SDA line low dur-ing this Acknowledge bit, the A8293 responds by sending the data from register 2 to the master. Data bytes continue to be sent to the master until the master releases the SDA line during the Acknowledge bit. When this is detected, the A8293 stops sending data and waits for a stop signal. Interrupt RequestThe A8293 also provides an interrupt request pin, IRQ, which is an open-drain, active-low output. This output may be connect-ed to a common IRQ line with a suitable external pull-up and can be used with other I 2C™-compatible devices to request attention from the master controller.The IRQ output becomes active when either the A8293 first recognizes a fault condition, or at power-on, when the main sup-ply, V IN , and the internal logic supply, V REG , reach the correct operating conditions. It is only reset to inactive when the I 2C™ master addresses the A8293 with the Read/Write bit set (caus-ing a read). Fault conditions are indicated by the TSD, VUV , and OCP bits, and are latched in the Status register. See the Status register section for full description.The DIS and PNG status bits do not cause an interrupt. The PNG bit is continually updated, apart from the DIS bit, which changes when the LNB is either disabled, faulted, or is enabled. When the master recognizes an interrupt, it addresses allslaves connected to the interrupt line in sequence, and then reads the status register to determine which device is requesting atten-tion. The A8293 latches all conditions in the Status register until the completion of the data read. The action at the resampling point is further defined in the Status Register section. The bits in the Status register are defined such that the all-zero condition in-dicates that the A8293 is fully active with no fault conditions. When V IN is initially applied, the I 2C™-compatible interface does not respond to any requests until the internal logic supply V REG has reached its operating level. Once V REG has reached this point, the IRQ output goes active, and the VUV bit is set. After the A8293 acknowledges the address, the IRQ flag is reset. After the master reads the status registers, the registers are updated with the VUV reset.Status Register 1Address Start R Stop1 2 3 4 5 6 7 8 9SCL IRQFaultEventReloadStatus RegisterRead after InterruptFigure 3. I 2C™ Interface. Read sequences after interrupt request.Control Registers (I2C™-Compatible Write Register) All main functions of the A8293 are controlled through the I2C™-compatible interface via the 8-bit Control registers. As the A8293 contains numerous control options, it is necessary to have two control registers. Each register contains up to 6 bits of data (bit 0 to bit 5), followed by 2 bits for the register address (bit 6 and bit 7). The power-up states for the control functions are all 0s.The following tables define the control bits for each address and the settings for output voltage:Table 1. Control Register Address (I1, I0) = 00 Bit Name Function0VSEL0See table 3, Output Voltage Amplitude Selection 1VSEL12VSEL23VSEL30: LNB = Low range1: LNB = High range4ODT 1 (recommended): The ODT functions are always enabled, but setting 1 recommended at all times.5ENB0: Disable LNB Output1: Enable LNB Output6I0Address Bit: 07I1Address Bit: 0Bit 0 VSEL0 These three bits provide incremental control over the voltage on the LNB output.Bit 1 VSEL1 The available voltages provide the necessary levels for all the common standards Bit 2 VSEL2 plus the ability to add line compensation in increments of 333 mV. The voltage levels are defined in table 3, Output V oltage Amplitude Selection.Bit 3 VSEL3 Switches between the low level and high level output voltages on the LNB output.0 selects the low level voltage and 1 selects the high level. The low-level center voltageis 12.709 V nominal and the high level is 18.042 V nominal. These may be increasedin steps of 333 mV using the VSEL2, VSEL1 and VSEL0 control register bits.Bit 4 ODT The overcurrent disable timer is always enabled.Bit 5 ENB Enables the LNB output. When set to 1 the LNB output is switched on. When set to 0, the LNB output is disabled.Bit 6 I0 AddressBit 7 I1 AddressTable 2. Control Register Address (I1, I0) = 10 and 11Bit Name Function0: External Tone0TMODE1: Internal Tone0: Tone Gated Off1TGATE1: Tone Gated On2-Not Used (0 recommended)3-Not Used4-Not Used5-Not Used6I0Address Bit: 07I1Address Bit: 1Bit 0 TMODE Tone Mode. Selects between the use of an external 22 kHz logic signal or the use of the internal 22 kHz oscillator to control the tone generation on the LNB output. A 0selects the external tone and a 1 selects the internal tone. See the Tone Generationsection for more informationBit 1 TGATE Tone Gate. Allows either the internal or external 22 kHz tone signals to be gated, unless the EXTM is selected for gating. When set to 0, the selected tone (viaTMODE) is off. When set to 1, the selected tone is on. See Tone Generation Sectionfor more information.Bit 2 – Not Used.Bit 3 – Not Used.Bit 4 – Not Used.Bit 5 – Not Used.Bit 6 I0 Address.Bit 7 I1 Address.Table 3. Output Voltage Amplitude Selection VSEL3VSEL2VSEL1VSEL0LNB (V) 000012.709 000113.042 001013.375 010014.042 100018.042 101018.709 101119.042Status Registers (I2C™-Compatible Read Register)The main fault conditions: overcurrent (OCP), undervoltage (VUV) and overtemperature (TSD), are all indicated by setting the relevant bits in the Status registers. In all fault cases, once the bit is set, it remains latched until the A8293 is read by the I2C™ master, assuming the fault has been resolved.The current status of the LNB output is indicated by the dis-able bit, DIS. The DIS bit is set when either a fault occurs or if the LNB is disabled intentionally. This bit is latched, and is reset when the LNB is commanded on again. The power not good (PNG) is the only bit which may be reset without an I2C™ read sequence. Table 4 summarizes the condition of each bit when set and how it is reset.As the A8293 has a comprehensive set of status reporting bits, it is necessary to have two Status registers. When performing a multiple read function, register 1 is read followed by register 2, then register 1 again and so on. Whenever a new read function is performed, register 1 is always read first.The normal sequence of the master in a fault condition will be to detect the fault by reading the Status registers, then rereading the Status registers until the status bit is reset indicating the fault condition is reset. The fault may be detected either by continuously polling, by responding to an interrupt request (IRQ), or by detect-ing a fault condition externally and performing a diagnostic poll of all slave devices. Note that the fully-operational condition of the Status registers is all 0s, to simplify checking of the Status bit.Table 4. Status Register Bit SettingStatus Bit Function SetReset Condition–Not used–Not usedDIS LNB disabled, either intentionally ordue to faultLatched LNB enabled and no faultOCP Overcurrent Latched I2C™ read and fault removed PNG Power not good Non-latched LNB volts in range–Not used–Not usedTSD Thermal shutdown Latched I2C™ read and fault removed VUV Undervoltage Latched I2C™ read and fault removedTable 5. Status Register 1Bit Name Function0DIS LNB output disabled1–Not Used2OCP Overcurrent3–Not Used4PNG Power Not Good5–Not Used6TSD Thermal Shutdown7VUV V IN UndervoltageBit 0 DIS LNB Output Disabled. DIS is used to indicate the current condition of the LNB output. At power-on, or if a fault condition occurs, DIS will be set. This bit changingto 1 does not cause the IRQ to activate because the LNB output may be disabled in-tentionally by the I2C™ master. This bit will be reset at the end of a write sequenceif the LNB output is enabled.Bit 1 – Not used.Bit 2 OCP Overcurrent. If the LNB output detects an overcurrent condition, for greater than48 ms, the LNB output will be disabled. The OCP bit will be set to indicate that anovercurrent has occurred and the disable bit, DIS, will be set. The Status register isupdated on the rising edge of the 9th clock pulse in the data read sequence, where theOCP bit is reset in all cases, allowing the master to reenable the LNB output.If the overcurrent timer is not enabled, the device operate in current limit indefinitelyand the OCP bit will be set. If the overcurrent condition is removed, the OCP bit willautomatically be reset. Note that if the overcurrent operates long enough, and a ther-mal shutdown occurs, the LNB output will be disabled and the TSD bit will be set.Bit 3 – Not used.Bit 4 PNG Power Not Good. Set to 1 when the LNB output is enabled and the LNB voltage is below 85% of the programmed voltage. The PNG is reset when the LNB volts arewithin 90% of the programmed LNB voltage.Bit 5 – Not used.Bit 6 TSD Thermal Shutdown. 1 indicates that the A8293 has detected an overtemperature condition and has disabled the LNB output. The disable bit, DIS, will also be set.The status of the overtemperature condition is sampled on the rising edge of the 9thclock pulse in the data read sequence. If the condition is no longer present, then theTSD bit will be reset, allowing the master to reenable the LNB output if required. Ifthe condition is still present, then the TSD bit will remain at 1.Bit 7 VUV Undervoltage Lockout. 1 indicates that the A8293 has detected that the input sup-ply, V IN is, or has been, below the minimum level and an undervoltage lockout hasoccurred disabling the LNB outputs. The disable bit, DIS, will also be set and theA8293 will not reenable the output until so instructed by writing the relevant bit intothe control registers. The status of the undervoltage condition is sampled on the risingedge of the 9th clock pulse in the data read sequence. If the condition is no longerpresent, then the VUV bit will be reset allowing the master to reenable the LNB out-put if required. If the condition is still present, then the VUV bit will remain at 1.。
正常循环前缀-概述说明以及解释
正常循环前缀-概述说明以及解释1.引言1.1 概述正常循环前缀是一种在计算机科学领域中常见的概念，它可以帮助我们更好地理解和优化算法的性能。
在算法设计中，循环前缀通常用于描述循环过程中的一组操作或指令的组合。
正常循环前缀则是指在循环执行过程中，这些操作按照指定的次序和规律依次执行，且不会出现死循环或执行顺序混乱的情况。
本文将详细探讨正常循环前缀的概念、特征以及其在算法设计和优化中的应用。
通过深入理解正常循环前缀，我们可以更好地把握算法执行的逻辑和效率，提高代码的可读性和可维护性。
在接下来的篇章中，我们将逐步展开对正常循环前缀的探讨，希望读者能够通过本文的学习，对这一概念有更加清晰的认识。
1.2 文章结构本文分为引言、正文和结论三个部分。
在引言部分，将对正常循环前缀的概念、文章结构和目的进行简要介绍，为读者提供整体的把握。
在正文部分，将详细探讨正常循环前缀的概念、特征和应用，对该概念进行深入解析，并分析其在实际应用中的意义和价值。
最后，在结论部分，将对本文进行总结，展望正常循环前缀未来可能的发展方向，并给出一些结束语，为读者留下深刻印象。
整体结构清晰，层次分明，希望能够为读者提供全面的了解和思考。
1.3 目的本文旨在探讨正常循环前缀在计算机科学领域中的重要性和应用。
通过对正常循环前缀的概念、特征和应用进行深入分析和讨论，旨在帮助读者更好地理解和运用正常循环前缀技术。
同时，通过本文的撰写，也旨在促进对正常循环前缀的研究和探讨，为相关领域的学术进步和技术发展提供有益的参考和启示。
希望读者能够通过本文的阅读，对正常循环前缀有更深入的了解，并能够将其运用到实际问题的解决中，从而提升工作和学习的效率和质量。
2.正文2.1 正常循环前缀的概念：正常循环前缀是指在一个给定的循环中，首先具有某个长度的前缀，并且该前缀不会在循环的其余部分中再次出现。
换句话说，正常循环前缀是不重复出现的、与循环其他部分不同的序列。
这种特殊的前缀在循环中起着重要的作用，可以帮助我们更好地理解循环的结构和特征。
Java Runtime Systems Characterization and Architectural Implications
Java Runtime Systems: Characterization and Architectural ImplicationsRamesh Radhakrishnan,Member,IEEE,N.Vijaykrishnan,Member,IEEE, Lizy Kurian John,Senior Member,IEEE,Anand Sivasubramaniam,Member,IEEE,Juan Rubio,Member,IEEE,and Jyotsna SabarinathanAbstractÐThe Java Virtual Machine(JVM)is the cornerstone of Java technology and its efficiency in executing the portable Java bytecodes is crucial for the success of this technology.Interpretation,Just-In-Time(JIT)compilation,and hardware realization are well-known solutions for a JVM and previous research has proposed optimizations for each of these techniques.However,each technique has its pros and cons and may not be uniformly attractive for all hardware platforms.Instead,an understanding of the architectural implications of JVM implementations with real applications can be crucial to the development of enabling technologies for efficient Java runtime system development on a wide range of platforms.Toward this goal,this paper examines architectural issues from both the hardware and JVM implementation perspectives.The paper starts by identifying the important execution characteristics of Javaapplications from a bytecode perspective.It then explores the potential of a smart JIT compiler strategy that can dynamically interpret or compile based on associated costs and investigates the CPU and cache architectural support that would benefit JVMimplementations.We also study the available parallelism during the different execution modes using applications from the SPECjvm98 benchmarks.At the bytecode level,it is observed that less than45out of the256bytecodes constitute90percent of the dynamic bytecode stream.Method sizes fall into a trinodal distribution with peaks of1,9,and26bytecodes across all benchmarks.Thearchitectural issues explored in this study show that,when Java applications are executed with a JIT compiler,selective translation using good heuristics can improve performance,but the saving is only10-15percent at best.The instruction and data cacheperformance of Java applications are seen to be better than that of C/C++applications except in the case of data cache performance in the JIT mode.Write misses resulting from installation of JIT compiler output dominate the misses and deteriorate the data cacheperformance in JIT mode.A study on the available parallelism shows that Java programs executed using JIT compilers haveparallelism comparable to C/C++programs for small window sizes,but falls behind when the window size is increased.Java programs executed using the interpreter have very little parallelism due to the stack nature of the JVM instruction set,which is dominant in the interpreted execution mode.In addition,this work gives revealing insights and architectural proposals for designing an efficient Java runtime system.Index TermsÐJava,Java bytecodes,CPU and cache architectures,ILP,performance evaluation,benchmarking.æ1I NTRODUCTIONT HE Java Virtual Machine(JVM)[1]is the cornerstone of Java technology,epitomizing theªwrite-once run-any-whereºpromise.It is expected that this enabling technology will make it a lot easier to develop portable software and standardized interfaces that span a spectrum of hardware platforms.The envisioned underlying platforms for this technology include powerful(resource-rich)servers,net-work-based and personal computers,together with resource-constrained environments such as hand-held devices,specialized hardware/embedded systems,and even household appliances.If this technology is to succeed,it is important that the JVM provide an efficient execution/ runtime environment across these diverse hardware plat-forms.This paper examines different architectural issues, from both the hardware and JVM implementation perspec-tives,toward this goal.Applications in Java are compiled into the bytecode format to execute in the Java Virtual Machine(JVM).The core of the JVM implementation is the execution engine that executes the bytecodes.This can be implemented in four different ways:1.An interpreter is a software emulation of the virtualmachine.It uses a loop which fetches,decodes,andexecutes the bytecodes until the program ends.Dueto the software emulation,the Java interpreter has anadditional overhead and executes more instructionsthan just the bytecodes.2.A Just-in-time(JIT)compiler is an execution modelwhich tries to speed up the execution of interpretedprograms.It compiles a Java method into nativeinstructions on the fly and caches the nativesequence.On future references to the same method,the cached native method can be executed directlywithout the need for interpretation.JIT compilers.R.Radhakrishnan,L.K.John,and J.Rubio are with the Laboratory forComputer Architecture,Department of Electrical and Computer Engineer-ing,University of Texas at Austin,Austin,TX78712.E-mail:{radhakri,ljohn,jrubio}@..N.Vijaykrishnan and A.Sivasubramaniam are with the Department ofComputer Science and Engineering,220Pond Lab.,Pennsylvania State University,University Park,PA16802.E-mail:{vijay,anand}@..J.Sabarinathan is with the Motorola Somerset Design Center,6263McNeil Dr.#1112,Austin,TX78829.E-mail:jyotsna@.Manuscript received28Apr.2000;revised16Oct.2000;accepted31Oct.2000.For information on obtaining reprints of this article,please send e-mail to:tc@,and reference IEEECS Log Number112014.0018-9340/01/$10.00ß2001IEEEhave been released by many vendors,like IBM[2],Symantec[3],and piling duringprogram execution,however,inhibits aggressiveoptimizations because compilation must only incura small overhead.Another disadvantage of JITcompilers is the two to three times increase in theobject code,which becomes critical in memoryconstrained embedded systems.There are manyongoing projects in developing JIT compilers thataim to achieve C++-like performance,such asCACAO[4].3.Off-line bytecode compilers can be classified intotwo types:those that generate native code and thosethat generate an intermediate language like C.Harissa[5],TowerJ[6],and Toba[7]are compilersthat generate C code from bytecodes.The choice of Cas the target language permits the reuse of extensivecompilation technology available in different plat-forms to generate the native code.In bytecodecompilers that generate native code directly,likeNET[8]and Marmot[9],portability becomesextremely difficult.In general,only applications thatoperate in a homogeneous environment and thosethat undergo infrequent changes benefit from thistype of execution.4.A Java processor is an execution model thatimplements the JVM directly on silicon.It not onlyavoids the overhead of translation of the bytecodesto another processor's native language,but alsoprovides support for Java runtime features.It can beoptimized to deliver much better performance than ageneral purpose processor for Java applications byproviding special support for stack processing,multithreading,garbage collection,object addres-sing,and symbolic resolution.Java processors can becost-effective to design and deploy in a wide rangeof embedded applications,such as telephony andweb tops.The picoJava[10]processor from SunMicrosystems is an example of a Java processor.It is our belief that no one technique will be universally preferred/accepted over all platforms in the immediate future.Many previous studies[11],[12],[13],[10],[14]have focused on enhancing each of the bytecode execution techniques.On the other hand,a three-pronged attack at optimizing the runtime system of all techniques would be even more valuable.Many of the proposals for improve-ments with one technique may be applicable to the others as well.For instance,an improvement in the synchronization mechanism could be useful for an interpreted or JIT mode of execution.Proposals to improve the locality behavior of Java execution could be useful in the design of Java processors,as well as in the runtime environment on general purpose processors.Finally,this three-pronged strategy can also help us design environments that efficiently and seamlessly combine the different techniques wherever possible.A first step toward this three-pronged approach is to gain an understanding of the execution characteristics of different Java runtime systems for real applications.Such a study can help us evaluate the pros and cons of the different runtime systems(helping us selectively use what works best in a given environment),isolate architectural and runtime bottlenecks in the execution to identify the scope for potential improvement,and derive design enhance-ments that can improve performance in a given setting.This study embarks on this ambitious goal,specifically trying to answer the following questions:.Do the characteristics seen at the bytecode level favor any particular runtime implementation?Howcan we use the characteristics identified at thebytecode level to implement more efficient runtimeimplementations?.Where does the time go in a JIT-based execution(i.e., in translation to native code or in executing thetranslated code)?Can we use a hybrid JIT-inter-preter technique that can do even better?If so,whatis the best we can hope to save from such a hybridtechnique?.What are the execution characteristics when execut-ing Java programs(using an interpreter or JITcompiler)on general-purpose CPU(such as theSPARC)?Are these different from those for tradi-tional C/C++programs?Based on such a study,canwe suggest architectural support in the CPU(eithergeneral-purpose or a specialized Java processor)thatcan enhance Java executions?To our knowledge,there has been no prior effort that has extensively studied all these issues in a unified framework for Java programs.This paper sets out to answer some of the above questions using applications drawn from the SPECjvm98[15]benchmarks,available JVM implementa-tions such as JDK1.1.6[16]and Kaffe VM0.9.2[17],and simulation/profiling tools on the Shade[18]environment. All the experiments have been conducted on Sun Ultra-SPARC machines running SunOS5.6.1.1Related WorkStudies characterizing Java workloads and performance analysis of Java applications are becoming increasingly important and relevant as Java increases in popularity,both as a language and software development platform.A detailed characterization of the JVM workload for the UltraSparc platform was done in[19]by Barisone et al.The study included a bytecode profile of the SPECjvm98 benchmarks,characterizing the types of bytecodes present and its frequency distribution.In this paper,we start with such a study and extend it to characterize other metrics, such as locality and method sizes,as they impact the performance of the runtime environment very strongly. Barisone et e the profile information collected from the interpreter and JIT execution modes as an input to a mathematical model of a RISC architecture to suggest architectural support for Java workloads.Our study uses a detailed superscalar processor simulator and also includes studies on available parallelism to understand the support required in current and future wide-issue processors. Romer et al.[20]studied the performance of interpreters and concluded that no special hardware support is needed for increased performance.Hsieh et al.[21]studied the cache and branch performance of interpreted Java code,C/C++version of the Java code,and native code generated by Caffine (a bytecode to native code compiler)[22].They attribute the inefficient use of the microarchitectural resources by the interpreter as a significant performance penalty and suggest that an offline bytecode to native code translator is a more efficient Java execution model.Our work differs from these studies in two important ways.First,we include a JIT compiler in this study which is the most commonly used execution model presently.Second,the benchmarks used in our study are large real world applications,while the above-mentioned study uses microbenchmarks due to the unavailability of a Java benchmark suite at the time of their study.We see that the characteristics of the application used affects favor different execution modes and,therefore,the choice of benchmarks used is important.Other studies have explored possibilities of improving performance of the Java runtime system by understand-ing the bottlenecks in the runtime environment and ways to eliminate them.Some of these studies try to improve the performance through better synchronization mechan-isms [23],[24],[25],more efficient garbage collection techniques [26],and understanding the memory referen-cing behavior of Java applications [27],etc.Improving the runtime system,tuning the architecture to better execute Java workloads and better compiler/interpreter perfor-mance are all equally important to achieve efficient performance for Java applications.The rest of this paper is organized as follows:The next section gives details on the experimental platform.In Section 3,the bytecode characteristics of the SPECjvm98are presented.Section 4examines the relative performance of JIT and interpreter modes and explores the benefits of a hybrid strategy.Section 5investigates some of the questions raised earlier with respect to the CPU and cache architec-tures.Section 6collates the implications and inferences that can be drawn from this study.Finally,Section 7summarizes the contributions of this work and outlines directions for future research.2E XPERIMENTAL P LATFORMWe use the SPECjvm98benchmark suite to study the architectural implications of a Java runtime environment.The SPECjvm98benchmark suite consists of seven Java programs which represent different classes of Java applica-tions.The benchmark programs can be run using three different inputs,which are named s100,s10,and s1.Theseproblem sizes do not scale linearly,as the naming suggests.We use the s1input set to present the results in this paper and the effects of larger data sets,s10and s100,has also been investigated.The increased method reuse with larger data sets results in increased code locality,reduced time spent in compilation as compared to execution,and other such issues as can be expected.The benchmarks are run at the command line prompt and do not include graphics,AWT (graphical interfaces),or networking.A description of the benchmarks is given in Table 1.All benchmarks except mtrt are single-threaded.Java is used to build applications that span a wide range,which includes applets at the lower end to server-side applications on the high end.The observations cited in this paper hold for those subsets of applications which are similar to the SPECjvm98bench-marks when run with the dataset used in this study.Two popular JVM implementations have been used in this study:the Sun JDK 1.1.6[16]and Kaffe VM 0.9.2[17].Both these JVM implementations support the JIT and interpreted mode.Since the source code for the Kaffe VM compiler was available,we could instrument it to obtain the behavior of the translation routines for the JIT mode in detail.Some of the data presented in Sections 4and 5are obtained from the instrumented translate routines in Kaffee.The results using Sun's JDK are presented for the other sections and only differences,if any,from the KaffeVM environment are mentioned.The use of two runtime implementations also gives us more confidence in our results,filtering out any noise due to the implementation details.To capture architectural interactions,we have obtained traces using the Shade binary instrumentation tool [18]while running the benchmarks under different execution modes.Our cache simulations use the cachesim5simulators available in the Shade suite,while branch predictors have been developed in-house.The instruction level parallelism studies are performed utilizing a cycle-accurate superscalar processor simulator This simulator can be configured to a variety of out-of-order multiple issue configurations with desired cache and branch predictors.3C HARACTERISTICSAT THEB YTECODE L EVELWe characterize bytecode instruction mix,bytecode locality,method locality,etc.in order to understand the benchmarks at the bytecode level.The first characteristic we examine is the bytecode instruction mix of the JVM,which is a stack-oriented architecture.To simplify the discussion,weRADHAKRISHNAN ET AL.:JAVA RUNTIME SYSTEMS:CHARACTERIZATION ANDARCHITECTURAL IMPLICATIONS 133TABLE 1Description of the SPECjvm98Benchmarksclassify the instructions into different types based on their inherent functionality,as shown in Table 2.Table 3shows the resulting instruction mix for the SPECjvm98benchmark suite.The total bytecode count ranges from 2million for db to approximately a billion for compress .Most of the benchmarks show similar distribu-tions for the different instruction types.Load instructions outnumber the rest,accounting for 35.5percent of the total number of bytecodes executed on the average.Constant pool and method call bytecodes come next with average frequen-cies of 21percent and 11percent,respectively.From an architectural point of view,this implies that transferring data elements to and from the memory space allocated for local variables and the Java stack paring this with the benchmark 126.gcc from the SPEC CPU95suite,which has roughly 25percent of memory access operations when run on a SPARC V.9architecture,it can be seen that the JVM places greater stress on the memory system.Consequently,we expect that techniques such as instruction folding proposed in [28]for Java processors and instructioncombining proposed in [29]for JIT compilers can improve the overall performance of Java applications.The second characteristic we examine is the dynamic size of a method.1Invoking methods in Java is expensive as it requires the setting up of an execution environment and a new stack for each new method [1].Fig.1shows the method sizes for the different benchmarks.A trinodal distribution is observed,where most of the methods are either 1,9,or 26bytecodes long.This seems to be a characteristic of the runtime environment itself (and not of any particular application)and can be attributed to a frequently used library.However,the existence of single bytecode methods indicates the presence of wrapper methods to implement specific features of the Java language like private and protected methods or interfaces .These methods consist of a control transfer instruction which transfers control to an appropriate routine.Further analysis of the traces shows that a few unique bytecodes constitute the bulk of the dynamic bytecode134IEEE TRANSACTIONS ON COMPUTERS,VOL.50,NO.2,FEBRUARY 2001TABLE 2Classification ofBytecodesTABLE 3Dynamic Instruction Mix at the BytecodeLevel1.A java method is equivalent to a ªfunctionºor ªprocedureºin a procedural language like C.stream.In most benchmarks,fewer than 45distinct bytecodes constitute 90percent of the executed bytecodes and fewer than 33bytecodes constitute 80percent of the executed bytecodes (Table 4).It is observed that memory access and memory allocation-related bytecodes dominate the bytecode stream of all the benchmarks.This also suggests that if the instruction cache can hold the JVM interpreter code corresponding to these bytecodes (i.e.,all the cases of the switch statement in the interpreter loop),the cache performance will be better.Table 5presents the number of unique methods and the frequency of calls to those methods.The number of methods and the dynamic calls are obtained at runtime by dynamically profiling the application.Hence,only methods that execute at least once have been counted.Table 5also shows that the static size of the benchmarks remain constant across the different data sets (since the number of unique methods does not vary),although the dynamic instruction count increases for the bigger data sets (due to increased method calls).The number of unique calls has an impact on the number of indirect call sites present in the application.Looking at the three data sets,we see that there is very little difference in the number of methods across data sets.Another bytecode characteristic we look at is the method reuse factor for the different data sets.The method reuse factor can be defined as the ratio of method calls to number of methods visited at least once.It indicates the locality of methods.The method reuse factor is presented in Table 6.The performance benefits that can be obtained from using a JIT compiler are directly proportional to the method reuse factor since the cost of compilation is amortized over multiple calls in JIT execution.The higher number of method calls indicates that the method reuse in the benchmarks for larger data sets would be substantially more.This would then lead to better performance for the JITs (as observed in the next section).In Section 5,we show that the instruction count when the benchmarks are executed using a JIT compiler is much lower than when using an interpreter for the s100data set.Since there is higher method reuse in all benchmarks for the larger data sets,using a JIT results in better performance over an interpreter.The bytecode characteristics described in this section help in understanding some of the issues involved in the performance of the Java runtime system (presented in the remainder of the paper).4W HENORW HETHERTOT RANSLATEDynamic compilation has been popularly used [11],[30]to speed up Java executions.This approach avoids the costly interpretation of JVM bytecodes while sidestepping the issue of having to precompile all the routines that could ever be referenced (from both the feasibility and perfor-mance angles).Dynamic compilation techniques,however,pay the penalty of having the compilation/translation to native code falling in the critical path of program execution.Since this cost is expected to be high,it needs to be amortized over multiple executions of the translated code.Or else,performance can become worse than when the code is just interpreted.Knowing when to dynamically compile a method (using a JIT),or whether to compile at all,is extremely important for good performance.To our knowledge,there has not been any previous study that has examined this issue in depth in the context of Java programs,though thereRADHAKRISHNAN ETAL.:JAVA RUNTIME SYSTEMS:CHARACTERIZATION AND ARCHITECTURAL IMPLICATIONS 135Fig.1.Dynamic method size.TABLE 4Number of Distinct Bytecodes that Account for 80Percent,90Percent,and 100Percent of the Dynamic Instruction StreamTABLE 5Total Number ofMethod Calls (Dynamic)and Unique Methods for the Three Data Setshave been previous studies [13],[31],[12],[4]examining efficiency of the translation procedure and the translated code.Most of the currently available execution environ-ments,such as JDK 1.2[16]and Kaffe [17],employ limited heuristics to decide on when (or whether)to JIT.They typically translate a method on its first invocation,regardless of how long it takes to interpret/translate/execute the method and how many times the method is invoked.It is not clear if one could do better (with a smarter heuristic)than what many of these environments provide.We investigate these issues in this section using five SPECjvm98[15]benchmarks (together with a simple HelloWorld program 2)on the Kaffe environment.Fig.2shows the results for the different benchmarks.All execution times are normalized with respect to the execu-tion time taken by the JIT mode on Kaffe.On top of the JIT execution bar is given the ratio of the time taken by this mode to the time taken for interpreting the program using Kaffe VM.As expected (from the method reuse character-istics for the various benchmarks),we find that translating (JIT-ing)the invoked methods significantly outperforms interpreting the JVM bytecodes for the SPECjvm98.The first bar,which corresponds to execution time using the default JIT,is further broken down into two components,the total time taken to translate/compile the invoked methods and the time taken to execute these translated (native code)methods.The considered workloads span the spectrum,from those in which the translation times dominate,such as hello and db (because most of the methods are neither time consuming nor invoked numerous times),to those in which the native code execution dominates,such as compress and jack (where the cost of translation is amortized over numerous invocations).The JIT mode in Kaffe compiles a method to native code on its first invocation.We next investigate how well the smartest heuristic can do so that we compile only those methods that are time consuming (the translation/compila-tion cost is outweighed by the execution time)and interpret the remaining methods.This can tell us whether we should strive to develop a more intelligent selective compilation heuristic at all and,if so,what the performance benefit is that we can expect.Let us say that a method i takes s i time to interpret, i time to translate,and i i time to execute the translated code.Then,there exists a crossover point x i i a s i Ài i ,where it would be better to translate themethod if the number of times a method is invoked n i b x i and interpret it otherwise.We assume that an oracle supplies n i (the number of times a method is invoked)and x i (the ideal cut-off threshold for a method).If n i `x i ,we interpret all invocations of the method,and otherwise translate it on the very first invocation.The second bar in Fig.2for each application shows the performance with this oracle,which we shall call opt .It can be observed that there is very little difference between the naive heuristic used by Kaffe and opt for compress and jack since most of the time is spent in the execution of the actual code anyway (very little time in translation or interpretation).As the translation component gets larger (applications like db ,javac ,or hello ),the opt model suggests that some of the less time-consuming (or less frequently invoked)methods be inter-preted to lower the execution time.This results in a 10-15percent savings in execution time for these applica-tions.It is to be noted that the exact savings would definitely depend on the efficiency of the translation routines,the translated code execution and interpretation.The opt results give useful insights.Fig.2shows that,by improving the heuristic that is employed to decide on when/whether to JIT,one can at best hope to trim 10-15percent in the execution time.It must be observed that the 10-15percent gains observed can vary with the amount of method reuse and the degree of optimization that is used.For example,we observed that the translation time for the Kaffe JVM accounts for a smaller portion of overall execution time with larger data sets (7.5percent for the s10dataset (shown in Table 7)as opposed to the 32percent for the s1dataset).Hence,reducing the translation overhead will be of lesser importance when execution time dominates translation time.However,as more aggressive optimizations are used,the translation time can consume a significant portion of execution time for even larger datasets.For instance,the base configuration of the translator in IBM's Jalapeno VM [32]takes negligible translation time when using the s100data set for javac.However,with more aggressive optimizations,about 30percent of overall execution time is consumed in translation to ensure that the resulting code is executed much faster [32].Thus,there exists a trade-off between reducing the amount of time spent in optimizing the code and the amount of time spent in actually executing the optimized code.136IEEE TRANSACTIONS ON COMPUTERS,VOL.50,NO.2,FEBRUARY2001Fig.2.Dynamic compilation:How well can we do?2.While we do not make any major conclusions based on this simple program,it serves to observe the behavior of the JVM implementation while loading and resolving system classes during system initialization.TABLE 6Method Reuse Factor for the Different DataSets。
Infoprint 250 導入と計画の手引き 第 7 章ホスト
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黑莓手机所有软硬件错误代码中译参考
黑莓手机所有软硬件错误代码中译参考现在国内使用黑莓手机的玩家是越来越多了，但很多玩家在使用的过程中遇上了一些错误提示时不明白提示的内容。
下面小编就提供从网络上收集到的黑莓BlackBerry 手持设备所有软/硬件在使用过程中出现的错误提示代码的翻译参考资料及部分问题的解决办法。
下列表格将列出在BlackBerry手持设备上java虚拟机可能出现的错误代码和详细信息！101 Previous startup failed当jvm启动过程中，前一个启动的项目失败了，设备已经被重置。
这个错误表明jvm在启动时找到“启动进行中”这个标志位已经设置了，当前屏幕信息为：有意停止“系统继续重置”这个死循环，来纠正系统当前不正确的启动操作102 Invalid code in filesystem在文件系统中发现无效的代码。
手持设备的系统检查.cod文件的变动时，在一些.cod文件中检测到这个问题。
他肯可能是表明生成过程中发生了错误，即在cod文件中存在一个有问题的签名。
如果一些用户操作设备导致这个问题的发生，文件系统的代码被破坏，复位的周期将是连续循环的。
唯一的恢复方法是擦去设备并且恢复一个新的系统。
103 Cannot find starting address找不到启动的地址，用于启动系统的引导cod文件找不到。
这个错误表明一个用于引导系统的cod文件没有安装到设备上，或者格式不正确。
104 Uncaught:非预期：《java模块名》jvm诊断出一个非预期的java代码异常错误抛出，程序可以继续执行，或者手持设备可以用桌面管理器连是USB线安装一个程序调试器来查看这些错误信息。
事件日志里应该包含了异常错误的信息105 Example, DbRecSize( %d ) -> %d举例，DbRecSize( %d ) -> %d文件系统API已经为一种特定的操作返回一种错误状态码，他可能表明在jvm上存在一个无效的或者错误的文件系统106 Graphics system error图形系统错误，在设备的图形系统里一个错误发生并被检测到107 operator new() called在jvm里，操作new()回调一个c++类，该函数代码没有被正确的从VMRamObject 对象来继承，新操作符需要被正确的继承。
TMS320x28xx, 28xxx Enhanced Capture (ECAP) Module Reference Guide (Rev. A)
TMS320x28xx,28xxx Enhanced Capture(eCAP)ModuleReference GuideLiterature Number:SPRU807ANovember2004–Revised October20062SPRU807A–November2004–Revised October2006Submit Documentation FeedbackPreface (6)1Introduction (9)2Description (9)3Capture and APWM Operating Mode (10)4Capture Mode Description (12)4.1Event Prescaler (12)4.2Edge Polarity Select and Qualifier (13)4.3Continuous/One-Shot Control (13)4.432-Bit Counter and Phase Control (14)4.5CAP1-CAP4Registers (15)4.6Interrupt Control (15)4.7Shadow Load and Lockout Control (16)4.8APWM Mode Operation (17)5Capture Module-Control and Status Registers (18)6Register Mapping (26)7Application of the ECAP Module (27)7.1Example1-Absolute Time-Stamp Operation Rising Edge Trigger (28)7.2Example2-Absolute Time-Stamp Operation Rising and Falling Edge Trigger (30)7.3Example3-Time Difference(Delta)Operation Rising Edge Trigger (32)7.4Example4-Time Difference(Delta)Operation Rising and Falling Edge Trigger (34)8Application of the APWM Mode (36)8.1Example1-Simple PWM Generation(Independent Channel/s) (36)8.2Example2-Multi-channel PWM Generation With Synchronization (37)8.3Example3-Multi-channel PWM Generation With Phase Control (39)Appendix A Revision History (42)SPRU807A–November2004–Revised October2006Table of Contents3 Submit Documentation Feedback1Multiple eCAP Modules In A28x System (10)2Capture and APWM Modes of Operation (11)3Capture Function Diagram (12)4Event Prescale Control (13)5Prescale Function Waveforms (13)6Details of the Continuous/One-shot Block (14)7Details of the Counter and Synchronization Block (15)8Interrupts in eCAP Module (16)9PWM Waveform Details Of APWM Mode Operation (17)10Time-Stamp Counter Register(TSCTR) (18)11Counter Phase Control Register(CTRPHS) (18)12Capture-1Register(CAP1) (18)13Capture-2Register(CAP2) (18)14Capture-3Register(CAP3) (19)15Capture-4Register(CAP4) (19)16ECAP Control Register1(ECCTL1) (19)17ECAP Control Register2(ECCTL2) (21)18ECAP Interrupt Enable Register(ECEINT) (23)19ECAP Interrupt Flag Register(ECFLG) (24)20ECAP Interrupt Clear Register(ECCLR) (24)21ECAP Interrupt Forcing Register(ECFRC) (25)22Capture Sequence for Absolute Time-stamp and Rising Edge Detect (28)23Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect (30)24Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect (32)25Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect (34)26PWM Waveform Details of APWM Mode Operation (36)27Multichannel PWM Example Using4eCAP Modules (38)28Multi-phase(channel)Interleaved PWM Example Using3eCAP Modules (40)4List of Figures SPRU807A–November2004–Revised October2006Submit Documentation Feedback1Time-Stamp Counter Register(TSCTR)Field Descriptions (18)2Counter Phase Control Register(CTRPHS)Field Descriptions (18)3Capture-1Register(CAP1)Field Descriptions (18)4Capture-2Register(CAP2)Field Descriptions (19)5Capture-3Register(CAP3)Field Descriptions (19)6Capture-4Register(CAP4)Field Descriptions (19)7ECAP Control Register1(ECCTL1)Field Descriptions (19)8ECAP Control Register2(ECCTL2)Field Descriptions (21)9ECAP Interrupt Enable Register(ECEINT)Field Descriptions (23)10ECAP Interrupt Flag Register(ECFLG)Field Descriptions (24)11ECAP Interrupt Clear Register(ECCLR)Field Descriptions (25)12ECAP Interrupt Forcing Register(ECFRC)Field Descriptions (25)13Control and Status Register Set (26)A-1Changes Made in This Revision (42)SPRU807A–November2004–Revised October2006List of Tables5 Submit Documentation FeedbackPrefaceSPRU807A–November2004–Revised October2006The enhanced capture(eCAP)module is used in systems where accurate timing ofexternal events is important.This guide describes the module and how to use it.Related Documentation From Texas InstrumentsThe following documents describe the TMS320C28x and related support tools and can be downloaded from the TI website():Data Manuals—SPRS357:contains the pinout,signalF28044device.User's Guides—SPRU051:describes theSCI,modulessupport digital communications between the CPU and other asynchronous peripherals that use thestandard non-return-to-zero(NRZ)format.SPRU059:describes the SPI-a ofprogrammed length(one to sixteen bits)to be shifted into and out of the device at a programmedbit-transfer rate.SPRU074:in electrically noisy environments.SPRU430:describes the centralfixed-point digital signal processors(DSPs).It also describes emulation features available on these DSPs.SPRU513:—describes the assembly languagetools code),assembler directives,macros,common object file format,and symbolic debugging directives for the TMS320C28x device.SPRU514:describes the TMS320C28x™C/C++code and produces TMS320DSP assembly language source code for the TMS320C28x device.SPRU566:describes the peripheral referenceguidesSPRU608:—describes the simulator,the instruction set of the C28x™core.6Preface SPRU807A–November2004–Revised October2006Submit Documentation FeedbackRelated Documentation From Texas Instruments SPRU625:SPRU712:describes the(DSPs).SPRU716:SPRU721:—describes the featuresand TMS320x280xdigital signal processor(DSP).SPRU722:describes the purpose andIt also describes other contents of the device on-chip boot ROM and identifies where all of the information is located withinthat memory.SPRU790:encoder to get position,direction,and speed information from a rotating machine in highperformance motion and position control systems.It includes the module description and registers SPRU791:switch mode power supply control,UPS(uninterruptible power supplies),and other forms of powerconversionSPRU807:describes theSPRU924:describes theApplication Reports—SPRAA58:—describes differences between theTexas assist in application migration fromthe281x to the280x.While the main focus of this document is migration from281x to280x,usersconsidering migrating in the reverse direction(280x to281x)will also find this document useful.SPRA550:describes a scenario of a3.3-V-only motor controllerissue of interfacing between3.3V and5V exists.On-chip3.3-V analog-to-digital converter(ADC)versus5-V ADC is also discussed.Guidelines for component layout and printed circuit board(PCB)design that can reduce systemnoise and EMI effects are summarized.SPRA820:presents the methodology foronline code is provided thatcontains functions for implementing the overflow detection on both DSP/BIOS™andnon-DSP/BIOS applications.SPRA861:provides an easy way to use thean arbitrary device.This application report presents a sample implementation of a user-defined device driver.SPRA873:signal processor(DSP)and DRV592power amplifier.The DSP implements a digitalproportional-integral-derivative feedback controller using an integrated12-bit analog-to-digitalconverter to read the thermistor,and direct output of pulse-width-modulated waveforms to theH-bridge DRV592power amplifier.A complete description of the experimental system,along withsoftware and software operating instructions,is provided.SPRU807A–November2004–Revised October2006Read This First7 Submit Documentation Feedback Related Documentation From Texas InstrumentsSPRA876:contains several programmingmodes of operation to help you come up to speed quickly in programming the eCAN.All projects and CANalyzer configuration filesare included in the attached SPRA876.zip file.SPRA953:describes the traditional and new thermal metrics and will puttheir to system level junction temperature estimation.SPRA958:coverson-chip flash memory.Requirements for both DSP/BIOS™and non-DSP/BIOS projects arepresented.Example code projects are included.SPRA963:describes reliability data forSPRA989:describes a method for improving the absolutefound on the F2810/F2811/F2812devices.This application note is accompanied by an example program(ADCcalibration.zip)that executesfrom RAM on the F2812eZdsp.SPRA991:them to evaluate system alternatives more effectively.TrademarksTMS320C28x,C28x are trademarks of Texas Instruments.8Read This First SPRU807A–November2004–Revised October2006Submit Documentation Feedback1Introduction2DescriptionReference GuideSPRU807A–November 2004–Revised October 2006The enhanced Capture (eCAP)module is essential in systems where accurate timingof external events is important.This reference guide is applicable for the eCAP found on the TMS320x28xx andTMS320x28xxx family of processors.This includes all Flash-based,ROM-based,andRAM-based devices within the 280xx and 28xxx family.Uses for eCAP include:•Speed measurements of rotating machinery (e.g.,toothed sprockets sensed via Hall sensors)•Elapsed time measurements between position sensor pulses•Period and duty cycle measurements of pulse train signals•Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors The eCAP module described in this guide includes the following features:•32-bit time base with 10-nS time resolution with a 100-MHz system clock•4-event time-stamp registers (each 32bits)•Edge polarity selection for up to four sequenced time-stamp capture events•Interrupt on either of the four events•Single shot capture of up to four event time-stamps•Continuous mode capture of time-stamps in a four-deep circular buffer•Absolute time-stamp capture•Difference (Delta)mode time-stamp capture•All above resources dedicated to a single input pin•When not used in capture mode,the ECAP module can be configured as a single channel PWM output The eCAP module represents one complete capture channel that can be instantiated multiple times depending on the target device.In the context of this guide,one eCAP channel has the followingindependent key resources:•Dedicated input capture pin•32-bit time base (counter)•4x 32-bit time-stamp capture registers (CAP1-CAP4)•4-stage sequencer (Modulo4counter)that is synchronized to external events,ECAP pin rising/falling edges.•Independent edge polarity (rising/falling edge)selection for all 4events•Input capture signal prescaling (from 2-62)•One-shot compare register (2bits)to freeze captures after 1to 4time-stamp events•Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4)scheme •Interrupt capabilities on any of the 4capture eventsSPRU807A–November 2004–Revised October 2006Enhanced Capture (eCAP)Module 9Submit Documentation Feedback Capture and APWM Operating ModeMultiple identical eCAP modules can be contained in a280x system as shown in Figure1.The number of modules is device-dependent and is based on target application needs.Figure1.Multiple eCAP Modules In A28x System3Capture and APWM Operating ModeYou can use the eCAP module resources to implement a single-channel PWM generator(with32bitcapabilities)when it is not being used for input captures.The counter operates in count-up mode,providing a time-base for asymmetrical pulse width modulation(PWM)waveforms.The CAP1and CAP2 registers become the active period and compare registers,respectively,while CAP3and CAP4registers become the period and capture shadow registers,respectively.Figure2is a high-level view of both the capture and auxiliary pulse-width modulator(APWM)modes of10Enhanced Capture(eCAP)Module SPRU807A–November2004–Revised October2006Submit Documentation FeedbackCapture and APWM Operating Mode Figure2.Capture and APWM Modes of OperationA A single pin is shared between CAP and APWM functions.In capture mode,it is an input;in APWM mode,it is anoutput.B In APWM mode,writing any value to CAP1/CAP2active registers also writes the same value to the correspondingshadow registers CAP3/CAP4.This emulates immediate mode.Writing to the shadow registers CAP3/CAP4invokesthe shadow mode.4Capture Mode Description4.1Event PrescalerCapture Mode DescriptionFigure 3shows the various components that implement the capture function.Figure 3.Capture Function Diagram•An input capture signal (pulse train)can be prescaled by N =2-62(in multiples of 2)or can bypass the prescaler.This is useful when very high frequency signals are used as inputs.Figure 4shows a functional diagram and Figure 5shows the operation of the prescale function.12Enhanced Capture (eCAP)ModuleSPRU807A–November 2004–Revised October 2006ECAPx pin (from GPIO)PSoutECAPxPSout div 2PSout div 4PSout div 6PSout div 8PSout div 104.2Edge Polarity Select and Qualifier4.3Continuous/One-Shot ControlCapture Mode DescriptionFigure 4.Event Prescale ControlAWhen a prescale value of 1is chosen (i.e.ECCTL1[13:9]=0,0,0,0,0)the input capture signal by-passes the prescale logic completely.Figure 5.Prescale Function Waveforms•Four independent edge polarity (rising edge/falling edge)selection MUXes are used,one for each capture event.•Each edge (up to 4)is event qualified by the Modulo4sequencer.•The edge event is gated to its respective CAPx register by the Mod4counter.The CAPx register is loaded on the falling edge.•The Mod4(2bit)counter is incremented via edge qualified events (CEVT1-CEVT4).•The Mod4counter continues counting (0->1->2->3->0)and wraps around unless stopped.•A 2-bit stop register is used to compare the Mod4counter output,and when equal stops the Mod4counter and inhibits further loads of the CAP1-CAP4registers.This occurs during one-shot operation.CEVT1CEVT2CEVT3CEVT4ECCTL2[CONT/ONESHT]4.432-Bit Counter and Phase ControlCapture Mode DescriptionThe continuous/one-shot block controls the start/stop and reset (zero)functions of the Mod4counter via a mono-shot type of action that can be triggered by the stop-value comparator and re-armed via software control.Once armed,the eCAP module waits for 1-4(defined by stop-value)capture events before freezing both the Mod4counter and contents of CAP1-4registers (i.e.,time-stamps).Re-arming prepares the eCAP module for another capture sequence.Also re-arming clears (to zero)the Mod4counter and permits loading of CAP1-4registers again,providing the CAPLDEN bit is set.In continuous mode,the Mod4counter continues to run (0->1->2->3->0,the one-shot action is ignored,and capture values continue to be written to CAP1-4in a circular buffer sequence.Figure 6.Details of the Continuous/One-shot BlockThis counter provides the time-base for event captures,and is clocked via the system clock.A phase register is provided to achieve synchronization with other counters,via a hardware and software forced sync.This is useful in APWM mode when a phase offset between modules is needed.On any of the four event loads,an option to reset the 32-bit counter is given.This is useful for time difference capture.The 32-bit counter value is captured first,then it is reset to 0by any of the LD1-LD4signals.14Enhanced Capture (eCAP)ModuleSPRU807A–November 2004–Revised October 2006SYNCOSYNCECCTL2[SYNCI_EN]Delta−modeCTR−OVFCTR[31−0]4.5CAP1-CAP4Registers4.6Interrupt ControlCapture Mode DescriptionFigure 7.Details of the Counter and Synchronization BlockThese 32-bit registers are fed by the 32-bit counter timer bus,CTR[0-31]and are loaded (i.e.,capture a time-stamp)when their respective LD inputs are strobed.Loading of the capture registers can be inhibited via control bit CAPLDEN.During one-shot operation,this bit is cleared (loading is inhibited)automatically when a stop condition occurs,i.e.StopValue =Mod4.CAP1and CAP2registers become the active period and compare registers,respectively,in APWM mode.CAP3and CAP4registers become the respective shadow registers (APRD and ACMP)for CAP1and CAP2during APWM operation.An Interrupt can be generated on capture events (CEVT1-CEVT4,CTROVF)or APWM events (CTR =PRD,CTR =CMP).A counter overflow event (FFFFFFFF->00000000)is also provided as an interrupt source (CTROVF).The capture events are edge and sequencer qualified (i.e.,ordered in time)by the polarity select and Mod4gating,respectively.One of these events can be selected as the interrupt source (from the eCAPx module)going to the PIE.Seven interrupt events (CEVT1,CEVT2,CEVT3,CEVT4,CNTOVF,CTR=PRD,CTR=CMP)can be generated.The interrupt enable register (ECEINT)is used to enable/disable individual interrupt eventsources.The interrupt flag register (ECFLG)indicates if any interrupt event has been latched and contains the global interrupt flag bit (INT).An interrupt pulse is generated to the PIE only if any of the interrupt events are enabled,the flag bit is 1,and the INT flag bit is 0.The interrupt service routine must clear the global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR)before any other interrupt pulses are generated.You can force an interrupt event via the interrupt force register (ECFRC).This is useful for test purposes.4.7Shadow Load and Lockout ControlCapture Mode DescriptionNote:The CEVT1,CEVT2,CEVT3,CEVT4flags are only active in capture mode (ECCTL2[CAP/APWM ==0]).The CTR=PRD,CTR=CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM ==1]).CNTOVF flag is valid in both modes.Figure 8.Interrupts in eCAP ModuleIn capture mode,this logic inhibits (locks out)any shadow loading of CAP1or CAP2from APRD and ACMP registers,respectively.In APWM mode,shadow loading is active and two choices are permitted:•Immediate -APRD or ACMP are transferred to CAP1or CAP2immediately upon writing a new value.•On period equal,i.e.,CTR[31:0]=PRD[31:0]Enhanced Capture (eCAP)Module16SPRU807A–November 2004–Revised October 20064.8APWM Mode OperationAPRDACMPtimeCapture Mode DescriptionMain operating highlights of the APWM section:•The time-stamp counter bus is made available for comparison via 2digital (32-bit)comparators.•When CAP1/2registers are not used in capture mode,their contents can be used as Period and Compare values in APWM mode.•Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4).The shadow register contents are transferred over to CAP1/2registers either immediately upon a write,or on a CTR =PRD trigger.•In APWM mode,writing to CAP1/CAP2active registers will also write the same value to thecorresponding shadow registers CAP3/CAP4.This emulates immediate mode.Writing to the shadow registers CAP3/CAP4will invoke the shadow mode.•During initialization,you must write to the active registers for both period and compare.Thisautomatically copies the initial values into the shadow values.For subsequent compare updates,i.e.,during run-time,you only need to use the shadow registers.Figure 9.PWM Waveform Details Of APWM Mode OperationThe behavior of APWM active high mode (APWMPOL ==0)is as follows:CMP =0x00000000,output low for duration of period (0%duty)CMP =0x00000001,output high 1cycle CMP =0x00000002,output high 2cycles CMP =PERIOD,output high except for 1cycle (<100%duty)CMP =PERIOD+1,output high for complete period (100%duty)CMP >PERIOD+1,output high for complete periodThe behavior of APWM active low mode (APWMPOL ==1)is as follows:CMP =0x00000000,output high for duration of period (0%duty)CMP =0x00000001,output low 1cycle CMP =0x00000002,output low 2cycles CMP =PERIOD,output low except for 1cycle (<100%duty)CMP =PERIOD+1,output low for complete period (100%duty)CMP >PERIOD+1,output low for complete period Capture Module-Control and Status Registers5Capture Module-Control and Status RegistersFigure10.Time-Stamp Counter Register(TSCTR)R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable1.Time-Stamp Counter Register(TSCTR)Field Descriptions Bit(s)Field Description31:0TSCTR Active32-bit counter register that is used as the capture time-baseFigure11.Counter Phase Control Register(CTRPHS)R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable2.Counter Phase Control Register(CTRPHS)Field Descriptions Bit(s)Field Description31:0CTRPHS Counter phase value register that can be programmed for phase lag/lead.This register shadowsTSCTR and is loaded into TSCTR upon either a SYNCI event or S/W force via a control edto achieve phase control synchronization with respect to other eCAP and EPWM time-bases.Figure12.Capture-1Register(CAP1)R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable3.Capture-1Register(CAP1)Field DescriptionsBit(s)Field Description31:0CAP1This register can be loaded(written)by:)Time-Stamp(i.e.,counter value TSCTR)during a captureevent)Software-may be useful for test purposes/initialization)APRD shadow register(i.e.,CAP3)when used in APWM modeFigure13.Capture-2Register(CAP2)R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after reset18Enhanced Capture(eCAP)Module SPRU807A–November2004–Revised October2006Capture Module-Control and Status RegistersTable4.Capture-2Register(CAP2)Field DescriptionsBit(s)Field Description31:0CAP2This register can be loaded(written)by:•Time-Stamp(i.e.,counter value)during a capture event•Software-may be useful for test purposes•APRD shadow register(i.e.,CAP4)when used in APWM modeNote:In APWM mode,writing to CAP1/CAP2active registers also writes the same value to thecorresponding shadow registers CAP3/CAP4.This emulates immediate mode.Writing tothe shadow registers CAP3/CAP4invokes the shadow mode.Figure14.Capture-3Register(CAP3)R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable5.Capture-3Register(CAP3)Field DescriptionsBit(s)Field Description31:0CAP3In CMP mode,this is a time-stamp capture register.In APWM mode,this is the period shadow(APER)register.You update the PWM period value through this register.In this mode,CAP3(APRD)shadows CAP1.Figure15.Capture-4Register(CAP4)R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable6.Capture-4Register(CAP4)Field DescriptionsBit(s)Field Description31:0CAP4In CMP mode,this is a time-stamp capture register.In APWM mode,this is the compare shadow(ACMP)register.You update the PWM compare value via this register.In this mode,CAP4(ACMP)shadows CAP2.Figure16.ECAP Control Register1(ECCTL1)R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0 LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable7.ECAP Control Register1(ECCTL1)Field Descriptions Bit(s)Field Value Description15:14FREE/SOFT Emulation Control00TSCTR counter stops immediately on emulation suspend Capture Module-Control and Status RegistersTable7.ECAP Control Register1(ECCTL1)Field Descriptions(continued) Bit(s)Field Value Description01TSCTR counter runs until=01x TSCTR counter is unaffected by emulation suspend(Run Free)13:9PRESCALE Event Filter prescale select00000Divide by1(i.e,.no prescale,by-pass the prescaler)00001Divide by200010Divide by400011Divide by600100Divide by800101Divide by10...11110Divide by6011111Divide by628CAPLDEN Enable Loading of CAP1-4registers on a capture event0Disable CAP1-4register loads at capture event time.1Enable CAP1-4register loads at capture event time.7CTRRST4Counter Reset on Capture Event40Do not reset counter on Capture Event4(absolute time stamp operation)1Reset counter after Capture Event4time-stamp has been captured(used in difference mode operation)6CAP4POL Capture Event4Polarity select0Capture Event4triggered on a rising edge(RE)1Capture Event4triggered on a falling edge(FE)5CTRRST3Counter Reset on Capture Event30Do not reset counter on Capture Event3(absolute time stamp)1Reset counter after Event3time-stamp has been captured(used in difference mode operation)4CAP3POL Capture Event3Polarity select0Capture Event3triggered on a rising edge(RE)1Capture Event3triggered on a falling edge(FE)3CTRRST2Counter Reset on Capture Event20Do not reset counter on Capture Event2(absolute time stamp)1Reset counter after Event2time-stamp has been captured(used in difference mode operation)2CAP2POL Capture Event2Polarity select0Capture Event2triggered on a rising edge(RE)1Capture Event2triggered on a falling edge(FE)1CTRRST1Counter Reset on Capture Event10Do not reset counter on Capture Event1(absolute time stamp)1Reset counter after Event1time-stamp has been captured(used in difference modeoperation)0CAP1POL Capture Event1Polarity select0Capture Event1triggered on a rising edge(RE)1Capture Event1triggered on a falling edge(FE)20SPRU807A–November2004–Revised October2006 Enhanced Capture(eCAP)ModuleCapture Module-Control and Status RegistersFigure17.ECAP Control Register2(ECCTL2)R-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-1R/W-1R/W-0 LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable8.ECAP Control Register2(ECCTL2)Field DescriptionsBit(s)Field Description15:11Reserved Reserved10APWMPOL APWM output polarity select.This is applicable only in APWM operating mode0Output is active high(i.e.,Compare value defines high time)1Output is active low(i.e.,Compare value defines low time)9CAP/APWM CAP/APWM operating mode select0ECAP module operates in capture mode.This mode forces the followingconfiguration:•Inhibits TSCTR resets via CTR=PRD event•Inhibits shadow loads on CAP1and2registers•Permits user to enable CAP1-4register load•CAPx/APWMx pin operates as a capture input1ECAP module operates in APWM mode.This mode forces the followingconfiguration:•Resets TSCTR on CTR=PRD event(period boundary•Permits shadow loading on CAP1and2registers•Disables loading of time-stamps into CAP1-4registers•CAPx/APWMx pin operates as a APWM output8SWSYNC Software-forced Counter(TSCTR)Synchronizing.This provides a convenientsoftware method to synchronize some or all ECAP time bases.In APWM mode,the synchronizing can also be done via the CTR=PRD event.0Writing a zero has no effect.Reading always returns a zero1Writing a one forces a TSCTR shadow load of current ECAP module and anyECAP modules down-stream providing the SYNCO_SEL bits are0,0.After writinga1,this bit returns to a zero.Note:Selection CTR=PRD is meaningful only in APWM mode;however,you canchoose it in CAP mode if you find doing so useful.7:6SYNCO_SEL Sync-Out Select00Select sync-in event to be the sync-out signal(pass through)01Select CTR=PRD event to be the sync-out signal10Disable sync out signal11Disable sync out signal5SYNCI_EN Counter(TSCTR)Sync-In select mode0Disable sync-in option1Enable counter(TSCTR)to be loaded from TSCTR register upon either a SYNCIsignal or a S/W force event.4TSCTRSTOP Time Stamp(TSCTR)Counter Stop(freeze)Control0TSCTR stopped1TSCTR free-running3RE-ARM One-Shot Re-Arming Control,i.e.wait for stop trigger.Note:The re-arm function isvalid in one shot or continuous mode.0Has no effect(reading always returns a0)SPRU807A–November2004–Revised October2006Enhanced Capture(eCAP)Module21 Submit Documentation Feedback。
Moxa NPort Express DE-211快速安装指南（第七版，2011年5月）说明书
– 1 –– 2 – – 3 –P/N: 1802002112401NPort DE-211 Quick Installation GuideSeventh Edition, May 2011OverviewWelcome to Moxa’s NPort Express DE-211, a compact palm-sized data communication device that allows you to controlRS-232/422/485 serial devices over a TCP/IP based Ethernet network.Package ChecklistBefore installing the NPort Express DE-211, verify that the package contains the following items: • 1 NPort Express DE-211• NPort DE-211 quick installation guide • Documentation and software CD • Warranty cardOptional Accessories• NP21101: RS-232 cable: DB25 (M) to DB9 (F), 30 cm • NP21102: RS-232 cable: DB25 (M) to DB9 (M), 30 cm • NP21103: DB25 Terminal Block Kit for RS-422/485 •DK-35A: DIN-Rail Mounting Kit (35 mm)Notify your sales representative if any of the above items are missing or damaged.Hardware IntroductionThe NPort DE-211 device server has one female DB25 serial port. The four DIP switches located on the rear panel are used to select RS-232 COM mode, and one of four data modes: RS-232, RS-422, 4-wire RS-485, and 2-wire RS-485. See the “DIP Switch Settings and Explanation” section for details.Reset Button •Press the Reset button continuously for 3 sec to erase the password. After 3 sec, the Ready LED will flash on/off every half second. Release the reset button at this time to erase the password.•Press the Reset button continuously for 10 sec to load factory defaults. After 10 sec, the Ready LED will flash on/off every half second. Release the reset button at this time to load factory defaults.Hardware Installation ProcedurePlacement Options In addition to placing the DE-211 unit on a desktop or otherhorizontal surface, you may also make use of the DIN-Rail or Wall Mount options, as illustrated here.Wall MountDIN-RailDIP Switch Settings and ExplanationThe top panel of the DE-211 contains the following table, which describes how to set up the serial port using the four DIP switches located on DE-211’s rear panel.SW1 SerialConnection SW2 SW3 SW4Serial Interface Mode OFF OFF OFF RS-232 ONRS-232 ConsoleOFF ON ON RS-422ON OFF ON 4-wire RS-485 by RTS OFF Data CommON ON ON 4-wire RS-485 by ADDC ON OFF OFF 2-wire RS-485 by RTS ON ON OFF 2-wire RS-485 by ADDCSwitch SW1 controls the function of the serial port. Note that after changing the setting of SW1, the DE-211 will reboot to initialize the new setting. You must wait a few seconds for the green Ready light to blink off and then on again, indicating that the function of the serial port has been changed. Switches SW2, SW3, and SW4control the serial port’s data communication Interface Mode. (RTS stands for Ready To Send and ADDC stands for Automatic Data Direction Control.)Keep the following points in mind when setting the DIP switches: •To use the serial port as an RS-232 console connection, such as when using MOXA PComm Terminal Emulator or HyperTerminal, set SW1 to the ON position.•Some setup procedures can be carried out through a Telnet connection, in which case data is transmitted through the DE-211’s Ethernet port. However, you must set SW1 to the OFF position to establish a Telnet connection.owerPC– 4 – – 5 – – 6 –/supportThe Americas: +1-714-528-6777 (toll-free: 1-888-669-2872)Europe: +49-89-3 70 03 99-0 Asia-Pacific: +886-2-8919-1230China:+86-21-5258-9955 (toll-free: 800-820-5036)2011 Moxa Inc. All rights reserved.Software Installation InformationDetailed information about installing the software that comes with the DE-211 can be found on the NPort Documentation andSoftware CD in the “NPort Family Software Installation Guide”.Pin Assignments and Cable WiringFemale DB25 Connector PinoutsRS-232 WiringRS-422 WiringRS-485 WiringDB25 Terminal Block Kit (RS-422, RS-485-2W/4W)Environmental SpecificationsPower requirements 12 to 30 VDC150 mA (max.) at 12 V92 mA (max.) at 24 VOperating Temp. 0 to 55°C Ambient Relative Humidity 5 to 95% (non-condensing) Dimensions Including ears: 90.2 × 100.4 × 22 mm(3.55 × 3.95 × 0.87 in)Without ears: 67 × 100.4 × 22 mm (2.64 × 3.95 × 0.87 in)Surge Protection 15 KV ESD for the serial port Magnetic Isolation Protection 1.5 KV for the Ethernet port Regulatory Approvals FCC Class B, CE Class B, UL 60950-1, EN 60950-1。
Spring框架参考文档-5.0.0-中文完整版
Spring框架参考文档-5.0.0-中文完整版AuthorsRod Johnson , Juergen Hoeller , Keith Donald , Colin Sampaleanu , Rob Harrop , Thomas Risberg , Alef Arendsen , Darren Davison , Dmitriy Kopylenko , Mark Pollack , Thierry Templier , Erwin Vervaet , Portia Tung , Ben Hale , Adrian Colyer , John Lewis , Costin Leau , Mark Fisher , Sam Brannen , Ramnivas Laddad , Arjen Poutsma , Chris Beams , Tareq Abedrabbo , Andy Clement , Dave Syer , Oliver Gierke , Rossen Stoyanchev , Phillip Webb , Rob Winch , Brian Clozel , Stephane Nicoll , Sebastien Deleuze版本号：5.0.0.RELEASECopyright ? 2004-2016Copies of this document may be made for your own use and for distribution to others, provided that you do not charge any fee for such copies and further provided that each copy contains this Copyright Notice, whether distributed in print or electronically.文档官网：https://docs.spring.io/spring/docs/5.0.0.RELEASE/spring-framework-reference/index.html现在官网的5.0.0已经在2017年9月28日出了release版，为此翻译了5.0.0版本（从4.3.10升级到此版本，如果还在使用4.3.10版本，请看本人的前一个版本），翻译前后历时15天，十多次的修改和校对。
ML5239 Datasheet
If the number of connected battery cells is in the range of 5 to 10, input the I
same potential as the highest V pin (V5 to V10) of the battery connected to
O Battery cell 5 cell balance control output pin.
I Battery cell 5 low voltage input and Battery cell 4 high voltage input pins.
IC.
O Battery cell 9 cell balance control output pin.
Battery cell 9 low voltage input and Battery cell 8 high voltage input pins.
If the number of connected battery cells is in the range of 5 to 7, input the I
SPI communication speed = 500kHz (max) at four-stage configuration Multi-stage connection ICs: 16 (max)
Cell balance FET driving pin
Temperature sensor input: 4 channels
Operational temperature: -40 to 85°C
Package: 64-pin plastic TQFP
Note)
ABB Jokab Safety TSR20 安全开关说明书
[DE] Die komplette Originalbetriebsanleitung ist zu finden unter:[IT] Le istruzioni originali complete si trovano qui:[FR] La notice originale intégrale est disponible sur:[ES] La versión original de las instrucciones está disponible en:/jokabsafetyABB ABJokab SafetyVarlabergsvägen 11 SE-434 39 Kungsbacka Tel. +46 (0) 21-32 50 /jokabsafetyProduct descriptionTSR20 is a safety relay that has timer functions and configuration possibilities.InstallationWARNING: The product must be installed by a trained electrician following applicable safety regulations, standards and the machinedirective.CAUTION: The safety relay shall be attached on a 35 mm DIN railin an enclosure that has at least protection class IP54.CAUTION: Make sure there is at least 10 mm distance between the safety relay and other non-Sentry safety relay units to preventuncontrolled heating.CAUTION: Make sure there is at least 50 mm distance above and below the safety relay and other units for correct air flow in the venting holes of the safety relay.ConnectionWARNING: The safety relay and the sensor device for monitoring must be connected to SELV/PELV power supply.A)B)A. Two signals from T1/T2B. One signal from T1C. Two OSSD signalsD. Two signals from +24VDCE. One signal from +24VDCLED indicationCH1/MODE/CH2CommentActionoff/off/offThe safety relay is not powered.Check A1-A2 voltage and connections.green/green/greenCH1 and CH2 closed. Reset made and outputs activated.off/flash green/offCH1 and CH2 not close. A timer function is counting down while the safety relay remain activated.off/blue/offNo channels closed.Check CH1 and CH2.green/blue/green CH1 and CH2 closed, the safety relay wait for reset.Check reset wiring and reset circuit.red/fast flash red/redThe safety relay is in failsafe mode.Do a power cycling.Technical dataMeasurements Height/width/depth 120 mm/22.5 mm/120 mmPower supply Power supply type PELV/SELVOperating voltage +24 VDC +15 %, -20 %Consumption 8 WRequired fuse4 A gG (4 A according to UL 248)Relay output specification Maximum operating switching voltage250 VAC Overvoltage category IINO contactAC load (AC15, AC1), ratedoperational voltage, current 1/2/3 contact(s)250 VAC, 5 A/ 5 A/ 4.6 A DC load (DC13, DC1), ratedoperational voltage, current 1/2/3 contact(s)+24 VDC, 6 A/5.6 A/4.6 ARequired fuse 6.3 A gG, 1 kA short circuit protection (6 A according to UL248)NC contactAC load (AC15, AC1), rated operational voltage/current250 VAC/0.5 A DC load (DC13, DC1), rated operational voltage/current +24 VDC/2 ARequired fuse4 A gG, 1 kA short circuit protection (4 A according to UL248)Sensor interface specification Output T1 and T2Maximum output current (current limited internally to typical 70 mA)50 mA, nom 24 VDCInput R1 and R2Maximum OSSD pulse length 1.0 msInput/output (I/O) X4Maximum output current (currently limited internally to typical 70 mA)50 mA 2TLC010013M0201 Rev BWhile every effort has been taken to ensure the accuracy of information contained in this book and any associated promotional and information material ABB JokabSafety cannot accept responsibility for errors or omissions and reserves the right to make any improvements without notice. It is the users responsibility to ensure that this equipment is correctly designed, specified, installed, cared for and operated to meet all applicable local, national and international codes/regulations. Technical data in our book is correct to the level of accuracy of ABB Jokab Safety´s test procedures as verified by various international approved bodies. Other information (such as application examples, wiring diagrams, operation or use) is intended solely to illustrate the various uses of our products. ABB Jokab Safety does not quarantee or imply that the product when used in accordance with such examples in a particular environment will fulfil any particular safety requirement and does not assume any responsibility or liability for actual use of the product based on the examples given.[DE] Die komplette Originalbetriebsanleitung ist zu finden unter:[IT] Le istruzioni originali complete si trovano qui:[FR] La notice originale intégrale est disponible sur:[ES] La versión original de las instrucciones está disponible en:/jokabsafetyConnection block and wire properties Maximum screw torque 0.8 NmSolid conductor, minimum 1 x 24 AWG (0.2 mm 2), 2 x 24 AWG (0.2 mm 2)Solid conductor, maximum 1 x 12 AWG (3.31 mm 2), 2 x 16 AWG (1.31 mm 2)Conductor with crimp sleeve, minimum1 x 24 AWG (0.2 mm 2), 2 x 24 AWG (0.2 mm 2)Conductor with crimp sleeve, maximum 1 x 12 AWG (3.31 mm 2), 2 x 16 AWG (1.31 mm 2)Wire strip length6-7 mmMaximum response time Delay at power on1.5 s Response time at activation automatic reset/manual reset 50 ms/50ms Response time at deactivation 20 ms Electrical operations life time Load Σlth² ≤ 64, AC1, AC15160 000 operations Load Σlth² ≤ 64, DC1, DC13100 000 operations Mechanical operations lifetime 107 operations Environmental data Protection class, safety relay IP20Protection class, enclosureAt least IP54Ambient temperature range foroperation within specified operation range-10°C – +65°C Humidity range for operation25 % ≤ Rh ≤ 90 %, non-condensing and without icingSuitable for use at ≤ 2000 metres above sea level.Standard compliance and approvals Functional safety standard complianceEN 61508-1:2010, up to SIL3 EN ISO 13849-1:2008, up to PLe/Cat.4EN 62061:2005, up to SILCL3 EN 61511-1:2003 IEC 60947-5-1ApprovalsCE, TÜV SÜD, cULus Declaration of conformityCan be found at:/jokabsafety Information for use in USA/Canada Intended use Applications according to NFPA 79Power sourceA suitable isolating source in conjunction with a fuse in accordance with UL 248FuseThe fuse shall be rated max. 4 A and be installed in the +24 VDC power supply to the device in order to limit the available current.MaintenanceWARNING: The safety functions and mechanics shall be testedevery year to confirm that the safety functions work properly.WARNING: Repair and exchange of parts of the safety relay is not permitted since it may accidentally cause permanent damage to the product, imparing safety of the device which in turn could lead to serious injury to personnel. In case of breakdown or damage to the product contact ABB Jokab safety to replace the safety relay with a similar product.。
05SFD10
05SFD10IntroductionThe 05SFD10 is a high-performance electronic device designed specifically for use in the telecommunications industry. This document provides an overview of the device, its key features, and its applications. It also includes information on how to set up and maintain the 05SFD10 for optimal performance.Key FeaturesThe 05SFD10 offers several key features that make it a top choice for telecommunications professionals:1.High Speed: The device is equipped with advancedcircuitry that enables high-speed data transfer, ensuringseamless communication between network components.2.Reliability: With robust construction and top-quality components, the 05SFD10 delivers reliableperformance even in challenging environments. It isdesigned to withstand extreme temperatures, humidity,and other factors that could potentially affect its operation.3.Scalability: The device is highly scalable, making itsuitable for various network sizes and configurations. It can easily be integrated with existing systems and expanded as needed without significant disruptions to the network.4.Secure Connections: The 05SFD10 incorporatesadvanced encryption technologies to ensure secure datatransmission. This helps to protect sensitive information from potential threats and unauthorized access.5.Easy Installation and Configuration: Setting upthe 05SFD10 is a straightforward process, thanks to itsuser-friendly interface and intuitive design. It also offerscomprehensive configuration options to meet specificnetwork requirements.6.Remote Management: The device supports remotemanagement, allowing network administrators to monitor and control its operation from a central location. Thisfeature simplifies troubleshooting and maintenance tasks, saving time and effort.ApplicationsThe 05SFD10 is widely used in various applications within the telecommunications industry. Some of the key applications include:1.Data Centers: The device is frequently used in datacenters to facilitate high-speed data transmission between servers, storage devices, and networking equipment.2.Telecom Networks: The 05SFD10 is an essentialcomponent in telecom networks, enabling seamlesscommunication between different parts of the networkinfrastructure, such as routers, switches, and access points.3.Internet Service Providers: ISPs often rely on the05SFD10 to deliver high-speed internet connectivity totheir customers. The device ensures reliable and securedata transfer, essential for providing a satisfactory userexperience.4.Enterprises: Large enterprises with extensiveinternal networks benefit from the scalability andperformance of the 05SFD10. It helps to ensure smoothcommunication between various departments and branch offices.Setup and MaintenanceTo ensure optimal performance and longevity of the05SFD10, it is essential to follow proper setup and maintenance procedures. Here are some guidelines:1.Installation: The device should be installed in awell-ventilated area away from sources of heat, moisture, and electromagnetic interference. It should be securelymounted to prevent movement or accidental damage.2.Power Requirements: Ensure that the device isconnected to a stable power source that meets the specified voltage and current requirements. Power surges andfluctuations can damage the device and affect itsperformance.3.Regular Inspections: Perform regular visualinspections of the device to check for any physical damage or anomalies. Look for loose wires, damaged connectors, or signs of overheating. If any issues are identified, contact the manufacturer or authorized service center for assistance.4.Firmware Updates: Stay up to date with the latestfirmware releases for the 05SFD10. Firmware updatesoften include performance enhancements, bug fixes, andsecurity patches. Follow the manufact urer’s instructions for installing firmware updates.5.Cleaning: Keep the device clean and free from dustand debris. Use a soft, lint-free cloth to wipe the casing and connectors. Avoid using harsh chemicals or abrasivematerials that could damage the device.6.Troubleshooting: In case of any issues orperformance problems, refer to the troubleshooting guide provided by the manufacturer. Follow the suggested steps to identify and resolve the problem. If necessary, contacttechnical support for additional assistance.ConclusionThe 05SFD10 is a versatile and reliable device that plays a crucial role in the telecommunications industry. Its high-speed data transfer capabilities, scalability, and advanced security features make it an ideal choice for various applications. By following the recommended setup and maintenance procedures, users can ensure optimal performance and longevity of the device.。
HPE MEOS NAS 产品说明书
Photo courtesy MEOS™ NAS is fully compatible with MEOS™ Capture and MEOS™ Polar. Data can also be provided from other systems supporting (S)FTP.When arriving at MEOS™ NAS, the data files will be stored in catalogs corre sponding to file name s. Catalogs are created automatically as needed. Data files are by default under automatic storage management.The NAS storage is maintained automatically by the MEOS™ NAS:• Files older than a configurable age will be deleted (hard links removed) per FIFO scheme• The oldest files will be deleted when storage capacity limit is reachedStored data files can be retrieved by external clients using SLE (Offline RCF/RAF) per mission and time, or interactively using the embedded GUI (Graphical User Interface). Data files can also be retrieved via FTP.Re-distribution of particular ISP files can be done by manual selection of ISP files in the MEOS™ NAS GUI.MEOS™ NAS supports monitoring and control through a well-defined, socket based API, as well as through the embedded GUI. MEOS™ NAS will also generate reports upon data arrival and extraction.To ensure maximum reliability, MEOS™ NAS uses disks with RAID technology for data redundancy and dual power supplies. Cooling fan status and temperatures are monitored.This product is typically use d in ground systems requiring high availability and high reliability.MEOS™ NAS is MEOS™ Connect Ready for seamless integration under KSPT’s overall monitoring and control systems.MEOS™ NAS is a data storage accessible from the network. It provides scalable data storage and automatic data storage management, FTP based data input and output, and data distribution via the Space Link Extension (SLE) protocol. This product can also be used as an online rate buffer.© K S G S - M E O S -P A -K S P T -N A S -1672, I s s u e /r e v i s i o n 2/1, J a n u a r y 2021FEATURES• Diskbased and no consumables • Scalable data storage • VM or dedicated HW• Ideal for station cache • Input:Specifications subject to change without any further notice.MEOS™ is a registered trademark of Kongsberg Defence & Aerospace AS - in Norway and other countriesKONGSBERGSPACE GROUND SYSTEMSTelephone: +47 77 66 08 00E-mailsales:*********************spacetec.noMEOS™ NAS interfaces: • IP inThe MEOS™ NAS receives the real-time data through the ‘IP in’ interfaces, as ISPsand / or VCDUs. The data received is stored to file in the Online storage. •IP OutThe data from an ‘IP in’ interface is forwarded to the ‘IP out’ interface and distributed •(S)FTP(S) inCADU / VCDU / ISP data files are received via FTP / SFTP / FTPS and stored in the online storage•(S)FTP(S) outCADU / VCDU / ISP data files are sent via FTP / SFTP / FTPSSpace Link Extention (SLE) SLE support includes:• RAF (Return All Frames)• RCF (Return Channel Frames)• UIB (User Initiated Bind):- Data pull from an external system • PIB (Provider Initiated Bind):- Data push to an external systemMEOS™ NAS Hardware*• The MEOS™ NAS consists of the followinghardware: - HPE server- Disk Array Configurable 15-500 TB in one unit.• The MEOS™ NAS is configured with RAID6.• The storage capacity of the MEOS™ NAS can beincreased if needed, by adding additional disk storage units.• The online storage is a rolling archive,oldest files will be rolled out according to a configurable disk usage limit.* Available also as VM。
persistence的用法
persistence的用法一级标题：介绍Persistence概念和重要性在计算机科学中，持久化（Persistence）是指将数据存储在持久存储介质上，以便稍后检索和使用。
持久化对于各种应用程序非常重要，尤其是在需要长期保存数据、保护数据免受系统故障或停电影响的情况下。
通过持久化，我们可以确保数据的安全和可靠性，并为用户提供无缝的体验。
二级标题：数据库持久化数据库持久化是最常见和广泛使用的一种情况。
数据库是一个结构化存储数据的集合，可以实现对数据的高效检索、修改和删除操作。
当应用程序需求需要长期保存大量数据或处理复杂查询时，数据库的使用尤为突出。
通过在磁盘上创建表，并将数据存储在这些表中，应用程序可以随时访问并利用这些数据。
传统关系型数据库如MySQL和Oracle通常采用事务模型来实现持久化。
事务是一系列操作单元组成的逻辑工作单位，它要么全部执行成功并永久保存结果，要么完全不执行以保证一致性。
支持事务特性使得数据库能够实现高度可靠且可恢复的持久化。
近年来，越来越多的应用程序开始采用NoSQL数据库。
与传统关系型数据库不同，NoSQL数据库更加弹性、可扩展，并且通常可以处理大规模数据集。
NoSQL数据库的一种持久化方法是将数据保存在分布式文件系统或键值存储中。
持久化提供了对于海量、支撑高负载的数据访问的必要基础。
二级标题：文件系统持久化除了使用数据库之外，应用程序还可以通过文件系统进行持久化。
文件系统将数据组织为文件和目录的形式，并以二进制或文本格式存储在磁盘上。
这种方式使得用户可以直接通过文件浏览器或命令行接口操作数据。
在文件系统持久化中，开发人员可以利用标准的I/O操作读取和写入数据。
无论是保存配置信息、日志记录还是用户生成的内容，使用文件系统进行持久化提供了灵活性和可维护性。
针对不同类型的应用场景，常见的文件格式包括文本（如JSON、XML）、二进制（如图片、视频）以及特定领域相关的格式（如CSV）。
k8s restartpolicy 默认值
k8s restartpolicy 默认值Kubernetes（简称K8s）是为容器化的应用程序提供自动部署、扩展和管理的开源容器编排工具。
在K8s集群中，我们可以通过Pod来部署应用程序。
Pod是Kubernetes的最小单位，包含一个或多个容器。
在Pod的定义中，我们可以定义重启策略来指定当容器异常终止时如何处理。
本文将介绍K8s的重启策略，以及其默认值。
1. 重启策略Kubernetes中的重启策略定义了容器异常终止后该如何处理。
具体包括以下三种策略：- Always: 总是重启容器。
- OnFailure：在容器失败时自动重启容器。
如果容器成功运行就不会重启。
- Never：从不重启容器。
即使容器失败，也会保持它的状态。
我们可以在Pod的定义文件中通过在spec.containers[].restartPolicy字段中指定相应的策略。
2. 默认值在Kubernetes中，Pod的重启策略默认为Always。
这意味着，在任何情况下，容器出现异常终止都会被重启。
这个默认值对于大多数应用程序是合理的，因为容器异常终止通常意味着应用程序出现了问题，需要重新启动。
当然，在某些情况下，重启策略需要手动修改。
例如，在运行有状态应用程序时，如果出现异常情况，需要手动处理数据恢复，并且不能自动重启容器。
在这种情况下，我们需要将重启策略设置为Never。
3. 修改重启策略要修改Pod的重启策略，可以编辑Pod的定义文件，找到spec.containers[].restartPolicy字段，将其修改为需要的值。
如下是一个使用OnFailure策略的Pod示例：apiVersion: v1kind: Podmetadata:name: example-podspec:containers:- name: example-containerimage: nginxrestartPolicy: OnFailure4. 总结本文介绍了Kubernetes的重启策略，以及其默认值和修改方法。
persistentprerun的用法 cobra -回复
persistentprerun的用法cobra -回复persistentprerun的用法是指在cobra命令行工具中，在执行root.PersistentPreRun函数之前会先运行子命令的PersistentPreRun函数。
本文将为您详细介绍persistentprerun的用法，以及一步一步回答与其相关的问题。
一、什么是persistentprerun？persistentprerun是cobra命令行工具提供的一个特性。
当父命令和子命令都定义了PersistentPreRun函数时，执行子命令时会先运行子命令的PersistentPreRun函数，然后再运行父命令的PersistentPreRun函数。
这种机制使得在执行子命令之前能够先进行一些预处理操作，例如初始化某些参数、验证用户权限、打印日志等。
二、如何使用persistentprerun？使用persistentprerun需要定义一个继承自mand的自定义命令结构体，并在其中定义PersistentPreRun函数。
下面是使用persistentprerun的一些具体步骤：步骤一：导入cobra包和其他所需的包首先，要在Go源代码中导入所需的包，其中包括"github/spf13/cobra"。
goimport ("github/spf13/cobra")步骤二：定义自定义命令结构体接下来，在Go源代码中定义一个继承自mand的自定义命令结构体，并在其中定义PersistentPreRun函数。
PersistentPreRun函数的签名为：gofunc(cmd *mand, args []string)在PersistentPreRun函数中，可以添加任何在执行子命令之前需要进行的逻辑。
例如，可以初始化某些参数、验证用户权限、打印日志等。
gotype rootCmd struct {...}func (r *rootCmd) PersistentPreRun(cmd *mand, args []string) {在执行子命令之前执行的逻辑例如，初始化某些参数、验证用户权限、打印日志等fmt.Println("Running PersistentPreRun for root command") }func execute() error {root := &rootCmd{}...rootCmd.PersistentPreRun = root.PersistentPreRun...return rootCmd.Execute()}步骤三：定义子命令在自定义命令结构体中，还可以定义子命令。
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<persistenceFactory> <journalPersistenceAdapterFactory journalLogFiles="5" dataDirectory="amq-data" dataSource="#mysql-ds" /> </persistenceFactory>
开源力量，帮助你成功使用开源技术
开源力量，帮助你成功使用开源技术
Persistence(KahaDB )
/kahadb.html
开源力量，帮助你成功使用开源技术
Persistence(KahaDB )
Concurrent Store and Dispatch--SlowConsumers
开源力量，帮助你成功使用开源技术
Persistence(Journal )
• Journal
• Transactional Message Store • Reliable – and x10 faster than just JDBC • Applicable for shared nothing Master/Slave
Persistence
开源力量，帮助你成功使用开源技术
Overview
• This chapter covers the following areas
– Persistence
开源力量，帮助你成功使用开源技术
Persistence
• Message Storage Options
• • • • KahaDB AMQStore Journal JDBC
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Persistence(KahaDB )
• The KahaDB message store is an embedded Lightweight Non-Relational Database • It is an embeddable, transactional message store that is fast and reliable.It uses a transactional journal to store message data and a B-tree index to store message locations for quick retrieval.
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Persistence(KahaDB )
• Messages are stored in filebased data logs. • The metadata cache is an in-memory cache consisting mainly of destinations and message references. • The metadata store contains the complete broker metadata, consisting mainly of a B-tree index giving the message locations in the data logs.
Exercises 4
• The exercises cover
– kahaDB – AMQStore – Journal – JDBC
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Summary • KahaDB （default message store）
AMQStore Journal JDBC
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Persistence(KahaDB )
<persistenceAdapter> <amq:kahaDB directory="kahadb-data" enableIndexWriteAsync="true"> </amq:kahaDB> </persistenceAdapter>
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Persistence(AMQ Store )
<persistenceAdapter> <amqPersistenceAdapter brokerName="amq-broker" directory="amq-data" maxFileLength="50b" directoryArchive="dir-arc" archiveDataLogs="true" /> </persistenceAdapter>
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Persistence(JDBC)
• JDBC
• • • • • • • • • • • Apache Derby Axion DB2 HSQL Informix MaxDB MySQL Oracle Postgresql SQLServer Sybase
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Persistence(JDBC)
<persistenceAdapter> <jdbcPersistenceAdapter dataSource="#mysql-ds" /> </persistenceAdapter> <bean id="mysql-ds" class="mons.dbcp.BasicDataSource" destroy-method="close"> <property name="driverClassName" value="com.mysql.jdbc.Driver"/> <property name="url" value="jdbc:mysql://localhost:3307/amq?relaxAutoCommit=true"/> <property name="username" value="root"/> <property name="password" value="mysql"/> <property name="maxActive" value="200"/> <property name="poolPreparedStatements" value="true"/> </bean>
• Transactional Message Store • Extremely fast designed for messaging • Messages always written to a Journal • References to Message held in persistent indexes
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Persistence(KahaDB )
Concurrent Store and Dispatch--FastConsumers
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Persistence(AMQ Store )
• AMQ Store - the default store for ActiveMQ