FM25L256铁电存储器数据手册pdf

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铁电存储器在仪表中的应用

摘要：FRAM是一种新型存贮器，最大特点是可以随总线速度无限次的擦写，而且功耗低。

FRAM 性能优越于EEPROMAT24C256。

关键词：存贮器；FM24C256；AT24C256；EEPROM一．概述：FRAM是最近几年由RAMTRON公司研制的新型存贮器，它的核心技术是铁电晶体材料，拥有随即存取记忆体和非易失性存贮产品的特性。

FM24C256是一种铁电存贮器（FRAM）,容量为256KBIT存贮器，它和AT24C256容量等同，总线结构兼容，但FM24C256的性能指标远大于AT24C256。

在存贮器领域中，FM24C256应用逐渐被推广和认可，尤其是大容量存贮器，它的优良特性远高于同等容量的EEPROM。

在电子式电能表行业中，数据安全保存是最重要的。

随着电子表功能的发展，保存的数据量越来越大，这就需要大容量的存储器，而大容量的EEPROM性能指标不是很高，尤其是擦写次数和速度影响电能表自身的质量。

FM24C256在电能表中的使用，会提高电能表的数据安全存贮特性。

二．铁电存贮器（FRAM）FM24C256的特性：传统半导体记忆体有两大体系：易失性记忆体（volatilememory）和非易失性记忆体（non-volatilememory）。

易失性记忆体像SRAM和DRAM在没有电源的情况下都不能保存数据。

但这种存贮器拥有高性能、易用等优点。

非易失性记忆体像EPROM，EEPROM和FLASH能在断电后仍保存数据。

但由于所有这些记忆体均起源自ROM技术，所以不难想象得到他们都有不易写入的缺点：写入缓慢、读写次数低、写入时工耗大等。

FM24C256是一个256Kbit的FRAM，总线频率最高可达1MHz，10亿次以上的读写次数，工耗低。

与典型的EEPROMAT24C256相比较，FM24C256可跟随总线速度写入，无须等待时间，而AT24C256必须等待几毫秒（ms）才能进行下一步写操作。

FM24C256可读写10亿次以上，几乎无限次读写。

fm25256

This is a product in the pre-production phase of development. Device Ramtron International Corporationcharacterization is complete and Ramtron does not expect to change the 1850 Ramtron Drive, Colorado Springs, CO 80921FM25256256Kb FRAM Serial 5V MemoryFeatures256K bit Ferroelectric Nonvolatile RAM • Organized as 32,768 x 8 bits • Unlimited Read/Write Cycles • 10 Year Data Retention • NoDelay™ Writes• Advanced High-Reliability Ferroelectric ProcessVery Fast Serial Peripheral Interface - SPI • Up to 25 MHz Frequency• Direct Hardware Replacement for EEPROM • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)Write Protection Scheme • Hardware Protection • Software ProtectionWide Operating Range• Wide Voltage Operation 4.0V – 5.5VIndustry Standard Configurations• Industrial Temperature -40°C to +85°C •8-pin SOIC (-S)• “Green” 8-pin SOIC (-G)DescriptionThe FM25256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.Unlike serial EEPROMs, the FM25256 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The next bus cycle may start immediately. In addition, the product offers virtually unlimited write endurance. Also, FRAM exhibits much lower power consumption than EEPROM.These capabilities make the FM25256 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss.The FM25256 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25256 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C.Pin ConfigurationPin Name Function/CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage (4.0 to 5.5V) VSS GroundOrdering InformationFM25256-S 8-pin SOIC FM25256-G “Green” 8-pin SOICFigure 1. Block DiagramPin DescriptionsPin Name I/O Description/CS Input Chip Select: This active low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. Whenlow, the device internally activates the SCK signal. A falling edge on /CS must occurprior to every op-code.SCK Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, theclock frequency may be any value between 0 and 25 MHz and may be interrupted atany time./HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The deviceignores any transition on SCK or /CS. All transitions on /HOLD must occur whileSCK is low./WP Input Write Protect: This active low pin prevents write operations to the status register only.A complete explanation of write protection is provided on pages 6 and 7.SI Input Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a validlogic level to meet I DD specifications.* SI may be connected to SO for a single pin data interface.SO Output Serial Output: This is the data output pin. It is driven during a read and remains tri-stated at all other times including when /HOLD is low. Data transitions are driven onthe falling edge of the serial clock.* SO may be connected to SI for a single pin data interface.VDD Supply Power Supply (4.0V to 5.5V)GroundVSS SupplyOverviewThe FM25256 is a serial FRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25256 and a serial EEPROM with the same pinout is the FRAM’s superior write performance and power consumption. Memory ArchitectureWhen accessing the FM25256, the user addresses 32K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two-byte address. The upper bit of the address range is a “don’t care” value. The complete address of 15-bits specifies each byte address uniquely.Most functions of the FM25256 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25256 due to its fast write cycle and high endurance as compared to EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle.Note that the FM25256 contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active.Serial Peripheral Interface – SPI BusThe FM25256 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 25 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25256 operates in SPI Mode 0 and 3.The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25256 devices with a microcontroller that has a dedicated SPI port, as Figure 2 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25256 device.For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 3 shows a configuration that uses only three pins.Protocol OverviewThe SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25256 will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25256 supports only modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25256 on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge.The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the WREN and WRDI op-codes are commands with no subsequent data transfer.Important: The /CS must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.SS : Slave SelectFigure 2. System Configuration with SPI portFigure 3. System Configuration without SPI portSPI Mode 0: CPOL=0, CPHA=0SPI Mode 3: CPOL=1, CPHA=1Figure 4. SPI Modes 0 & 3Power Up to First AccessThe FM25256 is not accessible for a period of time (10 ms) after power up. Users must comply with the timing parameter t PU , which is the minimum time from V DD (min) to the first /CS low.Data TransferAll data transfers to and from the FM25256 occur in 8-bit groups. They are synchronized to the clock signal (SCK), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of SCK. Outputs are driven from the falling edge of SCK.Command StructureThere are six commands called op-codes that can be issued by the bus master to the FM25256. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the status register. The third group includes commands for memory transactions followed by address and one or more bytes of data.Table 1. Op-code Commands Name Description Op-codeWREN Set Write Enable Latch00000110b WRDIWrite Disable 0000 0100b RDSRRead Status Register 0000 0101b WRSRWrite Status Register 0000 0001b READRead Memory Data 0000 0011b WRITE Write Memory Data 0000 0010bWREN - Set Write Enable LatchThe FM25256 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory.Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no effect on the state of this bit. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 illustrates the WREN command bus configuration.WRDI - Write DisableThe WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration.Hi-Z0 1 2 3 4 5 6 7CSSCKSI SOFigure 5. WREN Bus ConfigurationCSSCKSI SO0 1 2 3 4 5 6 7Figure 6. WRDI Bus ConfigurationRDSR - Read Status RegisterThe RDSR command allows the bus master to verify the contents of the Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR op-code, the FM25256 will return one byte with the contents of the Status register. The Status register is described in detail in a later section. WRSR – Write Status RegisterThe WRSR command allows the user to select certain write protection features by writing a byte to the Status register. Prior to issuing a WRSR command, the /WP pin must be high or inactive. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch.Figure 7. RDSR Bus ConfigurationFigure 8. WRSR Bus ConfigurationStatus Register & Write ProtectionThe write protection features of the FM25256 are multi-tiered. Taking the /WP pin to a logic low state is the hardware write protect function. All write operations are blocked when /WP is low. To write the memory with /WP high, a WREN op-code must first be issued. Assuming that writes are enabled using WREN and by /WP, writes to memory are controlled by the Status register. As described above, writes to the status register are performed using the WRSR command and subject to the /WP pin. The Status register is organized as follows.Table 2. Status RegisterBit 76 5 4 321 0NameWPEN 0 0 0 BP1BP0 WEL 0Bits 0 and 4-6 are fixed at 0 and cannot be modified. Note that bit 0 (Ready in EEPROMs) is unnecessary as the FRAM writes in real-time and is never busy. The BP1 and BP0 control software write protection features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the status register has no effect on its state. This bit is internally set by the WREN command and clearedby terminating a write cycle (/CS high) or by using the WRDI command.BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write protected as shown in the following table.Table 3. Block Memory Write ProtectionBP1 BP0 Protected Address Range0 0 None0 1 6000h to 7FFFh (upper ¼)1 0 4000h to 7FFFh (upper ½)1 1 0000h to 7FFFh (all)The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits. The WPEN bit controls the effect of the hardware /WP pin. When WPEN is low, the /WP pin is ignored. When WPEN is high, the /WP pin controls write access to the status register. Thus the Status register is write protected if WPEN=1 and /WP=0. This scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. This occurs if the BP1 and BP0 are set to 1, the WPEN bit is set to 1, and /WP is set to 0. This occurs because the block protect bits prevent writing memory and the /WP signal in hardware prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions.Table 4. Write ProtectionWEL WPEN /WP Protected Blocks Unprotected Blocks Status RegisterXXProtected Protected Protected1 0 XProtected Unprotected Unprotected1 1 0Protected Unprotected Protected1 1 1Protected Unprotected UnprotectedMemory OperationThe SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus EEPROMs, the FM25256 can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write OperationAll writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code is followed by a two-byte address value. The upper bit of the address is a “don’t care”. In total, 15-bits specify the address of the first data byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. A write operation is shown in Figure 9.Unlike EEPROMs, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8th clock). The rising edge of /CS terminates a WRITE op-code operation. Asserting /WP active in the middle of a write operation will have no effect until the next falling edge of /CS.Read OperationAfter the falling edge of /CS, the bus master can issue a READ op-code. Following this instruction is a two-byte address value. The upper bit of the address is a don’t care. In total, 15-bits specify the address of the first byte of the read operation. After the op-code and address are complete, the SI line is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /CS terminates a READ op-code operation.A read operation is shown in Figure 10.HoldThe /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK and /CS pins can toggle during a hold state.Figure 9. Memory WriteFigure 10. Memory ReadElectrical SpecificationsAbsolute Maximum RatingsSymbol Description Ratings V DD Power Supply Voltage with respect to V SS-1.0V to +7.0VV IN Voltage on any pin with respect to V SS-1.0V to +7.0Vand V IN < V DD+1.0V T STG StorageTemperature -55°C to + 125°C T LEAD Lead Temperature (Soldering, 10 seconds) 300° CV ESD Electrostatic Discharge Voltage- Human Body Model (JEDEC Std JESD22-A114-B)- Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A)3kV 1kV 100VPackage Moisture Sensitivity Level MSL-1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stressrating only, and the functional operation of the device at these or any other conditions above those listed in the operationalsection of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affectdevice reliability.DC Operating Conditions(T A = -40°C to + 85°C, V DD = 4.0V to 5.5V unless otherwise specified)Symbol Parameter MinTypMaxUnitsNotes V DD Power Supply Voltage 4.0 - 5.5 VI DD Power Supply Current@ SCK = 1.0 MHz @ SCK = 5.0 MHz @ SCK = 25.0 MHz ---0.81.87.0mA 1I SB StandbyCurrent - 150 µA 2 I LI InputLeakageCurrent - ±1 µA 3 I LO Output Leakage Current - ±1 µA 3 V IH Input High Voltage 0.7 V DD V DD + 0.5 VV IL Input Low Voltage -0.3 0.3 V DD VV OH Output High Voltage@ I OH = -2 mAV DD – 0.8 - VV OL Output Low Voltage@ I OL = 2 mA - 0.4VV HYS Input Hysteresis 0.05 V DD- V 4 Notes1. SCK toggling between V DD-0.3V and V SS, other inputs V SS or V DD-0.3V.2. SCK = SI = /CS=V DD. All inputs V SS or V DD.3. V SS≤ V IN≤ V DD and V SS≤ V OUT≤ V DD.4. This parameter is characterized but not 100% tested.AC Parameters (T A = -40°C to + 85°C, V DD = 4.0V to 5.5V, C L = 30pF)Symbol Parameter Min Max Units Notesf CK SCK Clock Frequency 0 25 MHzt CH Clock High Time 18 ns 1LowTime 18 ns 1t CL Clockt CSU Chip Select Setup 10 nst CSH Chip Select Hold 10 nst OD Output Disable Time 15 ns 2t ODV Output Data Valid Time 15 nst OH Output Hold Time 0 nsTime 60 nst D Deselectt R Data In Rise Time 50 ns 1,3t F Data In Fall Time 50 ns 1,3t SU Data Setup Time 5 nst H Data Hold Time 5 nst HS/Hold Setup Time 10 nsTime 10 nst HH /HoldHoldt HZ/Hold Low to Hi-Z 20 ns 2t LZ/Hold High to Data Active 15 ns 2Notes1.t CH + t CL = 1/f CK.2.This parameter is characterized but not 100% tested.3.Rise and fall times measured between 10% and 90% of waveform.Power Cycle Timing (T A = -40° C to + 85° C, V DD = 4.0V to 5.5V)NotesUnitsSymbol Parameter MinMaxt PU Power Up (V DD min) to First Access (/CS low) 10 - mst PD Last Access (/CS high) to Power Down (V DD min) 0 - µst VR V DD Rise Time 50 µs/V 1,2t VF V DD Fall Time 100 - µs/V 1,2Capacitance (T A = 25° C, f=1.0 MHz, V DD = 5.0V)UnitsNotesMaxSymbol Parameter MinC O Output capacitance (SO) - 8 pF 1capacitance - 6 pF 1C I InputNotes1. This parameter is characterized and not 100% tested.2. Slope measured at any point on V DD waveform.AC Test ConditionsInput Pulse Levels 10% and 90% of V DDInput rise and fall times 5 nsInput and output timing levels 0.5 V DDOutput Load Capacitance 30 pFSerial Data Bus Timing/Hold TimingPower Cycle TimingV DDCSData Retention (V DD = 4.0V to 5.5V)Parameter Min Max Units NotesData Retention 10 - YearsMechanical Drawing8-pin SOIC (JEDEC MS-012 variation AA)Refer to JEDEC MS-012 for complete dimensions and notes.All dimensions in millimeters.Revision HistoryRevision Date Summary 0.1 9/9/03 Initial release. 0.11 12/9/03 Reduced I DD spec limits. 0.12 1/7/04 Added t VR spec, “green” package, and modified Power Cycling diagram. 0.13 4/28/04 Changed t OD , t ODV , and t LZ timing specs. Changed t VR and t VF conditions. 1.0 8/16/04 Changed V DD range in AC Parameters table. Changed I DD limits. Addedpackage marking scheme. Changed t ODV spec. New rev. number to comply with new scheme.1.1 3/14/05 New part number FM25256 replaces FM25W256 since operating voltage isno longer wide (2.7V – 5.5V). Added note about powering down with /CS active (pg 3). Added ESD and package MSL ratings. Changed I SB spec.2.0 4/5/05 Changed to Pre-Production status.。

MSP430 与FM25L256 铁电存储器SPI接口原理与实现

SPI1Rxflg 变量为 1，就表示一个字节已经接收完毕。详细实现如下：
unsigned char RxTxSPI1(unsigned char c)
{
while(!(U1TCTL & TXEPT));
SPI1Rxflg=0;
TXBUF1=c;
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始，下表示所有这些操作的代码：
名称
描述
操作码
WREN 设置写操作允许，每次写操作（写存储器数据或者状态寄存器）时，都必 0000 0110b 须首先使用这个命令,执行这个命令后，状态寄存器中WEL位被设置为1。
WRDI
写操作不允许，在每次写操作完成后，器件会自动改变为写操作不允许， 0000 0100b 用户也可使用这个命令，设置写操作不允许。执行这个命令后，状态寄存器中的WEL位被清除。
2.3
FM25L256 的 SPI 通信..................................................................................................6
2.3.1 FM25L256 的访问操作..........................................................................................6
UTCTL1=SSEL1+STC;
//选择 SMCLK 为 SPI 时钟源
UBR11=0; UBR01=8;
//SPI 时钟频率为 1M @ 外部 8 MHz 晶振

FM25F02.04使用说明手册

FM25F04/02使用手册1.产品概述FM25F04/02为4M/2M位的串行Flash存储器，内部组织为524,288个字节（FM25F04）/262144个字节（FM25F02），另外还有一个256字节的OTP扇区，每个字节8位。

芯片接口为兼容SPI协议(模式3/0)的串行接口总线，广泛应用于消费类电子市场。

主要用于存储固件和配置、设置信息。

产品的基本性能如下：✧工作电压：2.3V - 3.6V✧统一扇区架构：-128个4-Kbyte扇区（FM25F04），64个4-Kbyte扇区（FM25F02）-8个64K-byte区块（FM25F04），4个64K-byte区块（FM25F02）-任意扇区或区块都可以被单独擦除✧可锁定的256 byte OTP安全扇区✧SPI串行接口(模式0及模式3)✧支持Dual Output Fast Read操作✧支持Dual I/O Fast Read操作，在此操作下也支持Continuous Read✧支持软/硬件写保护✧支持256字节页编程模式Manu ID：A1JEDEC ID：A13112（FM25F02），A13113（FM25F04）2.引脚定义FM25F04/023.直流参数(TA=-40℃~85℃，Vcc=2.3V~3.6V)f CLK=100MHZ时CL=20 pF, f CLK=75MHZ时CL=30 pF5.上电时序上电时序及写禁止电压FM25F04/02状态寄存器定义注意：1.在OTP模式下，SRP位定义为OTP_LOCK位2.见"保护区域表”7.操作命令说明所有的命令、地址和数据都是移位进出芯片，最高位（MSB）在第一位。

DI在CS#为低后的第一个CLK的上升沿被采样，之后，一字节的命令码必须被移位输入芯片，最高位在第一位，每位都在时钟的上升沿被采样。

下表列出了命令集。

每种命令序列都由一个单字节命令码开始。

根据不同的命令，后面跟随的可能是地址字节或数据字节，或什么都不跟。

M95128.M95256--128k.256K存储芯片手册免费下载

1/39October 2004M95256M95128256Kbit and 128Kbit Serial SPI Bus EEPROMWith High Speed ClockFEATURES SUMMARY■Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes)■Single Supply Voltage:– 4.5 to 5.5V for M95xxx – 2.5 to 5.5V for M95xxx-W – 1.8 to 5.5V for M95xxx-R ■High Speed–10MHz Clock Rate, 5ms Write Time ■Status Register■Hardware Protection of the Status Register ■BYTE and PAGE WRITE (up to 64 Bytes)■Self-Timed Programming Cycle■Adjustable Size Read-Only EEPROM Area ■Enhanced ESD Protection■More than 100000 Erase/Write Cycles ■More than 40-Year Data RetentionTable 1. Product ListReferencePart NumberM95256M95256M95256-W M95256-R M95128M95128M95128-W M95128-RM95256, M95128TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 3.DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 2.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Serial Clock (C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6CONNECTING TO THE SPI BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 4.Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 5.SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8OPERATING FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Power On Reset: VCC Lock-Out Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Active Power and Standby Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 6.Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 3.Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Data Protection and Protocol Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 4.Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 7.Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 5.Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 8.Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132/39M95256, M95128Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 9.Write Disable (WRDI) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 10.Read Status Register (RDSR) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 6.Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 11.Write Status Register (WRSR) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 12.Read from Memory Array (READ) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Write to Memory Array (WRITE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 13.Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 14.Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 7.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 8.Operating Conditions (M95xxx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 9.Operating Conditions (M95xxx-W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 10.Operating Conditions (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 11.AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 15.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 12.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 13.DC Characteristics (M95xxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 14.DC Characteristics (M95xxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 15.DC Characteristics (M95xxx-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 16.DC Characteristics (M95xxx-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 17.DC Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 18.AC Characteristics (M95xxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 19.AC Characteristics (M95xxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 20.AC Characteristics (M95xxx-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 21.AC Characteristics (M95xxx-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 22.AC Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 16.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 17.Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 18.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333/39M95256, M951284/39Figure 19.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .33 Table 23.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . .33 Figure 20.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .34 Table 24.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 34Figure 21.SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline. . . . . .35 Table 25.SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data 35Figure 22.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .36 Table 26.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data. . . . . . . . . . . .36PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 27.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 28.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38M95256, M95128SUMMARY DESCRIPTIONThese electrically erasable programmable memo-ry (EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 32768 x 8 bit (M95256) and 16384 x 8 bit (M95128).The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figure 2..The device is selected when Chip Select (S) is tak-en Low. Communications with the device can be interrupted using Hold (HOLD).sions, and how to identify pin-1.Table 2. Signal NamesC SerialClockD Serial Data InputQ Serial Data OutputS Chip SelectW WriteProtectHOLD HoldV CC Supply VoltageV SS Ground5/39M95256, M951286/39SIGNAL DESCRIPTIONDuring all operations, V CC must be held stable and within the specified valid range: V CC (min) to V CC (max).All of the input and output signals must be held High or Low (according to voltages of V IH , V OH , V IL or V OL , as specified in Table 13. to Table 17.).These signals are described next.Serial Data Output (Q).This output signal is used to transfer data serially out of the device.Data is shifted out on the falling edge of Serial Clock (C).Serial Data Input (D).This input signal is used to transfer data serially into the device. It receives in-structions, addresses, and the data to be written.Values are latched on the rising edge of Serial Clock (C).Serial Clock (C).This input signal provides the timing of the serial interface. Instructions, address-es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).When this input signal is High,the device is deselected and Serial Data Output(Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Stand-by Power mode. Driving Chip Select (S) Low se-lects the device, placing it in the Active Power mode.is required prior to the start of any instruction. pause any serial communications with the device without deselecting the device.During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D)and Serial Clock (C) are Don’t Care.To start the Hold condition, the device must be se-The main purpose of this in-put signal is to freeze the size of the area of mem-ory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register).This pin must be driven either High or Low, and must be stable during all write instructions.M95256, M95128 CONNECTING TO THE SPI BUSThese devices are fully compatible with the SPI protocol.All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip All output data bytes are shifted out of the device, most significant bit first. The Serial Data Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register in-structions) have been clocked into the device. Figure 4. shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance.7/39M95256, M951288/39SPI ModesThese devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:–CPOL=0, CPHA=0–CPOL=1, CPHA=1For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).The difference between the two modes, as shown in Figure 5., is the clock polarity when the bus master is in Stand-by mode and not transferring data:– C remains at 0 for (CPOL=0, CPHA=0)– C remains at 1 for (CPOL=1, CPHA=1)M95256, M95128 OPERATING FEATURESPower-upWhen the power supply is turned on, V CC rises from V SS to V CC.During this time, the Chip Select (S) must be al-lowed to follow the V CC voltage. It must not be al-lowed to float, but should be connected to V CC via a suitable pull-up resistor.sensitive as well as level sensitive. After Power-up, the device does not become selected until a falling edge has first been detected on Chip Selectbeen High, prior to going Low to start the first op-eration.Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write instructions during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until V CC has reached the Power On Reset (POR) threshold voltage, and all operations are disabled – the device will not respond to any instruction. In the same way, when V CC drops from the operating voltage, below the Power On Reset (POR) threshold voltage, all operations are dis-abled and the device will not respond to any in-struction.A stable and valid V CC must be applied before ap-plying any logic signal.Power-downAt Power-down, the device must be deselected.voltage applied on V CC.Active Power and Standby Power Modes When Chip Select (S) is Low, the device is select-ed, and in the Active Power mode. The device consumes I CC, as specified in Table 13. to Table 17..lected. If an Erase/Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to I CC1.Hold ConditionThe Hold (HOLD) signal is used to pause any se-rial communications with the device without reset-ting the clocking sequence.During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care.To enter the Hold condition, the device must be Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the de-vice while it is in the Hold condition, has the effect of resetting the state of the device, and this mech-anism can be used if it is required to reset any pro-cesses that had been in progress.The Hold condition starts when the Hold (HOLD) signal is driven Low at the same time as Serial Clock (C) already being Low (as shown in Figure 6.).The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low.Figure 6. also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being Low.9/39M95256, M9512810/39Status RegisterFigure 7. shows the position of the Status Register in the control logic of the device. The Status Reg-ister contains a number of status and control bits that can be read or set (as appropriate) by specific instructions.WIP bit.The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle.WEL bit.The Write Enable Latch (WEL) bit indi-cates the status of the internal Write Enable Latch.BP1, BP0 bits.The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. SRWD bit.The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits.Table 3. Status Register FormatData Protection and Protocol ControlNon-volatile memory devices can be used in envi-ronments that are particularly noisy, and within ap-plications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms:■Write and Write Status Register instructionsare checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.■All instructions that modify data must bepreceded by a Write Enable (WREN) instruction to set the Write Enable Latch(WEL) bit. This bit is returned to its reset state by the following events:–Power-up–Write Disable (WRDI) instructioncompletion–Write Status Register (WRSR) instructioncompletion–Write (WRITE) instruction completion ■The Block Protect (BP1, BP0) bits allow part ofthe memory to be configured as read-only. This is the Software Protected Mode (SPM).■The Write Protect (W) signal allows the BlockProtect (BP1, BP0) bits to be protected. This is the Hardware Protected Mode (HPM).For any instruction to be accepted, and executed,Chip Select (S) must be driven High after the rising edge of Serial Clock (C) for the last bit of the in-struction, and before the next rising edge of Serial Clock (C).Two points need to be noted in the previous sen-tence:–The ‘last bit of the instruction’ can be theeighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions).–The ‘next rising edge of Serial Clock (C)’ might(or might not) be the next bus transaction for some other device on the SPI bus.Table 4. Write-Protected Block Sizeb7 b0SRWD0 0 0 BP1 BP0 WEL WIPStatus Register Write ProtectBlock Protect Bits Write Enable Latch BitWrite In Progress BitStatus Register Bits Protected BlockArray Addresses Protected BP1 BP0M95256M951280 0 none none none 0 1 Upper quarter 6000h - 7FFFh 3000h - 3FFFh 1 0 Upper half 4000h - 7FFFh 2000h - 3FFFh 11Whole memory0000h - 7FFFh0000h - 3FFFhMEMORY ORGANIZATIONThe memory is organized as shown in Figure 7..11/39INSTRUCTIONSEach instruction starts with a single-byte code, as summarized in Table 5..If an invalid instruction is sent (one not contained in Table 5.), the device automatically deselects it-self.Table 5. Instruction SetInstructionDescriptionInstructionFormat WREN Write Enable0000 0110 WRDI Write Disable0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read from Memory Array0000 0011 WRITE Write to Memory Array 0000 001012/39Write Enable (WREN)The Write Enable Latch (WEL) bit must be set pri-or to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device.As shown in Figure 8., to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High.One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device.As shown in Figure 9., to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D).The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) be-ing driven High.The Write Enable Latch (WEL) bit, in fact, be-comes reset by any of the following events:–Power-up–WRDI instruction execution–WRSR instruction completion–WRITE instruction completion.13/39Read Status Register (RDSR)The Read Status Register (RDSR) instruction al-lows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is rec-ommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register con-tinuously, as shown in Figure 10..The status and control bits of the Status Register are as follows:WIP bit.The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.WEL bit.The Write Enable Latch (WEL) bit indi-cates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register in-struction is accepted.BP1, BP0 bits.The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Regis-ter (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the rele-vant memory area (as defined in Table 3.) be-comes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protect-ed mode has not been set.SRWD bit.The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect bits of the Status Register (SRWD, BP1, BP0) be-come read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for exe-cution.14/39Write Status Register (WRSR)The Write Status Register (WRSR) instruction al-lows new values to be written to the Status Regis-ter. Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex-ecuted. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).The Write Status Register (WRSR) instruction is by the instruction code and the data byte on Serial Data Input (D).The instruction sequence is shown in Figure 11.. The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the Status Register. b6, b5 and b4 are always read as 0. Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is t W) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 dur-ing the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is com-pleted, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction al-lows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3..The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hard-ware Protected Mode (HPM) is entered.The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0) bits are fro-zen at their current values from just before the start of the execution of Write Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the ex-ecution of Write Status Register (WRSR) instruc-tion.Table 6. Protection ModesNote: 1.As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6..The protection features of the device are summa-rized in Table 4..When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) in-struction, regardless of the whether Write Protect (W) is driven High or Low.When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W):–If Write Protect (W) is driven High, it is possible to write to the Status Registerprovided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable(WREN) instruction.–If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit haspreviously been set by a Write Enable(WREN) instruction. (Attempts to write to the Status Register are rejected, and are notaccepted for execution). As a consequence,all the data bytes in the memory area that are software protected (SPM) by the Block ProtectW Signal SRWDBitModeWrite Protection of theStatus RegisterMemory ContentProtected Area1Unprotected Area110SoftwareProtected(SPM)Status Register is Writable(if the WREN instructionhas set the WEL bit)The values in the BP1 andBP0 bits can be changedWrite ProtectedReady to accept Writeinstructions00 1101HardwareProtected(HPM)Status Register isHardware write protectedThe values in the BP1 andBP0 bits cannot bechangedWrite ProtectedReady to accept Writeinstructions15/39。

FM25L256操作子程序

#include "FM25L256.h"//FM25L256数据读取子程序//参数: *pDestination要读入数据的主机内存地址指针; uiSourceAddress要读取的数据在FM25L256中的地址(整形); uiNum数据个数(整形)//参数条件: uiSourceAddress+(uiNum-1)不能大于器件的最高地址; uiNum必须>0;void ReadFM25L256(unsigned char *pDestination, unsigned int uiSourceAddress, unsigned int uiNum){unsigned char ucHighAddress = uiSourceAddress >> 8; //高位地址SPCR = (1<<SPE)|(1<<MSTR)|(0<<CPOL)|(0<<SPR0);EnableFM25256; //CS变低SPDR = 0x03; //写入读命令字while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕SPDR = ucHighAddress; //写入高位地址while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕SPDR = (unsigned char) (uiSourceAddress & 0x00FF); //写入低位地址while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕for(;uiNum > 0;uiNum--){SPDR = 0; //为了读取数据，需要写入数据，发送SCK，故写入0while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕*pDestination = SPDR; //从器件读出一个字节pDestination++;}DisableFM25256; //CS变高}//FM25L256数据读取并发送至串口子程序//参数: uiSourceAddress要读取的数据在FM25L256中的地址(整形); uiNum数据个数(整形) //参数条件: uiSourceAddress+(uiNum-1)不能大于器件的最高地址; uiNum必须>0;//返回值：所发送数据的检验和unsigned char ReadFM25L256SendToUsart(unsigned int uiSourceAddress, unsigned int uiNum) {unsigned char ucHighAddress = uiSourceAddress >> 8; //高位地址unsigned char ucTemp;EnableFM25256; //CS变低SPCR = (1<<SPE)|(1<<MSTR)|(0<<CPOL)|(0<<SPR0);SPDR = 0x03; //写入读命令字while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕SPDR = ucHighAddress; //写入高位地址while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕SPDR = (unsigned char) (uiSourceAddress & 0x00FF); //写入低位地址while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕for(;uiNum > 0;uiNum--){SPDR = 0; //为了读取数据，需要写入数据，发送SCK，故写入0while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕ucTemp = SPDR; //读取SPDRSendChar(ucTemp); //发送至串口}DisableFM25256; //CS变高return (1);}//FM25L256数据写入子程序//参数: *pSource要写入数据的主机内存地址指针; uiDestinationAddress要写入的数据在FM25L256中的地址(整形); uiNum数据个数(整形)void WriteFM25L256(unsigned char *pSource, unsigned int uiDestinationAddress, unsigned int uiNum){unsigned char ucHighAddress = uiDestinationAddress >> 8; //高位地址EnableFM25256; //CS变低SPCR = (1<<SPE)|(1<<MSTR)|(0<<CPOL)|(0<<SPR0);SPDR = 0x06; //写入写使能WREN命令while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕DisableFM25256; //CS变高_delay_us(50);EnableFM25256; //CS变低SPDR = 0x02; //写入写命令字while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕SPDR = ucHighAddress; //写入高位地址CI-FM25H20-DGwhile((SPSR&(1<<SPIF))==0); //等待SPI发送完毕SPDR = (unsigned char) (uiDestinationAddress & 0x00FF); //写入低位地址while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕for(;uiNum > 0;uiNum--){SPDR = *pSource; //发送要写入的数据while((SPSR&(1<<SPIF))==0); //等待SPI发送完毕pSource++;}DisableFM25256; //CS变高}//FM25L256自检子程序//返回值：0:自检成功，1：自检失败unsigned char FM25L256SelfTest(void){unsigned int uiTemp;uiTemp = ReadInt(FM25L256_CHECK_ADDRESS);if (uiTemp == 0xA55A) //判断是否存储器是否能读return (0);else{ //存储器不能读或未进行出厂设置SetDefault(); //出厂设置，函数定义在System.c WriteInt (0xA55A,FM25L256_CHECK_ADDRESS); //设置已出厂设置标志uiTemp = ReadInt(FM25L256_CHECK_ADDRESS);if (uiTemp == 0xA55A) //若读取正确返回0return (0);elsereturn (1); //若仍读取错误则返回1}}/*//测试FM25L256子程序void VerifyFM25L256(void){unsigned int uiCheckAddress = 0;unsigned int uiMemoryNum = ReadInt(MEMORY_ADDRESS);unsigned int uiOldData;unsigned char ucError = 0;unsigned char ucSendChkSum;unsigned char i;union tagSTOREINT siUsartDataInt; //整型共用体，将整形分解为字节型存取，在DataStore.h中定义for (;uiCheckAddress < uiMemoryNum;uiCheckAddress += 2){uiOldData = ReadInt(uiCheckAddress); //保存原有数据WriteInt (0xA55A,uiCheckAddress); //写入测试字// __delay_cycles(10);if (ReadInt(uiCheckAddress) != 0xA55A){WriteInt (uiOldData,uiCheckAddress); //写回原有数据SendChar(COMM_FRAME_START); //发送反馈帧头ucSendChkSum = COMM_FRAME_START; //计算反馈帧的校验和SendChar(VERIFY_FRAM_COMMAND); //发送命令字ucSendChkSum += VERIFY_FRAM_COMMAND; //计算反馈帧的校验和siUsartDataInt.uiStoreInt = uiMemoryNum; //发送地址总长for (i = 0;i <= 1;i++){SendChar(siUsartDataInt.ucStoreBuff[i]);ucSendChkSum += siUsartDataInt.ucStoreBuff[i];}siUsartDataInt.uiStoreInt = uiCheckAddress; //发送测试地址for (i = 0;i <= 1;i++){SendChar(siUsartDataInt.ucStoreBuff[i]);ucSendChkSum += siUsartDataInt.ucStoreBuff[i];}SendChar(FINISHED_SEND);ucSendChkSum += FINISHED_SEND; //发送结束上传标志SendChar(ucSendChkSum); //发送检验和SendChar(COMM_FRAME_END); //发送帧尾ucError = 1; //置错误标志break; //退出循环}else if ((((uiCheckAddress + 2) % 1024) == 0) && ((uiCheckAddress + 2) < uiMemoryNum)){WriteInt (uiOldData,uiCheckAddress); //写回原有数据SendChar(COMM_FRAME_START); //发送反馈帧头ucSendChkSum = COMM_FRAME_START; //计算反馈帧的校验和SendChar(VERIFY_FRAM_COMMAND); //发送命令字ucSendChkSum += VERIFY_FRAM_COMMAND; //计算反馈帧的校验和siUsartDataInt.uiStoreInt = uiMemoryNum; //发送地址总长for (i = 0;i <= 1;i++){SendChar(siUsartDataInt.ucStoreBuff[i]);ucSendChkSum += siUsartDataInt.ucStoreBuff[i];}siUsartDataInt.uiStoreInt = uiCheckAddress + 2; //发送测试完成地址for (i = 0;i <= 1;i++){SendChar(siUsartDataInt.ucStoreBuff[i]);ucSendChkSum += siUsartDataInt.ucStoreBuff[i];}SendChar(GO_ON_SEND);ucSendChkSum += GO_ON_SEND; //发送结束上传标志SendChar(ucSendChkSum); //发送检验和SendChar(COMM_FRAME_END); //发送帧尾// __watchdog_reset(); //复位看门狗}WriteInt (uiOldData,uiCheckAddress); //写回原有数据}if (ucError == 0){SendChar(COMM_FRAME_START); //发送反馈帧头ucSendChkSum = COMM_FRAME_START; //计算反馈帧的校验和SendChar(VERIFY_FRAM_COMMAND); //发送命令字ucSendChkSum += VERIFY_FRAM_COMMAND; //计算反馈帧的校验和siUsartDataInt.uiStoreInt = uiMemoryNum; //发送地址总长for (i = 0;i <= 1;i++){SendChar(siUsartDataInt.ucStoreBuff[i]);ucSendChkSum += siUsartDataInt.ucStoreBuff[i];}siUsartDataInt.uiStoreInt = uiCheckAddress; //发送测试完成地址for (i = 0;i <= 1;i++){SendChar(siUsartDataInt.ucStoreBuff[i]);ucSendChkSum += siUsartDataInt.ucStoreBuff[i];}SendChar(FINISHED_SEND);ucSendChkSum += FINISHED_SEND; //发送结束上传标志SendChar(ucSendChkSum); //发送检验和SendChar(COMM_FRAME_END); //发送帧尾}}*/。

FM25V02铁电存储器数据手册pdf格式

This is a product under development. Device specifications are design Ramtron International CorporationFM25V02256Kb Serial 3V F-RAM MemoryFeatures256K bit Ferroelectric Nonvolatile RAM • Organized as 32K x 8 bits• High Endurance 100 Trillion (1014) Read/Writes • 10 Year Data Retention • NoDelay™ Writes• Advanced High-Reliability Ferroelectric ProcessVery Fast Serial Peripheral Interface - SPI • Up to 40 MHz Frequency• Direct Hardware Replacement for Serial Flash • SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)Write Protection Scheme • Hardware Protection • Software ProtectionDevice ID and Serial Number• Device ID reads out Manufacturer ID & Part ID • Unique Serial Number (FM25VN02)Low Voltage, Low Power• Low Voltage Operation 2.0V – 3.6V • 90 µA Standby Current (typ.) • 5 µA Sleep Mode Current (typ.)Industry Standard Configurations• Industrial Temperature -40°C to +85°C • 8-pin “Green”/RoHS SOIC PackageDescriptionThe FM25V02 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.Unlike Serial Flash, the FM25V02 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after it has been transferred to the device. The next bus cycle may commence without the need for data polling. The product offers very high write endurance, orders of magnitude more endurance than Serial Flash. Also, F-RAM exhibits lower power consumption than Serial Flash.These capabilities make the FM25V02 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of Serial Flash can cause data loss.The FM25V02 provides substantial benefits to users of Serial Flash as a hardware drop-in replacement. The devices use the high-speed SPI bus, which enhances the high-speed write capability of F-RAMtechnology. The FM25VN02 is offered with a unique serial number that is read-only and can be used to identify a board or system. Both devices incorporate a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The devices are guaranteed over an industrial temperature range of -40°C to +85°C.Pin ConfigurationPin Name Function/S Chip Select /W Write Protect /HOLD HoldC Serial ClockD Serial Data Input Q Serial Data Output VDD Supply Voltage VSS GroundWFigure 1. Block DiagramPin DescriptionsPin Name I/O Description/S Input Chip Select: This active-low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. Whenlow, the device internally activates the C signal. A falling edge on /S must occur priorto every op-code.C Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched onthe rising edge and outputs occur on the falling edge. Since the device is static, theclock frequency may be any value between 0 and 40 MHz and may be interrupted atany time./HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The deviceignores any transition on C or /S. All transitions on /HOLD must occur while C is low.This pin has a weak internal pull-up (see R IN spec, pg 11). However, if it is not used,the /HOLD pin should be tied to V DD./W Input Write Protect: This active-low pin prevents write operations to the Status Register only. A complete explanation of write protection is provided on pages 6 and 7. If notused, the /W pin should be tied to V DD.D Input Serial Input: All data is input to the device on this pin. The pin is sampled on therising edge of C and is ignored at other times. It should always be driven to a validlogic level to meet I DD specifications.* D may be connected to Q for a single pin data interface.Q Output Serial Output: This is the data output pin. It is driven during a read and remains tri-stated at all other times including when /HOLD is low. Data transitions are driven onthe falling edge of the serial clock.* Q may be connected to D for a single pin data interface.SupplyVDD SupplyPowerGroundVSS SupplyOverviewThe FM25V02 is a serial F-RAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the F-RAM is similar to Serial Flash. The major differences between the FM25V02 and a Serial Flash with the same pinout are the F-RAM’s superior write performance, very high endurance, and lower power consumption.Memory ArchitectureWhen accessing the FM25V02, the user addresses 32K locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two-byte address. The complete address of 15-bits specifies each byte address uniquely.Most functions of the FM25V02 either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike Serial Flash, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25V02 due to its fast write cycle and high endurance as compared to Serial Flash. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than Serial Flash since it is completed quickly. By contrast, Serial Flash requiring milliseconds to write is vulnerable to noise during much of the cycle.Serial Peripheral Interface – SPI BusThe FM25V02 employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 40MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25V02 operates in SPI Mode 0 and 3. Protocol OverviewThe SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25V02 will begin monitoring the clock and data lines. The relationship between the falling edge of /S, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25V02 supports only modes 0 and 3. Figure 2 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the FM25V02 on the rising edge of C and data is expected on the first rising edge after /S goes active. If the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge.The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After /S is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred.Certain op-codes are commands with no subsequent data transfer. The /S must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per active chip select.SPI Mode 0: CPOL=0, CPHA=0SPI Mode 3: CPOL=1, CPHA=1Figure 2. SPI Modes 0 & 3System HookupThe SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. A typical system configuration uses one or more FM25V02 devices with a microcontroller that has a dedicated SPI port, as Figure 3 illustrates. Note that the clock, data-in, and data-out pins are common among all devices. The Chip Select and Hold pins must be driven separately for each FM25V02 device. For a microcontroller that has no dedicated SPI bus, a general purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the Hold pin. Figure 4 shows a configuration that uses only three pins.Figure 3. 512Kbit (64KB) System Configuration with SPI portFigure 4. System Configuration without SPI portPower Up to First AccessThe FM25V02 is not accessible for a period of time (t PU) after power up. Users must comply with the timing parameter t PU, which is the minimum timefrom V DD (min) to the first /S low.Data TransferAll data transfers to and from the FM25V02 occur in 8-bit groups. They are synchronized to the clock signal (C), and they transfer most significant bit (MSB) first. Serial inputs are registered on the rising edge of C. Outputs are driven from the falling edge of clock C.Command StructureThere are ten commands called op-codes that can be issued by the bus master to the FM25V02. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function, such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the Status Register. The third group includes commands for memory transactions followed by address and one or more bytes of data.Table 1. Op-code CommandsName Description Op-code WREN Set Write Enable Latch 00000110b WRDI Write Disable 00000100b RDSR Read Status Register 00000101b WRSR Write Status Register 00000001b READ Read Memory Data 00000011b FSTRD Fast Read Memory Data 00001011b WRITE Write Memory Data 00000010b SLEEP Enter Sleep Mode 10111001b RDID Read Device ID 10011111b SNR Read S/N 11000011b WREN – Set Write Enable LatchThe FM25V02 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the Status Register (WRSR) and writing the memory (WRITE).Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the Status Register has no effect on the state of this bit. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another WREN command. Figure 5 below illustrates the WREN command bus configuration.SCDQFigure 5. WREN Bus ConfigurationWRDI – Write DisableThe WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the Status Register and verifying that WEL=0. Figure 6 illustrates the WRDI command bus configuration.SCDQFigure 6. WRDI Bus ConfigurationRDSR – Read Status RegisterThe RDSR command allows the bus master to verify the contents of the Status Register. Reading Status provides information about the current state of the write protection features. Following the RDSR op-code, the FM25V02 will return one byte with the contents of the Status Register. The Status Register is described in detail in the section below.WRSR – Write Status RegisterThe WRSR command allows the user to select certain write protection features by writing a byte to the Status Register. Prior to issuing a WRSR command, the /W pin must be high or inactive. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. The bus configuration of RDSR and WRSR are shown below.Figure 7. RDSR Bus ConfigurationFigure 8. WRSR Bus ConfigurationStatus Register & Write ProtectionThe write protection features of the FM25V02 are multi-tiered. Taking the /W pin to a logic low state is the hardware write-protect function. Status Register write operations are blocked when /W is low. To write the memory with /W high, a WREN op-code must first be issued. Assuming that writes are enabled using WREN and by /W, writes to memory are controlled by the Status Register. As described above, writes to the Status Register are performed using the WRSR command and subject to the /W pin. The Status Register is organized as follows.Table 2. Status RegisterBit 76 5 4 321 0NameWPEN 1 0 0 BP1BP0 WEL 0Bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and none of these bits can be modified. Note that bit 0 (“Ready” in Serial Flash) is unnecessary as the F-RAM writes in real-time and is never busy, so it reads out as a ‘0’. There is an exception to this when the device is waking up from Sleep Mode, which is described on the following page. The BP1 and BP0 control software write protection features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the Status Register hasno effect on its state. This bit is internally set and cleared via the WREN and WRDI commands, respectively.BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected as shown in the following table.Table 3. Block Memory Write Protection BP1 BP0 Protected Address Range 0 0 None 0 1 6000h to 7FFFh (upper ¼) 1 0 4000h to 7FFFh (upper ½) 1 1 0000h to 7FFFh (all)The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits.The WPEN bit controls the effect of the hardware /W pin. When WPEN is low, the /W pin is ignored. When WPEN is high, the /W pin controls write access to the Status Register. Thus the Status Register is write protected if WPEN=1 and /W=0.This scheme provides a write protection mechanism, which can prevent software from writing the memoryunder any circumstances. This occurs if the BP1 and BP0 bits are set to 1, the WPEN bit is set to 1, and the /W pin is low. This occurs because the block protect bits prevent writing memory and the /W signal in hardware prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions.Table 4. Write ProtectionWEL WPEN /W Protected Blocks Unprotected Blocks Status RegisterXXProtected Protected Protected1 0 XProtected Unprotected Unprotected1 1 0Protected Unprotected Protected1 1 1Protected Unprotected UnprotectedMemory OperationThe SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike Serial Flash, the FM25V02 can perform sequential writes at bus speed. No page buffer is needed and any number of sequential writes may be performed.Write OperationAll writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction. This op-code is followed by a two-byte address value, which specifies the 15-bit address of the first data byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. A write operation is shown in Figure 9.Unlike Serial Flash, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8th clock). The rising edge of /S terminates a WRITE op-code operation. Asserting /W active in the middle of a write operation will have no effect until the next falling edge of /S.Read OperationAfter the falling edge of /S, the bus master can issue a READ op-code. Following this instruction is a two-byte address value (A14-A0), specifying the address of the first data byte of the read operation. After the op-code and address are complete, the D pin is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /S terminates a READ op-code operation and tri-states the Q pin. A read operation is shown in Figure 10.Fast Read OperationThe FM25V02 supports the FAST READ op-code (0Bh) that is found on Serial Flash devices. It is implemented for code compatibility with Serial Flash devices. Following this instruction is a two-byte address (A14-A0), specifying the address of the first data byte of the read operation. A dummy byte follows the address. It inserts one byte of read latency. The D pin is ignored after the op-code, 2-byte address, and dummy byte are complete. The bus master issues 8 clocks, with one bit read out for each. The Fast Read operation is otherwise the same as an ordinary READ. If the last address of 7FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /S terminates a FAST READ op-code operation and tri-states the Q pin. A Fast Read operation is shown in Figure 11. HoldThe FM25V02 and FM25VN02 devices have a /HOLD pin that can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while C is low, the current operation will pause. Taking the /HOLD pin high while C is low will resume an operation. The transitions of /HOLD must occur while C is low, but the C and /S pins can toggle during a hold state.Figure 9. Memory Write with 2-Byte AddressFigure 10. Memory Read with 2-Byte AddressFigure 11. Fast Read with 2-Byte Address and Dummy ByteSCDQSCDQSleep ModeA low power mode called Sleep Mode is implemented on both FM25V02 and FM25VN02 devices. The device will enter this low power state when the SLEEP op-code B9h is clocked-in and a rising edge of /S is applied. Once in sleep mode, the C and D pins are ignored and Q will be high-Z, but the device continues to monitor the /S pin. On the next falling edge of /S, the device will return to normal operation within t REC (400 µs max.). The Q pin remains in a hi-Z state during the wakeup period. The device will not necessarily respond to an opcode within the wakeup period. To start the wakeup procedure, the controller may send a “dummy” read, for example, and wait the remaining t REC time.Device IDThe FM25V02 and FM25VN02 devices can be interrogated for its manufacturer, product identification, and die revision. The RDID op-code 9Fh allows the user to read the manufacturer ID and product ID, both of which are read-only bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7, therefore there are six bytes of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which includes a Family code, a Density code, a Sub code, and Product Revision code.Table 6. Manufacturer and Product IDBit7 65 4 3 2 1 0 HexManufacturer ID 0 1 1 1 1 1 1 1 7F Continuation code 0 1 1 1 1 1 1 1 7F Continuation code 0 1 1 1 1 1 1 1 7F Continuation code 0 1 1 1 1 1 1 1 7F Continuation code 0 1 1 1 1 1 1 1 7F Continuation code 0 1 1 1 1 1 1 1 7F Continuation code 1 1 0 0 0 0 1 0 C2 JEDEC assigned Ramtron C2h in bank 7Family Density Hex Device ID (1st Byte) 0 0 1 0 0 0 1 0 22h Density: 02h=256K, 03h=512K, 04=1MSub Rev. RsvdDevice ID (2nd Byte)0 0 0 0 0 0 0 0 00h 00h=FM25V02, 01h=FM25VN02,02h=FM25VR02, 03h=FM25VRN02Figure 13. Read Device IDSC DQSix bytes of continuation code 7Fh1 6FM25V02 - 256Kb SPI FRAMUnique Serial Number (FM25VN02 only)The FM25VN02 device incorporates a read-only 8-byte serial number. It can be used to uniquely identify a pc board or system. The serial number includes a 40-bit unique number, an 8-bit CRC, and a 16-bit number that can be defined upon request by the customer. If a customer-specific number is not requested, the 16-bit Customer Identifier is 0x0000.The serial number is read by issuing the SNR op-code (C3h).The 8-bit CRC value can be used to compare to the value calculated by the controller. If the two values match, then the communication between slave and master was performed without errors.CUSTOMER IDENTIFIER *40-bit UNIQUE NUMBER 8-bit CRCSN(63:56) SN(55:48) SN(47:40) SN(39:32) SN(31:24) SN(23:16) SN(15:8) SN(7:0) * Contact factory for requesting a customer identifier number.Figure 14. 8-Byte Serial Number (read-only)Figure 15. Read Serial NumberEnduranceThe FM25V02 and FM25VN02 devices are capable of being accessed at least 1014 times, reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A14-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array as 4K rows of 64-bits each. The entire row is internally accessedonce whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited even at 40MHz clock rate.Table 7. Time to Reach 100 Trillion Cycles for Repeating 64-byte Loop SCK Freq (MHz) Endurance Cycles/sec. Endurance Cycles/year Years to Reach 1014 Cycles 40 74,620 2.35 x 101242.620 37,310 1.18 x 101285.1 10 18,660 5.88 x 1011170.2 5 9,330 2.94 x 1011 340.3SC DQFM25V02 - 256Kb SPI FRAM Electrical SpecificationsAbsolute Maximum RatingsSymbol Description RatingsV DD Power Supply Voltage with respect to V SS-1.0V to +4.5VV IN Voltage on any pin with respect to V SS-1.0V to +4.5Vand V IN < V DD+1.0V T STG StorageTemperature -55°C to + 125°C T LEAD Lead Temperature (Soldering, 10 seconds) 300° CV ESD Electrostatic Discharge Voltage- Human Body Model (JEDEC Std JESD22-A114-B)- Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A)TBD TBD TBDPackage Moisture Sensitivity Level MSL-1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ratingonly, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.DC Operating Conditions(T A = -40°C to + 85°C, V DD = 2.0V to 3.6V unless otherwise specified)Symbol Parameter Min Typ Max Units Notes V DD Power Supply Voltage 2.0 3.3 3.6 VI DD Power Supply Operating Current@ C = 1 MHz @ C = 40 MHz-1.50.33.0mAmA1I SB StandbyCurrent 90 150 µA 2I ZZ Sleep Mode Current 5 8 µA 3 I LI InputLeakageCurrent - ±1 µA 4 I LO Output Leakage Current - ±1 µA 4 V IH Input High Voltage 0.7 V DD V DD + 0.3 VV IL Input Low Voltage -0.3 0.3 V DD VV OH1Output High Voltage (I OH = -1 mA, V DD=2.7V) 2.4 - VV OH2Output High Voltage (I OH = -100 µA)V DD-0.2 - VV OL1Output Low Voltage (I OL = 2 mA, V DD=2.7V) - 0.4 VV OL2Output Low Voltage (I OL = 150 µA) - 0.2V R IN Input Resistance (/HOLD pin)For V IN = V IH(min) For V IN = V IL(max)401KΩMΩ5Notes1. C toggling between V DD-0.2V and V SS, other inputs V SS or V DD-0.2V.2. /S=V DD. All inputs V SS or V DD.3. In Sleep mode and /S=V DD. All inputs V SS or V DD.4. V SS≤ V IN≤ V DD and V SS≤ V OUT≤ V DD.5. The input pull-up circuit is stronger (> 40KΩ) when the input voltage is above V IH and weak (> 1MΩ) when the inputvoltage is below V IL.Data Retention(T A = -40°C to + 85°C)Parameter Min Max Units NotesData Retention 10 - YearsAC Parameters (T A = -40°C to + 85°C, C L = 30pF, unless otherwise specified) V DD 2.0 to 2.7V V DD 2.7 to 3.6V Symbol Parameter Min Max Min Max Units Notes f CK C Clock Frequency 0 25 0 40 MHz t CH Clock High Time 20 11 ns 1 t CL Clock Low Time 20 11 ns 1 t CSU Chip Select Setup 12 10 ns t CSH Chip Select Hold 12 10 ns t OD Output Disable Time 20 12 ns 2 t ODV Output Data Valid Time 18 9 t OH Output Hold Time 0 0 ns t D Deselect Time 60 40 ns t R Data In Rise Time 50 50 ns 2,3 t F Data In Fall Time 50 50 ns 2,3 t SU Data Setup Time 8 5 ns t H Data Hold Time 8 5 ns t HS /HOLD Setup Time 12 10 ns t HH /HOLD Hold Time 12 10 ns t HZ /HOLD Low to Hi-Z 25 20 ns 2 t LZ /HOLD High to Data Active 25 20 ns 2 Notes1. t CH + t CL = 1/f CK .2. This parameter is characterized but not 100% tested.3. Rise and fall times measured between 10% and 90% of waveform.Capacitance (T A = 25° C, f=1.0 MHz, V DD = 3.3V) Symbol Parameter Min Max Units Notes C O Output Capacitance (Q) - 8 pF 1C I Input Capacitance - 6 pF 1Notes1. This parameter is characterized and not 100% tested.AC Test Conditions Input Pulse Levels10% and 90% of V DD Input rise and fall times3 ns Input and output timing levels 0.5 V DD Output Load Capacitance30 pFSerial Data Bus Timing/HOLD TimingPower Cycle TimingVSPower Cycle & Sleep Timing (T A = -40° C to + 85° C, V DD = 2.0V to 3.6V, unless otherwise specified)Symbol Parameter Min Max Units Notest VR V DD Rise Time 50 - µs/V 1,2 t VF V DD Fall Time 100 - µs/V 1,2 t PU Power Up (V DD min) to First Access (/S low) 250 - µs t PD Last Access (/S high) to Power Down (V DD min) 0 - µs t REC Recovery Time from Sleep Mode - 400 µsNotes1.This parameter is characterized and not 100% tested.2.Slope measured at any point on V DD waveform.Mechanical Drawing8-pin SOIC (JEDEC MS-012 variation AA)Refer to JEDEC MS-012 for complete dimensions and notes.All dimensions in millimeters.Revision HistoryRevision Date Summaryrelease.Initial0.1 3/24/2009Ordering InformationPackagePart Number Features OperatingVoltageFM25V02-G Device ID 2.0-3.6V 8-pin “Green”/RoHS SOIC FM25VN02-G Device ID, S/N 2.0-3.6V 8-pin “Green”/RoHS SOIC FM25V02-GTR Device ID 2.0-3.6V 8-pin “Green”/RoHS SOICin Tape & ReelFM25VN02-GTR Device ID, S/N 2.0-3.6V 8-pin “Green”/RoHS SOICin Tape & Reel。

FM25L256中文资料

CS
1
SO
2
WP
3
VSS
4
8
VDD
7
1 SO 2 /WP 3 VSS 4
8 VDD 7 /HOLD 6 SCK 5 SI
Top View
Pin Name /CS /WP /HOLD SCK SI SO VDD VSS
Function Chip Select Write Protect Hold Serial Clock Serial Data Input Serial Data Output Supply Voltage (2.7 to 3.6V) Ground
Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Page 1 of 14
元器件交易网
The FM25L256 provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25L256 uses the high-speed SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over an industrial temperature range of -40°C to +85°C.
Unlike serial EEPROMs, the FM25L256 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The next bus cycle may start immediately. In addition, the product offers virtually unlimited write endurance. Also, FRAM exhibits much lower power consumption than EEPROM.

铁电存储器数据手册

The DATASHEET China Service Center of RAMTRONa b s o r b e d i n f e r r o e l e c t r i c sprofessional technology and attentive service特性高集成度用于替换多个器件 l 串行非易失性存储器 l 实时时钟 l 低电压复位 l 看门狗记数器l 早期电压失效告警/NMI l 双16位事件记数器 l 串行数字标识铁电非易失性RAMl 4Kb 、16Kb 、64Kb 、256 Kb 版本 l 无限制的读写次数 l 10年掉电数据保存期 l 无延时写操作实时时钟/日历l 备用电流低至1UAl 秒至年采用BCD 格式编码 l 自动闰年调整l 使用标准的32.768KHZ 晶振（6PF ） l 时钟软件校准l 支持电池及电容后备处理器辅助功能l 电源及看门狗低有效复位输出 l 可编程低电压复位门限 l 手动复位l 可编程看门狗记数器l 电池后备的双事件记数器用于记录系统干扰或其它事件l 比较器用于电源失效中断或者其它用途 l 带锁定的64位串行数字标识快速的二线制串行接口l 最高达1M 总线时钟频繁l 支持以前的100K&400K 总线速度 l 器件选择管脚用于最多四只芯片寻址l RTC 、监测控制功能统一通过进行二线制接口操作方便使用的构造l 操作电源范围2.7V-5.5V l 小封装14引脚SOICl 低操作电流，150UA 的静态工作电流 l -40°C 至 +85°C 温度操作范围描述FM31系列产品是一族包含基于处理器系统的通用功能需求的集成器件，主要功能包含各种容量大小的铁电非易性存储器、实时时钟、低电压复位、看门狗记数器、非易失的事件记数器、可锁定的串行数字标识，和一个通用的比较器，用于电源失效中断输出或其它用途，所有器件的操作电压范围为2.7V-5.5V .。

AR-256L_316L_M258部品手册

MiR MLT MOT PAK PFT PiP PLG PLT PLU PLY PNL PWB RAL RDA RLY RNG ROL SEL SFT SHE SHT SLD Sli SLP SOC SOU
镜子垫片电机包装盒法兰片导管塞、销固定板螺线管滑轮面板基板导轨散热片继电器环辊、轴密封片轴贴片遮光板防护物、盾状物滑块电极插槽、孔托盘、纸盒
部品名称成套工具标签杆连接物、环透镜、镜头灯磁体
BOX BRC BRG BRK BRS BSH CAB CAS CAU CHS CiL CLC CLE CLR CNC COV CRA CUS DAI DTC DUC FiL FiX FRM FSFSH
盒支架、托架轴承制动器刷、刷子衬套、套管盖板、箱盒、箱标签底盘线圈、感应器离合器清洁刮板轴环连接器盖板夹子、夹具衬垫、垫片基座传感器管、输送管键、过滤器控制板机架、框架保险丝定影固定架
价格等级部品等级
AN
D
AN
D
AN
D
AK
C
AB
C
AV
D
AK
C
AP
D
BA
B
AB
C
光学左机壳光学右机壳玻璃固定板遮光垫片螺钉后机壳上 OR 导板稿台玻璃固定板稿台玻璃后机壳上垫片
中文名称
–1–
1 外观1
1 5
3
5 4
25 11
5 5
5
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6
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26 5
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PRP03331
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2 外观2

ATMEL AT24C256B 数据手册

Two-wire Serial EEPROM256K (32,768 x 8)25080D–SEEPR–7/07AT24C256BFigure 1-1.Block Diagram1.Absolute Maximum Ratings*Operating T emperature ..................................−55°C to +125°C *NOTICE:Stresses beyond those listed under “AbsoluteMaximum Ratings” may cause permanent dam-age to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature .....................................−65°C to +150°C Voltage on Any Pinwith Respect to Ground .....................................−1.0V to +5.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA35080D–SEEPR–7/07AT24C256B2.Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices.When the pins are hardwired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capaci-tive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhib-ited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.45080D–SEEPR–7/07AT24C256B3.Memory OrganizationAT24C256B, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64bytes each. Random word addressing requires a 15-bit data word address.Note:1.This parameter is characterized and is not 100% tested.Notes:1.V IL min and V IH max are reference only and are not tested.Table 3-1.Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, SCL)6pFV IN = 0VTable 3-2.DC CharacteristicsApplicable over recommended operating range from: T AI = −40°C to +85°C, V CC = +1.8V to +3.6V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.83.6V I CC1Supply Current V CC = 3.6V READ at 400 kHz 1.0 2.0mA I CC2Supply Current V CC = 3.6V WRITE at 400 kHz 2.0 3.0mA I SB1Standby Current(1.8V option)V CC = 1.8V V IN = V CC or V SS1.0µAV CC = 3.6V 3.0I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)−0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low LevelV CC = 1.8VI OL = 0.15 mA0.2V55080D–SEEPR–7/07AT24C256BNotes:1.This parameter is ensured by characterization and is not 100% tested.2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.5V , 3.6V), 10 k Ω (1.8V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤ 50 nsInput and output timing reference voltages: 0.5 V CCTable 3-3.AC Characteristics (Industrial Temperature)Applicable over recommended operating range from T AI = −40°C to +85°C, V CC = +1.8V to +3.6V, CL = 100 pF (unless oth-erwise noted). Test conditions are listed in Note 2.Symbol Parameter1.8-volt2.5,3.6-volt Units MinMax MinMax f SCL Clock Frequency, SCL 4001000kHz t LOW Clock Pulse Width Low 1.30.4µs t HIGH Clock Pulse Width High 0.60.4µs t i Noise Suppression Time (1)10050ns t AA Clock Low to Data Out Valid 0.050.90.050.55µs t BUF Time the bus must be free before anew transmission can start (1) 1.30.5µs t HD.ST A Start Hold Time 0.60.25µs t SU.ST A Start Set-up Time 0.60.25µs t HD.DA T Data In Hold Time 00µs t SU.DAT Data In Set-up Time 100100ns t R Inputs Rise Time (1)0.30.3µs t F Inputs Fall Time (1)300100ns t SU.STO Stop Set-up Time 0.60.25µs t DH Data Out Hold Time 5050ns t WRWrite Cycle Time 55ms Endurance (1)25°C, Page Mode, 3.3V1,000,000Write Cycles65080D–SEEPR–7/07AT24C256B4.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.Data on the SDA pin may change only during SCL low time periods (see Figure 4-1). Data changes during SCL high periods will indicate a start or stop condition as defined below.Figure 4-1.Data ValiditySTART CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 4-2).Figure 4-2.Start and Stop DefinitionSTOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-ure 4-2).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.STANDBY MODE: The AT24C256B features a low-power standby mode that is enabled uponpower-up and after the receipt of the stop bit and the completion of any internal operations.75080D–SEEPR–7/07AT24C256BSOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed.Figure 4-3.Software ResetFigure 4-4.Bus TimingFigure 4-5.Write Cycle TimingNote:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.85080D–SEEPR–7/07AT24C256BFigure 4-6.Output Acknowledge95080D–SEEPR–7/07AT24C256B5.Device AddressingThe 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5-1). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices.Figure 5-1.Device AddressThe next three bits are the A2, A1, A0 device address bits to allow as many as eight devices onthe same bus. These bits must compare to their corresponding hardwired input pins. The A2,A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read operation is ini-tiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,the device will return to a standby state.DATA SECURITY: The AT24C256B has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at V CC.105080D–SEEPR–7/07AT24C256B6.Write OperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, must then terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6-1).Figure 6-1.Byte WriteNote:* = DON’T CARE bitPAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must termi-nate the page write sequence with a stop condition (see Figure 6-2).Figure 6-2.Page WriteNote:* = DON’T CARE bitThe data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the fol-lowing byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond witha “0”, allowing the read or write sequence to continue.115080D–SEEPR–7/07AT24C256B7.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations:current address read, random address read, and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over”during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 7-1).Figure 7-1.Current Address ReadRANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 7-2).Figure 7-2.Random ReadNote:*= DON’T CARE bit125080D–SEEPR–7/07AT24C256BSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 7-3).Figure 7-3.Sequential Read135080D–SEEPR–7/07AT24C256B8.AT24C256B Ordering CodesNotes:1.“-B” denotes bulk.2.“-T” denotes tape and reel. SOIC = 4K per reel. TSSOP , MAP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K perreel.3.Available in tape & reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Pleasecontact Serial Interface Marketing.Ordering CodeVoltage Package Operation RangeA T24C256B-PU (Bulk Form Only)A T24C256BN-SH-B (1) (NiPdAu Lead Finish)A T24C256BN-SH-T (2) (NiPdAu Lead Finish)A T24C256BW-SH-B (1) (NiPdAu Lead Finish)A T24C256BW-SH-T (2) (NiPdAu Lead Finish)A T24C256B-TH-B (1) (NiPdAu Lead Finish)A T24C256B-TH-T (2) (NiPdAu Lead Finish)A T24C256BY1-YH-T (2) (NiPdAu Lead Finish)A T24C256BY7-YH-T (2) (NiPdAu Lead Finish)A T24C256BU2-UU-T (2) (NiPdAu Lead Finish) 1.81.81.81.81.81.81.81.81.81.88P38S18S18S28S28A28A28Y18Y78U2-1Lead-free/Halogen-free Industrial Temperature (−40°C to 85°C)A T24C256B-W-11 1.8Die SaleIndustrial Temperature (−40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)8S28-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)8U2-18-ball, die Ball Grid Array Package (dBGA2)8A28-lead, 4.40 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y78-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)Options−1.8Low-voltage (1.8V to 3.6V)145080D–SEEPR–7/07AT24C256B9.Packaging Information 8P3 – PDIP155080D–SEEPR–7/07AT24C256B8S1 – JEDEC SOIC165080D–SEEPR–7/07AT24C256B8S2 - EIAJ SOIC175080D–SEEPR–7/07AT24C256B8U2-1 – dBGA2185080D–SEEPR–7/07AT24C256B8A2 – TSSOP195080D–SEEPR–7/07AT24C256B8Y1 – MAP205080D–SEEPR–7/07AT24C256B8Y7 – SAP215080D–SEEPR–7/07AT24C256B10.Revision HistoryDoc. Rev.Date Comments5080D7/2007Updated to new T emplateReplaced Ordering Page with page from A T24C256B5080C 4/2007Deleted NC from Pin ConifigurationsDeleted ISB and MSB from Figures 8, 9, 10, 115080B 12/2006Pg. 12 ordering information- Changed part number from A T24C256BW-10SH-1.8 to A T24C256BW-10SU-1.8Pg. 19- Added 8A2 package drawing Pg. 1- Added 8-lead Ultra Thin SAP in Features and Descriptions- Added 8-lead Ultra Thin SAP package drawing Pg. 12 ordering information-Added new part number A T24C256BY7-10YH-1.8-Add note regarding die sale options -Add 8Y7 package type description -Add 8Y7 package drawing 5080A 9/2004Initial document release5080D–SEEPR–7/07HeadquartersInternationalAtmel Corporation 2325 Orchard Parkway San Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel Asia Room 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Atmel Europe Le Krebs8, Rue Jean-Pierre Timbaud BP 30978054 Saint-Quentin-en-Yvelines Cedex FranceTel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11Atmel Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Product ContactWeb SiteTechnical Support ******************Sales Contact/contactsLiterature Requests /literatureDisclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.© 2007 Atmel Corporation . All rights reserved. Atmel ®, logo and combinations thereof, and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.。

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型号: SRPS20 / SRPS40 / SRPS60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents1法规遵从性FCC 符合性声明FCC A 类信息加拿大工业部欧洲 – 欧盟符合性申明电源2安全准则安全处理安全环境设备处理注意事项数据安全3介绍目标用户盒内物品希捷网络存储功能4系统概览规格前面板视图. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FCC 警告. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 重要注意事项：FCC 辐射暴露声明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 移动设备使用重要事项. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOTE IMPORTANTE pour l'utilisation de dispositifs mobiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 电源. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 电池. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储放置. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 客户端类型. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 存储文件格式. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 许可. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 数据管理. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 存储管理. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 硬盘盒尺寸. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 硬盘盒重量. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 温度范围. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 潮湿. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 电子. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 噪音555556666899999910101012121213131414141415151515212223232324. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .后面板视图USB 端口5系统 LED 指示灯网络存储 LED 指示灯LED 指示灯状态6安装网络存储：含硬盘网络存储：无盘硬盘盒7操作开启/关闭产品开启 NAS 电源关闭网络存储8LCD 菜单（“4-盘位”和“6-盘位”）访问 LCD 显示屏菜单. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储“2-盘位”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储“4-盘位”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储“6-盘位”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储“2-盘位”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储“4-盘位”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储“6-盘位”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 状态和硬盘 LED 指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 网络存储以太网 LED 指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 状态 LED 指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 硬盘 LED 指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 功能 LED 指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 以太网活动 LED 指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 以太网速度 LED 指示灯. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 1 - 连接线. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 连接. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 2 – 开启网络存储. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 3 - 通过远程桌面连接进行连接. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 1 - 连接线. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 连接. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 2 - 插入硬盘. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 3 – 开启网络存储（恢复模式）. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 4 - 安装 Windows Storage Server 2012 R2 Essentials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 步骤 5 - 通过远程桌面连接进行连接. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 短按. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 长按242526272727282930303030313132323233343434343537383939394142434646464747484949. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9软件10硬盘维护注意事项添加/更换硬盘3.5 英寸硬盘2.5 英寸硬盘/固态硬盘11获得帮助故障排除主题12希捷网络存储恢复为恢复做准备执行恢复. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 图 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 图 B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 备份网络存储. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 关闭网络存储. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 找到恢复按钮50515151525355566060626363636363法规遵从性FCC 符合性声明此设备遵守 FCC 规则第 15 部分的要求。

铁电存储FM25640(中文)

The DATASHEET
China Service Center of RAMTRON
absorbed in ferroelectrics professional technology and attentive service
特性
64K位的非易失性铁电随机存储器
l 结构容量为8192*8位 l 100亿次的读写次数 l 在85℃下掉电数据保持10年 l 写数据无延时 l 先进的高可靠的铁电制造工艺
RDSR允许总线控制器验证状态状态寄存器的内容，状态寄存器的内容提供了有关当前写保护的信息，紧跟着 RDSR操作码， FM25640会送出一个字节，包含了当前状态寄存器的内容。状态寄存器的详细内容将在下面的章节中描述。
WRSR-Write Status Register
WRSR 命令允许用户通过向状态寄存器写一个字节来选择特定的写保护状态。在发布一个 WRSR 命令之前，/WP 引脚必须为高电
内存操作
拥有高速时钟频率的SPI接口，增强了FRAM的快写性能，不像 SPI接口的EEPROM，FM25640可以跟随总线速度连续写入数据，不需要页缓冲区，任意连续字节可以被写入。
写操作所有的写操作都必须以写WREN命令为开始，下一个操作码是WRITE指令，这个操作码后面跟随两个字节的地址值，地址的高三位是不关心的，实际上，13个字节的地址指定了写操作的起始地址，连续字节的数据能被连续写入，只要总线控制器连续提供时钟，那么地址是内部递增的。如果到达最后地址1FFFH，那么地址记数器翻转为
与EEPROM不同，FM25640以总线速度进行写操作，无须延时。当数据被移入芯片后，写操作仅需几百个纳秒，下一个总线周期可以立刻开始而无须进行数据轮循。另外，FM25640 具有比其它非易失性存储器高得多的读写操作次数，可以承受超过100亿次的读写操作，这远远超过了一般系统对串行存储器的读写次数要求。

铁电存储器的原理及应用

Ramtron推出首款2兆位串行F-RAM存储器FM25H20类别：新品推荐发布时间：2008-4-17 阅读：879Ramtron推出首款2兆位串行F-RAM存储器，采用8脚TDFN (5.0 x 6.0 mm) 封装。

FM25H20采用先进的130纳米CMOS工艺生产，是高密度的非易失性F-RAM存储器，以低功耗操作，并备有高速串行外设接口(SPI)。

该3V、2Mb串行F-RAM器件以最大的总线速度写入，具有几乎无限的耐用性，通过微型封装提供更大的数据采集能力，使系统设计人员能够在计量和打印机等高级应用中减少成本和板卡空间。

FM25H20是串行闪存的理想替代产品，用于要求低功耗和最小板卡空间的精密电子系统中，包括便携式医疗设备如助听器等，它们实际上是微型数据处理器，但受到空间有限及功耗低的限制。

与闪存相比，F-RAM的优势包括大幅降低工作电流、写入速度更快、写入耐用性更比闪存高出多个数量级。

Ramtron 战略市场拓展经理Duncan Bennett 解释道：“对于那些需要在其新一代应用中提高数据采集能力，却不增加板卡空间的计量和打印机客户而言，这款2Mb 串行F-RAM 是自然的产品延伸。

FM25H20以相同的小占位面积，为半兆位串行F-RAM 客户提供高达四倍的存储能力。

除提升现有系统外，这种技术发展还推动F-RAM 进入多个需要低功耗存储器而空间严重受限的新兴市场，如便携式医疗设备。

”FM25H20是256K x 8位非易失性存储器，以高达40MHz的总线速度进行读写操作，具有几乎无限的耐用性、10年的数据保存能力，以及低工作电流。

该器件设有工业标准SPI接口，优化了F-RAM的高速写入能力。

FM25H20还备有软件和硬件写保护功能，能避免意外的写入与数据损坏。

该2Mb串行F-RAM以低功耗工作，在40MHz下读/写操作的耗电低于10mA，待机状态下耗电为80μA (典型值)，超低电流睡眠模式下耗电为3μA (典型值)。