FPGA可编程逻辑器件芯片10AX066N3F40I2SG中文规格书

ADSP-BF54x Blackfin Processor Hardware Reference
System Reset and Booting
count of the boot stream, but it is not required to have any knowledge about the content of the boot stream. Further information regarding auto-baud detection is given in “Autobaud Mode” on page 10-33.
When the boot kernel is processing fill or initcode blocks it might require extra processing time and needs to hold the host off from sending more data. This is signalled with the HWAIT output as well as by the RTS output. When equipped with a pull-up resistor the HWAIT signal imitates the behavior of an RTS output and could be connected to the CTS input of the booting host. The host is not allowed to send data until HWAIT turns inac-tive after a reset cycle. Therefore a pulling resistor on the HWAIT signal is required.
If the resistor pulls to ground, the host must pause transmission when HWAIT is low and is permitted to send when HWAIT is high. A pull-up resis-tor inverts the signal polarity of HWAIT . The host should test HWAIT at every transmitted byte.
During ADSP-BF54x boot operation, the host device more likely relies on the RTS output of UART1. Then, the use of HWAIT becomes optional. At boot time the Blackfin does not evaluate RTS signals driven by the host and the UART1 CTS input is inactive. Since the RTS is in a high impedance state when the Blackfin processor is in reset or while executing preboot, an external pull-up resistor to VDDEXT is recommended.
Figure 17-28. UART Autobaud Waveform
Memory set associative Cache architecture that limits line placement to a number
of sets (or ways).
tag Upper address bits, stored along with the cached data line, to identify the specific address source in memory that the cached line represents.
valid A state bit, stored with the tag, indicating the corresponding tag and data are current and correct and can be used to satisfy memory access
requests.
victim A dirty cache line that must be written to memory before it can be replaced to free space for a cache line allocation.
Way An array of line storage elements in an N-way cache (see Figure3-4 on page3-15).
write-back A cache write policy, also known as copyback. The write data is written only to the cache line. The modified cache line is written to source memory only when it is replaced. Cache lines are allocated on both reads and writes.
write-through A cache write policy, also known as store through. The write data is written to both the cache line and to the source memory. The modified cache line is not written to the source memory when it is
replaced. Cache lines must be allocated on reads, and may be allocated on writes (depending on mode).
ADSP-BF54x Blackfin Processor Hardware Reference。