KIC9208N中文资料
ks0108中文资料
电子发烧友 电子技术论坛点阵图形液晶显示模块HD61202控制器使用手册目录注意事项----------------------------------------------------------------------------------------------------------------------------2第一章、关于HD61202 及其兼容控制驱动器的一般介绍----------------------------------4一、HD61202 及其兼容控制驱动器的特点-------------------------------------------------------------------------4二、HD61202 及其兼容控制驱动器的引脚功能-------------------------------------------------------------------4三、HD61202 及其兼容控制驱动器的时序-------------------------------------------------------------------------6四、HD61202 及其兼容控制驱动器显示RAM 的地址结构-----------------------------------------------------7五、HD61202 及其兼容控制驱动器的指令系统-------------------------------------------------------------------7第二章：内藏HD61202 及其兼容控制驱动器图形液晶显示模块的电路结构特点-------------------------------------------------------------------------------------9第三章：内藏HD61202 及其兼容控制驱动器图形液晶显示模块的应用用----------------------------------------------------------------11注意事项十分感谢您购买我公司的产品。
Microchip PD69200、PD69210和PD69220 PoE 控制器的LED流接口简介
AN3528BT PoE LED Stream InterfaceIntroductionThe LED stream feature supports IEEE 802.3bt PoE port status LEDs for products based on the Microchip PD69200, PD69210 or PD69220 PoE controllers. The LED stream is a serial bit stream between the PoE Controller, dedicated circuit, and the LED, as shown in the following figure.The shift registers in the dedicated circuit extract the ports LEDs status out of the stream. Up to 48 logical ports are supported.Figure 1. LED Interface ApplicationAN3528 Table of ContentsIntroduction (1)1.Description (3)2.LED Stream Operational Modes (4)2.1.Unicolor Indication Mode (4)2.2.Bicolor Indication Mode (4)3.Detailed Schematics (5)4.Revision History (11)The Microchip Website (12)Product Change Notification Service (12)Customer Support (12)Microchip Devices Code Protection Feature (12)Legal Notice (12)Trademarks (13)Quality Management System (13)Worldwide Sales and Service (14)Description 1. DescriptionThe LED Stream feature is software configurable by individual mask 0x20. See the PD692x0 Serial CommunicationProtocol User Guide for more information.Mask 0x20 comprises three LED parameters:•LED Stream Type: select one of the three serial stream types.–0: LED Stream Disabled—Port indication is disabled.–1: Unicolor LED Stream—Single color led indication is transmitted per logical port.–2: Bicolor LED Stream—Dual color indication is transmitted per logical port.The following table lists a set of commands that sets the LED stream types.Table 1-1. Set Individual Mask 0x20Figure 1-1. Set Individual Mask2. LED Stream Operational ModesThe serial bit of the LED Stream has three operation modes configured via the LED Stream type.The two modes are: Unicolor and Bicolor.2.1 Unicolor Indication ModeLogical port status is indicated by a single color per port LED, typically in green.The LED stream communication data structure is as follow:Figure 2-1. Unicolor Indication48 PortsThe stream data contains 48 bits – a single bit per each logical port.Port#47 data is transmitted first and port #0 data is transmitted last.LEDs indication, corresponding to the logical port status, is described in Table 1-1.2.2 Bicolor Indication ModePort status is indicated by bicolored LED per each logical port, typically in green and yellow).The LED stream serial data structure is as follows.Figure 2-2. Bicolor Indication48p ortsThe serial LED stream supports 48 ports. The ports LEDs state is sent sequentially to all ports, two bits per logicalport, giving a total of 96 bits.Port #47 data is transmitted first and port #0 data is transmitted last.LEDs indication, corresponding to the logical port status, is described in Table 1-1.LED Stream Operational Modes3. Detailed SchematicsFigure 2-1 describes the detailed schematics of the LED stream application for unicolored indication with 24 ports and bicolored indication with 12 ports. The schematic is based on the block diagram shown in Figure 1.Figure 3-1. Bicolored LED Stream Interface with PD692x0The following table lists the bill of material for LED Stream Interface, Bicolored. Table 3-1. Bill of Material for LED Stream Interface, BicoloredRevision History 4. Revision HistoryThe revision history describes the changes that were implemented in the document. The changes are listed byrevision, starting with the most current publication.The Microchip WebsiteMicrochip provides online support via our website at /. This website is used to make files and information easily available to customers. Some of the content available includes:•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software•General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip design partner program member listing•Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representativesProduct Change Notification ServiceMicrochip’s product change notification service helps keep customers current on Microchip products. Subscribers will receive email notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.To register, go to /pcn and follow the registration instructions.Customer SupportUsers of Microchip products can receive assistance through several channels:•Distributor or Representative•Local Sales Office•Embedded Solutions Engineer (ESE)•Technical SupportCustomers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document.Technical support is available through the website at: /supportMicrochip Devices Code Protection FeatureNote the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operatingspecifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Legal NoticeInformation contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets withyour specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.TrademarksThe Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, , Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, , PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial QuadI/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.All other trademarks mentioned herein are property of their respective companies.© 2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.ISBN: 978-1-5224-6309-2Quality Management SystemFor information regarding Microchip’s Quality Management Systems, please visit /quality.Worldwide Sales and Service。
EV14Y36A评测板用户指南说明书
EV14Y36A EV14Y36A Evaluation Board User Guide IntroductionThe EV14Y36A evaluation board is developed based on Microchip’s PD69210 and PD69208 (PD69208M/PD69208T4/PD69204T4) Power over Ethernet (PoE) chipset for use with Microchip’s VSC56xx Ethernet switch development boards. The board operates on 24 4-pair PoE ports (two pairsets) based on the IEEE® 802.3bt specification.Microchip’s PD69208M/PD69208T4/PD69204T4 PoE manager IC integrates power, analog, and state-of-the-art logic into a single 56-pin, plastic QFN package. The device is used in Ethernet switches and midspans/injectors to allow network devices to share power and data over the same Ethernet cable.The PD69208M/PD69208T4 device is an eight-port, and the PD69204T4 device is a four-port, mixed-signal andhigh‑voltage PoE driver. With the PD69210 external MCU, it performs as a Power Sourcing Equipment (PSE) system. Microchip’s PD69210 PoE controller is a cost-effective and pre-programmed MCU designed to implement the Enhanced Mode PoE system.The PD69208M/PD69208T4/PD69204T4 and PD69210 chipset supports PoE Powered Device (PD) detection, power-up, and protection according to IEEE 802.3af/at/bt standards and a legacy/pre-standard PD detection.It provides real-time PD protection through the following mechanisms: overload, under-load, over-voltage, over-temperature, and short circuit, and enables operation in a Standalone mode. It also executes all real-time functions as specified in IEEE 802.3at and IEEE 802.3bt standards, including PD detection (AF and AT).The PD69208M/PD69208T4/PD69204T4 device supports supply voltages between 32 V and 57 V without additional power sources. A system that powers over four pairs is implemented by combining two ports of PD69208M/T4and PD69204T4, enabling an extra feature for simple and low-cost, high-power PD devices. Ongoing monitoring of system parameters for the host software is available through communication. For higher reliability, internal thermal protection is implemented in the chip. The PD69208M/PD69208T4/PD69204T4 is the most integrated PSE IC including internal MOSFET and sense resistor to achieve a low-power dissipation.The PD69210 features an eSPI bus for each PD69208M/PD69208T4/PD69204T4. It is based on the Microchip D21 family. The PD69210 utilizes an I2C or UART interface to the host CPU. It is designed to support the software thatis field-upgradable through the communication interface. The evaluation system provides designers with the required environment to evaluate the performance.The evaluation system has the following features.•Interface to SparX VSC56xx switch development board•Two connector gangs (each contains 12 4-pair ports)•Switch domain isolated from PoE domain•PoE controller manual Reset and serial communication settings•LED status indication for all ports (LED–stream)•Single power source•0 °C to 40 °C operating temperature•RoHS compliantFigure 1. EV14Y36A Evaluation Board and DimensionsFigure 2. EV14Y36A Evaluation System Block DiagramControl Signals:1-Reset2-Ports disableTable of Contents Introduction (1)1.Overview (4)1.1.Power (4)1.2.Interface and Control (5)1.3.LED Indication (8)2.Installation and Settings (9)2.1.Ports Matrix (9)2.2.Fuses (10)2.3.Connectors J7, J9, and J10 (11)2.4.Schematics (11)3.Revision History (12)The Microchip Website (13)Product Change Notification Service (13)Customer Support (13)Microchip Devices Code Protection Feature (13)Legal Notice (14)Trademarks (14)Quality Management System (15)Worldwide Sales and Service (16)1. OverviewThis section provides the basic overview of the EV14Y36A evaluation board.1.1 PowerThe Evaluation Board (EVB) is powered by a single source via the DC connector J8. The input voltage level can be selected according to the IEEE 802.3 PoE standards.•IEEE 802.3af: 44 V DC to 57 V DC•IEEE 802.3at: 50 V DC to 57 V DC•IEEE 802.3bt: 50 V DC to 57 V DC for type 3 and 52 V DC to 57 V DC for type 4.The recommended voltage level is 55 V DC that covers all PoE standards.The EVB has two power domains:•PoE domain, which is fed directly by the main supply, and it is the power domain provided by the J9 and J10 connectors.•Isolated 3.3 V DC, which feeds PD69210, LED-stream, and serial communication peripherals. The isolated 3.3 V DC is generated by motherboard, provided by the J7 connector (a DC/DC module).Note: The EVB DC is polarity sensitive. The correct polarity is shown in the following figure.Important: The DC connector J8 is limited to current level up to 24 A (4 x 6 A per pin). If higher current is needed, the two via holes next to J8 can be used by soldering a cable to it. The two via holes support up to 40 A to feed the whole EVB.Figure 1-1. Power via Holes1.2 Interface and ControlThis section describes the set-up procedures for serial communication, reset push-button, PoE ports disable, and power good input (PGD0–PGD3).1.2.1 Serial Communication SettingsThe EVB supports serial communication with the PD69210 by UART and I2C, to allow a user-friendly experience using Microchip’s dedicated GUI.Two different I2C address can be set by the host:•When the host sets the address pin to 3.3 V (‘1’), the PD69210 I2C address is set to 0x3C.•When the host sets the address pin to 0 V (‘0’), the PD69210 I2C address is set to 0x1C.To change I2C address, R439 should be installed according to the following table (while R411 is not installed). The EVB is set to I2C address 0x3C (R439=7.5K, R441=20K).When R439 and R441 are not installed, the PD69210 is set to UART.The following figure shows I2C address settings.Figure 1-2. I2C Address Settings DiagramTable 1-1. I2C Address Settings1.2.2 Reset Push–button SettingsThe push–button is connected to the Reset pin of the PD69210 (Pin 26). Pressing on switch SW4 connects the Reset pin to GND. The host can reset the board by setting this pin to ‘0’.The following figure shows switch SW4.Figure 1-3. Reset Control Diagram1.2.3 PoE Ports Disable SettingsThe jumper J12 is connected to the Disable pin of the PD69210 (Pin 4). When the jumper J12 is installed, the Disable pin is connected to GND. The host can disable all port by setting this pin to ‘0’.The following figure shows the J12 jumper settings.Figure 1-4. Ports Disable Control Jumper DiagramFigure 1-5. I2C Bus Test Point and Control Signals1.2.4 Power Good Input (PGD0–PGD3) SettingsThe EVB supports feeding from up to four power supplies, which includes 16 power banks (bank0 to bank15). Each power supply must generate a digital signal (3.3 V DC), which indicates the power supply is active. The generateddigital signal must be connected to one of the PGD pins of PD69208 (pins 41, 46, 47, and 56).On the EVB, four PGD pins are pulled–down with a 10K resistor to DGND, which sets the default power bank to0x00. To set a different bank than 0x00, the user can use the PG0-PG3 tests points, located next to U3.Figure 1-6. PGD0-PGD3 Test Points DiagramFigure 1-7. PGD0-PGD3 Test Points1.3 LED IndicationThe following table lists the evaluation board status indication LEDs.Table 1-2. LED List2. Installation and SettingsThis section describes the installation and operation settings of the EV14Y36A evaluation board.Take the following precautions before starting the installation.•Ensure that the power supply of the board is turned off before plugging in the DC connecter.•Ensure the correct polarity of the power supply cable. The polarity of the power supply cable is as shown in Figure 1-1.•Install the EVB into the motherboard using both ports connectors (J9 and J10) and signal connector (J7).•Turn the main supply ON after the DC connector is plugged in.•After turning on the EVB DC power supply, turn on the motherboard power supply.2.1 Ports MatrixEnsure that the ports matrix is configured according to the following table.Table 2-1. Ports Matrix2.2 FusesOn the main board, there are eight fuses for the PD69208, located on top and bottom side, close to the output portconnectors J9 and J10. The fuse is connected on the Vport_Negpin of each port.IEC62368-1 Ed2 (released in October 2018 and effective December 2020) requires per port fuses for a system power supply greater than 250 W.Figure 2-1. Fuses—Top ViewFigure 2-2. Fuses—Bottom ViewImportant: U1 (PD69208T4 #1) is not populated. Therefore, the EVB supports 8 2-pair ports and 16 4-pair ports. The following figure shows the unconnected pins 1, 7, 9, 15, 17, 23, 25, and 31 in J9.Figure 2-3. Unconnected Pins in J92.3Connectors J7, J9, and J10The EV14Y36A EVB contains three connectors that are connected to the host motherboard.•The J7 carries isolated 3.3 V, control signals, communication signals, and the isolated ESPI signals.Figure 2-4. Connector J7 Pinout Diagram•The J9 and J10 carry the 24 PoE ports that have high PoE current.Signals named VPORT_NEG_OUTn and VPORT_NEG_OUT_Un are connected to the physical ports of PD69208.The current can reach up to 1 A.Figure 2-5. Connector J9 Pinout DiagramFigure 2-6. Connector J10 Pinout Diagram2.4 SchematicsThe full schematics of the EVB are available on the Microchip website .Installation and SettingsRevision History 3. Revision HistoryThe Microchip WebsiteMicrochip provides online support via our website at /. This website is used to make files and information easily available to customers. Some of the content available includes:•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software•General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip design partner program member listing•Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representativesProduct Change Notification ServiceMicrochip’s product change notification service helps keep customers current on Microchip products. Subscribers will receive email notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.To register, go to /pcn and follow the registration instructions.Customer SupportUsers of Microchip products can receive assistance through several channels:•Distributor or Representative•Local Sales Office•Embedded Solutions Engineer (ESE)•Technical SupportCustomers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document.Technical support is available through the website at: /supportMicrochip Devices Code Protection FeatureNote the following details of the code protection feature on Microchip devices:•Microchip products meet the specifications contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Attempts to breach these codeprotection features, most likely, cannot be accomplished without violating Microchip’s intellectual property rights.•Microchip is willing to work with any customer who is concerned about the integrity of its code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products.Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act.If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Legal NoticeInformation contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.THIS INFORMATION IS PROVIDED BY MICROCHIP “AS IS”. MICROCHIP MAKES NO REPRESENTATIONSOR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORYOR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.TrademarksThe Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, , Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge,In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, , PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.All other trademarks mentioned herein are property of their respective companies.© 2021, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.ISBN: 978-1-5224-7942-0Quality Management SystemFor information regarding Microchip’s Quality Management Systems, please visit /quality.Worldwide Sales and Service。
Skyworks Solutions SKY77807 四频带LTE电源放大器模块产品概述说明书
PRODUCT SUMMARYSKY77807 Quad-Band Power Amplifier Module for FDD/TDD LTE (Tx Bands 7, 38, 40, 41)Applications•Multi-band 4G handsets •Long Term Evolution (LTE)-Up to 20 MHz bandwidth/ 100resource blocks Features•Envelope Tracking(ET)FDD band•Average Power Tracking (APT) for TDD/FDD bands•50 ohm input/output impedance with internal DC-blocking •Fully programmable Mobile Industry Processor Interface digital control •Continuous bias control for3G/4G PA High Power Mode via MIPI/RFFE interface•Low Supply voltage•Low voltage support (0.6 V) for APT/SMPS applications •Low Leakage current in power-down mode •Temperature Sensor •Integrated TDD TX-Rx switch for single SAW architecture •Low voltage support forAPT/SMPS applications •Small, low profile package-4.0x 3.0x 1.0 (Max.) mm-24-pad configurationDescriptionThe SKY77807Quad-Band Power Amplifier Module (PAM) is a fully matched, 24-pad surface mount module developed for 4G LTE applications. The PAM consists of PA blocks, input and output matching, and a MIPI standard logic control block for multiple power control levels, output input switch control in a single 4.0mm x 3.0mm x 1.0 (Max.)mm package.The SKY77807uses an enhanced architecture to cover multiple bands and meet the spectral linearity requirements of LTE QPSK and 16QAM modulations with up to 20 MHz bandwidth and up to 100 resource block allocations. Output power is controlled by varying the input power and VCC is adjusted using an ET modulator or DCDC converter to maximize efficiency for each power level. Extremely low leakage current maximizes handset standby time.Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100•*********************•203049C• Skyworks Proprietary Information. • Products and product information are subject to change without notice. • January 13, 20141Ordering InformationProduct Name Order Number Evaluation Board Part NumberSKY77807SKY77807© 2013,Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. 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模块化仪器的广泛选择
√ 4-10
2
DAQ
3
PXI
4
模块仪器
5
GPIB及 总线扩展
6
PAC
7
运动控制
8
实时 分布式I/O
9
远程I/O
10
串行通信
型号 模拟输出 DAC分辨率 更新率 输出范围 输出阻抗 偏移范围
标准波形
任意波形存储 采样时钟调制
SYNC/Marker 10MHz基准频率输入 正弦输出 页码
PXI-7921 两线多路
切换器 24（两线） 48（单线）
DPDT(2路C类) 2 A@30 VDC
220VDC,125VAC 50VA,60W 2A
10μA@10mVDC 最大100mΩ 1024步 125次/秒 √ √ 4-19
PXI-7931 4组2x4 两线制矩阵模
块 32（两线） DPDT(2路C类) 2A@30 VDC 220VDC,125VAC 50 VA, 60 W
BNC, SMB 512 MB
±5 V, ±1 V 50 Ω, 1.5 MΩ
30 MHz
<-80 dB, DC to 1MHz BNC, SMB
512 MB, 128 MB
-
2通道(PXI-9820)
√
√
√
√
√
√
√
√
√I-9812(A)/PCI-9810 PCI
4通道 20 MS/s
PXI-9816/9826/9846
简介
凌华科技PXI/PCI-9816/9826/9846是4通道16位10MS/s，20MS/s，40MS/s采样数字化仪，专为输入信号频率高 达20MHz的高频和高动态范围的信号而设计。模拟输入范围可以通过编程设置为±1V/±0.2V或±5V/±0.4V。 配备了容量高达512MB的板载内存的PXI/PCI-9816/9826/9846，摆脱了PCI总线的约束，使之能储存更长时间 的波形。
LM9820CCWM资料
Connection Diagrams
VREFVREFMID VREF+ RefBypass OSR OSG OSB AGND VA SampCLK
1 2 3 4 5 6 7 8 9 10
LM9810 & LM9820
20 19 18 17 16 15 14 13 12 11
DGND VD MCLK D5 D4 D3 D2 (SCLK) D1 (Latch) D0 (SDI) NewLine
Ordering Information
Commercial (0°C ≤ TA ≤ +70°C) LM9810CCWM LM9810CCWMX LM9820CCWM LM9820CCWMX Package 20 Pin Wide SOIC 20 Pin Wide SOIC, Tape & Reel 20 Pin Wide SOIC 20 Pin Wide SOIC, Tape & Reel
Electrical Characteristics
The following specifications apply for AGND=DGND=0V, VA=VD=+5.0VDC, fMCLK=24MHz, Rs=25Ω. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 7, 8, & 12) Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits)
Full Channel Linearity (Note 14) INL DNL Integral Non-Linearity Error (Note 11) Differential Non-Linearity ±0.9 ±0.40 LSB LSB
NI 9208 16通道、±20mA、24位模拟输入模块数据手册说明书
DAT ASHEET NI 920816-Channel, ±20 mA, 24-Bit Analog Input Module•16 channels, current inputs,500 S/s•High-resolution mode with50/60 Hz rejection; Vsuppins for external powerrouting (2 A/30 V max)•±20 mA, 24-bit resolution•250 Vrms, CAT II, channel-to-earth isolation (springterminal); 60 VDC, CAT I,channel-to-earth isolation(DSUB)•DSUB or spring-terminalconnectivity•-40 °C to 70 °C operatingrange, 5 g vibration, 50 gshockThe NI 9208 current input C Series module has 16 channels of ±20 mA input with built-in50/60 Hz rejection for noise rejection.The NI 9208 has a standard 37-pin DSUB connection for use with available cables and connector blocks, or the NI 9937 DSUB connector kit. The NI 9937 contains a DSUB to screw terminal accessory as well as a protective shell. With this kit, you can create a custom cable that plugs directly into the module, eliminating the need for a separate terminal block.Kit ContentsAccessories• NI 9208• NI 9208 Getting Started Guide• NI 9940 Backshell Connector Kit (Spring Terminal)• NI 9923 Screw-Terminal Block (DSUB)NI C Series OverviewNI provides more than 100 C Series modules for measurement, control, and communication applications. C Series modules can connect to any sensor or bus and allow for high-accuracy measurements that meet the demands of advanced data acquisition and control applications.•Measurement-specific signal conditioning that connects to an array of sensors and signals •Isolation options such as bank-to-bank, channel-to-channel, and channel-to-earth ground •-40 °C to 70 °C temperature range to meet a variety of application and environmental needs•Hot-swappableThe majority of C Series modules are supported in both CompactRIO and CompactDAQ platforms and you can move modules from one platform to the other with no modification. CompactRIOCompactRIO combines an open-embedded architecturewith small size, extreme ruggedness, and C Seriesmodules in a platform powered by the NI LabVIEWreconfigurable I/O (RIO) architecture. Each systemcontains an FPGA for custom timing, triggering, andprocessing with a wide array of available modular I/O tomeet any embedded application requirement. CompactDAQCompactDAQ is a portable, rugged data acquisition platformthat integrates connectivity, data acquisition, and signalconditioning into modular I/O for directly interfacing to anysensor or signal. Using CompactDAQ with LabVIEW, youcan easily customize how you acquire, analyze, visualize, andmanage your measurement data.2| | NI 9208 DatasheetSoftwareLabVIEW Professional Development System for Windows•Use advanced software tools for large project development•Generate code automatically using DAQ Assistant and InstrumentI/O Assistant•Use advanced measurement analysis and digital signal processing•Take advantage of open connectivity with DLLs, ActiveX, and .NETobjects•Build DLLs, executables, and MSI installersNI LabVIEW FPGA Module•Design FPGA applications for NI RIO hardware•Program with the same graphical environment used for desktop andreal-time applications•Execute control algorithms with loop rates up to 300 MHz•Implement custom timing and triggering logic, digital protocols, andDSP algorithms•Incorporate existing HDL code and third-party IP including Xilinx IPgenerator functions•Purchase as part of the LabVIEW Embedded Control and MonitoringSuiteNI LabVIEW Real-Time Module•Design deterministic real-time applications with LabVIEWgraphical programming•Download to dedicated NI or third-party hardware for reliableexecution and a wide selection of I/O•Take advantage of built-in PID control, signal processing, andanalysis functions•Automatically take advantage of multicore CPUs or setprocessor affinity manually•Take advantage of real-time OS, development and debuggingsupport, and board support•Purchase individually or as part of a LabVIEW suiteNI 9208 Datasheet| © National Instruments| 3CircuitryV VThe input signals are scanned, amplified, conditioned, and then sampled by a single 24-bit ADC. The module provides overvoltage protection for each channel. Only one channel can be in an overvoltage condition at a time.NI 9208 SpecificationsThe following specifications are typical for the range -40 °C to 70 °C unless otherwise noted.All voltages are relative to COM unless otherwise noted.Caution Do not operate the NI 9208 in a manner not specified in this document.Product misuse can result in a hazard. You can compromise the safety protection built into the product if the product is damaged in any way. If the product is damaged, return it to NI for repair.Input CharacteristicsNumber of channels 16 analog input channels ADC resolution 24 bits Type of ADC Delta-Sigma Sampling mode ScannedInput rangeMinimum ±21.5 mA Typical±22 mA4 | | NI 9208 DatasheetConversion time (per channel)High-resolution mode52 msHigh-speed mode 2 msOvervoltage protection, channel-to-COM±30 V maximum on one channel at a time Vsup pinsCurrent 2 A maximumV oltage30 V maximumInput impedance85 ΩInput noiseHigh-resolution mode50 nArmsHigh-speed mode200 nArmsStabilityGain drift20 ppm/°COffset drift62 nA/°CNMRR (High-resolution mode only)50 Hz66 dB60 Hz68 dBPower RequirementsPower consumption from chassisActive mode282 mW maxSleep mode25 μW maxThermal dissipation (at 70 °C)Active mode 1.29 W maxSleep mode0.72 W max1Range equals 22 mANI 9208 Datasheet| © National Instruments| 5Physical CharacteristicsIf you need to clean the module, wipe it with a dry towel.Tip For two-dimensional drawings and three-dimensional models of the C Seriesmodule and connectors, visit /dimensions and search by module number.Push-in spring-terminal wiringGauge0.14 mm2 to 1.5 mm2 (26 AWG to 16 AWG)copper conductor wireWire strip length10 mm (0.394 in.) of insulation stripped fromthe endTemperature rating90 °C minimumWires per spring terminal One wire per spring terminal; two wires perspring terminal using a 2-wire ferrule Ferrules0.14 mm2 to 1.5 mm2Connector securementSecurement type Screw flanges providedTorque for screw flanges0.2 N · m (1.80 lb · in.)WeightNI 9208 with spring terminal161 g (5.7 oz)NI 9208 with DSUB144 g (5.1 oz)NI 9208 with Spring Terminal Safety VoltagesConnect only voltages that are within the following limits:IsolationChannel-to-channel NoneChannel-to-earth groundContinuous250 Vrms, Measurement Category IIWithstand up to 4,000 m3,000 Vrms, verified by a 5 s dielectricwithstand testMeasurement Category II is for measurements performed on circuits directly connected to the electrical distribution system. This category refers to local-level electrical distribution, such as that provided by a standard wall outlet, for example, 115 V for U.S. or 230 V for Europe.Caution Do not connect the NI 9208 to signals or use for measurements withinMeasurement Categories III or IV.6| | NI 9208 DatasheetNI 9208 with DSUB Safety VoltagesConnect only voltages that are within the following limits:IsolationChannel-to-channel NoneChannel-to-earth groundContinuous60 VDC, Measurement Category IWithstand up to 2,000 m1,000 Vrms, verified by a 5 s dielectricwithstand testMeasurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage. MAINS is a hazardous live electrical supply system that powers equipment. This category is for measurements of voltages from specially protected secondary circuits. Such voltage measurements include signal levels, special equipment, limited-energy parts of equipment, circuits powered by regulated low-voltage sources, and electronics.Caution Do not connect the NI 9208 with DSUB to signals or use formeasurements within Measurement Categories II, III, or IV.Note Measurement Categories CAT I and CAT O are equivalent. These test andmeasurement circuits are not intended for direct connection to the MAINS buildinginstallations of Measurement Categories CAT II, CAT III, or CAT IV. Hazardous LocationsU.S. (UL)Class I, Division 2, Groups A, B, C, D, T4;Class I, Zone 2, AEx nA IIC T4Canada (C-UL)Class I, Division 2, Groups A, B, C, D, T4;Class I, Zone 2, Ex nA IIC T4Europe (ATEX) and International (IECEx)Ex nA IIC T4 GcSafety and Hazardous Locations StandardsThis product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:•IEC 61010-1, EN 61010-1•UL 61010-1, CSA 61010-1•EN 60079-0:2012, EN 60079-15:2010•IEC 60079-0: Ed 6, IEC 60079-15; Ed 4NI 9208 Datasheet| © National Instruments| 7•UL 60079-0; Ed 6, UL 60079-15; Ed 4•CSA 60079-0:2011, CSA 60079-15:2012Note For UL and other safety certifications, refer to the product label or the OnlineProduct Certification section.Electromagnetic CompatibilityThis product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:•EN 61326-1 (IEC 61326-1): Class A emissions; Industrial immunity•EN 55011 (CISPR 11): Group 1, Class A emissions•EN 55022 (CISPR 22): Class A emissions•EN 55024 (CISPR 24): Immunity•AS/NZS CISPR 11: Group 1, Class A emissions•AS/NZS CISPR 22: Class A emissions•FCC 47 CFR Part 15B: Class A emissions•ICES-001: Class A emissionsNote In the United States (per FCC 47 CFR), Class A equipment is intended foruse in commercial, light-industrial, and heavy-industrial locations. In Europe,Canada, Australia and New Zealand (per CISPR 11) Class A equipment is intendedfor use only in heavy-industrial locations.Note Group 1 equipment (per CISPR 11) is any industrial, scientific, or medicalequipment that does not intentionally generate radio frequency energy for thetreatment of material or inspection/analysis purposes.Note For EMC declarations and certifications, and additional information, refer tothe Online Product Certification section.Caution For EMC compliance, operate the NI 9208 with DSUB with shieldedcables.CE ComplianceThis product meets the essential requirements of applicable European Directives, as follows:•2014/35/EU; Low-V oltage Directive (safety)•2014/30/EU; Electromagnetic Compatibility Directive (EMC)•2014/34/EU; Potentially Explosive Atmospheres (ATEX)Online Product CertificationRefer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit /8| | NI 9208 Datasheetcertification, search by model number or product line, and click the appropriate link in the Certification column.Shock and VibrationTo meet these specifications, you must panel mount the system.Operating vibrationRandom (IEC 60068-2-64) 5 g rms, 10 Hz to 500 HzSinusoidal (IEC 60068-2-6) 5 g, 10 Hz to 500 HzOperating shock (IEC 60068-2-27)30 g, 11 ms half sine; 50 g, 3 ms half sine;18 shocks at 6 orientations EnvironmentalRefer to the manual for the chassis you are using for more information about meeting these specifications.Operating temperature-40 °C to 70 °C(IEC 60068-2-1, IEC 60068-2-2)-40 °C to 85 °CStorage temperature(IEC 60068-2-1, IEC 60068-2-2)Ingress protection IP40Operating humidity (IEC 60068-2-78)10% RH to 90% RH, noncondensing Storage humidity (IEC 60068-2-78)5% RH to 95% RH, noncondensing Pollution Degree2Maximum altitudeFor NI 9208 with spring terminal4,000 mFor NI 9208 with DSUB2,000 mIndoor use only.Environmental ManagementNI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.For additional environmental information, refer to the Minimize Our Environmental Impact web page at /environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.NI 9208 Datasheet| © National Instruments| 9Waste Electrical and Electronic Equipment (WEEE) EU Customers At the end of the product life cycle, all NI products must bedisposed of according to local laws and regulations. For more information abouthow to recycle NI products in your region, visit /environment/weee.电子信息产品污染控制管理办法（中国RoHS）中国客户National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。
E2SCA18-7.999M中文资料(ECLIPTEK)中文数据手册「EasyDatasheet - 矽搜」
(5 DigitsMaximum + Decimal)
HC-49/UP
规格如有更改,恕不另行通知.
CR44
.
08/08
包装选择
空白=散装,TR =卷带式
频率
负载电容
S =串联谐振 XX = XXpF并联谐振
动作模式 /水晶切割 A =基本/ AT, B =三次泛音/ AT D =基本/ BT
外形尺寸 ALL DIMENSIONS IN MILLIMETERS
建议焊盘布局 ALL DIMENSIONS IN MILLIMETERS
电气特性
频率范围频率ຫໍສະໝຸດ 差 /稳定性在工作温 度范围
工作温度范围
老化（ 25°C）
存储温度范围
并联电容
绝缘电阻
驱动电平
负载电容（C
)
3.579545MHz为50.000MHz
为±50ppm /±100ppm（标准）,±30ppm/为±50ppm（AT切割只）,±15ppm/±30ppm（AT切割只）,
环境/机械特性
PARAMETER
ESD敏感性
精细泄漏测试 可燃性 总泄漏测试 机械冲击 耐湿性 湿度敏感度 耐焊接热 抗溶剂 可焊性 温度循环 振荡
SPECIFICATION
MIL-STD-883,方法3015,1级,HBM：1500V MIL-STD-883,方法1014,条件A UL94-V0 MIL-STD-883,方法1014,条件C MIL-STD-202,方法213,条件C MIL-STD-883,法1004 J-STD-020, MSL1 MIL-STD-202,方法210,满足条件K MIL-STD-202,方法215 MIL-STD-883,方法2003 MIL-STD-883,方法1010,条件B MIL-STD-883,方法2007条件A
PD69208_AN_211_v1_0
IntroductionThis application note provides detailed information and circuitry design guidelines for the implementation of a 48-port Power over Ethernet (PoE) system, based on Microsemi’s™ PD69208 8-channel or PD69204 4-channel PoE manager and PD69200 PoE Controller. A layout guideline for PoE system based on PD69208 is also included in this document.This document enables designers to integrate PoE capabilities, as specified in IEEE802.3af, IEEE802.3at and PoH standards, into an Ethernet switch.PD69208/4 PoE manager implements real time functions as specified in the standards, including detection, classification, port-status monitoring, and system level activities such as power management and MIB (Management Information Base) support for system management. The PoE manager is designed to detect and disable disconnected PDs (Powered Devices), using DC disconnection methods, as specified in the standards.The PD69208/4 provides PD real time protection through the following mechanisms: overload, under load, over voltage and short-circuit.PD69208/4 share the same design, package and features. The only different between PD69208 and PD69204 is the number of ports.An evaluation board (P/N PD-IM-7648) can be ordered.Applicable Documents♦IEEE 802.3af-2003 standard, DTE Power via MDI♦IEEE802.3at-2009 standard, DTE Power via MDI♦PD69208 and PD69200 datasheet, catalogue number DS_PD69208♦Serial Communication Protocol user guide catalogue number PD63000_UG Features♦IEEE 802.3af-2003 standard compliant♦IEEE802.3at-2009 standard compliant♦Power over HDBasT standard compliant (60W/95W)♦Configurable AT/AF modes♦Configurable standard/tiny cap detection mode♦Supports pre-standard PD detection♦Supports Cisco devices detection♦Single DC voltage input (44 – 57V DC)♦Two & three event classification♦Voltage monitoring/protection♦Low power dissipation♦Internal sense resistor (0.1Ω)♦Internal MOSFET with Low R DS_ON(~0.24Ω)♦Internal power on reset♦Only one external front end component per port♦Includes Reset input from hosting system♦Four direct address configuration pins♦Continuous port monitoring and system data ♦Configurable load current setting♦On-chip thermal protection♦Built in 3.3V DC and 5V DC regulators♦Emergency power management supporting sixteen configurable power banks♦Can be cascaded to up to 12 PoE devices (48 logical ports in 4pairs configuration).♦Supports 4 pair connection♦Wide temperature range: -40° to +85°C MSL1,RoHS compliantaA♦♦2C ♦Isolation Circuit for ESPI bus.ESPI BusThe Enhanced Serial Peripheral Interface (ESPI) bus, used for internal communication, includes the following lines:♦MOSI (Master Out/Slave In) provides communication from PoE Controller toPD69208♦MISO (Master In/Slave Out) provides communication from PD69208 to PoEController♦SCK is the serial clock generated by the Controller♦CS (Chip Select) is utilized by PoE Controller to transmit data simultaneously to allPD69208 ICs, while only chosen PoE managerresponds backControlRefer to Figure 3.♦An xReset_IN control signal driven by Host CPU is used to reset the PoE system♦An xDisable_ports control signal driven by Host CPU is used to disable all PoE ports atonceIndications♦An xSystem_ok signal is generate by The PoE Controller, indicates that the input mainvoltage is within range this pin is determinedby 15 byte serial communication protocol.♦An xInt_out interrupt signal, utilized to indicate PoE events.♦An I2C_Message_Ready indicates signals message is ready to be read by Host Communication FlowHost CPU issues commands, utilizing a dedicated Serial Communication Protocol to the PoE Controller.PoE Controller converts Serial Communication Protocol to ESPI Communication and sends it via isolation is a basic requirement of IEEE PoE standards.Main SupplyPoE system operates within a range of 44 to 57V DC (802.3at port's range is 50 to 57V DC). To comply with UL SELV regulations, maximum output voltage should not exceed 60V DC.GroundsSeveral grounds are utilized in the system.♦PoE Domain Analog♦PoE Domain Digital♦Chassis♦Host Domain FloatingDigital and analog grounds are electrically same ground, however, to reduce noise coupling, grounds are physically separated and connected only at a single point.Chassis ground is connected to switch’s chassis ground. This ground plane should be 1500V rms isolated from PoE circuitry.PoE controller relates to Host domain floating ground which is isolated from PoE domain grounds. 5V DC and 3.3 V DC RegulatorsEach PD69208 has a 5V DC and a 3.3V DC regulators providing up to 6mA each. These currents are utilized for powering components in the PoE domain; those components must also be isolated from the switch circuitry by 1500V rms.An external boost transistor can be added to the 5V DC regulator’s output (instead of R166) to increase the current (see Error! Reference source not found.). The transistor can provide a total of 30mA to the PoE Controller and to the isolation circuits. This total current is the sum of the 5V and 3.3V currents.Detailed Circuit DescriptionThere are two control lines driven by Host CPU to PoE Controller:PoE Controller Circuitry Refer to Figure 8.LED support for port status indication is accomplished by utilizing the ESPI bus (SCK andBus behavior is 1Mhz synchronous serial communication (clock, data) in one direction (write is not used, the pin must be connected to GND or VDD. Figure 5 illustrates the connections between power supplies’ logic signals and PoE Manager.222120192423MSC PD69208DATE CODEFigure 6: 8-ports Front End componentsshould use a 2C R93.( Figure 8) This resistor sets the analog level into pin #22 (I2C_ADDR_Meas_ADC0), as specified in the following table.configuration process is further explained in the not theCopyright © 2015 MicrosemiPage 11 of 23Rev. 1.0, 05 Jan 2015Analog Mixed Signal GroupOne Enterprise Aliso Viejo, CA 92656 USACONFIDENTIALTable 2: Main Block Components***Fuses per port are not required for use in circuits with total power level of up to 3kW. That's because PD69208 is UL 2367 (category QVRQ2) recognized component and fulfills limited power source (LPS) requirements of latest editions of IEC60950-1 and EN60950-1.Figure 17: Output Ports Design DetailsLayout GuidelinesMicrosemi’s PD69208 PoE Manager is designed to simplify the integration of PoE-circuitry, based on the IEEE PoE standards, into switches. The pin-out arrangement has been configured for optimal PCB routing.Figure 18 describes the various circuits and elements surrounding the PD69208 PoE Manager in the block diagram. This block diagram includes the following peripheral elements, identified by numbers:♦5 V Voltage source (V AUX5) (1)♦ 3.3 V Voltage source (V AUX3P3) (2)♦Power Good Inputs (3)♦Output capacitor used for filtering (4)♦ESPI Bus, ESPI Address Lines (5)Note The V AUX5supply may include an external transistor connected to pin 20, destined to increase current drive for external circuitry. To prevent heat from being transferred to the PD69208, place this transistor away from the PoE Managers. Locating PoE Circuitry in a SwitchTo minimize the length of high current traces, as well as RFI pick-up, place the PoE circuitry as close as possible to the switch’s pulse transformers. The circuit can be fully integrated into the switch’s PCB, or can be easily placed on top of the switch's using daughter board. Typical integration of PoE modules inside a switch is shown in Error! Reference source not found.and Error! Reference source not found.Ground and Power PlanesSince the PoE solution is a mixed-signal (analog and digital) circuitry, special care must be taken when routing the ground and power signals lines. The reference design assumes a four layer board: top, mid1, mid2, bottom. The main planes are Vmain/AGND, DGND.Ground planes are crucial for proper operation and should be designed in accordance with the following guidelines, as illustrated in Error! Reference source not found.:♦Separate analog and digital grounds, with a gap of at least 40 mils♦Analog ground plane (AGND) is utilized to transfer the heat generated by thePD69208 (see Thermal Pad Definition andDesign).♦The AGND should be located on external layer♦Earth ground is used to tie in the metal frame of the RJ-45 connectors. This groundis to be routed separately and connected tothe s witch’s metal chassis/enclosure♦To prevent ground loop currents, use onlya single connection point between thedigital and analog grounds as shown inError! Reference source not found.♦To connect various DGND points and to enable stable impedance to the ESPI bustraces, extend the digital ground (DGND)surface under pins 41 – 56 of the PD69208Managers♦ A focal interconnection point for the digital and analog grounds should be located atabout the middle of the overlappingsection♦Leave spacing for a ceramic 1 nF bypass capacitor + two parallel and inversedSchottky diodes near each PoE Manager(Error!between the analog and digital layers. Thecapacitors form low impedance paths fordigital driving signals♦The power and return (ground) planes for the 48V supply must be designed to carrythe system maximum continuous current,based on the design capacity. Minimize DCpower losses on these planes by using awide copper lands. When implementingthe PoE circuitry on a daughter board, thehigh current does not have to be routedthrough the daughter board but only thereturn path as can be note from Figure 19 Current Flow through the PoE applicationSee Figure 19The port's DC current flows in an application utilizing a PoE daughter board (DB) as follow:1. Coming from the switch's power supply positive to the center taps of the line transformer via a mother board wide trace (not through the DB)2. From the center tap of the line transformer via the switch's RJ45 to the PD side3. The return current from the PD flows via the RJ45 and the line transformer to the DB PoE circuitry.4. From the DB analog ground (AGND) the current flows back to the switch's power supply negative via harnessNote The positive port's heavy current flows directly to the PD side without going through the PoE Managers on the DB.Specific Component PlacementPeripheral ComponentsTo minimize heat transfer among various components a gap between them should be maintained. The following are suggested gaps however any gap can be used as long as the designer monitors the thermal performance during the design and follows the maximum temperatures allowed at the various components. ♦Minimum gap between PD69208 ICs should be 50mm♦Minimum gap between PD69208 to PoE controller should be 30mm♦Minimum gap between PD69208 to NPN transistor regulator (if used) should be50mm.PoE Controller and PeripheralsRefer to the Freescale Semiconductor MKL15Z128VFM4 Data Sheet, for recommendations related to the PoE controller layout guidelines.The following guidelines are destined for the integration of the PoE Controller into a PoE circuit.♦Locate the filtering capacitors for VDD and for VDDA close to power and ground pins.♦Termination resistors for the outgoing ESPI digital lines should be located close to therespective driving pins.PD69208 PoE Manager and Peripherals♦The side of the PoE Manager that includes pins 41 to 56 should face the digital ground(DGND plane.) The pins function ascommunication and control pins for theManager (connect between the PoEManager and the PoE controller viaisolation circuitry)♦Locate theManager supply input close to the relevantpin. In cases where two bypass capacitorsare placed on the same line, locate thelower value capacitor closer to the pin onthe same layer and place the higher valuecapacitor at a more distant location.♦Locate VAUX5 and VAUX3P3 0.1 µF and4.7 µF filtering capacitors as close aspossible to the PoE Manager pins 20 and22 respectively.Vmain CapacitorsIt's a good design to have 3 x 47uF capacitors over Vmain in order to prevent noise and spikes events to penetrant into Vmain rail.(note 4 Figure 7). Conductor RoutingGeneral GuidelinesConductor (or printed lands) routing is to be performed as practiced in general layout guidelines, specifically:♦Conductors that deliver a digital signal are to be routed between the analog and thedigital ground planes.♦Avoid routing analog signals above the digital ground.Specific Requirements for Clock and Sensitive SignalsIssues that require special design considerations: ♦The IREF resistor (connects to pin 24), used for current reference, is directly connectedpath.♦Carefully route the ESPI communication clock (SCK) line coming from the PoEController so that it will not disturb otherlines. Two ground lines (connected toDGND) could be routed alongside the clockline to isolate it from the rest of the lines. Port OutputsFor robust design, the ports output traces are to be 45-mil wide so as to handle maximum current and port power.♦H owever to obtain a 10° C (maximum) copper rise under 0.6A per port, set the minimum width for traces in accordance with the layer location and copper thickness:♦F or two ounce copper, external layer: 15 mils♦F or two ounce copper, internal layer: 20 mils♦F or one ounce copper, external layer: 25 mils♦F or one ounce copper, internal layer: 30 mils♦F or 1/2 ounce copper, external layer: 30 mils♦F or 1/2 ounce copper, internal layer: 55 mils (20° C copper rise)♦T he ports output traces must be short and parallel to each other, to reduce RFI pickup and to keep the series resistance low.♦T he PoE ports outputs must be connected to the switch’s pulse transformers as shown in Figure 17. The common mode choke and ‘Bob-Smith’ termination (resistor-capacitor) to chassis ground are optional and used to reduce RFI noise. The circuit is to be located as close as possible to the pulse transformer.Thermal Pad Definition and DesignThe PD69208 utilizes a thermal dissipation exposed pad in a 56-pin 8 x 8 mm QFN package. The package isFor proper heat dissipation, the following footprint / layout guidelines must be followed:All thermal vias are to be connected to the AGND area under the PD69208♦Via diameterinto the vias from the component side can result in voids during the solder process and this must be avoided.A。
SEMIKRON ESD9L系列电路保护扇形电阻说明书
ESD9L, SESD9L Series Transient Voltage SuppressorsESD Protection Diodes with Ultra−Low CapacitanceThe ESD9L Series is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications.Specification Features:•Ultra Low Capacitance 0.5 pF •Low Clamping V oltage•Small Body Outline Dimensions:0.039″ x 0.024″(1.00 mm x 0.60 mm)•Low Body Height: 0.016″ (0.4 mm)•Stand−off V oltage: 3.3 V , 5 V •Low Leakage•Response Time is Typically < 1.0 ns •IEC61000−4−2 Level 4 ESD Protection•S and SZ Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101Qualified and PPAP Capable•These Devices are Pb−Free and are RoHS CompliantMechanical Characteristics:CASE: V oid-free, transfer-molded, thermosetting plasticEpoxy Meets UL 94 V−0LEAD FINISH: 100% Matte Sn (Tin)MOUNTING POSITION: AnyQUALIFIED MAX REFLOW TEMPERATURE: 260°CDevice Meets MSL 1 RequirementsMAXIMUM RATINGSRatingSymbolValue Unit IEC 61000−4−2 (ESD)ContactAir±10±15kVTotal Power Dissipation on FR−5 Board (Note 1) @ T A = 25°C P D 150mW Storage Temperature Range T stg −55 to +150°CJunction Temperature Range T J −55 to +150°C Lead Solder Temperature − Maximum(10 Second Duration)TL 260°CStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.1.FR−5 = 1.0 x 0.75 x 0.62 in.See Application Note AND8308/D for further description of survivability specs.Device PackageShipping †ORDERING INFORMATIONSOD−923CASE 514ABESD9LxxxST5G SOD−923(Pb−Free)8000/T ape & Reel MARKING DIAGRAMSee specific marking information in the device marking column of the Electrical Characteristics tables starting on page 2 of this data sheet.DEVICE MARKING INFORMATION†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.X = Specific Device Code M = Date Code*Date Code orientation and/or position may vary depending upon manufacturing location.PIN 1.CATHODE2.ANODE12122SESD9LxxxST5G SOD−923(Pb−Free)8000/T ape & Reel SZESD9LxxxST5GSOD−923(Pb−Free)8000/T ape & ReelELECTRICAL CHARACTERISTICS(T A = 25°C unless otherwise noted)Symbol ParameterI PP Maximum Reverse Peak Pulse Current V C Clamping Voltage @ I PP V RWM Working Peak Reverse VoltageI R Maximum Reverse Leakage Current @ VRWM V BR Breakdown Voltage @ I T I T Test Current I F Forward Current V F Forward Voltage @ I F P pk Peak Power DissipationCMax. Capacitance @ V R = 0 and f = 1.0 MHz*See Application Note AND8308/D for detailed explanations of datasheet parameters.ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted, V F = 1.0 V Max. @ I F = 10 mA for all types)Device*Device Marking V RWM (V)I R (m A)@ VRWM V BR (V) @ I T (Note 2)I T C (pF)V C (V)@ I PP = 1 AV CMax Max Min mA Typ Max Max Per IEC61000−4−2(Note 4)ESD9L3.3ST5G 6** 3.3 1.0 4.8 1.00.50.99.0Figures 1 and 2See Below ESD9L5.0ST5GD5.01.05.41.00.50.99.8Figures 1 and 2See Below*Includes S and SZ-prefix devices where applicable.**Rotated 180°.2.V BR is measured with a pulse test current I T at an ambient temperature of 25°C.3.Surge current waveform per Figure 5.4.For test procedure see Figures 3 and 4 and Application Note AND8307/D.Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2IEC 61000−4−2 Spec.Level Test Volt-age (kV)First Peak Current (A)Current at 30 ns (A)Current at 60 ns (A)127.5422415843622.51264830168IEC61000−4−2 WaveformFigure 3. IEC61000−4−2 SpecOscilloscopeThe following is taken from Application NoteAND8308/D − Interpretation of Datasheet Parameters for ESD Devices.ESD Voltage ClampingFor sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for largersystems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.Figure 5. 8 X 20 ms Pulse Waveform1009080706050403020100t, TIME (m s)% O F P E A K P U L S E C U R R E N TPACKAGE DIMENSIONSSOD−923CASE 514AB ISSUE CNOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.4.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.DIM MIN NOM MAX MILLIMETERS A 0.340.370.40b 0.150.200.25c 0.070.120.17D 0.750.800.85E 0.550.600.650.95 1.00 1.05L 0.19 REF H E 0.0130.0150.0160.0060.0080.0100.0030.0050.0070.0300.0310.0330.0220.0240.0260.0370.0390.0410.007 REFMIN NOM MAX INCHEScADIMENSIONS: MILLIMETERS*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*See Application Note AND8455/D for more mounting details 2X0.252XOUTLINE2X0.08X YTOP VIEW2XBOTTOM VIEWL2XL20.050.100.150.0020.0040.006ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent PUBLICATION ORDERING INFORMATION。
Analog Devices ADTL082A ADTL082J ADTL084J 双通道操作电路模
Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.引脚配置OUT A1–IN A2+IN A3–V4+V8OUT B7–IN B6+IN B5ADTL082JTOP VIEW(Not to Scale)6275-1OUT A1–IN A2+IN A3–V4+V8OUT B7–IN B6+IN B5ADTL082ATOP VIEW(Not to Scale)6275-2OUT A1–IN A2+IN A3+V4OUT D14–IN D13+IN D12–V11+IN B5+IN C10–IN B6–IN C9OUT B7OUT C8ADTL084JTOP VIEW(Not to Scale)6275-3ADTL084A1234567–IN A+IN A+VOUT B–IN B+IN BOUT A141312111098–IN D+IN D–VOUT C–IN C+IN COUT DTOP VIEW(Not to Scale)6275-4低成本、JFET输入运算放大器ADTL082/ADTL084产品特性TL082/TL084兼容低输入偏置电流：10 pA(最大值)失调电压5.5 mV(最大值，ADTL082A/ADTL084A)9 mV(最大值，ADTL082J/ADTL084J)工作电压：±15 V低噪声：16 nV/√Hz宽带宽：5 MHz压摆率：20 V/μs共模抑制比(CMRR)：80 dB(最小值)总谐波失真： 0.001%电源电流：1.2 mA(典型值)单位增益稳定应用通用放大功率控制和监测有源滤波器工业/过程控制数据采集采样保持电路积分器输入缓冲图1. 8引脚SOIC_N(R-8)图2. 8引脚MSOP(RM-8)图3. 14引脚SOIC_N(R-14)图4. 14引脚TSSOP(RU-14)概述ADTL082和ADTL084均为具有业界领先性能的JFET输入放大器，其性能优于TL08x器件。
MURATA LQW18AN_00系列芯片电容器（芯片电感）产品说明书
SpecNo.JELF243A-0024Y-01 P.1/11Reference OnlyCHIP COIL (CHIP INDUCTORS) LQW18AN □□□□00D REFERENCE SPECIFICATION1.ScopeThis reference specification applies to LQW18AN_00 series, Chip coil (Chip Inductors).2.Part Numbering(ex) LQ W 18 A N 2N2 D 0 0 DProduct ID Structure Dimension Applications Category Inductance Tolerance Features Electrode Packaging(L×W) andD:Taping Characteristics*B:Bulk *Bulk packing also available. (A product is put in the plastic bag under the taping conditions.)3.Rating・Operating Temperature Range. –55°C to +125°C ・Storage Temperature Range. –55°C to +125°CCustomer Part NumberMURATA Part NumberInductance Q (min.)DC Resistance (Ω max.)Self Resonant Frequency (MHz min.)Rated Current (mA)(nH)ToleranceLQW18AN2N2D00D 2.2D:±0.5nH 160.042 6000700LQW18AN3N6C00D 3.6C:±0.2nH D:±0.5nH250.059 850LQW18AN3N6D00D LQW18AN3N9C00D 3.935LQW18AN3N9D00D LQW18AN4N3C00D 4.3 LQW18AN4N3D00D LQW18AN4N7D00D 4.7D:±0.5nHLQW18AN5N6C00D 5.6C:±0.2nH D:±0.5nH0.082 750LQW18AN5N6D00D LQW18AN6N2C00D 6.2 LQW18AN6N2D00D LQW18AN6N8C00D 6.8 LQW18AN6N8D00D LQW18AN7N5C00D 7.5 LQW18AN7N5D00D LQW18AN8N2C00D 8.20.11 650LQW18AN8N2D00D LQW18AN8N7C00D 8.7 LQW18AN8N7D00D LQW18AN9N1C00D 9.1 LQW18AN9N1D00D LQW18AN9N5D00D 9.5D:±0.5nHLQW18AN10NG00D 10G:±2% J:±5%LQW18AN10NJ00D LQW18AN11NG00D 11 LQW18AN11NJ00D LQW18AN12NG00D 120.13 600LQW18AN12NJ00D LQW18AN13NG00D 13 LQW18AN13NJ00D LQW18AN15NG00D 1540 LQW18AN15NJ00D LQW18AN16NG00D 160.165500550LQW18AN16NJ00D LQW18AN18NG00D 18 LQW18AN18NJ00D LQW18AN20NG00D 204900LQW18AN20NJ00D LQW18AN22NG00D 220.17 4600 500LQW18AN22NJ00DSpecNo.JELF243A-0024Y-01 P.2/11Reference OnlyCustomerPart NumberMURATA Part NumberInductance Q (min.)DC Resistance (Ω max.)Self Resonant Frequency (MHz min.)Rated Current (mA)(nH)ToleranceLQW18AN24NG00D 24 G:±2%J:±5%400.213800 500LQW18AN24NJ00D LQW18AN27NG00D 27 3700 440 LQW18AN27NJ00D LQW18AN30NG00D 300.23 3300420LQW18AN30NJ00D LQW18AN33NG00D 33 3200 LQW18AN33NJ00D LQW18AN36NG00D 360.26 2900400LQW18AN36NJ00D LQW18AN39NG00D 39 2800 LQW18AN39NJ00D LQW18AN43NG00D 430.292700380LQW18AN43NJ00D LQW18AN47NG00D 47382600 LQW18AN47NJ00D LQW18AN51NG00D 51 0.33 2500 370LQW18AN51NJ00D LQW18AN56NG00D 56 0.35 2400 360LQW18AN56NJ00D LQW18AN62NG00D 62 0.51 2300 280LQW18AN62NJ00D LQW18AN68NG00D 68 0.38 2200 340 LQW18AN68NJ00D LQW18AN72NG00D 72340.56 2100270LQW18AN72NJ00D LQW18AN75NG00D 75 2050LQW18AN75NJ00D LQW18AN82NG00D 82 0.60 2000 250LQW18AN82NJ00D LQW18AN91NG00D 91 0.64 1900 230 LQW18AN91NJ00D LQW18ANR10G00D 1000.68 1800 220 LQW18ANR10J00D LQW18ANR11G00D 110321.2 1700 200 LQW18ANR11J00D LQW18ANR12G00D 120 1.3 1600 180 LQW18ANR12J00D LQW18ANR13G00D 130 1.4 1450 170 LQW18ANR13J00D LQW18ANR15G00D 150 1.5 1400 160 LQW18ANR15J00D LQW18ANR16G00D 1602.1 1350 150 LQW18ANR16J00D LQW18ANR18G00D 18025 2.2 1300 140 LQW18ANR18J00D LQW18ANR20G00D 200 2.4 1250120LQW18ANR20J00D LQW18ANR22G00D 220 2.5 1200LQW18ANR22J00D LQW18ANR27G00D 270303.4 960 110 LQW18ANR27J00D LQW18ANR33G00D 3305.580085LQW18ANR33J00D LQW18ANR39G00D 390 6.2 80 LQW18ANR39J00D LQW18ANR47G00D 4707.0 700 75LQW18ANR47J00DSpecNo.JELF243A-0024Y-01 P.3/11Reference Only4. Testing Conditions《Unless otherwise specified》《In case of doubt》Temperature : Ordinary Temperature / 15°C to 35°C Temperature: 20°C±2°CHumidity : Ordinary Humidity / 25%(RH) to 85%(RH) Humidity : 60%(RH) to 70%(RH)Atmospheric Pressure : 86kPa to 106 kPa5.Appearance and Dimensions■Unit Mass (Typical value)0.003g(in mm).Reference OnlySpecNo.JELF243A-0024Y-01 P.4/11SpecNo.JELF243A-0024Y-01 P.5/11Reference Only8.Environmental Performance It shall be soldered on the substrate.No. Item Specification Test Method 8.1 Heat Resistance Appearance:No damage Inductance Change: within ±5% Q Change: within ±20% Temperature:125°C±2°CTime:1000h (+48h,0h) Then measured after exposure in the room condition for 24h±2h.8.2 Cold Resistance Appearance:No damage Inductance Change: within ±5% Q Change: within ±20%Temperature:-55°C±2°CTime:1000h (+48h,-0h) Then measured after exposure in the roomcondition for 24h±2h.8.3 Humidity Temperature:40°C±2°CHumidity:90%(RH) to 95%(RH) Time:1000h (+48h,-0h)Then measured after exposure in the room condition for 24h±2h.8.4 Temperature Cycle 1 cycle:1 step:-55°C±2°C / 30min±3 min2 step:Ordinary temp. / 10min to 15 min3 step:+125°C±2°C / 30min±3 min4 step:Ordinary temp. / 10min to15 min Total of 10 cyclesThen measured after exposure in the room condition for 24h±2h.9.Specification of Packaging9.1 Appearance and Dimensions of paper tape (8mm-wide)(in mm)9.2 Specification of Taping(1) Packing quantity (standard quantity)4,000 pcs. / reel(2) Packing MethodProducts shall be packed in the cavity of the base tape and sealed by top tape and bottom tape. (3) Sprocket holeThe sprocket holes are to the right as the tape is pulled toward the user. (4) Spliced pointBase tape and Top tape has no spliced point. (5) Missing components numberMissing components number within 0.1 % of the number per reel or 1 pc., whichever is greater, and are not continuous. The Specified quantity per reel is kept.9.3 Pull StrengthTop tape 5N min.Bottom tape4.0±0.1φ1.5±2.0±0.054.0±0.1Direction of feed1.1max.1.0±0.051.8±0.058.0±0.23.5±0.051.75±0.10.10SpecNo.JELF243A-0024Y-01 P.6/11Reference Only9.4 Peeling off force of cover tapeSpeed of Peeling off 300mm/min Peeling off force0.1N to 0.6N(minimum value is typical)9.5 Dimensions of Leader-tape,Trailer and ReelThere shall be leader-tape ( top tape and empty tape) and trailer-tape (empty tape) as follows.9.6 Marking for reelCustomer part number, MURATA part number, Inspection number(∗1) ,RoHS Marking (∗2), Quantity etc ･･･∗1) <Expression of Inspection No.> □□ OOOO ×××(1) (2) (3)(1) Factory code(2) Date First digit: Year / Last digit of yearSecond digit: Month / Jan. to Sep. → 1 to 9, Oct. to Dec. → O, N, D Third, Fourth digit : Day(3) Serial No.∗2) <Expression of RoHS Marking >ROHS – Y (△)(1) (2)(1) RoHS regulation conformity parts.(2) MURATA classification number9.7 Marking for Outside package (corrugated paper box)Customer name, Purchasing order number, Customer part number, MURATA part number, RoHS Marking (∗2) ,Quantity, etc ･･･9.8. Specification of Outer CaseOuter Case Dimensions(mm)Standard Reel Quantityin Outer Case (Reel)W D H 186 186 93 5∗ Above Outer Case size is typical. It depends on a quantity of an order.10. ！ CautionLimitation of ApplicationsPlease contact us before using our products for the applications listed below which require especially high reliability for the prevention of defects which might directly cause damage to the third party's life, body or property.(1) Aircraft equipment (6) Transportation equipment (vehicles, trains, ships, etc.) (2) Aerospace equipment (7) Traffic signal equipment (3) Undersea equipment (8) Disaster prevention / crime prevention equipment (4) Power plant control equipment (9) Data-processing equipment (5) Medical equipment (10) Applications of similar complexity and /or reliability requirements to the applications listed in the aboveF165to 180degreeTop tapeBottom tape Base tapeWDLabelHSpecNo.JELF243A-0024Y-01 P.7/11Reference Only11. NoticeProducts can only be soldered with reflow.This product is designed for solder mounting.Please consult us in advance for applying other mounting method such as conductive adhesive.11.1 Land pattern designingRecommended land patterns for reflow soldering are as follows:These have been designed for Electric characteristics and solderability.Please follow the recommended patterns. Otherwise, their performance which includes electrical performance or solderability may be affected, or result to "position shift" in soldering process.(in mm)11.2 Flux, Solder・Use rosin-based flux.Includes middle activator equivalent to 0.06(wt)% to 0.1(wt)% Chlorine.Don’t use highly acidic flux with halide content exceeding 0.2(wt)% (chlorine conversion value). Don’t use water-soluble flux. ・Use Sn-3.0Ag-0.5Cu solder.・Standard thickness of solder paste : 100μm to 150μm.11.3 Reflow soldering conditions・Pre-heating should be in such a way that the temperature difference between solder and product surface is limited to 150°C max. Cooling into solvent after soldering also should be in such a way that the temperature difference is limited to 100°C max.Insufficient pre-heating may cause cracks on the product, resulting in the deterioration of products quality.・Standard soldering profile and the limit soldering profile is as follows.The excessive limit soldering conditions may cause leaching of the electrode and / or resulting in the deterioration of product quality.・Reflow soldering profileStandard Profile Limit Profile Pre-heating 150°C ～180°C 、90s ±30s Heating above 220°C ､30s ～60s above 230°C ､60s max. Peak temperature 245°C ±3°C 260°C,10s Cycle of reflow 2 times 2 timesA 0.6 to 0.8B 1.9 to 2.0 C0.7 to 1.0Limit ProfileStandard Profile90s±30s230℃260℃245℃±3℃220℃30s ～60s60s max.180150Temp.(s)(℃)Time.resistSpecNo.JELF243A-0024Y-01 P.8/11Reference Only11.4 Reworking with soldering ironThe following conditions must be strictly followed when using a soldering iron.Pre-heating 150°C,1 min Tip temperature 350°C max. Soldering iron output 80W max. Tip diameter φ3mm max. Soldering time 3(+1,-0)sTime 2 timesNote :Do not directly touch the products with the tip of the soldering iron in order to prevent thecrack on the products due to the thermal shock.11.5 Solder Volume・Solder shall be used not to be exceeded the upper limits as shown below.・Accordingly increasing the solder volume, the mechanical stress to Chip is also increased. Exceeding solder volume may cause the failure of mechanical or electrical performance.1/3T ≦t ≦TT ：thickness of product11.6 Product’s locationThe following shall be considered when designing and laying out P.C.B.'s.(1) P.C.B. shall be designed so that products are not subject to the mechanical stress due to warping the board.［Products direction ］Products shall be located in the sidewaysdirection (Length:a ＜b) to the mechanical stress.(2) Components location on P.C.B. separation.It is effective to implement the following measures, to reduce stress in separating the board.It is best to implement all of the following three measures; however, implement as many measures as possible to reduce stress.Contents of MeasuresStress Level (1) Turn the mounting direction of the component parallel to the board separation surface. A > D *1 (2) Add slits in the board separation part.A >B (3) Keep the mounting position of the component away from the board separation surface. A > C*1 A > D is valid when stress is added vertically to the perforation as with Hand Separation.If a Cutting Disc is used, stress will be diagonal to the PCB, therefore A > D is invalid.〈Poor example〉〈Good example〉baSeamSlitADBCbaLength:a <bReference OnlySpecNo.JELF243A-0024Y-01 P.9/11(3) Mounting Components Near Screw HolesWhen a component is mounted near a screw hole, it may be affected by the board deflection that occurs duringthe tightening of the screw. Mount the component in a position as far away from the screw holes as possible.11.7 Cleaning ConditionsProducts shall be cleaned on the following conditions.(1) Cleaning temperature shall be limited to 60°C max.(40°C max for IPA)(2) Ultrasonic cleaning shall comply with the following conditions with avoiding the resonancephenomenon at the mounted products and P.C.B.Power : 20 W / l max. Frequency : 28kHz to 40kHz Time : 5 min max.(3) Cleaner1. Alcohol type cleanerIsopropyl alcohol (IPA)2. Aqueous agentPINE ALPHA ST-100S(4) There shall be no residual flux and residual cleaner after cleaning.In the case of using aqueous agent, products shall be dried completely after rinse with de-ionizedwater in order to remove the cleaner.(5) Other cleaning Please contact us.11.8 Resin coatingThe inductance value may change due to high cure-stress of resin to be used for coating/molding products.An open circuit issue may occur by mechanical stress caused by the resin, amount/cured shape of resin, oroperating condition etc. Some resin contains some impurities or chloride possible to generate chlorine byhydrolysis under some operating condition may cause corrosion of wire of coil, leading to open circuit.So, please pay your careful attention in when you select resin in case of coating/molding the productswith the resin.Prior to use the coating resin, please make sure no reliability issue is observed by evaluating productsmounted on your board.11.9 Caution for use・Sharp material such as a pair of tweezers or other material such as bristles of cleaning brush , shall not be touched to the winding portion to prevent the breaking of wire.・Mechanical shock should not be applied to the products mounted on the board to prevent the breaking of the core.11.10 Notice of product handling at mountingIn some mounting machines,when picking up components support pin pushes up the components from thebottom of base tape. In this case, please remove the support pin. The support pin may damage the componentsand break wire.In rare case ,the laser recognition can not recognize this component. Please contact us when you use laserrecognition. (There is no problem with the permeation and reflection type.)11.11 Handling of a substrateAfter mounting products on a substrate, do not apply any stress to the product caused by bending or twisting to thesubstrate when cropping the substrate, inserting and removing a connector from the substrate or tightening screwto the substrate.Excessive mechanical stress may cause cracking in the product.Bending TwistingReference OnlySpecNo.JELF243A-0024Y-01 P.10/1111.12 Storage and Handing Requirements(1) Storage periodUse the products within 12 months after delivered.Solderability should be checked if this period is exceeded.(2) Storage conditions・Products should be stored in the warehouse on the following conditions.Temperature ：-10°C to 40°CHumidity ：15% to 85% relative humidity No rapid change on temperature and humidity・Don't keep products in corrosive gases such as sulfur,chlorine gas or acid, or it may causeoxidization of electrode, resulting in poor solderability.・Products should not be stored on bulk packaging condition to prevent the chipping of thecore and the breaking of winding wire caused by the collision between the products.・Products should be stored on the palette for the prevention of the influence from humidity,dust and so on.・Products should be stored in the warehouse without heat shock, vibration, direct sunlight and so on.(3) Handling ConditionCare should be taken when transporting or handling product to avoid excessive vibration ormechanical shock.12．! Note(1)Please make sure that your product has been evaluated in view of your specifications with our product beingmounted to your product.(2)You are requested not to use our product deviating from the reference specifications.(3)The contents of this reference specification are subject to change without advance notice.Please approve our product specifications or transact the approval sheet for product specificationsbefore ordering.Reference OnlySpecNo.JELF243A-0024Y-01 P.11/11Mouser ElectronicsAuthorized DistributorClick to View Pricing, Inventory, Delivery & Lifecycle Information:M urata:LQW18AN10NG00D LQW18AN10NJ00D LQW18AN11NG00D LQW18AN11NJ00D LQW18AN12NG00D LQW18AN12NJ00D LQW18AN13NG00D LQW18AN13NJ00D LQW18AN15NG00D LQW18AN15NJ00D LQW18AN16NG00D LQW18AN16NJ00D LQW18AN18NG00D LQW18AN18NJ00D LQW18AN20NG00D LQW18AN20NJ00D LQW18AN22NG00D LQW18AN22NJ00D LQW18AN24NG00D LQW18AN24NJ00D LQW18AN27NG00D LQW18AN27NJ00D LQW18AN2N2D00D LQW18AN30NG00D LQW18AN30NJ00D LQW18AN33NG00D LQW18AN33NJ00D LQW18AN36NG00D LQW18AN36NJ00D LQW18AN39NG00D LQW18AN3N6C00D LQW18AN3N6D00D LQW18AN3N9C00D LQW18AN3N9D00D LQW18AN43NG00D LQW18AN43NJ00D LQW18AN47NG00D LQW18AN47NJ00D LQW18AN4N3C00D LQW18AN4N3D00D LQW18AN4N7D00D LQW18AN51NG00D LQW18AN51NJ00D LQW18AN56NG00D LQW18AN56NJ00D LQW18AN5N6C00D LQW18AN5N6D00D LQW18AN62NG00D LQW18AN62NJ00D LQW18AN68NG00D LQW18AN68NJ00D LQW18AN6N2C00D LQW18AN6N2D00D LQW18AN6N8C00D LQW18AN6N8D00D LQW18AN72NG00D LQW18AN72NJ00D LQW18AN75NG00D LQW18AN75NJ00D LQW18AN7N5D00D LQW18AN82NG00D LQW18AN82NJ00D LQW18AN8N2D00D LQW18AN8N7D00D LQW18AN91NG00D LQW18AN91NJ00D LQW18AN9N1D00D LQW18AN9N5D00D LQW18ANR10G00D LQW18ANR10J00D LQW18ANR11G00D LQW18ANR11J00D LQW18ANR12G00D LQW18ANR12J00D LQW18ANR13G00D LQW18ANR13J00D LQW18ANR15G00D LQW18ANR15J00D LQW18ANR16G00D LQW18ANR16J00D LQW18ANR18G00D LQW18ANR18J00D LQW18ANR20G00D LQW18ANR20J00D LQW18ANR22G00D LQW18ANR22J00D LQW18ANR27G00D LQW18ANR27J00D LQW18ANR33G00D LQW18ANR33J00D LQW18ANR39G00D LQW18ANR39J00D LQW18ANR47G00D LQW18ANR47J00D LQW18AN9N1C00D LQW18AN8N7C00D LQW18AN7N5C00D LQW18AN8N2C00D。
N80C196KC20中文资料
270942 – 45
NOTE RSV Reserved bits must be e 0
Figure 2 8XC196KC New SFR Bit (CLKOUT Disable)
2
元器件交易网
8XC196KC 8XC196KC20
PROCESS INFORMATION
270942 – 43
Address 0FFFFH 06000H 5FFFH 2080H 207FH 205EH 205DH 2040H 203FH 2030H 202FH 2020H 201FH 201AH 2019H 2018H 2017H 2014H 2013H 2000H 1FFFH 1FFEH 1FFDH 0200H 01FFH 0018H 0017H 0000H
Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y
Register-to-Register Architecture
Full Duplex Serial Port High Speed I O Subsystem 16-Bit Timer 16-Bit Up Down Counter with Capture 3 Pulse-Width-Modulated Outputs Four 16-Bit Software Timers 8- or 10-Bit A D Converter with Sample Hold HOLD HLDA Bus Protocol OTPROM One-Time Programmable Version
Y Y
The 80C196KC 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM 16 and 20 MHz operation and an optional 16 Kbytes of ROM OTPROM Intel’s CHMOS III process provides a high performance processor along with low power consumption The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM The 83C196KC is an 80C196KC with 16 Kbytes factory programmed ROM In this document the 80C196KC will refer to all products unless otherwise stated Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start an A D conversion Events can be based on the timer or up down counter With the commercial (standard) temperature option operational characteristics are guaranteed over the temperature range of 0 C to a 70 C With the extended (Express) temperature range option operational characteristics are guaranteed over the temperature range of b 40 C to a 85 C Unless otherwise noted the specifications are the same for both options See the Packaging information for extended temperature designators
applent ab4202 04 08 多路温度测试仪用户手册说明书
AB4202/04/08多路温度测试仪Rev.C3固件说明：适用于主程序RevC1.0及以上的版本@Instruments常州安柏精密仪器有限公司.江苏省常州市武进区漕溪路9号联东U谷14栋电话：*************传真：*************销售服务电子邮件: *****************技术支持电子邮件: ****************©2005-2023 Applent Instruments Ltd.声明根据国际版权法，未经常州安柏精密仪器有限公司（Applent Instruments Inc.）事先允许和书面同意，不得以任何形式复制本文内容。
安全信息为避免可能的电击和人身安全，请遵循以下指南进行操作。
免责声明用户在开始使用仪器前请仔细阅读以下安全信息，对于用户由于未遵守下列条款而造成的人身安全和财产损失，安柏仪器将不承担任何责任。
仪器接地为防止电击危险，请连接好电源地线。
不可在爆炸性气体环境使用仪器不可在易燃易爆气体、蒸汽或多灰尘的环境下使用仪器。
在此类环境使用任何电子设备，都是对人身安全的冒险。
不可打开仪器外壳非专业维护人员不可打开仪器外壳，以试图维修仪器。
仪器在关机后一段时间内仍存在未释放干净的电荷，这可能对人身造成电击危险。
不要超出本说明书指定的方式使用仪器超出范围，仪器所提供的保护措施将失效。
警告：不要加直流电压或电流到测试端，否则会损坏仪器。
安全标志：设备由双重绝缘或加强绝缘保护废弃电气和电子设备(WEEE) 指令2002/96/EC切勿丢弃在垃圾桶内有限担保和责任范围常州安柏精密仪器有限公司（以下简称Applent）保证您购买的每一台AB4202/4204/4208在质量和计量上都是完全合格的。
此项保证不包括保险丝以及因疏忽、误用、污染、意外或非正常状况使用造成的损坏。
本项保证仅适用于原购买者，并且不可转让。
自发货之日起，Applent提供玖拾（90）天保换和贰年免费保修，此保证也包括VFD或LCD。
K9F2G08U0M-PCB0中文资料
2
元器件交易网
K9F2G08Q0M-YCB0,YIB0 K9F2G08U0M-YCB0,YIB0
K9F2G16Q0M-YCB0,YIB0 K9F2G16U0M-YCB0,YIB0
Advance FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9F2GXXX0M-YCB0/YIB0 X16
Draft Date
Sep. 19.2001 Nov. 22. 2002
Remark
Advance Advance
0.2
Mar. 6.2003
Advance
0.3
Few current value is changed. Before K9F2G08Q0M Typ. ISB2 ILI ILO After K9F2G08Q0M Typ. ISB2 ILI ILO 10 Max. 50 ±10 ±10 20 Max. 100 ±20 ±20
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C
X8
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
X8
N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C PRE Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
Modicon ABL8RPM24200电源数据手册说明书
Product data sheetCharacteristicsABL8RPM24200Regulated Switch Power Supply, 1 or 2-phase,100..240V, 24V, 20 AMainRange of productModicon Power Supply Product or component type Power supplyPower supply type Regulated switch modeNominal input voltage 100...120 V AC single phase, terminal(s): N-L1200...240 V AC phase to phase, terminal(s): L1-L2Input voltage limits 85...132 V AC 170...264 V AC Rated power in W 480 W Output voltage24 V DC Power supply output current 20 APermissible temporary current boost 1.5 x In (for 4 s)Anti-harmonic filterLow frequency harmonic currentsComplementaryInrush current 30 APower factor 0.68 at 240 V AC 0.69 at 120 V AC Efficiency88 %Output voltage adjustment 24...28.8 V adjustable Power dissipation in W 57.6 WProvided equipment Power factor correction filter conforming to IEC 61000-3-2Output protection typeAgainst overload, protection technology: manual or automatic reset Against overvoltage, protection technology: 30...32 V, manual reset Against short-circuits, protection technology: manual or automatic reset Against undervoltage, protection technology: tripping if U < 21.6 V Thermal, protection technology: automatic resetConnections - terminalsRemovable screw terminal block: 2 x 2.5 mm², for diagnostic relayScrew type terminals: 3 x 0.5...3 x 4 mm², (AWG 22...AWG 12) for input connectionScrew type terminals: 1 x 0.5...1 x 4 mm², (AWG 22...AWG 12) for input ground connectioni s c l a i m e r : T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t e f o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i n g s u i t a b i l i t y o r r e l i a b i l i t y o f t h e s e p r o d u c t s f o r s p e c i f i c u s e r a p p l i c a t i o n sScrew type terminals: 4 x 0.5...4 x 4 mm², (AWG 22...AWG 12) for output connection Status LED 1 LED (green and red)output voltage1 LED (green, red and orange)output currentDepth145 mmHeight125 mmWidth146 mmNet weight 1.6 kgOutput coupling SeriesParallelMarking CEMounting support35 x 7.5 mm symmetrical DIN rail35 x 15 mm symmetrical DIN railOperating position VerticalEnvironmentStandards CSA C22.2 No 60950-1UL 508Product certifications CCSAusEACKCRCMULEnvironmental characteristic EMC conforming to EN 61000-6-1EMC conforming to EN 61000-6-3EMC conforming to EN 55024EMC conforming to EN/IEC 61000-6-4EMC conforming to EN/IEC 61204-3Safety conforming to EN/IEC 60950-1Safety conforming to EN/IEC 61204-3Safety conforming to SELVOperating altitude2000 mIP degree of protection IP20 conforming to EN/IEC 60529IP10Ambient air temperature for operation50…60 °C (with derating factor)-25…50 °C (without)Ambient air temperature for storage-40…70 °CRelative humidity0…90 % during operation0…95 % in storageDielectric strength2500 V between input and ground3000 V between input and output500 V between output and groundPacking UnitsPackage 1 Weight 2.846 kgPackage 1 Height 2.000 dmPackage 1 width 1.850 dmPackage 1 Length 1.950 dmOffer SustainabilitySustainable offer status Green Premium productREACh Regulation REACh DeclarationEU RoHS Directive Pro-active compliance (Product out of EU RoHS legal scope)EU RoHS DeclarationMercury free YesRoHS exemption information YesChina RoHS Regulation China RoHS declarationEnvironmental Disclosure Product Environmental ProfileCircularity Profile End of Life InformationPVC free Yes Contractual warrantyWarranty18 monthsDimensions DrawingsRegulated Switch Mode Power Supplies DimensionsRegulated Switch Mode Power Supply Internal Wiring DiagramRegulated Switch Mode Power SupplyLine Supply Wiring DiagramSingle-phase (L-N) 100 to 120 VPhase-to-phase (L1-L2) 200 to 500 VSingle-phase (L-N) 200 to 500 VRegulated Switch Mode Power SuppliesSeries or Parallel ConnectionSeries Connection(1)Two Shottky diodes Imin = power supply In and Vmin = 50 VParallel ConnectionNOTE: Series or parallel connection is only recommended for products with identical references.For better availability, the power supplies can also be connected in parallel using the ABL8RED24400 Redundancy module.Regulated Switch Mode Power SuppliesDeratingThe ambient temperature is a determining factor that limits the power an electronic power supply can deliver continuously. If the temperature around the electronic components is too high, their life will be significantly reduced.The nominal ambient temperature for the Universal range of Phaseo power supplies is 50°C. Above this temperature, derating is necessary up to a maximum temperature of 60°C.The graph below shows the power (in relation to the nominal power) that the power supply can deliver continuously, depending on the ambient temperature.X Maximum operating temperature (°C)ABL 8RPM, ABL 8RPS, ABL 8WPS mounted verticallyDerating should be considered in extreme operating conditions:●Intensive operation (output current permanently close to the nominal current, combined with a high ambient temperature)●Output voltage set above 24 Vdc (to compensate for line voltage drops, for example)●Parallel connection to increase the total powerRegulated Switch Mode Power SupplyLoad LimitManual Reset Protection Mode(1)Boost 4sAutomatic Reset Protection Mode(1)Boost 4s“Boost” Repeat AccuracyThis type of operation is described in detail in the user manual, which can be downloaded from the website.。
Hyundai Micro Electronics 8-BIT SINGLE-CHIP MICROC
Device name GMS82512 GMS82516 es 16K bytes 24K bytes
RAM Size 448 bytes 448 bytes 448 bytes
OTP GMS82524T GMS82524T GMS82524T
2. BLOCK DIAGRAM ................................3
3. PIN ASSIGNMENT ...............................4
4. PACKAGE DIAGRAM .............................. 5
Description .........................................................1 Features .............................................................1 Development Tools ............................................2 Ordering Information ..........................................2
C. INSTRUCTION ................................... vii
Terminology List ............................................... vii Instruction Map ................................................ viii Alphabetic order table of instruction ..................ix Instruction Table by Function .......................... xiv
ISL9208_0711资料
®FN6446.1ISL9208Multi-Cell Li-ion Battery Pack OCP/Analog Front EndThe ISL9208 is an overcurrent protection device and analog front end for a microcontroller in a multi-cell Li-ion battery pack. The ISL9208 supports battery pack configurations consisting of 5-cells to 7-cells in series and 1 or more cells in parallel. The ISL9208 provides integral overcurrentprotection circuitry, short circuit protection, an internal 3.3V voltage regulator, internal cell balancing switches, cellvoltage monitor level shifters, and drive circuitry for external FET devices for control of pack charge and discharge. Selectable overcurrent and short circuit thresholds reside in internal RAM registers. An external microcontroller sets the thresholds by setting register values through an I 2C serial interface. Internal registers also contain the detection delays for overcurrent and short circuit conditions.Using an internal analog multiplexer the ISL9208 provides monitoring of each cell voltage plus internal and external temperature by a separate microcontroller with an A/D converter. Software on this microcontroller implements all battery pack control functionality, except for overcurrent and short circuit shutdown.Applications•Power Tools•Battery Backup Systems •E-Bikes•Portable Test Equipment •Medical Systems •Hybrid Vehicle •Military ElectronicsFeatures•Software selectable overcurrent protection levels and variable protect detection times - 4 discharge overcurrent thresholds - 4 short circuit thresholds- 4 charge overcurrent thresholds -8 overcurrent delay times (Charge)-8 overcurrent delay times (Discharge)- 2 short circuit delay times (Discharge)•Automatic FET turn-off and cell balance disable on reaching external (battery) or internal (IC) temperature limit.•Automatic override of cell balance on reaching internal (IC) temperature limit.•Fast short circuit pack shutdown•Can use current sense resistor, FET r DS(ON), or Sense FET for overcurrent detection.•Four battery backed software controlled flags.•Allows three different FET controls:-Back-to-back N-Channel FETs for charge and discharge control-Single N-Channel discharge FET.-Single N-Channel FET for discharge, with separate, optional (smaller) back-to-back N-channel FETs for charge.•Integrated Charge/Discharge FET Drive Circuitry with 200µA (typ) turn-on current and 150mA (typ) Discharge FET turn-off current.•10% Accurate 3.3V voltage regulator (minimum 25mA out with external NPN transistor having current gain of 70). •Monitored cell voltage output stable in 100µs.•Internal Cell balancing FETs handle up to 200mA of balancing current for each cell (with the number of cells being balanced limited by the maximum package power dissipation of 400mW).•SimpleI 2C host interface•Sleep operation with programmable negative edge or positive edge wake-up.•<10µA Sleep Mode •Pb-free (RoHS compliant)Ordering InformationPART NUMBER(Note)PART MARKING PACKAGE (Pb-free)PKG. DWG. #ISL9208IRZ*ISL9208 IRZ32 Ld 5x5 QFNL32.5x5B*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.NOTE:These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attachmaterials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.Data SheetNovember 2, 2007元器件交易网PinoutISL9208(32 LD QFN)TOP VIEWFunctional DiagramT E M P 3VVMON CFET R G CW K U P124DFET CB7VCELL6234523222120CSENSE DSENSE C B 2V C E L L 2VCELL4N C719141312C B 3V C E L L 3313230292891011CB6VCELL5CB56V C E L L 115S D A18TEMPI 27C B 1R G OAO 26VC7/VCCV S S17C B 48S C L25N C16NC DSREF3.3VDC REGULATORVSSVC7/VCCCB7C S E N S ED SE N S ESDACB5CB6CB4VCELL6VCELL5VCELL4RGOCB3VCELL3FET CONTROL CIRCUITRYAOCB2VCELL2CB1VCELL1D S REF TEMP3VSCL REGISTERSRGC WKUPPOWER CONTROLD FE TC F E TMUX7V M O NBACKUP SUPPLYCONTROL LOGIC LEVEL CIRCUITSBALANCE CELL SHIFTERS/CELLVOLTAGESOVERCURRENT PROTECTION CIRCUITS (THRESHOLD DETECT AND TIMING)OSCTEMPERATURE SENSOR, INT/EXT COMPARATOR EXT TEMP ENABLETEMPI I 2C I/F 2Pin DescriptionsSYMBOL DESCRIPTIONVC7/VCC Battery cell 7 voltage input/VCC supply. This pin is used to monitor the voltage of this battery cell externally at pin AO. This pin also provides the operating voltage for the IC circuitry.VCELLN Battery cell N voltage input. This pin is used to monitor the voltage of this battery cell externally at pin AO. VCELLN connects to the positive terminal of CELLN and the negative terminal of CELLN + 1.CBN Cell balancing FET control output N. This internal FET diverts a fraction of the current around a cell while the cell is being charged or adds to the current pulled from a cell during discharge in order to perform a cell voltage balancing operation. This function isgenerally used to reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned on or off by an external controller.VSS Ground. This pin connects to the most negative terminal in the battery string.DSREF Discharge current sense reference. This input provides a separate reference point for the charge and discharge current monitoring circuits. WIth a separate reference connection, it is possible to minimize errors that result from voltage drops on the ground lead when the load is drawing large currents. If a separate reference is not necessary, connect this pin to VSS.DSENSE Discharge current sense monitor. This input monitors the discharge current by monitoring a voltage. It can monitor the voltage across a sense resistor, or the voltage across the DFET, or by using a FET with a current sense pin. The voltage on this pin is measured with reference to DSREF.CSENSE Charge current sense monitor. This input monitors the charge current by monitoring a voltage. It can monitor the voltage across a sense resistor, or the voltage across the CFET, or by using a FET with a current sense pin. The voltage on this pin is measured with reference to VSS.DFET Discharge FET control. The ISL9208 controls the gate of a discharge FET through this pin. The power FET is a N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9208 also turns off the FET in the event of an overcurrent or short circuit condition. If the microcontroller detects an undervoltage condition on any of the battery cells, it can turn off the discharge FET by controlling this output with a control bit.CFET Charge FET control. The ISL9208 controls the gate of a charge FET through this pin. The power FET is a N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9208 also turns off the FET in the event of an overcurrent condition. If the microcontroller detects an overvoltage condition on any of the battery cells, it can turn off the FET by controlling this output with a control bit.VMON Discharge load monitoring. In the event of an overcurrent or short circuit condition, the microcontroller can enable an internal resistor that connects between the VMON pin and VSS. When the FETs open because of an overcurrent or short circuit condition and the load remains, the voltage at VMON will be near the VCC voltage. When the load is released, the voltage at VMON drops below a threshold indicating that the overcurrent or short circuit condition is resolved. At this point, the LDFAIL flag is cleared and operation can resume.AO Analog multiplexer output. The analog output pin is used by an external microcontroller to monitor the cell voltages and temperature sensor voltages. The microcontroller selects the specific voltage being applied to the output by writing to a control register.TEMP3V Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. The thermistor is located in close proximity to the cells. The TEMP3V output is connected internally to the RGO voltagethrough a PMOS switch only during a measurement of the temperature, otherwise the TEMP3V output is off. The TEMP3V output can be turned on continuously with a special control bit.Microcontroller wake up control. The TEMP3V pin is also turned on when any of the DSC, DOC, or COC bits are set. This can be used to wake up a sleeping microcontroller to respond to overcurrent conditions with its own control mechanism.TEMPI Temperature monitor input. This pin inputs the voltage across a thermistor to determine the temperature of the cells. When this input drops below TEMP3V/13, an external over-temperature condition exists. The TEMPI voltage is also fed to the AO output pin through an analog multiplexer so the temperature of the cells can be monitored by the microcontroller.RGO Regulated output voltage. This pin connects to the emitter of an external NPN transistor and works in conjunction with the RGC pin to provides a regulated 3.3V. The voltage at this pin provides feedback for the regulator and power for many of the ISL9208 internal circuits as well as providing the 3.3V output voltage for the microcontroller and other external circuits.RGC Regulated output control. This pin connects to the base of an external NPN transistor and works in conjunction with the RGO pin to provide a regulated 3.3V. The RGC output provides the control signal for the external transistor to provide the 3.3V regulated voltage on the RGO pin.WKUP Wake up Voltage. This input wakes up the part when the voltage crosses a turn-on threshold (wake up is edge triggered). The condition of the pin is reflected in the WKUP bit (The WKUP bit is level sensitive.)WKPOL bit = ”1”: the device wakes up on the rising edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pinvoltage > threshold.WKPOL bit = ”0”, the device wakes up on the falling edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pinvoltage < threshold.SDA Serial Data. This is the bidirectional data line for an I2C interface.SCL Serial Clock. This is the clock input for an I2C communication link.Absolute Maximum Ratings Thermal InformationPower Supply Voltage, VCC . . . . . . . . . .V SS - 0.5V to V SS+36.0V Cell voltage, VCELLVCELLN - (VCELLN-1), VCELL1-VSS . . . . . . . . . . . . .-0.5V to 5V Terminal Voltage, V TERM1(SCL, SDA, C SENSE, D SENSE, TEMPI, RGO, AO, TEMP3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V SS - 0.5 to V RGO + 0.5V Terminal Voltage, V TERM2 (CFET, VMON) . . . . V SS-22.0V to V CC Terminal Voltage, V TERM3 (WKUP). . . . . . . . . . . . . . . . . . . . . . . . . . . V SS-0.5V to V CC (V CC<27V) Terminal Voltage, V TERM4 (RGC) . . . . . . . . . . . . . V SS-0.5V to 5V Terminal Voltage, V TERM5, (all other pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V SS-0.5V to V CC+0.5VOperating ConditionsTemperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 5V to 10V Operating Voltage:VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.2V to 30.1V VCELL1-VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 4.3V VCELLN-(VCELLN-1). . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 4.3V Thermal Resistance (Typical, Notes 1, 2)θJA (°C/W)θJC (°C/W) 32 Ld QFN . . . . . . . . . . . . . . . . . . . . . .322 Continuous Package Power Dissipation . . . . . . . . . . . . . . . . .400mW Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-55 to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below /pbfree/Pb-FreeReflow.aspCAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.NOTES:1.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. SeeTech Brief TB379.2.θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.Operating Specifications Over the recommended operating conditions unless otherwise specified.PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT Operating Voltage V CC9.230.1V Power-Up Condition 1V PORVCC V CC voltage (Note 3)49.2V Power-Up Condition 2 Threshold V POR123V CELL1 - V SS and V CELL2 - V CELL1 andV CELL3 - V CELL2 (rising)(Note 3)1.1 1.72.3VPower-Up Condition 2 Hysteresis V PORhys V CELL1 - V SS and V CELL2 - V CELL1 andV CELL3 - V CELL2 (falling)(Note 3)70mV 3.3V Regulated Voltage V RGO0µA < I RGC < 350µA 3.0 3.3 3.6V3.3VDC Voltage Regulator Control Current Limit I RGC(Control current at output of RGC.Recommend NPN with gain of 70+)0.350.50mAV CC Supply Current I VCC1Power-up defaults, WKUP pin= 0V. 400510µA RGO Supply Current I RGO1Power-up defaults, WKUP pin= 0V.300410µA V CC Supply Current I VCC2LDMONEN bit=1, VMON floating,CFET=1, DFET=1, WKPOL bit = 1,VWKUP=10V, [AO3:AO0] bits=03H.500700µARGO Supply Current I RGO2LDMONEN bit=1, VMON floating,CFET=1, DFET=1, WKPOL bit = 1,VWKUP=10V, [AO3:AO0] bits=03H.450650µAV CC Supply Current I VCC3Default register settings, exceptSLEEP bit = 1. WKUP pin = VCELL110µARGO Supply Current I RGO3Default register settings, exceptSLEEP bit = 1. WKUP pin = VCELL11µA VCELL Input Current (V CELL1)I VCELL1AO3:AO0 bits = 0000H14µAVCELL Input Current (V CELLN)I VCELLN AO3:AO0 bits = 0000H10µA OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONSOvercurrent Detection Threshold (Discharge) Voltage Relative To DSREF(Default in Boldface)V OCD V OCD = 0.10V (OCDV1, OCDV0 = 0, 0)0.080.100.12V V OCD = 0.12V (OCDV1, OCDV0 = 0,1)0.100.120.14V V OCD = 0.14V (OCDV1, OCDV0 = 1,0)0.120.140.16V V OCD = 0.16V (OCDV1, OCDV0 = 1,1)0.140.160.18VOvercurrent Detection Threshold (Charge) Voltage Relative to DSREF (Default in Boldface)V OCC V OCC = 0.10V (OCCV1, OCCV0 = 0, 0)-0.12-0.10-0.07V V OCC = 0.12V (OCCV1, OCCV0 = 0,1)-0.14-0.12-0.09V V OCC = 0.14V (OCCV1, OCCV0 = 1,0)-0.16-0.14-0.11V V OCC = 0.16V (OCCV1, OCCV0 = 1,1)-0.18-0.16-0.13VShort Current Detection Threshold Voltage Relative to DSREF (Default in Boldface) V SC V OC = 0.20V (SCDV1, SCDV0 = 0, 0)0.150.200.25V V OC = 0.35V (SCDV1, SCDV0 = 0,1)0.300.350.40V V OC = 0.65V (SCDV1, SCDV0 = 1, 0)0.600.650.70V V OC = 1.20V (SCDV1, SCDV0 = 1,1) 1.10 1.20 1.30VLoad Monitor Input Threshold(Falling Edge)V VMON LDMONEN bit = “1” 1.1 1.45 1.8VLoad Monitor Input Threshold(Hysteresis)V VMONH LDMONEN bit = “1”0.25mV Load Monitor Current I VMON204060µAShort Circuit Time-out t SCD Short circuit detection delay (SCLONGbit = ‘0’)90190290µsShort circuit detection delay (SCLONGbit = ‘1’)51015msOver Discharge Current Time-out (Default In Boldface)t OCD t OCD = 160ms (OCDT1, OCDT0 = 0, 0and DTDIV = 0)80160240mst OCD = 320ms (OCDT1, OCDT0 = 0, 1 andDTDIV = 0)160320480mst OCD = 640ms (OCDT1, OCDT0 = 1, 0 andDTDIV = 0)320640960mst OCD = 1280ms (OCDT1, OCDT0 = 1, 1and DTDIV = 0)64012801920mst OCD = 2.5ms (OCDT1, OCDT0 = 0, 0 andDTDIV = 1)1.252.503.75mst OCD = 5ms (OCDT1, OCDT0 = 0, 1 andDTDIV = 1)2.557.5mst OCD = 10ms (OCDT1, OCDT0 = 1, 0 andDTDIV = 1)51015mst OCD = 20ms (OCDT1, OCDT0 = 1, 1 andDTDIV = 1)102030msOver Charge Current Time-out (Default In Boldface)t OCC t OCC = 80ms (OCCT1,OCCT0 = 0, 0 andCTDIV = 0)4080120mst OCC = 160ms (OCCT1, OCCT0 = 0, 1 andCTDIV = 0)80160240mst OCC = 320ms (OCCT1, OCCT0 = 1, 0 andCTDIV = 0)160320480mst OCC = 640ms (OCCT1, OCCT0 = 1, 1 andCTDIV = 0)320640960mst OCC = 2.5ms (OCCT1, OCCT0 = 0, 0 andCTDIV = 1)1.252.503.75mst OCC = 5ms (OCCT1, OCCT0 = 0, 1 andCTDIV = 1)2.557.5mst OCC = 10ms (OCCT1, OCCT0 = 1, 0 andCTDIV = 1)51015mst OCC = 20ms (OCCT1, OCCT0 = 1, 1 andCTDIV = 1)102030msOVER-TEMPERATURE PROTECTION SPECIFICATIONSInternal Temperature ShutdownThresholdT INTSD125°CInternal Temperature Hysteresis T HYS Temperature drop needed to restoreoperation after over-temperatureshutdown.20°CInternal Over-temperature Turn OnDelay Timet ITD128ms External Temperature Output Current I XT Current output capability at TEMP3V pin 1.2mAExternal Temperature Limit Threshold T XTF Voltage at V TEMPI; Relative to fallingedge-200+20mVExternal Temperature Limit Hysteresis T XTH Voltage at V TEMPI.60110160mV External Temperature Monitor Delay t XTD Delay between activating the externalsensor and the internal over-temperaturedetection.1msExternal Temperature Autoscan OnTimet XTAON TEMP3V is ON (3.3V)5msExternal Temperature Autoscan Off Time t XTAOFF TEMP3V output is off.635ms V TEMP3V13-----------------------------ANALOG OUTPUT SPECIFICATIONSCell Monitor Analog Output VoltageAccuracyV AOC[V CELLN - (V CELLN-1)]/2 - AO-15430mVCell Monitor Analog Output External Temperature Accuracy V AOXT External temperature monitoring accuracy.Voltage error at AO when monitoringTEMPI voltage (measured withTEMPI = 1V)-1010mVInternal Temperature Monitor Output Voltage Slope V INTMON Internal temperature monitor voltagechange-3.5mV/°CInternal Temperature Monitor Output T INT25Output at +25°C 1.31V AO Output Stabilization Time t VSC From SCL falling edge at data bit 0 ofcommand to AO output stable within 0.5%of final value. AO voltage steps from 0V to2V. (C AO = 10pF)(Note 7)0.1msCELL BALANCE SPECIFICATIONSCell Balance Transistor r DS(ON)R CB(Note 6)5ΩCell Balance Transistor Current I CB200mA WAKE UP/SLEEP SPECIFICATIONSDevice WKUP Pin Voltage Threshold (WKUP Pin Active High - Rising Edge)V WKUP1WKUP pin rising edge (WKPOL = 1)Device wakes up and sets WKUP flagHIGH.3.5 5.0 6.5VDevice Wkup Pin Hysteresis (WKUP Pin Active High)V WKUP1H WKUP pin falling edge hystersis(WKPOL = 1) sets WKUP flag LOW (doesnot automatically enter sleep mode)100mVInput Resistance On WKUP R WKUP Resistance from WKUP pin to VSS(WKPOL = 1)130230330kΩDevice WKUP Pin Active Voltage Threshold (WKUP Pin Active Low - Falling Edge)V WKUP2WKUP pin falling edge (WKPOL = 0)Device wakes up and sets WKUP flagHIGH.V CELL1-2.6V CELL1-2.0V CELL1-1.2VDevice Wkup Pin Hysteresis (WKUP Pin Active Low)V WKUP2H WKUP pin rising edge hysteresis(WKPOL = 0) sets WKUP flag LOW (doesnot automatically enter sleep mode)200mVDevice Wake-up Delay t WKUP Delay after voltage on WKUP pin crossesthe threshold (rising or falling) beforeactivating the WKUP bit.204060ms FET CONTROL SPECIFICATIONS (FOR VCELL1, VCELL2, VCELL3 VOLTAGES FROM 2.8V TO 4.3V)Control Outputs Response Time (CFET, DFET)t CO Bit 0 to start of control signal (DFET)Bit 1 to start of control signal (CFET)1.0µsCFET Gate Voltage VCFET No load on CFET V CELL3-0.5V CELL3V DFETGate Voltage VDFET No load on DFET V CELL3-0.5V CELL3V FET Turn On Current (DFET)I DFON DFET voltage = 0 to VCELL3-1.5V80130400µA FET Turn On Current (CFET)I CF(ON)CFET voltage = 0 to VCELL3 - 1.5V80200400µA FET Turn Off Current (DFET)I DF(OFF)DFET voltage = VDFET to 1V100180mA DFET Resistance to VSS R DF(OFF)VDFET <1V (When turning off the FET)11ΩSERIAL INTERFACE CHARACTERISTICSSCL Clock Frequency f SCL100kHzPulse Width Suppression Time at SDA and SCL Inputs t IN Any pulse narrower than the max spec issuppressed.50nsSCL Falling Edge to SDA Output Data Valid t AA From SCL falling crossing V IH(min), untilSDA exits the V IL(max) to V IH(min)window.3.5µsTime the Bus Must Be Free Before Start of New Transmission t BUF SDA crossing V IH(min) during a STOPcondition to SDA crossing V IH(min) duringthe following START condition.4.7µsClock Low Time t LOW Measured at the V IL(max) crossing. 4.7µs Clock High Time t HIGH Measured at the V IH(min) crossing. 4.0µs Start Condition Setup Time t SU:STA SCL rising edge to SDA falling edge. Bothcrossing the V IH(min) level.4.7µsStart Condition Hold Time t HD:STA From SDA falling edge crossing V IL(max)to SCL falling edge crossing V IH(min).4.0µsInput Data Setup Time t SU:DAT From SDA exiting the V IL(max) to V IH(min)window to SCL rising edge crossingV IL(min).250nsInput Data Hold Time t HD:DAT From SCL falling edge crossing V IH(min) toSDA entering the V IL(max) to V IH(min)window.300µsStop Condition Setup Time t SU:STO From SCL rising edge crossing V IH(min) toSDA rising edge crossing V IL(max).4.0µsStop Condition Hold Time t HD:STO From SDA rising edge to SCL falling edge.Both crossing V IH(min).4.0µsData Output Hold Time t DH From SCL falling edge crossing V IL(max)until SDA enters the V IL(max) to V IH(min)window. (Note 4)0nsSDA and SCL Rise Time t R From V IL(max) to V IH(min).1000ns SDA and SCL Fall Time t F From V IH(min) to V IL(max).300ns Capacitive Loading Of SDA Or SCL Cb Total on-chip and off-chip400pFSDA and SCL Bus Pull-up Resistor- Off Chip R OUT Maximum is determined by t R and t F.For C B = 400pF, max is about 2kΩ ~ 2.5kΩFor C B = 40pF, max is about 15kΩ to 20kΩ1kΩInput Leakage Current (SCL, SDA)I LI-1010µA Input Buffer Low Voltage (SCL, SDA)V IL Voltage relative to V SS of the device.-0.3V RGO x 0.3V Input Buffer High Voltage (SCL, SDA)V IH Voltage relative to V SS of the device.V RGO x 0.7V RGO+0.1VV Output Buffer Low Voltage (SDA)V OL I OL = 1mA0.4V SDA and SCL Input Buffer Hysteresis I2CHYST Sleep bit = 0 0.05*V RGO V NOTES:3.Power up of the device requires all V CELL1, V CELL2, V CELL3, and VCC to be above the limits specified.4.The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.5.Typical +125°C ±10%, based on design and characterization data.6.Typical 5Ω ±2Ω, based on design and characterization data.7.Maximum output capacitance = 15pF.Wake up timing (WKPOL = 0)Wake up timing (WKPOL = 1)Change in Voltage Source, FET ControlV WKUP2V WKUP2Ht WKUPt WKUP<t WKUP<t WKUPWKUP PINWKUP BITV WKUP1V WKUP1Ht WKUPt WKUP<t WKUP<t WKUPWKUP PINWKUP BITAOt VSCt VSCBIT 0DFETt CO SDASCLBIT 0t CODATACFETt COBIT 1BIT 2BIT 3BIT 1Automatic Temperature ScanDischarge Overcurrent/Short Circuit Monitor (Assumes DENOCD and DENSCD bits are ‘0’)AUTO TEMP CONTROL (INTERNAL ACTIVATION)TEMP3V PIN TMP3V/13DELAY TIME = 1ms635msMONITOR TIME = 5ms3.3VXOT BITEXTERNAL OVER-TEMPERATUREDELAY TIME = 1msFET SHUTDOWN AND CELL BALANCE TURN OFF MONITOR TEMP DURING THISHIGH IMPEDANCETIME PERIODTHRESHOLDTEMPERATURE(IF ENABLED)V SCV OCDt SCDt OCDt SCDDOC BIT DSC BIT TEMP3V V DSENSEREGISTER 1 READREGISTER 1 READOUTPUT 3.3V‘1’‘1’‘0’‘0’DFET OUTPUTUC TURNS ON DFETVCELL3Charge Overcurrent Monitor (Assumes DENOCC bit is ‘0’)Serial Interface Timing DiagramsBus TimingSymbol TableV OCCt OCCCOC BIT TEMP3V V CSENSEREGISTER 1 READOUTPUT3.3V‘1’‘0’CFET OUTPUTµC TURNS ON CFET12VSCLt t SDA(INPUT TIMING)SDA(OUTPUT TIMING)WAVEFORMINPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM LOW TO HIGH WILL CHANGE FROM LOW TO HIGH MAY CHANGE FROM HIGH TO LOWWILL CHANGE FROM HIGH TO LOWDON’T CARE:CHANGES ALLOWED CHANGING:STATE NOT KNOWN N/ACENTER LINE IS HIGHIMPEDANCEWAVEFORMINPUTS OUTPUTSRegistersTABLE 1.REGISTERSADDR REGISTER READ/WRITE7654321000H Config/OpStatus Read only Reserved Reserved SASingle AFEWKUPWKUP pinStatusReserved Reserved Reserved Reserved01H OperatingStatus(Note 10)Read only Reserved Reserved XOTExt overtempIOTInt overTempLDFAILLoad Fail(VMON)DSCShortCircuitDOCDischargeOCCOCCharge OC02H Cell Balance Read/Write CB7ON CB6ON CB5ON CB4ON CB3ON CB2ON CB1ON ReservedCell balance FET control bits03H Analog Out Read/Write UFLG1User Flag 1UFLG0User Flag 0Reserved Reserved AO3AO2AO1AO0Analog output select bits04H FET Control Read/Write SLEEPForceSleep(Note 11)LDMONENTurn onVMONconnectionReserved Reserved Reserved Reserved CFETTurn onChargeFET(Note 12)DFETTurn onDischargeFET(Note 12)05H Discharge Set Read/Write(Write only ifDISSETENbit set)DENOCD OCDV1OCDV0DENSCD SCDV1SCDV0OCDT1OCDT0 Turn offautomaticOCDcontrolOvercurrent DischargeThreshold VoltageTurn offautomaticSCD controlShort Circuit DischargeThreshold VoltageOvercurrent DischargeTime-out06H Charge Set Read/Write(Write only ifCHSETENbit set)DENOCC OCCV1OCCV0SCLONGLong Short-circuit delayCTDIVDividechargetime by 32DTDIVDividedischargetime by 64OCCT1OCCT0 Turn offautomaticOCCcontrolOvercurrent ChargeThreshold VoltageOvercurrent ChargeTime-out07H Feature Set Read/Write(Write only ifFSETENbit set)ATMPOFFTurn offautomaticexternaltemp scanDIS3Disable 3.3Vreg. (devicerequiresexternal3.3V)TMP3ONTurn onTemp3VDISXTSDDisableexternalthermalshutdownDISITSDDisableinternalthermalshutdownPORForce PORDISWKUPDisableWKUP pinWKPOLWake UpPolarity08H Write Enable Read/Write FSETENEnableFeatureSet writes CHSETENEnableCharge SetwritesDISSETENEnableDischargeSet writesUFLG3User Flag 3UFLG2User Flag 2Reserved Reserved Reserved09H:FFH Reserved NA RESERVEDNOTES:8.A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.9.“Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, and 8: write a reserved bit withthe value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.10.These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.11.This SLEEP bit is cleared on initial power up, by the WKUP pin going high (when WKPOL=”1”) or by the WKUP pin going low (whenWKPOL=”0”), and by writing a “0” to the location with an I2C command.12.When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turnsoff the FETs. At all other times, an I2C write operation controls the output to the respective FET and a read returns the current state of the FET drive output circuit (though not the actual voltage at the output pin.)。
COP87L20CJN-1N资料
TL DD11208COP820CJ COP822CJ COP823CJ 8-Bit Microcontroller with Multi-Input Wake Up and Brown Out DetectorSeptember1996 COP820CJ COP822CJ COP823CJ8-Bit Microcontrollerwith Multi-Input Wake Up and Brown Out DetectorGeneral DescriptionThe COP820CJ is a member of the COP8TM8-bit Microcon-troller family It is a fully static Microcontroller fabricatedusing double-metal silicon gate microCMOS technologyThis low cost Microcontroller is a complete microcomputercontaining all system timing interrupt logic ROM RAM andI O necessary to implement dedicated control functions in avariety of applications Features include an8-bit memorymapped architecture MICROWIRE TM serial I O a16-bittimer counter with capture register a multi-sourced inter-rupt Comparator WATCHDOG TM Timer Modulator TimerBrown out protection and Multi-Input Wakeup Each I O pinhas software selectable options to adapt the device to thespecific application The device operates over a voltagerange of2 5V to6 0V High throughput is achieved with anefficient regular instruction set operating at a1m s per in-struction rateKey FeaturesY Multi-Input Wake Up(on the8-bit Port L)Y Brown out detectorY Analog comparatorY Modulator timer(High speed PWM for IR transmission)Y16-bit multi-function timer supportingPWM modeExternal event counter modeInput capture modeY1024bytes of ROMY64bytes of RAMI O FeaturesY Memory mapped I OY Software selectable I O options(TRI-STATE outputpush-pull output weak pull-up input high impedanceinput)Y High current outputs(8pins)Y Schmitt trigger inputs on Port GY MICROWIRE PLUS TM serial I OY Packages16SO with12I O pins20DIP SO with16I O pins28DIP SO with24I O pinsCPU Instruction Set FeatureY1m s instruction cycle timeY Three multi-source vectored interrupts servicingExternal interrupt with selectable edgeTimer interruptSoftware interruptY Versatile and easy to use instruction setY8-bit Stack Pointer(SP) stack in RAMY Two8-bit register indirect data memory pointers(B X)Fully Static CMOSY Low current drain(typically k1m A)Y Single supply operation 2 5V to6 0VY Temperature range b40 C to a85 CDevelopment SupportY Emulation and OTP devicesY Real time emulation and full program debug offered byMetaLink Development SystemBlock DiagramTL DD 11208–1FIGURE1 Block DiagramTRI-STATE is a registered trademark of National Semiconductor CorporationCOP8TM Microcontrollers MICROWIRE TM MICROWIRE PLUS TM and WATCHDOG TM are trademarks of National Semiconductor CorporationiceMASTER TM is a trademark of MetaLink CorporationC1996National Semiconductor Corporation RRD-B30M106 Printed in U S A http www national comCOP820CJ COP822CJ COP823CJ Absolute Maximum RatingsIf Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC)7 0V Voltage at any Pin b0 3V to V CC a0 3V Total Current into V CC pin(Source)80mA Total Current out of GND pin(sink)80mA Storage Temperature Range b65 C to a150 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occurDC and AC electrical specifications are not ensured when operating the device at absolute maximum ratingsDC Electrical Characteristics b40 C s T A s a85 C unless otherwise specifiedParameter Conditions Min Typ Max Units Operating Voltage Brown Out Disabled2 56 0VPower Supply Ripple1(Note1)Peak to Peak0 1V CC V Supply Current(Note2)CKI e10MHz V CC e6V tc e1m s6 0mACKI e4MHz V CC e6V tc e2 5m s3 5mACKI e4MHz V CC e4 0V tc e2 5m s2 0mACKI e1MHz V CC e4 0V tc e10m s1 5mAHALT Current with Brown OutV CC e6V CKI e0MHz k110m A Disbled(Note3)HALT Current with Brown Out V CC e6V CKI e0MHzk50110m A EnabledBrown Out Trip Level1 83 14 2V(Brown Out Enabled)INPUT LEVELS(V IH V IL)Reset CKILogic High0 8V CC V Logic Low0 2V CC V All Other InputsLogic High0 7V CC V Logic Low0 2V CC V Hi-Z Input Leakage V CC e6 0V b2a2m A Input Pullup Current V CC e6 0V V IN e0V b40b250m A L-and G-Port Hysteresis(Note5)0 35V CC V Output Current LevelsD OutputsSource V CC e4 5V V OH e3 8V b0 4mAV CC e2 5V V OH e1 8V b0 2mA Sink V CC e4 5V V OL e1 0V10mAV CC e2 5V V OH e0 4V2mA L4–L7Output Sink V CC e4 5V V OL e2 5V15mA All OthersSource(Weak Pull-up Mode)V CC e4 5V V OH e3 2V b10b110m AV CC e2 5V V OH e1 8V b2 5b33m A Source(Push-pull Mode)V CC e4 5V V OH e3 8V b0 4mAV CC e2 5V V OH e1 8V b0 2mA Sink(Push-pull Mode)V CC e4 5V V OL e0 4V1 6mAV CC e2 5V V OL e0 4V0 7mA TRI-STATE Leakage b2 0a2 0m A Allowable Sink SourceCurrent Per PinD Outputs15mAL4–L7(Sink)20mA All Others3mAhttp www national com2DC Electrical Characteristics b40 C s T A s a85 C unless otherwise specified(Continued) Parameter Conditions Min Typ Max UnitsMaximum Input Current Room Temperatureg100mA without Latchup(Note4)RAM Retention Voltage V r500ns Rise and2 0VFall Time(Min)Input Capacitance7pFLoad Capacitance on D21000pFNote1 Rate of voltage change must be less than10V mSNote2 Supply current is measured after running2000cycles with a square wave CKI input CKO open inputs at rails and outputs openNote3 The HALT mode will stop CKI from oscillating in the RC and crystal configurations HALT test conditions L and G0 G5ports configured as outputs and set high The D port set to zero All inputs tied to V CC The comparator and the Brown Out circuits are disabledNote4 Pins G6and RESET are designed with a high voltage input network These pins allow input voltages greater than V CC and the pins will have sink current toV CC when biased at voltages greater than V CC(the pins do not have source current when biased at a voltage below V CC) The effective resistance to V CC is750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than14VAC Electrical Characteristics b40 C s T A s a85 C unless otherwise specifiedParameter Conditions Min Typ Max Units Instruction Cycle Time(tc)Crystal Resonator4 5V s V CC s6 0V1DC m s2 5V s V CC s4 5V2 5DC m sR C Oscillator4 5V s V CC s6 0V3DC m s2 5V s V CC s4 5V7 5DC m sV CC Rise Time when Using Brown Out V CC e0V to6V50m s Frequency at Brown Out Reset4MHzCKI Frequency For Modular Output4MHzCKI Clock Duty Cycle(Note5)fr e Max4060%Rise Time(Note5)fr e10MHz ext Clock12nsFall Time(Note5)fr e10MHz ext Clock8ns Inputst Setup4 5V s V CC s6 0V200ns2 5V s V CC s4 5V500nst Hold4 5V s V CC s6 0V60ns2 5V s V CC s4 5V150ns Output Propagation Delay R L e2 2k CL e100pFt PD1 t PD0SO SK4 5V s V CC s6 0V0 7m s2 5V s V CC s4 5V1 75m sAll Others4 5V s V CC s6 0V1m s2 5V s V CC s4 5V5m sInput Pulse WidthInterrupt Input High Time1tc Interrupt Input Low Time1tc Timer Input High Time1tc Timer Input Low Time1tc MICROWIRE Setup Time(t m WS)20ns MICROWIRE Hold Time(t m WH)56nsMICROWIRE Output220ns Propagation Delay(t m PD)Reset Pulse Width1 0m sNote5 Parameter characterized but not production tested3http www national comAC Electrical Characteristics (Continued)TL DD 11208–2FIGURE 2 MICROWIRE PLUS TimingComparator DC and AC Characteristics 4V s V CC s 6V b 40 C s T A s a 85 C (Note 1)ParametersConditionsMinTypeMaxUnits Input Offset Voltage0 4V k V IN k V CC b 1 5Vg 10g 25mV Input Common Mode Voltage Range 0 4V CC b 1 5V Voltage Gain300kV V DC Supply Current (when enabled)V CC e 6 0V250m A Response TimeTBD mV Step1m sTBD mV Overdrive 100pF LoadNote 1 For comparator output current characteristics see L-Port specsConnection DiagramsTL DD 11208–3Top ViewOrder Number COPCJ820-XXX N orCOPCJ820-XXX WMTL DD 11208–4Top ViewOrder Number COPCJ822-XXX N orCOPCJ822-XXX WMTL DD 11208–5Top ViewOrder Number COPCJ823-XXX WMFIGURE 3 Connection Diagramshttp www national com 4Typical Performance Characteristics(Crystal Clock Option)Dynamic I DD vs V CC (Brown Out Disabled)Halt I DD vs V CC(Brown Out Enabled)Halt I DD vs V CCPull-Up Source Current Ports L G WeakSource Current Ports L G Push-Pull Sink CurrentPorts L G Push-Pull Sink CurrentPorts L4–L7Port D Source Current Port D Sink Currentvs TemperatureBrown Out Voltage TL DD 11208–28http www national com5COP820CJ Pin AssignmentPortTyp ALT162028Pin Funct Pin Pin Pin L0I O MIWU CMPOUT5711 L1I O MIWU CMPIN b6812 L2I O MIWU CMPIN a7913 L3I O MIWU81014 L4I O MIWU91115 L5I O MIWU101216 L6I O MIWU111317 L7I O MIWU MODOUT121418 G0I O INTR1725 G1I O1826 G2I O1927 G3I O TIO152028 G4I O SO11G5I O SK1622G6I SI133G7I CKO244I0I7I1I8I2I9I3I10 D0O19 D1O20 D2O21 D3O22 V CC466 GND131523 CKI355 RESET141624Pin DescriptionV CC and GND are the power supply pinsCKI is the clock input This can come from an external source a R C generated oscillator or a crystal(in conjunc-tion with CKO) See Oscillator descriptionRESET is the master reset input See Reset description PORT I is a4-bit Hi-Z input portPORT L is an8-bit I O portThere are two registers associated with the L port a data register and a configuration register Therefore each L I O bit can be individually configured under software control as shown belowPort L Port L Port LConfig Data Setup00Hi-Z Input(TRI-STATE)01Input with Weak Pull-up10Push-pull Zero Output11Push-pull One Output Three data memory address locations are allocated for this port one each for data register 00D0 configuration regis-ter 00D1 and the input pins 00D2Port L has the following alternate featuresL0MIWU or CMPOUTL1MIWU or CMPIN bL2MIWU or CMPIN aL3MIWUL4MIWU(high sink current capability)L5MIWU(high sink current capability)L6MIWU(high sink current capability)L7MIWU or MODOUT(high sink current capability)The selection of alternate Port L functions is done through registers WKEN 00C9 to enable MIWU and CNTRL2 00CC to enable comparator and modulatorAll eight L-pins have Schmitt Triggers on their inputs PORT G is an8-bit port with6I O pins(G0–G5)and2input pins(G6 G7)All eight G-pins have Schmitt Triggers on the inputs There are two registers associated with the G port a data register and a configuration register Therefore each G port bit can be individually configured under software control as shown belowPort G Port G Port GConfig Data Setup00Hi-Z Input(TRI-STATE)01Input with Weak Pull-up10Push-pull Zero Output11Push-pull One Output Three data memory address locations are allocated for this port one for data register 00D3 one for configuration reg-ister 00D5 and one for the input pins 00D6 Since G6 and G7are Hi-Z input only pins any attempt by the user to configure them as outputs by writing a one to the configura-tion register will be disregarded Reading the G6and G7 configuration bits will return zeros Note that the device will be placed in the Halt mode by writing a‘‘1’’to the G7data bitSix pins of Port G have alternate featuresG0INTR(an external interrupt)G3TIO(timer counter input output)G4SO(MICROWIRE serial data output)G5SK(MICROWIRE clock I O)G6SI(MICROWIRE serial data input)G7CKO crystal oscillator output(selected by mask option) or HALT restart input general purpose input(if clock option is R C or external clock)http www national com6Pin Description(Continued)Pins G1and G2currently do not have any alternate func-tionsThe selection of alternate Port G functions are done through registers PSW 00EF to enable external interrupt and CNTRL1 00EE to select TIO and MICROWIRE operations PORT D is a four bit output port that is preset when RESET goes low One data memory address location is allocated for the data register 00DCNote Care must be exercised with the D2pin operation At RESET the external loads on this pin must ensure that the output voltages stay above 0 8V CC to prevent the chip from entering special modes Also keep the external loading on D2to less than1000pFFunctional DescriptionThe internal architecture is shown in the block diagram Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the deviceALU and CPU RegistersThe ALU can do an8-bit addition subtraction logical or shift operations in one cycle time There are five CPU regis-tersA is the8-bit Accumulator registerPC is the15-bit Program Counter registerPU is the upper7bits of the program counter(PC)PL is the lower8bits of the program counter(PC)B is the8-bit address register and can be auto incre-mented or decrementedX is the8-bit alternate address register and can be auto incremented or decrementedSP is the8-bit stack pointer which points to the subrou-tine stack(in RAM)B X and SP registers are mapped into the on chip RAM The B and X registers are used to address the on chip RAM The SP register is used to address the stack in RAM during subroutine calls and returns The SP must be preset by soft-ware upon initializationMemoryThe memory is separated into two memory spaces program and dataPROGRAM MEMORYProgram memory consists of1024x8ROM These bytes of ROM may be instructions or constant data The memory is addressed by the15-bit program counter(PC) ROM can be indirectly read by the LAID instruction for table lookup DATA MEMORYThe data memory address space includes on chip RAM I O and registers Data memory is addressed directly by the in-struction or indirectly through B X and SP registers The device has64bytes of RAM Sixteen bytes of RAM are mapped as‘‘registers’’ these can be loaded immediately decremented and tested Three specific registers X B and SP are mapped into this space the other registers are avail-able for general usageAny bit of data memory can be directly set reset or testedAll I O and registers(except A and PC)are memorymapped therefore I O bits and register bits can be directlyand individually set reset and tested except the write onceonly bit(WDREN WATCHDOG Reset Enable) and the un-used and read only bits in CNTRL2and WDREG registersNote RAM contents are undefined upon power-upResetEXTERNAL RESETThe RESET input pin when pulled low initializes the micro-controller The user must insure that the RESET pin is heldlow until V CC is within the specified voltage range and theclock is stabilized An R C circuit with a delay5x greaterthan the power supply rise time is recommended(Figure4)The device immediately goes into reset state when theRESET input goes low When the RESET pin goes high thedevice comes out of reset state synchronously The devicewill be running within two instruction cycles of the RESETpin going high The following actions occur upon resetPort L TRI-STATEPort G TRI-STATEPort D HIGHPC CLEAREDRAM Contents RANDOM with Power-On-ResetUNAFFECTED with externalReset(power already applied)B X SP Same as RAMPSW CNTRL1 CNTRL2and WDREG Reg CLEAREDMulti-Input Wakeup RegWKEDG WKEN CLEAREDWKPND UNKNOWNData and ConfigurationRegisters for L G CLEAREDWATCHDOG Timer Prescaler Counter eachloaded with FFThe device comes out of the HALT mode when the RESETpin is pulled low In this case the user has to ensure that theRESET signal is low long enough to allow the oscillator torestart An internal256t c delay is normally used in conjunc-tion with the two pin crystal oscillator When the devicecomes out of the HALT mode through Multi-Input Wakeupthis delay allows the oscillator to stabilizeThe following additional actions occur after the devicecomes out of the HALT mode through the RESET pinIf a two pin crystal resonator oscillator is being usedRAM Contents UNCHANGEDTimer T1and A Contents UNKNOWNWATCHDOG Timer Prescaler Counter ALTEREDhttp www national com 7Functional Description(Continued)If the external or RC Clock option is being usedRAM Contents UNCHANGED Timer T1and A Contents UNCHANGED WATCHDOG Timer Prescaler Counter ALTEREDThe external RESET takes priority over the Brown Out Re-setNote If the RESET pin is pulled low while Brown Out occurs(Brown Out circuit has detected Brown Out condition) the external reset will not occur until the Brown Out condition is removed External reset has priority only if V CC is greater than the Brown Out voltageRC l5c Power Supply Rise Time TL DD 11208–6 FIGURE4 Recommended Reset Circuit WATCHDOG RESETWith WATCHDOG enabled the WATCHDOG logic resets the device if the user program does not service the WATCH-DOG timer within the selected service window The WATCHDOG reset does not disable the WATCHDOG Upon WATCHDOG reset the WATCHDOG Prescaler Counter are each initialized with FF HexThe following actions occur upon WATCHDOG reset that are different from external resetWDREN WATCHDOG Reset Enable bit UNCHANGED WDUDF WATCHDOG Underflow bit UNCHANGED Additional initialization actions that occur as a result of WATCHDOG reset are as followsPort L TRI-STATEPort G TRI-STATEPort D HIGHPC CLEAREDRam Contents UNCHANGEDB X SP UNCHANGEDPSW CNTRL1and CNTRL2(exceptWDUDF Bit)Registers CLEAREDMulti-Input Wakeup RegistersWKEDG WKEN CLEAREDWKPND UNKNOWNData and ConfigurationRegisters for L G CLEARED WATCHDOG Timer Prescalar Countereach loaded with FFBROWN OUT RESETThe on-board Brown Out protection circuit resets the device when the operating voltage(V CC)is lower than the Brown Out voltage The device is held in reset when V CC stays below the Brown Out Voltage The device will remain in RESET as long as V CC is below the Brown Out Voltage The Device will resume execution if V CC rises above the Brown Out Voltage If a two pin crystal resonator clock option is selected the Brown Out reset will trigger a256tc delay This delay allows the oscillator to stabilize before the device ex-its the reset state The delay is not used if the clock option is either R C or external clock The contents of data registers and RAM are unknown following a Brown Out reset The external reset takes priority over Brown Out Reset and will deactivate the256tc cycles delay if in progress The Brown Out reset takes priority over the WATCHDOG resetThe following actions occur as a result of Brown Out resetPort L TRI-STATEPort G TRI-STATEPort D HIGHPC CLEAREDRAM Contents RANDOMB X SP UNKNOWNPSW CNTRL1 CNTRL2and WDREG Registers CLEAREDMulti-Input Wakeup RegistersWKEDG WKEN CLEAREDWKPND UNKNOWNData and ConfigurationRegisters for L G CLEAREDWATCHDOG Timer Prescalar Counter eachloaded with FFTimer T1and Accumulator Unknown data aftercoming out of the HALT(through Brown OutReset)with any ClockoptionNote The development system will detect the BROWN OUT RESET exter-nally and will force the RESET pin low The Development System does not emulate the256tc delayBrown Out DetectionAn on-board detection circuit monitors the operating voltage (V CC)and compares it with the minimum operating voltage specified The Brown Out circuit is designed to reset the device if the operating voltage is below the Brown Out volt-age(between1 8V to4 2V at b40 C to a85 C) The Mini-mum operating voltage for the device is2 5V with BrownOut disabled but with BROWN OUT enabled the device is guaranteed to operate properly down to minimum Brown Out voltage(Max frequency4MHz) For temperature range of0 C to70 C the Brown Out voltage is expected to be between1 9V to3 9V The circuit can be enabled or dis-abled by Brown Out mask option If the device is intended to operate at lower V CC(lower than Brown Out voltage VBO max) the Brown Out circuit should be disabled by the mask optionThe Brown Out circuit may be used as a power-up reset provided the power supply rise time is slower than50m s(0V to6 0V)Note Brown Out Circuit is active in HALT mode(with the Brown Out mask option selected)http www national com8Functional Description(Continued)Oscillator CircuitsEXTERNAL OSCILLATORCKI can be driven by an external clock signal provided itmeets the specified duty cycle rise and fall times and inputlevels CKO is available as a general purpose input G7and or Halt controlCRYSTAL OSCILLATORBy selecting CKO as a clock output CKI and CKO can beconnected to create a crystal controlled oscillator Table Ishows the component values required for various standardcrystal valuesR C OSCILLATORBy selecting CKI as a single pin oscillator CKI can make aR C oscillator CKO is available as a general purpose inputand or HALT control Table II shows variation in the oscilla-tor frequencies as functions of the component(R and C)valuesTL DD 11208–7FIGURE5 Clock Oscillator ConfigurationsTABLE I Crystal Oscillator ConfigurationR1R2C1C2CKI FreqConditions(k X)(M X)(pF)(pF)(MHz)013030–3610V CC e5V013030–364V CC e5V5 61100100–1560 455V CC e5VTABLE II RC Oscillator Configuration(Part-To-Part Variation)R C CK1Freq Instr CycleConditions(k X)(pF)(MHz)(m s)3 3822 2to2 73 7to4 6V CC e5V5 61001 1to1 37 4to9 0V CC e5V6 81000 9to1 18 8to10 8V CC e5V9http www national comFunctional Description(Continued)Halt ModeThe device is a fully static device The device enters the HALT mode by writing a one to the G7bit of the G data register Once in the HALT mode the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted In this mode the chip will only draw leakage current(output current and DC current due to the Brown Out circuit if Brown Out is enabled)The device supports four different methods of exiting the HALT mode The first method is with a low to high transition on the CKO(G7)pin This method precludes the use of the crystal clock configuration(since CKO is a dedicated out-put) It may be used either with an RC clock configuration or an external clock configuration The second method of exit-ing the HALT mode is with the multi-Input Wakeup feature on the L port The third method of exiting the HALT mode is by pulling the RESET input low The fourth method is with the operating voltage going below Brown Out voltage(if Brown Out is enabled by mask option)If the two pin crystal resonator oscillator is being used and Multi-Input Wakeup or Brown Out causes the device to exit the HALT mode the WAKEUP signal does not allow the chip to start running immediately since crystal oscillators have a delayed start up time to reach full amplitude and freuqency stability The WATCHDOG timer(consisting of an 8-bit prescaler followed by an8-bit counter)is used to gen-erate a fixed delay of256tc to ensure that the oscillator has indeed stabilized before allowing instruction execution In this case upon detecting a valid WAKEUP signal only the oscillator circuitry is enabled The WATCHDOG Counter and Prescaler are each loaded with a value of FF Hex The WATCHDOG prescaler is clocked with the tc instruction cy-cle (The tc clock is derived by dividing the oscillator clock down by a factor of10) The Schmitt trigger following the CKI inverter on the chip ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs This Schmitt trigger is not part of the oscillator closed loop The start-up timeout from the WATCHDOG timer enables the clock sig-nals to be routed to the rest of the chip The delay is not activated when the device comes out of HALT mode through RESET pin Also if the clock option is either RC or External clock the delay is not used but the WATCHDOG Prescaler -Counter contents are changed The Develop-ment System will not emulate the256tc delayThe RESET pin or Brown Out will cause the device to reset and start executing from address X’0000 A low to high tran-sition on the G7pin(if single pin oscillator is used)or Multi-Input Wakeup will cause the device to start executing from the address following the HALT instructionWhen RESET pin is used to exit the device from the HALT mode and the two pin crystal resonator(CKI CKO)clock option is selected the contents of the Accumulator and the Timer T1are undetermined following the reset All other information except the WATCHDOG Prescaler Counter contents is retained until continuing If the device comes out of the HALT mode through Brown Out reset the contents of data registers and RAM are unknown following the reset All information except the WATCHDOG Prescaler Counter contents is retained if the device exits the HALT mode through G7pin or Multi-Input WakeupG7is the HALT-restart pin but it can still be used as an input If the device is not halted G7can be used as a gener-al purpose inputIf the Brown Out Enable mask option is selected the Brown Out circuit remains active during the HALT mode causing additional current to be drawnNote To allow clock resynchronization it is necessary to program two NOP’s immediately after the device comes out of the HALT mode The user must program two NOP’s following the‘‘enter HALT mode’’(set G7data bit)instructionhttp www national com10Functional Description (Continued)MICROWIRE PLUSMICROWIRE PLUS is a serial synchronous bidirectional communications interface The MICROWIRE PLUS capabil-ity enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i e A D con-verters display drivers EEPROMS etc )and with other mi-crocontrollers which support the MICROWIRE PLUS inter-face It consists of an 8-bit serial shift register (SIO)with serial data input (SI) serial data output (SO)and serial shift clock (SK) Figure 6shows the block diagram of the MICRO-WIRE PLUS interfaceTL DD 11208–8FIGURE 6 MICROWIRE PLUS Block Diagram The shift clock can be selected from either an internal source or an external source Operating the MICROWIRE PLUS interface with the internal clock source is called the Master mode of operation Operating the MICROWIRE PLUS interface with an external shift clock is called the Slave mode of operationThe CNTRL register is used to configure and control the MICROWIRE PLUS mode To use the MICROWIRE PLUS the MSEL bit in the CNTRL register is set to one The SK clock rate is selected by the two bits SL0and SL1 in the CNTRL register Table III details the different clock rates that may be selectedTABLE III SL1SL0SK Cycle Time002t c 014t c 1x8t cwheret c is the instruction cycle timeMICROWIRE PLUS OPERATIONSetting the BUSY bit in the PSW register causes the MI-CROWIRE PLUS arrangement to start shifting the data It gets reset when eight data bits have been shifted The user may reset the BUSY bit by software to allow less than 8bits to shift The device may enter the MICROWIRE PLUS mode either as a Master or as a Slave Figure 7shows how two device microcontrollers and several peripherals may be interconnected using the MICROWIRE PLUS arrangement Master MICROWIRE PLUS OperationIn the MICROWIRE PLUS Master mode of operation the shift clock (SK)is generated internally by the device The MICROWIRE PLUS Master always initiates all data ex-changes (Figure 7) The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration regis-ter Table IV summarizes the bit settings required for Master mode of operationSLAVE MICROWIRE PLUS OPERATIONIn the MICROWIRE PLUS Slave mode of operation the SK clock is generated by an external source Setting the MSEL bit in the CNTRL register enables the SO and SK functions on the G Port The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register Table IV summarizes the settings required to enter the Slave mode of operationTL DD 11208–23FIGURE 7 MICROWIRE PLUS Applicationhttp www national com11。
9208万用表说明
9208万用表说明为了更好地满足市场需求，满足用户的测试和测量要求，我们推出了新一代的9208万用表。
这款万用表集成了先进的技术和功能，为各行各业的专业人士提供了高精度、多功能和便捷的测试解决方案。
本文将向您介绍9208万用表的主要特点、功能和适用场景，帮助您更好地理解并使用这款仪器。
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