Quantitative strain and stress measurements in GeSi dual channels

Materials Science and Engineering B124–125(2005)118–122Quantitative strain and stress measurements in Ge/Si dual channelsgrown on a Si0.5Ge0.5virtual substrateN.Cherkashin a,∗,M.J.H¨y tch a,E.Snoeck a,A.Claverie a,J.M.Hartmann b,Y.Bogumilowicz ca CEMES-CNRS,29rue J.Marvig,31055Toulouse,Franceb CEA-DRT,LETI/D2NT,CEA—GRE,17avenue des Martyrs,38054Grenoble Cedex,Francec STMicroelectronics,850rue Jean Monnet,38921Crolles Cedex,FranceAbstractThe incorporation of compressive strained Ge/tensile strained Si bi-layers in the active regions of MOSFETs is a promising route for creating ultimate Si-based devices due to the considerable increase of the mobility of spatially confined holes/electrons.The main challenge in device application is to be able to control and manipulate strain within such thin layers.This paper reports on quantitative measurements of strain in a structure consisting of a8nm Ge/5nm Si heterostructure grown by chemical vapour deposition on top of a relaxed Si0.5Ge0.5buffer layer. Geometric phase analysis of high resolution TEM images is used to measure the strain within Ge and Si layers.The in-plane stress within each layer is deduced.Experimental results are compared with the predictions of elasticity theory and discussed in terms of effect of defect formation.©2005Elsevier B.V.All rights reserved.Keywords:Heterostructures;MOSFETs;Quantitative;Strain1.IntroductionThe incorporation of materials such as SiGe in the active regions of MOSFETs is a promising route for creating ulti-mate Si-based devices[1].By growing compressive strained Ge/tensile strained Si bi-layers on Si1−x Ge x virtual substrates, the mobility of spatially confined holes/electrons is consider-ably increased[2,3].Indeed,strain determines the alignment of energy bands at the interfaces thus influencing the confinement energy of electrons and holes in quantum wells.Strain modifies the local crystal symmetry and consequently allows the possibil-ity of influencing the recombination rates of electrons and holes in device structures.The main challenge with such complex het-erostructures is to be able to control and manipulate strain within each layer.Any strain relaxation(induced by defect generation,sur-face corrugation[4–6],diffusion through interfaces and etc.) would cause carrier delocalization and mobility loss,leading to severe degradation of device performance.It is therefore essen-∗Corresponding author.E-mail address:nikolay@cemes.fr(N.Cherkashin).tial to develop a method giving quantitative information on strain within nanometer thick layers.Existing strain measurement techniques like X-ray diffrac-tion and micro-Raman spectroscopy[7]have spatial resolutions on the orders of microns that restricts their application.On the other hand,convergent-beam electron diffraction(CBED)com-bined with the very small electron probe has proved versatile for analyzing strain in nanoscale devices[8].However,this method provides only discrete measurements of strain from point to point and often needs complicated simulations to interpret results. Geometric phase analysis(GPA)of high resolution transmission electron microscopy(HRTEM)images overcomes these limita-tions with direct mapping of continuous strain distributions and comparatively simple analysis[9,10].Here,we report on quantitative measurements of strain by means of GPA in a structure consisting of a8.5nm Ge/5.1nm Si bi-layers grown by reduced pressure chemical vapour deposi-tion(RP-CVD)on top of a relaxed Si0.5Ge0.5buffer layer.GPA consists in measuring the displacement of the crystalline lattice across the layers,compared with the reference Si0.5Ge0.5buffer layer,by Fourierfiltering of a cross-sectional HRTEM image. The in-plane stress within each layer is deduced.Experimen-tal results are compared with the elasticity theory predictions0921-5107/$–see front matter©2005Elsevier B.V.All rights reserved. doi:10.1016/j.mseb.2005.08.054N.Cherkashin et al./Materials Science and Engineering B124–125(2005)118–122119and discussed in terms of defect formation.Particular attention is paid to the characterisation of defects within these layers by weak beam TEM imaging.2.Experimental detailsThe Si0.49Ge0.51virtual substrate was grown by RP-CVD at 850◦C and consists of,starting from the Si(001)substrate, a5␮m-thick SiGe layer with a Ge content gradually increas-ing from a few%to51%,a0.8␮m-thick relaxed Si0.49Ge0.51 layer.After some polishing,a8nm c-Ge/5nm t-Si bi-layer was deposited on top(see[11]for more details).TEM samples were prepared for cross sectional(CS)imaging along the[110]directions and for plan-view(PV)imaging along the[001]directions using the standard techniques involving mechanical grinding followed by ion milling.Different TEM methods were used for characterising the structure:(1)Weak beam darkfield(WBDF)imaging with g=2–20and004in(110)CS and(001)PV was used to visualize extended defects[12].(2)Bright Field Off-Bragg imaging was used to distinguish thelayers of different Ge contents(SiGe,Ge,Si,oxide)[13].For this,the specimen was tilted away from the zone axis keeping the interface planes parallel to the electron beam.(3)HRTEM was performed to image the atomic columns in thestructure and thus identify the defect structure,measure the interface roughness and deduce the in-plane stress within the Ge and Si strained layers[9,10].A Jeol2010operating at200keV was used to acquire images using techniques(1)and(2).A CM30Philips operating at 300keV was used for HRTEM related work(3).Fig.2.Off Bragg BF images showing the near surface region.3.Results and discussionA typical WBDF image of the structure is presented in Fig.1a.A dislocation network is seen extending from the Si substrate and up to5␮m.Dislocations are either parallel(see Fig.1,marked by white arrows)or perpendicular to the electron beam direction [110](see Fig.1,marked by black arrows).The upper position of the dislocation network has been extracted from the positions of the dislocations parallel to the electron beam(see Fig.1b) which probability to be“seen”does not depend on the TEM specimen thickness.From such measurements it can be deduced that the graded layer where dislocations stand is roughly5␮m-thick.Meanwhile,the crystalline part free of defects on top including the relaxed constant composition Si0.49Ge0.51layer and the c-Ge/t-Si bi-layer is of about0.8␮m thick.Fig.2is an off-Bragg BF image showing the top layers of the sample.In this image,the darker the layer,the larger the Z and/or the atomic density.From this image the different layer thickness can be measured with an accuracy of about0.5nm.The thickness of the Ge strained layer,the Si strained layer andthe Fig.1.WBDF images showing the depth-distribution of dislocations within the graded SiGe layer.Dislocations ending at the TEM specimen surface are marked by white arrows.Dislocation lines lying within the image plane are marked by black arrows.(a)Overall structure of the sample and(b)upper region of the dislocations network.Note that only parallel dislocations are seen in the upper part of the image.120N.Cherkashin et al./Materials Science and Engineering B124–125(2005)118–122Fig.3.WBDF image showing defects at the SiGe/Ge*interface. native oxide are8.5,5.1and1.7nm,respectively.The interfaces areflat(±0.5nm range)except around defects.WBDF images of the near surface area(Figs.3and4)of the sample show that there are defects within the strained layers.A small number are dislocation loops pinned at,or close,to the SiGe/Ge strained layer interface(Fig.3).Stacking faults are also observed in the Si strained layer(see Fig.4a)and originate from the Ge/Si interface.The structure of these defects has been unambiguously determined by HRTEM(see Fig.4b)and PV (001)WBDF imaging(Fig.5)as being mostly{111}half-loops with dislocation ends at the surface.The density of{111} stacking faults in the Si strained layer seems to be considerably higher than that of dislocation loops at the SiGe/Ge strained layer interface.The size of such defects varies from5to60nm and the surface density is about6×1010cm−2.No misfit dislocations are detected in the50␮m2area.It is interesting to note that the interstitial defect located within the tensile Si layer helps relax the strain in this layer through the projection of its Burgers vector(1/3[111])onto the interface plane.The occurrence of such defects leads to local distortions of the matrix and to“bulbs”on the surface.Strain measurements are obtained from images such as Fig.6a following the GPA method[9,10].From a Fourier transform of HRTEM micrograph,two[1–11]and[−111]Fig.5.WBDF(001)PV image with g=220showing high density of dislocation half-loops(see the insertion)marked by arrows.reflections are chosen to reconstruct two phase images, P g(r)=−2πg.u(r),with g1=[002](Fig.6b)and g2=[−220] (Fig.6c)and u(r)the displacementfield.Taking the Si0.5Ge0.5 lattice as the reference(P g(r)=0),the phase image,P g(r),gives the component of the displacementfield,u(r),in the direction of the reciprocal lattice vector,g.A gradient in the phase parallel to g indicates a change in the local lattice parameter.The intensity profile in the[002]phase image and across the SiGe/Ge*/Si*structure,P g1(r),normalized by2π,is shown in Fig.6b(note that P g1(z)phase image was unwrapped to over-come0/2πphase jump).As seen in Fig.6b,the phase shift linearly decreases from0(region I,SiGe/Ge*interface)down to−0.7(region II,Ge*/Si*interface).It then changes slope and linearly increases up to−0.2(region III,Si*/surface oxide inter-face).Such a phase gradient reflects the homogeneous expansion and compression of the Ge*and Si*lattices in the z direction, respectively.In turn,linear slopes indicate a negligible effect of strain relaxation in the direction[110]parallel to the elec-tron beam that might appear at thin regions of a TEM specimen (typically within20–50nm range).Indeed,one would expect to observe non-linear behavior of P g1(z)if such strainrelaxation Fig.4.(a)WBDF image showing{111}stacking faults and(b)HRTEM image of a(111)stacking fault originating from the Ge*/Si*interface.N.Cherkashin et al./Materials Science and Engineering B124–125(2005)118–122121Fig.6.(a)original HRTEM image,(b)Phase shift image P g1(z),g1=[002]with intensity profile across the structure,(c)Phase image P g2(z),g2=[−220].has occurred as the effect should become more pronounced at a longer distance off the interfaces.The structure SiGe/Ge/Si is self-prevented from a relaxation due to the fact that tensile Si tends to shrink while compressive Ge tends to expand in the[110]direction thus leading to the preservation of bi-axial strain even at thin regions of a TEM specimen.The phase imageP g2(z),g2=[−220]is presented in Fig.6c.The brighter con-trast in the image of the Ge*layer in comparison with the SiGe matrix reflects that the in-plane lattice parameter is somewhat larger in Ge*than in the SiGe layer.This shows that partial relaxation of the Ge*layer has occurred,probably because of the defects at the SiGe/Ge*interface.The[002]phase profile across the SiGe/Ge*/Si*structure, P002(z)shown in Fig.6b can be used to obtain the strain com-ponent␧SiGe relative to SiGe[9,10]:εSiGe zz =c Ge∗,Si∗−a SiGe=−a SiGe∇z P0024π(1)where c Ge∗,Si∗is the lattice constant of Ge*or Si*in the[001] direction,a SiGe is the lattice constant of Si0.49Ge0.51and∇z P002 the phase gradient along[001].The map of the strainεSiGezz calculated from the local phasegradient is shown in Fig.7.It is seen that in the z,i.e.the [001]direction,the Ge*layer is under expansion(average valueεSiGe zz =+2.8%)while the Si*layer is under compression(aver-age valueεSiGezz =−3%).There is also a difference in abruptness between the two inter-faces.The Ge*/Si*interface appears sharp(in terms of strain) while the SiGe/Ge*interface is slightly smoother.εSiGe xx would be zero if no relaxation had occurred in the layersand is very small here.From theεSiGezz andεSiGexxcomponents measured by the GPAmethod,we can calculate the strain componentsεSi xx,εGe xx,εSi zz,εGe xx of the strained layers given by:εSi∗,Ge∗xx =a Ge∗,Si∗−a Si,Gea Si,Ge=a SiGe−a Si,Gea Si,Ge(2)εSi∗,Ge∗zz=c Ge∗,Si∗−a Si,Gea Si,Ge=(εSiGezz+1)εSi∗,Ge∗xx+εSiGezz(3)and the in-plane stressesσGe11andσSi11given by:σSi,Ge11=c Si,Ge11εSi∗,Ge∗xx+c Si,Ge12(εSi∗,Ge∗xx+εSi∗,Ge∗)(4)where c Ge12=4.4×1010Pa,c Ge22=12.6×1010Pa,c Si12=6.4×1010Pa and c Si12=16.6×1010Pa are the elastic constants of GeandSi.Fig.7.Strainfield image,εSiGezz,with the SiGe lattice as a reference,togetherwith the profile drawn across the interfaces.122N.Cherkashin et al./Materials Science and Engineering B124–125(2005)118–122 Table1Experimental and theoretical results of strain and stress calculationAA Ge SiεGe xx(%)εGe zz(%)εGe11(GPa)εSi xx(%)εSi zz(%)εSi11(GPa)Experimental−1.5+1.1−2.15+1.3−1.0+2.3Theoretical−2.0+1.4−2.79+2.1−1.6+3.78The following values have been used for the lattice parame-ters a Si=0.5431nm,a Ge=0.5.658nm,a SiGe=0.5545nm.Thelattice parameter of Si0.5Ge0.5was calculated using Vegard’slaw[3].These data can be compared to predictions from the elasticitytheory assuming that no relaxation has occurred in the strainedlayers.The theoretical value ofεSi∗,Ge∗zzis given by:εSi∗,Ge∗zz =−2c12c22εSi∗,Ge∗xx(5)The results of the measurements together with these theoretical values are presented in Table1.The in-plane stress measured within the Ge*layer is less than the theoretical value for no relaxation.This is a clear indication that the Ge*layer is slightly relaxed and might be related to the presence of some defects at the SiGe/Ge*interface.In turn,the in-plane lattice param-eter of Ge*is somewhat larger than that of Si0.5Ge0.5.This should lead to an increase of the in-plane stress within the Si* layer and,consequently,increase the probability of defect cre-ation.This is indeed observed,as the stress values measured in Si*are less than expected for no relaxation and the Si*layer contains dense array of half-loops.This stress increase is how-ever apparently not compensated by the defects seen in the Si* layer.Although the SiGe surface was polished before Ge deposition [11],few defects seen at the SiGe/Ge*interface(see Fig.3)could be created due to residual roughness of the SiGe surface(Fig.2, marked by an arrow).Meanwhile,as the Ge layer surface is always found to beflat(Fig.2),it is tempting to propose that due to the compressive stress within the Ge*layer being less than the tensile stress within the Si*layer,{111}stacking faults are formed during Si deposition.The lattice of the underlying Si0.49Ge0.51buffer layer causes the contraction of the in-plane Ge lattice equal to the expansion of the in-plane Si lattice.This would lead to an ideal compensa-tion of the compressive in-plane stressσGe11by the tensile stress σSi11,thus giving:σGe11+σSi11=0(6) only if the elastic constants of Si and Ge were the same.As c12,c22are different for Ge and Si,this equilibrium does not occur for a buffer layer of Si0.5Ge0.5.This should happen for a particular Ge content x which we have determined from eq.6 and4by calculation a SiGe.We have found that if x is less than 42.5%then the Ge*layer will be more stressed in compression than the Si*layer is stressed in expansion(σGe11>−σSi11).The opposite situation is observed if the Ge content is larger than 42.5%(σGe11<−σSi11)as we experimentally observed(Table1). Thus,to balance the stress found in the Ge and Si layers(σGe11=−σSi11),a Si1−x Ge x virtual substrate with x=42.5%should be selected.4.ConclusionsIn this paper,we have demonstrated that it is possible to grow at850◦C high quality Si1−x Ge x virtual substrate with x up to 50%and to achieve a high degree of symmetrical compensa-tion of in-plane compressive/tensile stress in pairs of strained Ge/Si thin layers subsequently grown on the top of such a vir-tual substrate.We have carried out quantitative measurements of strain on a structure consisting of strained8.5nm-thick Ge and 5.1nm-thick Si pared with elastic theory assuming no relaxation,the compressive stresses within the Ge*layer are lower by20%and the tensile stresses within the Si*layer lower by40%.Such partial relaxation is due to the creation of structural defects at the SiGe/Ge*interface.The tensile stress increase in the Si*layer is partly compensated by creation of high density of{111}dislocation half-loops.The nanometer scale measure-ment of strain in SiGe/Ge/Si heterostructures using GPA makes it a powerful tool for the characterization of active region in MOSFETs.AcknowledgementThis work was partly supported by the Integrated Project NanoCMOS funded by the European Union.References[1]D.W.Greve,Mater.Sci.Eng.B87(2001)271–276.[2]M.L.Lee,E.A.Fitggerald,Appl.Phys.Lett.83(2003)4202–4204.[3]M.A.Herman,Cryst.Res.Technol.34(5–6)(1999)583–595.[4]N.F.Izyumskaya,V.S.Avrutin,A.F.Vyatkin,Solid-state Electron.48(2004)1265–1278.[5]L.Vescan,S.Wickenhauser,Solid-State Electron.48(2004)1279–1284.[6]J.Tersoff,F.K.LeGoues,Phys.Rev.Lett.72(22)(1994)3570–3573.[7]X.H.Zheng,H.Chen,Y.K.Li,Q.huang,J.M.Zhou,J.Cryst.Growth264(2004)104–109.[8]F.Wu, A.Armigliato,R.Balboni,S.Frabboni,Micron31(2000)211–216.[9]M.J.Hytch, E.Snoeck,R.Kilaas,Ultramicroscopy74(1998)131–146.[10]E.Snoeck,B.Warot,H.Ardhuin,A.Rocher,M.J.Casanove,R.Kilaas,M.J.Hytch,Thin Solid Films319(1998)157–162.[11]Y.Bogumilowicz,J.M.Hartmann,N.Cherkashin,A.Claverie,G.Rol-land,T.Billon,Mater.Sci.Eng.124–125(2005)113.[12]D.B.Williams, C.B.Carter,Transmission electron microscopy,3,Plenum Press,New York and London,1996,pp.421–438.[13]D.B.Williams, C.B.Carter,Transmission electron microscopy,3,Plenum Press,New York and London,1996,pp.450–453.。