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CadenceAllegro16.5培训教程

CadenceAllegro16.5培训教程

CadenceAllegro16.5培训教程Cadence Allegro 16.5培训教程引言Cadence Allegro 16.5是一款功能强大的电子设计自动化工具,广泛应用于电子设计领域。

本文档旨在提供有关Cadence Allegro 16.5培训教程的详细信息,帮助初学者快速上手使用该工具。

第一部分:介绍1.1 Cadence Allegro 16.5概述Cadence Allegro是一款专业的PCB设计工具,提供从原理图设计到布局绘制和印制板制造的全面工作流程。

它具有强大的功能和灵活的工作环境,能够满足各类电子产品的设计需求。

1.2 Cadence Allegro 16.5的优点- 强大的功能:Cadence Allegro 16.5提供了丰富的设计工具,包括原理图绘制、版图设计、信号完整性分析等,能够满足复杂电路设计的需求。

-多种设计约束:Cadence Allegro 16.5支持多种设计约束设置,如电气约束、尺寸约束、信号完整性约束等,保证设计的可靠性和稳定性。

- 高度集成:Cadence Allegro 16.5与其他Cadence软件工具的无缝集成,如OrCAD、Allegro PCB SI等,方便设计师实现整个设计流程的协同工作。

- 内置验证机制:Cadence Allegro 16.5提供了强大的验证工具,如设计规则检查、布局识别检查等,帮助设计师快速发现和解决问题。

- 全面的制造支持:Cadence Allegro 16.5支持从布局到印制板制造的全面工作流程,包括设计生成、工艺规划、生产输出等,保证设计的可制造性和可靠性。

第二部分:基础知识2.1 Cadence Allegro 16.5界面介绍Cadence Allegro 16.5的界面由主窗口、菜单栏、工具栏、设计文件预览等组成。

本节介绍各个组件的功能和使用方法。

2.2 常用命令本节介绍Cadence Allegro 16.5中一些常用命令的使用方法,如绘制元件、连接电路、设置约束等。

Cadence Allegro 中文简易手册说明书

Cadence Allegro 中文简易手册说明书

Cadence Allegro简易手册Allegro PCB Layout SystemLab Manual.CHAPTER 1 熟悉环境在开始前请将范例复制到您的工作路径下如:<在安装路径下>\share\pcb\selfstudy\user1 Æ c:\allegroclass\user1启动程序开始Æ程序集ÆCadenceÆPCB systemÆAllegro(电路板工具)开始Æ程序集ÆCadenceÆPCB systemÆPad Designer(焊点编辑)开启旧档选 FILE/OPEN 请开启 C:\AllegroClass\User1\Cds_Routed.brd档如果选了Change Dir 则会将现有路径C:\AllegroClass\User1变成你的内定工作路径认识你的工作窗口有指令区menu bar图标区icon ribbon控制盘control panel工作区design window状态区status window命令区console window.若想自定窗口位置customize 则选View-Customization / Display可设左侧control panel 所放的新位置为浮动式undocked贴左侧Docked_left贴右侧Docked_right(系统值)View / customization / toolbar 则设定控制图标区显示效果项目…显示缩放Zoom by Point Æ显示框选区以左键框二点Zoom fit Æ显示资料全区Zoom in Æ放大比例Zoom out Æ缩小比例Zoom world Æ显示整个工作区Zoom center Æ光标点为下个屏幕中心按Ctrl键配合按着的鼠标右键画w即可Zoom fit.若画Z即可Zoom in画面平移PAN1.利用方向键可平移2.三键鼠标则按中间键即可动态平移.若为二键鼠标则为右键+shift显示项目控制在右侧的控制盘中有visibility 项目来控制显出的对象打勾者代表要显示详细的设定则用指令Setup-color/Visibility而这些对象分成群组 Group级Class次级 Subclass在此可控制图层及各项目的显示与否,我们顺便试一下如何录script1选File-Script指令,键入文件名为colors(勿按Enter键),再点选Record记录2 选Color/Visibility指令,如果要全关选右上角的Global Visibility将值改为All Invisible确定后选套用Apply.这样会关所有显示项目3 选群组中的Components,找到Class里的Ref Des请把它底下的Assembly_top 方框勾选起来表示开启其显示4 选群组中的Geometry把它Board Geometry里的OUTLINE打开, 也把Package Geometry里的Assembly_top 打开5 选群组中的Stack-up,把TOP和BOTTOM的Pin.Via.DRC.Etch打开.而GND及VCC只开DRC.ANTI ETCH如果要设新颜色请在下方色盘Palette中选要用的新颜色,再将它点到要修改项目的色块上就可改过来了6 停止script录制选 File-Script-Stop.先前的层面及颜色设定都会被存在colors.scr中.此colors.scr是一个文字文件,可用一般的文字编辑程序或File-File Viewer加以编辑如果要测试script,请先用All Invisible全关所有显示,再到下方命令列中输入replay colors就会看到程序把先前的设定重跑一次,而显示也回来了标示亮度Highlight将特定对象标示亮度以图形效果显示其特异性如以要找一颗U3的零件为例:1先Zoom in2选标示亮度Display Æ Highlight或其图示3在右侧选高亮度的颜色4选Control panel 中的Find 页面5在Find by name 后net改成symbol (因为是找零件)6点Move键找到U3 (敲入U3 U* 按Tab键)按Apply OK7光标移至右下角全图显示区按右键选Find Next 即可将此对象显示于画面中央控制可被选取对象在编辑对象如:移动复制删除之前须选到所要的对象所以选取对象等的控制会影响后续的动作流程以移动U4的零件及移动U4零件名称RefDes为例1Zoom in到U4附近(在左上角)2选Edit Æ Move指令3选右侧的Find页面4在Find的页面中选全选ALL ON5点 U4的字符串部份你会看到U4会被抓到游标上而你正在移动U4这颗零件(因为symbol有被选取)6选右键中的OOP取消移动U4的动作7在Find页面中选全关ALL OFF 只选Text项目8再选U4字符串部份只有U4字符串被抓起像在调文字面的位置所以跟选择项目很有关系9取消检查数据项利用Display Æ Element 或其图标检查对象内容1先Zoom in2选Display Æ Element或图示3在Find中选ALL ON4随点选对象的不同会显示其相关的资料CHAPTER 2零件的整备本阶段要试建一颗14PIN DIP 零件零件的组成有焊点 PADSACK零件Package symbol每一个接脚PIN及孔Via皆视为一焊点PADSTACK如以60-38为例进入程序开始Æ程序集Æ cadence Æ PCB Systems Æ PAD Designer改种类为贯孔Through单位为mil精确值为1 (小数后1位)焊点在每一铜箔层皆要有一般点regular PAD梅花瓣Thermal-relief PAD挖开点Anti-PAD的三种效果1选Layer 页面2点选Begin Layer3在一般点项目设形状为Circle width为60height为604在梅花瓣设形状为circle值为80Flash项目为TR805在挖开点设形状为circle值为80由于其它层设定相仿可点左侧Bgn按右键copy复制6点internal 的左侧按右键选右键paste即可贴入不须重key in7以同样方法贴到END层8在SOLDERMASK_TOP层的Regular PAD设circle大小为709一样复制到SOLDERMASK_BOTTOM钻孔定义如果定为Through-Hole焊点须定孔径及钻孔符号在Drill Hole 项目中定Plate Type 为Plated (孔壁镀铜)孔径38. Drill symbol的Figure为钻孔符号效果Character为标示字符串Width height为符号的宽及高储存焊点选File Æ Save as 存到 C:\allegroclass \ user1 档名为 60C38d.PAD实体零件的建立建立实体零件的格式不同所以须进入零件建立模式下1File / New 在DRAWING NAME中敲入新零件名如DIP14并在DRAWING TYPE中选PACKAGE SYMBOL2设作图环境选SETUP – DRAWING SIZE在Move Origin项目中的XY各敲入5000使原点调整至适当位置3加入焊点选ADD PIN或其图示并右侧OPTION项目中敲入焊点60S38D后按Tab键状态列会显示出Using ‘ 60S38D.PAD’4光标移至状态列点选后敲入x 0 0会把第一接点放到原点 00的位置上(x须为小写)窗口缩放到PIN1附近5在右侧OPTION中改焊点为60C38D后按Tab键在Y的Qty项目中输入6 6在状态列输x 0 100则会放入向下距100mil的27接点7把Y项目的Qty改7个次序order改up8状态列输入x 300 –600会放入第8PIN到14PIN之焊点但是其脚号仍位于焊点左侧可按右键之OOP取消9将OPTION中的OFFSET值由-100改为100 (表右边100mil处)于状态列输入x 300 -60010完成按右键中的DONE文字面绘制 SILKSCREEN要调整格点大小时请以SETUP /GRIDS将NON-ETCH的X Y值键入25表文字面绘制格点为251选ADD/LINE2将右侧OPTION选为Package Geometry下的SILKSCREEN_TOP设画线角度等3画上文字面的矩形框组装外型绘制Assembly outline (可省略)同文字面之动作但层面为Package Geometry下的Assembly-Top设文字面之零件名称及零件号1选Layout_Label Æ Ref Des或其图示2图面为 refDes下的Assembly_Top3点选放零件名称的好位置(须在Assembly outline中)4键入名称如U* (请先注意右侧的字体基准点角度)5选Layout_Label中Æ Device6选适当的位置后键入 dev type后按右键的DONE绘制零件限制区Package boundary (可省略自动抓)定义零件高度(需要有Package boundary才可定义)1Setup-Area-Package Boundry Height层面为Package Geometry下的Place_Bound_Top2点先前建的Package Boundry 区域3输入高度值如180若没设则以Drawing option下的symbol Height为其内定高度值存零件文件(两者都要存)1选File Æ Create Symbol存成可放到PCB上的.PSM檔2选File Æ SAVE存成供以后修改的图形.DRA檔以自动程序建零件利用Symbol Wizard填入参数自动建零件1、File /New后在Drawing Name键入名称如dip16在Drawing type选PackageSymbol [Wizard] 后选OK2选Package Type为dip后点Next (选零件包装)3套用CADENDCE规划选Default Cadence Supplied template套用其它零件则选Custom template后选.Dra档套入后选Next4设定使用的公英制准确位数及名称前字符串prefix5依不同零件外形设定其参数如脚数Number of Pins脚距LeadPitch行距Terminal row spacing文字面的宽及长Width&Length)6选套用的焊点(一般焊点及第一脚)7定零件原点为中心center of body或第一脚pin1 of symbol及是否另存.PSM檔8选Finish 即OKCHAPTER 3板框绘制板框在Allegro中属于特殊的Mechanical Symbol板框为电路板的外形尺寸,其来源可由手工绘入.,键坐标输入画成.如果有Option 接口的话可由AUTOCAD转入DXF或Pro-Engineer的IDF.键坐标画图框1选File一New,在檔名Drawing Name中敲入如cds_outline.请注意格式务必改成Mechanical Symbol后按OK2设绘图区选Setup一Drawing Size.将图区Size设成A.并把DRAW Extent改设成Left X与Lower Y在设原点偏移量.Width 与Height设工作区大小设工作格点选Setup一Grids.将Non-Etch的格点设为25后按OK画板框选Add一Line.注意层面须改成BOARD GEOMETRY/OUTLINE.请输入x 0 200iy 2300ix 4000iy –2300ix –100iy –200ix –3700iy 200x 0 200 完毕按右键下的Done定工具孔Tooling Hole选指令Add Pin在右侧的Padstack中输入hole109再按Tab键.请在命令列输入x 100 300x 100 2400x 3900 2400 完毕按Done 结束标尺寸Dimension利用Dimension linear指令,层面会自跳到BOARD GEOMETRY下的DIMENSION.点选被测线段就可拖出其尺寸标注线放上.倒角Chamfer如果画的板框有直角要倒角,可用指令Edit一Chamfer.在右侧Options中TrimSegment的First栏设50.表示未倒角的两边线段长为50mil.试着点要倒角的第一段线,再点它的垂直线,就可做出倒角效果来设走线及摆零件区1先Zoom in到图框的左下角,2选Setup一Area一Route Keepin(走线区)在板框内的50mil(二个格点)内画出其布线限制区.(会在ROUTE KEEPIN下的ALL.)3选Setup一Area一Package Keepin(摆零件)画出相同的限制区设禁止摆零件及走线区选Setup一Area一Route Keepout(走线)画上不能走线的范围,其显示为一填满区.试画过后请Edit一Delete删除(在Find中要勾Shape),否则稍后可布线区域可能不够.其它如ViaKeepout则为禁打贯孔区存板框檔1选File一Create Symbol设入档名如cds_outline后选Save会存成cds_outline.bsm的Board Symbol 檔.2再选File一Save存成cds_outline.dra的图形文件.建立环境档Master Design File (.brd)环境档通常是只先放入板框而未含有逻辑数据的作图文件.利用它把大家讨论过认证的Geometry先设好的存在图档上.达到统一作图环境的目的.当成公司内的标准档.1选File一New,在檔名Drawing Name中敲入如cds_master.请注意格式为Layout 后按OK2设绘图区选Setup一Drawing Size.将图区Size设成B.,小数后位数Accuracy设成2.并把DRAW Extent的Left X设成-5000 ,Lower Y设成-5000完成按OK3放入板框零件,选Place一By Symbol一Mechanical,先点Library键才会列出各Mechanical Symbol,选先前建的cds_outline后按OK键准备放到图上4在命令列敲入x 0 0 ,放到图上(0,0)点.完毕按Done加图框Format Symbols如果要加上图框或其它注意事项宣告1Place一By Symbol 一Format, 先点Library键使列出各Format Symbol.如果点选Asizeh.表示要挂上A Size 横向的图框2利用光标把图框放至工作区上(请并确定板框数据含于图框范围内)3按右键选Next选到Note这个Symbol4请放在图框内板框外的适当区域中预放零件如果有特定的零件位置或固定的某几颗零件如connector.switch.等等.可以先摆到板上1选Place一By Symbol一Package.点Library使列出各实体零件.请选其中的conn140后按OK2在命令列输入x 3775 -200后按Done摆到图上设颜色1进到Color/Visibility中设定显示项目或其颜色.如果先前已存有Script 文件请Replay控制图形效果,请在命令列输入 replay colors层数设定Cross SectionAllegro内定的板层为二层板(指二个电气层).您如果是多层板则必须先宣告其层面结构.如层数.材质.用途.Subclass name.正负底片效果等.而其材质的种类及特性定义在<cds ins dir>/share/pcb/text/materials.dat檔中1选Setup一Cross Section点FR-4层名左侧的Edit后选Insert新增,则在原层之上会加入一个新的FR-4层.请总共新加入8层,因为我们待会要宣告此板为六层板,加上五层FR-4介质层及二层原有的空气层全部为13层.2点选第二个FR-4层准备把改设为内层的GND.请点其材质Material项目改设为铜箔Copper,将层面特性Layer Type改选成Plane,而Etch Subclass name取名成GND.最后把其底片效果由念Positive改为Negative表示此层为负片.3最后设定完成如下.表示此板为47.2mil厚的六层板.如果要删层则点选那一层其左侧的Edit键后按右键选删除Delete即可存环境档宣告完毕要存成环境档,请用File-Save As另存新档设入档名为cds_master1.brd 存入.通常Allegro的环境档可统一放在<course inst dir>/allegro/project1/worklib/esdesign/physical路径下CHAPTER 4加载联机关系与设定规范载入联机关系Load the Netlist联机关后档是一个由线路图程序所产生的文字文件netlist目的在交代零件(外型名称)及联机关系(接点及讯号名).要是零件需要作功能互换(gate swap或pin swap)则需另定零件宣告文件device file.如果有同类型但不同名零件可用对应文件map file宣告其对应不需每颗皆定义.以ORCAD为例,再执行完ERC电器检查后.即可执行其Tools-Netlist将线路图档转出联机关系档,其格式请选用others页面里的Allegro.就可把整份图转成一个联机档 .net或.txt零件若是在布线时会做swap的联机交换则须为零件定义其Device file 以宣告其零件之脚数闸数等到时:7400会对应7400.TXT套入宣告如果二者名称不同可以devices.map档宣告其对应性.以下devices.map为例零件7400会对应到74abcd.txt的device檔而非7400.txt如果要零件宣告文件device file,新版的ORCAD 9.x可用指令Accessories-Allergo Netlist自动产生各零件的device file.不需手动以文字编辑程序逐一编写载入联机 Import Logic1. 选File/Import Logic定来源格式Logic Type为Third party.2. 来源档案 Import From 点选后再选Browse键选文字联机文件的3rdparty.txt.3. 是否替换新零件Replace changed component.设Always4. 是否允许拆原有布线Allow etch removed during eco依情况而定5. 设定转联机关系时取代原图上的逻辑数据supersede All logical.6. 要加载联机成为电路板文件选加载Import.设计规范Allegro的设计规范是在定义设计过程中的条件限制,这些条件的设定是用来作为设计时安全检查的标准.例如我们可以定义层数,各层的规范,特殊讯号的限制条件如线宽间距打贯孔数,或特定区域条件等等,以配合电器或机构考量.而且宣告过的规范存在图档上,可避免以后布线时因考量因素众多而疏漏所造成需重修的情况.设定内定设计规则内定设计规则是给图文件中未经特定宣告的任意讯号(一般线)所套用进入Setup-Constraints请点选内定标准值Default Value设定其线到线,线到点,点到点,线宽,套用的贯孔等设定其它的设计规则在一份图档上有些特殊的线有其不同的规则相对于先前定的内定标准值如CLOCK讯号它的间距如为10 mil不同于先前内定的 5 mil.其步骤为定RULE SET请点选SPACING RULE SET下的SET V ALUE.在DELETE后的空白处输入 10 MIL SPACE后点选加入键加入新的RULE SET.随后输入其各间距的值再按OK键确定宣告相关讯号选ATTACH PROPERTY -NET,选右侧的FIND点选下方的FIND BY NAME切换成NET后再输入CLK2.程序跳出其PROPERTY画面请选NET-SPACING-TYPE, 在其V ALUE中输入其组别名称如CLOCK后按APPLY确定讯号套上RULE SET选在SPACING RULE SET中的ASSIGMENT TABLE设定各个RULE SET之间的规范如CLOCK与NO_TYPE指先前订的CLOCK(本例中只有CLK2)与一般讯号NO_TYPE所套用的间距值为10 MIL SPACE设定实体规范在实体规范PHYSICAL RULE SET中选其SET V ALUE键,在DELETE后的空白处输入10 MIL LINE 后点选加入ADD键,建立新的PHYSICAL SET.随后输入其允许最小线宽MIN LINE WIDTH,缩线后最小线宽,最大线宽,是否形走线,套用的贯孔焊点为何等等.,结束按宣告相关讯号选ATTACH PROPERTY-NET,选右侧的FIND点选下方的FIND BY NAME切换成NET后再输入REF.程序跳出其PROPERTY画面请选NET-PHYSICAL_TYPE在其V ALUE中输入其组别名称如ANALOG后按APPLY确定讯号套上RULE SET选在PHYSICAL RULE SET中的ASSIGMENT TABLE套上各个RULE SET的规范如把ANALOG套上先前订的10 MIL LINE,NO_TYPE指一般讯号请套上DEFAULT.第二项为AREA是当有设定特定区域AREA时才有对应的新值可输入STUB LENGTH,允许最多贯孔数MAX VIA等等而AREA则是以特定区域的方式来宣告其特别的设定值如线宽间距等设计规范存盘我们可将前面所设好的规范存成一个技术文件TECH FILE,请选指令FILE-EXPORT-TECHFILE设好文件名再按执行RUN键即可产生下次开新文件时层面只有二层,也没有特殊线宽或间距等设定,这时你可以加载技术档..这样这些设定即不须重设只须要把新讯号重新指定其对应的规则就可了查属性要检查己订属性可用1选EDIT-PROPERTIES配合右侧FIND2 选DISPLAY-PROPERTIES指令后选要查询的值如NET_SPACING_TYPE,再于V ALUE栏输入查询值如 * 表示任意即可查到先前订的CLOCK.在您绘图的过程中Allegro会以先前订的规范持续的检查你的图档当它有违规时则会有DRC的标记在上面.而这个蝴蝶形的标记的两边各有一个英文字母代表它检查的数据种类如L表线段LINE,.V表VIA,P表PAD等等,使我们能很快的知道错误在那儿而侦测到的错误项目又是什么数据间的状况可以马上加以改正.您也可以用SHOW ELEMENT的指令来查看更详细的结果Chaper 5摆放零件在建完零件,传入联机关系,订好规则之后紧接着的就是零件的摆放动作在图示中通常已经挂上了一些有关摆放零件的图标而这些图标就如同指令PLACE下的各个摆放功能请开启位于c:\\allegroclass\user1\ 底下的constrainted.brd手动编名因为置于板上的金手指尚未命名所以我们必须手动的帮它编名请选Logic-Assign RefDes并点选右侧Options下方的RefDes字段中输入J1 点选金手指则会把这颗零件命名为J1设定摆放格点设摆放零件时移动零件的距离请选Setup-Grid下的Non-Etch将其Spacing X:值输入50,Y:值输入50.要不要显示格点则设定左上角的GRID ON以零件名称摆放Placed By RefDes一般摆零件时习惯边看线路图边摆零件,所以我们须将相关的零件逐一叫出这样就会用到此功能请选Place By RefDes指令敲入零件名U5后按OK就可抓出U5到图上准备摆入.如果想要旋转,请按鼠标右键选择Rotate这时零件上就会跑出一根控制杆到光标位置利用鼠标转动即可控制其旋转角度.按左键可停止旋转.移动到要摆的中下图区后按右键选Done放置如果摆上的零件看起来是一个填满的大方块是因为开启了它的限制区.想关闭请至Display-Color/Visibility把Package Geometry/Place_Bound_Top项目勾勾去掉除了此种方法外如果新摆入的零件都须转一个特定角度的话可到Setup-Draw Options选其中的SYMBOL把Angle字段输入或改选成90再点OK键试着抓U7进来摆,你可看到它己是旋转了90度等着您摆入移动零件如果已摆入零件其位置须要挪移请选Edit一Move后再到右侧的Find项中全关只留Symbols.请点选要移动的零件(最好点它的名称字符串)零件就会被抓到光标上,待移到新位置后,点右键按Done即完成移动一群零件同样以Edit一Move指令以鼠标左键框出一个区域,框住要一齐挪移的零件(如果要放弃框选范围可选右键下的Oops).再以左键定其基准点就可一齐移动到时再以右键下的Done确定.再框选时请勿框到 Board Outline,Keepins,keepouts的Board Symbol资料.其它摆放的动作有Place一Component一ICs 摆IC类零件Place一Component一IOs 摆输出入类零件Place一Component一Discrete 摆附属小零件Place一Component一ALL 摆所有零件联机互换的动作有Place一Swap一Component 零件位置互换Place一Swap一Functions 闸联机互换(需有device宣告)Place一Swap一pins 接点联机互换(需有device宣告)联机显示控制联机指点到点间用来表示其电气接续性的表示线.我们会依不同需求开关某些零件或讯号的显示效果来达到评估布线策略的目的显示(关闭)所有联机Display一Show(Blank) Rats一All显示(关闭)单颗零件Display一Show(Blank) Rats一Component显示(关闭)单条联机Display一Show(Blank) Rats一Net产生摆放零件报表您可以产生一份摆放零件报表它可列出图中已摆放及未摆放之零件数据您在摆完零件后可用它来再确认是否有漏网之鱼尚未摆入HAPTER 6 布线布线相关指令设定布线格点随着不同的布线须求.您可为不同层设定不同的布线格点或是设定所谓的不等距格点如8 9 8这样的工作格点.指令为Setup一Grids设定格点,其中左上角的Grids On 为设定是否显示格点.Non-Etch为非电气层格点如摆零件.All Etch为所有电气层之走线格点.Top….为各电气层之走线格点值在布线时我们必须在右侧的Options中设定布线的工作层Act及代换层Alt在走线时首先走在工作层上如果要换层只须连续点二下左键(双击)则您的工作层及代换层会自动互换并打上贯孔试走第一条线1请先关闭所有联机显示,然后选Display一Show Rats一Net按鼠标右键选其中的Net Name输入 clk2使只开此讯号的显示效果2 Zoom in到U15 选择布线图示或Route一Connect将右侧的Options中的Act 层设为Top,Alt层设为IS3,线的角度设45度线宽设5,布线效果RouteType设手动布线Manual.3 试着点线开始布线,一开始走出时是在正面ToP层,如果觉得走得不好请用右键按OoP取消删除布线如果不满意先前所走的布线结果可以用Delete指令予以删除但是请配合右侧Options或Find的选项让使用上更加的便利1.全线删除请选择删除示或指令Edit一Delete在Find下请先选ALL OFF再开Clines请点CLK2的布线,此线会全部高亮请再按右键下的Done就会把它删掉(请救回此线以执行以试作底下其它动作)2.线段删除如果要删掉的只是某些线段非整条布线,请在右侧的下Find关所有项目只留ClineSegs同样点CLK2你会只看到此线段高亮,如果点其它线段则先前的线段即消失被删除了3.二点间线段删除如果要删掉的只是某些线段内的一小段,选Edit一Delete按右键下的Cut,点要删掉线段内的第一点(线段变亮)再点第二点,则剩此区间高亮可删除.布线效果Routing Type在走线的过程中我们有三种效果可以选择,分别是手动布线Manual,循迹布线To Cursor,结点布线To Pick1.手动布线Manual--------在前一光标位置与目前的光标位置间显示出走线’不会自动闪其中的障碍但推线效果明显2.循迹布线To Cursor-----随游标带出布线的走向,可动态的看出将布线的效果,会自动的闪避其中的障碍3.结点布线To Pick--------前后光标点间无法看到动态的布线轨迹,但是会自动闪线且速度比较快走线的过程中按鼠标右键会出现一些选项Done =>布线停止,回到空-状态IdleOops =>取消前线段动作Cancel =>取消前指令Next =>布线暂停,改走其它线Temp Group =>宣告走bus线讯号Complete =>结束bus线讯号选入动作Reject =>放弃现有选取,可改选其它Add Via =>打贯孔Finish =>以同层自动走完未布线段Snap Rat T =>移动讯号T点位置Neck =>窄线布线,须依Physical Rule Set宣告New Target =>改定同讯号的目的点(布线终点)No Target =>尾段讯号不显示Swap Layer =>走线换层(Act层换到Alt层) Toggle =>出线角度切换(先直再斜或先斜再直)打贯孔贯孔是用来导通层到层之间的讯号关系,贯孔必须有焊点的特性在布线的过程若加入贯孔则其工作层与代换层就会自动切换走到对应的布线层面.动作为连续点二下左键(双击)或选右键里的Add Via.移线利用移线指令SLIDE可移动先前所布的线段.你只需要选好指令后用左键点选要移动的线段即可动态的移动此线段,而与此线段相连的线段效果也会自动调整保持整体的完整性1请开启档案CDS_ROUTED.BRD稍为Zoom in到局部区域上.请选图标区上的移线图示或ROUTE一SLIDE2在右侧的Find项目中全清只留Via及Segment3以左键点选线段移动看看,也以左键定其新的落点4可以试着改变调整右边设定如角度CORNER或最大斜线长度Max 45 Len看看它的效果修端点VERTEX要挪动,新增,重迭,删除(选右键下的DELETE VERTEX),请利用EDIT-VERTEX或按F7键.即可修整端点自动整线有Route-Custom Smooth或Route-Gloss可执行SPECCTRA自动布线当您执行ROUTE一SPECCTRA-Auto儿时Allegro会发起SPECCTRA的自动布线程序并建立一个同档名的.dsn檔.在自动布线结束后SPECCTRA会产生一个.ses檔在回到Allegro时转入成已布线档SPECCTRA手动布线执行ROUTE一SPECCTRA-Interactive,可转档到Specctra并以其EditRoute作手动布线产生未布线报表在布线完毕后.我们如果要确定定否有未布线点仍然存在.可以执行TOOLS一Reports选输出的资料为Unconnected pins再点Run键就会产生此报表加以查核CHAPTER 7 内层及铺铜如果您的设计超过二层,那么您就须要设定其内层铜箔的效果包括它的铺铜箔效果,所带的讯号名,避开的间距,内层切割等等的问题通常铜箔分二种,正片铜及负片铜.正片铜显示的是含铜的部分,也就是黑的部分以后就是铜箔.在Allegro中的正片铜您可以看到它所挖开的开孔void 及所接的梅花瓣Thermal 它的缺点是一但铜箔的接续性更改如移零件或贯孔.则铜箔须要重铺以重新连结正确的梅花瓣及挖开不同讯号点负片铜显示的是以后要挖掉铜的部分,反而是白色的部分以后才会有铺铜在Allegro中负片铜只是显示一些点在内层上面.随着所设定的讯号.程序会自动判定那些点该是要改成内层要接的Thermal Relief定义效果,那些不接的点其内层必须是挖开的Anti-Pad定义.Allegro并不会把那些焊点挂在层面上.好处是零件或是贯孔可随意移动不须重铺重算.只有在他产生底片输出时才会将焊点数据并入处理.而它的缺点是您无法在图上即看到真实的底片效果.(尤其是梅花瓣)宣告内层负片铜l.Add一Shape一Solid Fill画内层铺铜范围2.Edit一Change Net(Pick)宣告铜箔的讯号名3.Shape一Fill填铜箔1请开cds_routed.brd檔.设定Setup一Drawing Options在Display项目中勾选Thermal Pads(显示梅花瓣) 及Filled Pads and Cline Endcaps(填满式显示)选项2 选Display一Color/Visibility把Group项目改成Stack再把底下的Etch项全关只留VCC层.其它项的PIN与VIA也是只留VCC后跳出3选Add一Shape一Solid Fill在右侧设Etch及VCC层,在板内的走线区范围内Route Keepin画一个Polygon画完按右键Done结束4宣告内层讯号选Edit一Change Net(Name)在列表中选VCC后跳出5填铜箔.选Shape一Fill这样会灌满并显示出Thermal Pad(单线)及AntiPad的效果宣告内层正片铜l.Add一Shape一Solid Fill画内层铺铜范围2.Edit一Change Net(Pick)宣告铜箔的讯号名3Shape一Parameter设定自动挖开铜箔的效果4V oid一Auto执自动清铜动作(讯号不同者挖开,相同者挖开后架上桥接花辫)5Shape一Fill填满铜箔效果1 选Display一Color/Visibility把Group项目改成Stack再把底下的Etch项全关只留GND层.其它项的PIN与VIA也是只留GND后跳出2选Add一Shape一Solid Fill在右侧设Etch及GND层,在板内的走线区范围内Route Keepin画一个Polygon画完按右键Done结束3宣告内层讯号选Edit一Change Net(Name)在列表中选GND后跳出4选Shape一Parameters设定挖开的项目,间距值,效果等参数5选V oid一Auto在跑了几秒后可看到铜箔该接的变成正片的梅花瓣.不该接的自动避开挖空。

(完整word版)Cadence allegro菜单解释

(完整word版)Cadence allegro菜单解释

Cadence allegro菜单解释-—file已有 320 次阅读 2009—8-16 19:17 |个人分类:工作|关键词:Cadence allegro file 菜单解释每一款软件几乎都有File菜单,接下来详细解释一下allegro与其他软件不同的菜单。

new新建PCB文件,点new菜单进入对话框后,drawing type里面包含有9个选项,一般我们如果设计PCB就选择默认第一个board即可。

如果我们要建封装库选package symbol即可,其他7个选项一般很少用,大家可以理解字面意思就可以知道什么意思了。

open打开你所要设计的 PCB文件,或者封装库文件。

recent designs打开你所设计的PCB文件,一般是指近期所设计的或者打开过的PCB文件。

save保存save as另存为,重命名。

importimport 菜单包含许多项,下面详细解释一下我们经常用到的命令。

logic 导入网表,详细介绍在allegro基础教程连载已经有介绍,在此不再详细介绍。

artwork 导入从其他PCB文件导出的。

art的文件。

一般很少用词命令。

命令IPF和stream 很少用,略。

DXF 导入结构要素图或者其他DXF的文件。

导入方法如下:点import/DXF后,在弹出的对话框选择,在DXF file里选择你要导入的DXF的路径,DXF units 选择MM,然后勾选use default text table和incremental addition,其他默认即可.再点edit/view layers弹出对话框,勾选select all,DXF layer filter选择all,即为导入所有层的信息,然后在下面的class里选择board geometry,subclass选择assembly_notes,因为一般导入结构要素图都是导入这一层,然后点ok,进入了点import/DXF后弹出的对话框,然后点import即可将结构要素图导入.IDF IFF Router PCAD 这四个命令也很少用,略。

Cadence tutorial

Cadence tutorial

Cad ence tutorial----Design of Two-Stage Op Amps Chapter1 overviewThis tutorial will take a Two-Stage Op Amps for example to finish an analog design flow, using Cadence ICFB and verification tool, Calibre.To start a design, A Process Design Kit (PDK) is necessary. It’s a collection of verified data files that are used by a set of custom IC design EDA tools to provide a complete analog design flow. These data files include schematic symbols, SPICE models, Layout Technology File, Cell View, DRC rule file, LVS rule file, Extraction rule file, and script s that run EDA tools to automate the generation and verification of design data.Here use TSMC 0.18umPDK on Cadence ICFB platform for demo use. This tutorial will give a guide for IC designer to create a design from front-end to back-end by using this PDK.1.1Software RequirementSystem Version: Red Hat Enterprise Linux5Design Tool: Cadence IC610Verification Tool: Calibre20081.2Design Kit ContentsIn the installed PDK directory, there are following contents, shown as figure 1:(1)Design Rule(2)Spice Model(3)Skill(4)Cell View(5)CDS lib File(6)Technology File(7)Display File(8)Verification Rule File : calibre DRC/LVS/RCX(9)Document for introductionFigure1.1 PDK contents1.3Installation of PDKThe old Cadence Data Base (CDB) versions will no longer work with the new Cadence, so the old libraries need to be convert into the new OpenAccess database. Fortunately, Cadence has provided a converter, cdb2oa, that can do a good job of converting the data. This tool is part of the new ICv6 tools.To use this tool and install the PDK, do as following:Step1: create a directory to convert, here named OA_conversion.Step2: in the OA_conversion, create a directory to put the cds.lib file, here named cdb, shown as figure1.2.Figure1.2 Conversion DirectoryStep3: copy the cds.lib in the library into directory cdb. And open it with TXT, rewrite it as following, shown as figure 1.3. Save it and close.Figure1.3 rewrite cds.libStep4: in the directory of OA_conversion, start icfb&, shown as figure1.4. close What’s New in 6.1.0, and you can see the Virtuoso window as figure 1.5.Figure1.4 start icfb& in terminal of OA_conversionFigure1.5 Virtuoso windowStep5: open Conversion Tool Box by click Tools>>Conversion Tool Box…, then the window shown as figure1.6.Figure1.6 Conversion Tool BoxStep6: choose CDB to OpenAccess Translator…, then set the path of cds.llib file, then the window shown as figure1.7.Figure1.7 CBD to OpenAccess TranslatorSetp7: click ok. After it finish the conversion. Close icfb. In the directory of OA_conversion, a folder named tsmcrf18 appear, it contents the Cell View information that has been converted, and some log files are generated,too, as shown in figure1.8.Figure1.8 OA_conversion after convertStep8: in the directory of library (here is /home/eda/IC610/1P6M_1.8V_3.3V_MM_RF), delete the old Cell View folder(also named tsmc18rf). Then copy the converted tsmc18rf (in thedirectory /home/eda/IC610/OA_conversion) to the library directory (here is /home/eda/IC610/1P6M_1.8V_3.3V_MM_RF)Step9: start icfb& in work directory (here is /home/eda/IC610),click Tools>>Library Manager to open Library Manager window, shown as figure1.9.Figure1.9 Library Manager WindowStep10: in the Library Manager, click File>>New>>Library… then, find the library’s directory ,and the window shown as figure1.10.Figure1.10 New Library WindowStep11: click OK, then a window called Technology File for New Library appears, shown as figure 1.11. Here, we choose Compile an ASCII technology file, then the window appear as figure 1.12, choose the techfile.tf in the library’s directory, click OK. Then tsmc18rf along with its Cell Views appear in Library Manager, as shown in figure1.13.Figure1.11 T echnology File for New LibraryFigure1.12 Load T echnology FileFigure1.13 Library Manager after install TSMC0.18 PDK1.4Design Methodol ogy of Two-Stage Op AmpsFigure1.14 shows a block diagram that represents the important aspects of an op amp. CMOS op amps are very similar in architecture to their bipolar counterparts. The differential-transconductance stage forms the input of the op amp and sometimes provided the differential to single-ended conversion. Normally, a good portion of the overall gain is provided by the differential-input stage, which improves noise and offset performance. The second stage is typically an inverter. If the differential-input stage does not perform the differential-to-single-ended conversion, then it is accomplished in the second-stage inverter. If the op amp must drive a low-resistance load, the second stage must be followed by a buffer stage whose objective is to lower the output resistance and maintain a large signal swing. Bias circuits are provided to establish the proper operating point for each transistor in its quiescent state. And compensation is used to achieve stable closed-loop performance.Figure1.14 Block diagram of a general two-stage op ampChapter2 Front-end DesignBefore starting design op amps, a work directory need to be created. Do as following to create:Step1: start icfb& in work directory (here is /home/eda/IC610),click Tools>>Library Manager to open Library Manager window.Step2: in the Library Manager, click File>>New>>Library…, enter the Design Library’s name you want(here named mydesign_base_tsmc), and put it to the directory you want to put (here choose /home/eda/livia), as shown in figure2.1.Figure2.1 create design libraryStep3: click OK. Then a window called Technology File for New Library appears, shown as figure2.2. Here, we choose Attach to an existing technology library. Then the window appear as figure2.3, choose the tsmc18rf in Technology Library, click OK. Then design library mydesign_base_tsmc appears in Library Manager, as shown in figure2.4.Figure2.2 T echnology File for New LibraryFigure2.2 Attach Library to T echnology LibraryFigure2.4 Design Library creating finished2.1 Design of High Gain stageIn this tutorial, high gain stage is a Current-Source Load Inverter. This kind of inverter structure is a common-gate configuration using a p-channel transistor with the gate connected to a dc bias voltage.2.1.1 Schematic Cell ViewA Current-Source Load Inverter schematic cell view will be created in this section.Step1: in Library Manager, choose work library mydesign_base_tsmc, then click on File>>New>>Cell View, fill in the New File form with the following as follows (or figure 2.5) and click OK.Figure2.5 New FileStep2: The Schematic Editor window will pop up automatically when the new schematic cell view is created, as shown in figure2.6.Figure2.6 Schematic EditorStep3: click Create>>Instance or use the hot key ‘i’, Add Instance window will pop up. Browse ‘pmos3v’ symbol which belongs to library ‘tsmc18rf’>>Cell ‘pmos3v’>>View ‘symbol’, as shown in figure2.7. Put this symbol into the Schematic Editor. Do the same step to add a ‘nmos3v’. Figure2.8 show the schematic view.Figure2.7 Add InstanceFigure2.8 Add mos transistorsStep4: click Create>>Pin or use the hot key ‘p’, ‘V IN’ is Input pin, ‘V OUT’ is Output pin, ‘VDD’ and ‘GND’ are InOut pins, the schematic view is shown in fugure2.9.Figure2.9 Add PinsStep5: click Create>>Wire or use the hot key ‘w’, the schematic view is shown in fugure2.10. The property of each component can be seen or change by selecting the component and use the hot key ‘q’.Figure2.10 Current-Source Load Inverter schematicStep6: Up to now, we have completed a schematic design of a Current-Source Load inverter. Click File>>Check and Save to save this design.2.1.2 Schematic SimulationBefore simulate the circuit, we need build a top level cell and create test schematic for it.Step1: create a symbol view of ‘op_amp_stage2’. Click Create>>Cellview>>From Cellview, then the ‘Cellview From Cellview’ window will pop up automatically, as shown in figure2.11. After click ok, the symbol view will be created, as shown in fugure2.12.Figure2.11 Cellview From CellviewFigure2.12 Symbol View of Current-Source Load Inverter (op_amp_stage2)The default shape of a symbol is rectangle. Designer can change the style to the traditional circuit symbol of inverter by using some commands of Symbol Editor, such as Create>>Shape>>Polygon, Create>>Shape>>Circle, etc. This change is not necessary.Step2: create a test schematic. Create a new schematic cell called ‘op_amp_stage2_test’. The detail schematic is shown in figure2.13, and the property of each component is: V0:3.3V(vdc)V1:1.15V(dc) 500uV(amplitude) 1M(frequcy)V2:1.95V(vdc)C0: 15pFFigure2.13 Schematic View of op_amp_atage2_testFirst, the quiescent operating point should be pointed. From each transistor’s saturation relationship, here set BIAS voltage to 1.95V. To make M1 work at saturate state, change V1’s value to make a DC simulating.Step3: to make checking simulate result convenient, should name some special nets. Click Create>>Wire Name or use the hotkey ‘l’, then ‘Add Wire Name’ window popup automatically, as showed in figure2.14, then click on relevant wire of test schematic. Here, add two name ’vin’ and ‘vout’ to two nets respectively.Figure2.14 Add Wire NameStep4: click Launch>>ADE L, then ’Analog Design Environment’ deck will popup automatically, as showed in figure2.15.Figure2.15 Analog Design EnvironmentStep5: click Analyses>>choose, then the ‘Choosing Analyses’ will popup automatically, choose dc, and in the ‘Sweep Variable’ choose ‘Component Parameter’. Click ‘Select Component’, then select V1 on test circuit schematic, the ‘Select Component Parameter’ form will pop up, as showed in figure2.16, and choose ‘dc’, the first line, then click OK to close ‘Select Component Parameter’form. And in ‘Choosing Analyses’ window, in ‘Sweep Range’, we set V1change from 0V to 3.3V, as showed in figure2.17, then click OK.Figure2.16 Select Component ParameterFigure2.17 DC settingsStep6: setting outputs. Click Outputs>>To Be Plotted>>Select On Schematic, then choose the output you want on schematic, here we choose net vin, net vout and the drain of M1 (you can get into the symbol by select the top cell and type the hotkey ‘e’). Then the Analog DesignEnvironment is setting as figure 2.18.Figure2.18 DC setting on Analog Design EnvironmentStep7: click Simulation>>Netlist and Run, then after operating, the wave of simulation will be created as figure 2.19.Figure2.19 the DC simulation of op_amp_stage2(Current-Source Load Inverter)Gain is determined by the slope of the vout versus vin curve, and as can be seen from the figure2.19, if want a high gain and make M1 work in saturate area, then must set the DC voltage of VIN to about 1.15V. Then, so as to make output range is wide enough, set the property of MOS transistors as follows:M0:36u(W) 300n(L)M1:30u(W) 350n(L)Step8: after setting the quiescent operating point, then make the transient simulation. In Analog Design Environment, click Analyses>>choose, choose ‘tran’in the ‘Choosing Analyses’. Set the Stop Time to 10u, click OK. Then click Simulation>>Netlist and Run, after operating, the wave of transient will be created as figure 2.20. we can see from the figure2.20, the gain of this inverter is about 30.Figure2.20 the transient of op_amp_stage2(Current-Source Load Inverter)2.2 Design of Differential Transconductance Stage2.2.1 Schematic Cell ViewCreate a new schematic cell called ‘op_amp_stage1’. The schematic and the generate symbol is showed in figure 2.21.Figure2.21 the schematic view and s ymbol of op_amp_stage12.2.2 Schematic SimulationStep1: Create a test schematic called ‘op_amp_stage1_test’to do simulation for Differential Transconductance Stage. The schematic is showed in figure2.22. The property of each component is:V0:1.95V(vdc)V1:3.3V(vdc)V2:1V(dc) 1mV(amplitude) 1M(frequcy) 0(initial phase)V4:1V(dc) 1mV(amplitude) 1M(frequcy) 180(initial phase)Figure2.22 the test circuit of Differential Transconductance StageStep2: To match with op_amp_stage2, set the property of MOS transistors as follows:M0:12u(W) 300n(L)M1:48u(W) 300n(L)M2:48u(W) 300n(L)M3:5u(W) 350n(L)M4:5u(W) 350n(L)Step3: to make the transient simulation, in Analog Design Environment, click Analyses>>choose, choose ‘tran’ in the ‘Choosing Analyses’. Set the Stop Time to 10u, click OK. Choose the output net. Then click Simulation>>Netlist and Run, after operating, the wave of transient will be created as figure 2.23. we can see from the figure2.20, the gain of this inverter is about 30.Figure2.23 the transient of op_amp_stage2(Current-Source Load Inverter)2.3 Ad ding Compensation to OP Amps2.3.1 Schematic Cell ViewCreate a new schematic cell called ‘op_amp_2stage’. The schematic and the generate symbol is showed in figure 2.24. transistor M0 and capacitor C1 form the compensation circuit, and their property are :M0:1u(W) 1u(L)C1(mimcap):26u(W) 28u(L)Figure2.24 the schematic view and symbol of op_amp_2stage2.3.2 Schematic SimulationStep1: Create a test schematic called ‘op_amp_2stage_tes t’ to do simulation for op_amp_2stage. The schematic is showed in figure2.25. The property of each component is:V0:3.3V(vdc)V1:1.95V(vdc)V2:1V(dc) 0.5mV(AC amplitude) 0(AC phase)V3:1V(dc) 0.5mV(AC amplitude) 180(AC phase)V4:0.5mV(amplitude) 1M(frequcy) 0(initial phase)V5:0.5mV(amplitude) 1M(frequcy) 180(initial phase)Figure2.25 the test circuit of op_amp_2stageStep2: doing transient simulation for op_amp_2stage. In Analog Design Environment, click Analyses>>choose, choose ‘tran’ in the ‘Choosing Analyses’. Set the Stop Time to 10u, click OK. Choose the output net. Then click Simulation>>Netlist and Run, after operating, the wave of transient will be created as figure 2.26. we can see from the figure2.60, the close-loop gain of this op amp is about 860.Figure2.23 the transient of op_amp_2stageStep3: for op amps, we should do AC simulation to make sure the circuit is stable. In Analog Design Environment, click Analyses>>choose, choose ‘ac’, in the ‘Sweep Variable’, choose ‘Frequency’, then set the ‘Sweep Range’ from 1Hz to10G,as shown in figure2.24, click OK. Then click Simulation>>Netlist and Run.Figure2.24 setup acStep4: after operating, in Analog Design Environment, click Results>>Direct Plot>> AC Gain & Phase. Then in the schematic of op_amp_2stage, select vout net first, then select vin1, the graph of simulation wave gain and phase will appear as figure2.25. As can be seen from figure2.25, the phase margin is about 50 degree, the circuit is stable.Figure2.25 the AC analy sis of op_amp_2stageChapter3 Back-end DesignWe will create an op amp layout cell view in this section.3.1 Layout Cell ViewStep1: in Library Manager, choose op_amp_2stage in work library mydesign_base_tsmc, then click on File>>New>>Cell View, fill in the New File form with the following as follows (or figure 3.1) and click OK.Figure3.1 new lay out cellStep2: The layout Editor window as well as LSW will pop up automatically when the new schematic cell view is created, as shown in figure3.2.Figure3.2 an empty layout editor windowStep3: Change Grid and Snap option. In layout edit window, click Optons>>Display, then ‘Display Options’ window will pop up automatically. The X space and Y space is determined by the process used. Here we use tsmc0.18 process, so we set them to 0.005, as shown in figure 3.3. Click ‘Save To’, then click OK.Figure3.3 set Grid and Snap optionStep4: click Create>>Instance or use the hot key ‘i’, ‘Create Instance’ window will pop up. Browse ‘pmos3v’ layout which belongs to library ‘tsmc18rf’>>Cell ‘pmos3v’>>View ‘layout’, as shown in figure3.3. Put this layout into the Layout Editor. Do the same step to add a ‘nmos3v’. Figure3.4 show the layout view.Figure3.3 Create InstanceStep5: to create path, choose the layer to use in LSW, then in the layout, click Create>>Wire, or use hotkey ‘p’, then you can draw the path in the circuit. To draw different shapes, click Create>>Shape>>Rectangle…etc.Step6: to create via in the layout. Click Create>>Via, or use the hotkey ‘o’, then the ‘Create Via’will popup automatically, as shown in figure3.4. In this window, you can choose any via type and define the property of the via you want.Figure3.4 create viaStep7: to create pins in layout. Click Create>>Pin, then ‘Create Shape Pin’window will popup automatically. Click ‘Display Pin Name Option’ button, in the pop up window ‘Pin Name Display’, choose the right pin layer metal, here we choose ‘METAL1 pn’ as ‘Layer’. As it showed in figure 3.5.Figure3.5 create pinStep8: the finished layout of op amp is showed in figure3.6. Click File>>Save to save the design.Figure3.5 the layout view of op_amp_2stage3.2 Layout VerificationIn this section, we will check DRC, LVS for the op_amp_2stage by Calibre.3.2.1 Run Calibre DRCStep1: in the layout window of op_amp_2stage, click Calibre>>Run DRC, then ‘Calibre Interactive-nmDRC’ window will pop up automatically. For the first time run Calibre DRC, close ‘Load Runset File’ window. Set the ‘Calibre Interactive-nmDRC’ window as shown in figure3.6.Rules: DRC Rules File:/home/eda/IC610/1P6M_1.8V_3.3V_MM_RF/Calibre/calibre.drc DRC Rules File: /home/eda/livia/mydesign_base_tsmc/op_amp_2stage/drcInputs: layout, choose the ‘Export from layout viewer’Figure3.6 DRC settingsStep2: click Run DRC button. The result is showed in figure3.7. as can be seen in figure3.7, DRC has a error. However, as we only design a simple model, so here the density error can be ignored.Figure3.7 DRC result3.2.1 Run Calibre LVSStep1: in the layout window of op_amp_2stage, click Calibre>>Run LVS, then ‘Calibre Interactive-nmLVS’window will pop up automatically. For the first time run Calibre LVS, close ‘Load Runset File’ window. Set the ‘Calibre Interactive-nmLVS’ window as shown in figure3.8. Rules: DRC Rules File:/home/eda/IC610/1P6M_1.8V_3.3V_MM_RF/Calibre/calibre.lvs DRC Rules File: /home/eda/livia/mydesign_base_tsmc/op_amp_2stage/lvsInputs: Layout: choose the ‘Export from layout viewer’Netlist: choose the ‘Export from layout viewer’Figure3.8 LVS SettingsStep2: click Run LVS button. The result is showed in figure3.9. as can be seen in figure3.9, LVS has a error. However, as the capacitor in this layout is drawn by myself, the parameter of it is very hard to match the one set in schematic view, but we also can find that this capacitor only has a margin error of 0.0108%, so here error can be ignored.(by the way, if LVS has no errors, the result will give a smile face to designer)Figure 3.9 LVS Result。

cadence教程

cadence教程

Cadence TutorialI. IntroductionThis tutorial provides an introduction to analog circuit design and simulation with Cadence, and covers the features that are relevant for the homework assignments. The tutorial is divided into the following topics:•Logging on and Starting Cadence•Creating a Designo Creating a new library and cellviewo Placing the Partso Editing the Symbol Propertieso Wiring the Schematico Modifying Wire Attributes•Analyzing the Design and Plotting Resultso Finding the DC Operating Point and performing a DC Sweepo Performing a Transient Analysiso Performing an AC Analysiso Performing a Parametric Sweepo A Note on Measuring Currentso A Note on Plotting•Invoking Cadence Helpo Getting Additional Help with CadenceThroughout the document, the followingII. Logging on and Starting CadenceIn order to use the ECE164-provided installation of Cadence, you either need to be sitting at one of the Linux workstations provided for use by ECE264 students (see the ECE264 website for the locations of these workstations), or you can login remotely to . In either case, you should login with your Open Computing Environment account obtained via Academic Computing Services (ACS).If you wish to login remotely, you will need SSH and X-server software on your local machine. The necessary software is available as part of the operating systems on Sun Workstations, PCs running Linux, and Macintosh computers running OS X. It can be obtained via third parties for computers running Windows. Students who wish to login remotely are responsible for obtaining (if running Windows), learning how to use, and maintaining their own SSH and X-server software.Once you have logged in, open a terminal window if one does not open automatically and type the following in the window:ee264acd ece-cadenceicfb &A window containing text should appear at the bottom of the screen, labeled “icfb - ...”. This is sometimes called the CIW (Command Interpreter Window). A window explaining new features should also come up; in this window, select “Edit > Off at Startup”, and then close it. The CIW window is the main Cadence window, and much useful information is displayed here. If Cadence isn’t doing what you expect, it is often helpful to look here to read the error messages. You may find it helpful to enlarge the window.You now need to bring up the library manager. To do this, select “Tools > Library Manager” in the CIW. A “Library Manager” window appears. Notice the library “ece264lib”.This library contains most if not all of the IC components (e.g., transistors, resistors, etc.) that will be used in this class.II.Creating a DesignThe creation of a simple transistor amplifier is described in this section. The following notational conventions are used in the description:•The text “[LIB]” should be replaced with “164” if you are taking ECE164 and by “264” if you are taking ECE264.•Bracketed letters such as “[a]” denote keyboard shortcuts (bindkeys) which can be used instead of the menus or buttons to accomplish the given task. To use them, place the pointer over the appropriate window and simply press the key. Please note that these bindkeys are case sensitive.For letters enclosed by square brackets such as “[a]”, the pointer must be in a schematic window.For letters enclosed by curly brackets such as “{a}”, the pointer must be in a waveform window. A summary of the most useful bindkeys is listed in Appendix A.Creating a new library and cellview1.Create a new library named “tutorial”:(a)In the CIW, select “File > New > Library”, and a “New Library” windowwill appear.(b)In the “Name” field, enter “tutorial”.(c)Verify that the path (near the bottom of the dialog box) points to your working directory(or wherever you’d like to place all your class libraries). This path will by default pointto the directory from which you invoked Cadence(d)Select the “Don't need a techfile” button, then click “OK”. In the LibraryManager, an entry “tutorial” should appear.2.Create a new schematic cellview in our new library.(a)In the CIW, select “File > New > Cellview...”, and a “Create New File”dialog box appears.(b)Ensure that the “tutorial” is selected for Library Name (by clicking on the squarebutton).Type “tutorial” in the “Cell Name” field as well.(c) Type “schematic” in the “View Name” field.(d)Select “Composer - Schematic” in the “Tool” field if it is not already selected,then click “OK”. An empty schematic window appears.(e)In the schematic window, select “Design > Save”. You have now successfullycreated a cellview.Placing the PartsYou will now place symbols on the Schematic Window as shown in Figure 1.Figure 1: Initial parts placement.1.Find and place the pMOST symbol as follows:(a)With the schematic window active, press “i” on the keyboard. An “Add Instance”dialog box will appear. The “i” key is a bindkey, or shortcut key, to this dialog box.You can also get the same dialog box by click on the “Instance” button on the lefthand side of the schematic window (it looks like a little DIP), or by going to “Add >Instance” in the menu bar (there is an “i” next to this menu selection, notice). Thereare many shortcuts like this throughout Cadence, and you can create more if you wish -see the online help. Note also that at the bottom of the schematic window and the CIW,the instructions “Point at location for the instance” appears, along withinformation about what the mouse buttons do: “mouse L: ...”. It’s often importantto look at these messages to figure out what is going to happen when you press theleft/middle/right mouse buttons. The mouse buttons are bound to Skill functions, but canbe reconfigured - see the online help for more details.(b)In the dialog box Library field, enter “ece[LIB]lib”. For Cell, enter “pmos4”. ForView, enter “symbol”. You can also use the Browse button to invoke the LibraryBrowser to find a part.(c)When you move the mouse over the schematic window, you will see the outline of a 4-terminal pMOST. Move the cursor to the desired location and press the left mousebutton. Repeat for the other pMOST transistor.(d)To stop placing pMOST symbols, press “ESC” on the keyboard (with the SchematicWindow active), or click the “Cancel” button in the Add Instance dialog box.2.Place an nMOST using a similar procedure. This time, try using the Library Browser to place the“nmos4” symbol. Position it relative to the pMOST symbols as shown in Figure 1, then press “ESC” to get rid of the Add Instance window.3.Next, place the DC Current Source symbol as follows:(a)Press “i” as before, then click “Browse” to bring up the Library Browser.(b)Select “ece[LIB]lib” in the Browser library list, then find the “idc” componentsymbol using the scroll bar. Highlight this component in the browser by left-clicking on“idc”. Sometimes you may need to specify that you want to place the “symbol”version of this part.(c)Move the mouse over the schematic window and place it in the desired location. Don’tpress “ESC” yet.4.Go back to the Library Browser and find the “vdc” part. Place it.5.Similarly, place the “vsin”, “res”, and five copies of “gnd”. Finally, press “ESC” (remember,the Schematic Window must be active) to stop placing parts.6.If you need to move any of the parts, use the following procedure:(a)Press “M” (stretch) or “m” (move). Note the message at the bottom of the SchematicWindow. At this point, there is no difference between these two commands. But whenwires are attached to the parts, “M” will move the wires as well, whereas “m” will justmove the part.(b)Click on the part you wish to move. Again, keep an eye on the bottom of the SchematicWindow. Follow the instructions there. Repeat as needed.(c)Note that you can also move items by moving the cursor over the item, pressing andholding the left mouse button, moving the mouse, and then releasing the mouse button.Editing the Symbol PropertiesOnce all the parts are placed on the schematic, you can set property values that are specific to the design on each symbol. Figure 2 shows many of the property values that you will add in this part of the tutorial. The “vsin” symbol has many properties: “acm” is “AC Magnitude”, the amplitude of the AC signal applied to the linearized circuit (small signal circuit) during an AC Analysis. The “acp” is the “AC Phase”, “vo” refers to “DC Offset”, and “vm” refers to “Amplitude”, the amplitude of the signal applied to the large-signal (non-linear) circuit during a Transient Analysis.Figure 2: Symbol property values.e the following procedure to change a symbol’s properties. Before you begin, make sure thatyou have pressed ESC to clear the last action performed (the bottom line of the Schematic Window should read “>”):(a) Move the cursor to a location where there are no parts. Then press “q”. An “EditObject Properties” dialog box will appear.(b)Click on the item whose properties you’d like to change. The dialog box will expand todisplay a list of properties that can be changed. If you can’t see any properties, makesure thatthe “CDF” box is checked near the top of the “Edit Object Properties”window.(c)In the list of properties, edit those that you would like to change or specify. DO NOTinclude units such as “Volts” or “Ohms” - you’ll notice that these are filled inautomatically after you move on to the next property. DO NOT press return after youenter a property - use the mouse or use the “TAB” key to proceed. DO specifyabbreviations for scientific notation such as “k” (kilo),”u” (micro), “m” (milli), “M”(mega), “p” (pico), “f” (femto).(d)Click on the next part to change its properties. Cadence will ask whether you want tosave the property changes from the old part - say yes.(e)When you’re done entering properties, click “Cancel” at the top of the “EditObject Properties” dialog box.2. Change the names of the transistors according to Figure 2 by changing the “Instancename” field. Note: The name must be unique. Also insert the values for the transistor widthsand lengths.3.Flip the display of transistor M0 by first pressing “m” and clicking on the transistor to move it.While you are “holding” it, press “R” on the keyboard. The symbol outline should flip. Place theflipped part as shown in Figure 2.4.Note that the ac magnitude and phase of the “vsin” part are not displayed by default. Edit theproperties of this part (with the “q” key, and then look at the “AC Magnitude” property. Clickon the button to the right of the property value, and a list of choices will appear. Select “Both”.This will cause this property to be displayed on the schematic.Wiring the SchematicAfter the symbols are placed and the properties are set, you can wire the parts together as shownin Figure 3 by doing the following:1.One way to create a wire between two ports is as follows:(a)Position the mouse cursor over the first port (for example, start with the top of theconstant voltage source).(b)Click and hold the left mouse button.(c)Position the mouse cursor over the second port (the Vdd symbol above the Vdc symbol).(d)Release the left mouse button.(e)Repeat steps a through d to connect each Ground and Vdd symbol to the associatedparts, as shown in Figure 3.2. To connect the Gate terminals of the pMOSTs to the Drain terminal of M1, do the following:(a)Press “w” on the keyboard. Note the instructions at the bottom of the SchematicWindow.(b)Click and hold the left mouse button.(c)Position the cursor over the mid-point of the wire between the Gate terminals of M1 andM2, and click the left mouse button.(d)Move the mouse cursor four grid-points down, and click the left mouse button.(e)Move the mouse cursor six grid-points to the left, and click the left mouse button. Thiscompletes the connection.plete the remaining wire connections as shown in Figure 3.Figure 3: Schematic Wire Connections.Modifying Wire AttributesIf you do not label wires, Cadence automatically provides names for each wire, such as “net30”. It can be helpful later on during design and analysis if you label the wires with meaningful designators that are easy to understand and refer to. To add the attribute “vout” to the wire shown in Figure 3, do the following:1. Press “l” (for label) on the keyboard. An “Add Wire Name” dialog box appears.2.Enter “vout vin” in the “Names” field and press “Return”3.Move the cursor until the dot is on top of the wire to be labeled “vout”. Left click once with themouse. The label will be attached to the wire, and the label you are moving with your cursor changes.4.Place the “vin” label in an appropriate spot. Make sure the dot is on top of the wire before youleft-click.Finally, add a single instance of “ece[LIB]lib title” underneath your schematic. Please make sure that this is always placed in all your schematics.At this point you have a completed design that is ready to be analyzed. In the next part of the tutorial, you will simulate the amplifier. First, save the design by clicking the checkmark icon (the Check and Save icon) on the left hand side of the Schematic Window (top). Check the CIW. There should be a message saying that “Schematic Check completed with no errors”. Whenever you make a change to your design, you’ll need to check and save before you simulate. Otherwise, you may get an error, which will show up in the CIW window. Again, the CIW is extremely important for finding errors. You should read any errors carefully, and sometimes warnings are important too.III. Analyzing the DesignBefore performing the circuit analysis, you need to start the analog environment by going to “Tools > Analog Environment” in the schematic window. A new window called the“Simulation Window” will appear.Next you need to tell Cadence where to find the model library. For this class, we have a single model library file, called “cmos018.scs”, which contains an nMOST model named “N”, and a pMOST model named “P”. The symbols we’re using by default have these names specified in their symbol properties (look at the properties for one of the transistors). If you ever decide to use a different symbol, you’ll need to make sure the “Model name” property is correctly filled in. To tell Cadence where to look for the model file, go to “Setup > Model Libraries” in the Simulation Window. In the “Model Library File” field, enter:/home/linux/ieng6/ee164f/your_login_name/ece-cadence/cmos018.scs(if you are taking EE164)or/home/linux/ieng6/ee264a/your_login_name/ece-cadence/cmos018.scs(if you are taking EE264a)where “your_login_name” should be replaced by the name of the account under which you logged into the system (e.g., bobama). Then click on “Add” (NOT “OK”). You’ll see the path placed in the list of Model Library Files. Now click on “OK”.Finding the DC Operating Point and Performing a DC SweepIn this section, you’ll find and annotate the DC operating point, and you’ll sweep the input voltage to find the correct bias voltage for the nMOST transistor.1.Now go to “Analyses > Choose...”. A new dialog box will appear. [a]2.In the new dialog box, select the “dc” button. Check the “Save DC Operating Point” box.This will allow us to annotate node voltages later. Finally click “OK”3.We’ll now perform our first simulation. Click on the “Netlist and Run” icon, which is thegreen traffic light on the right hand side of the Simulation Window. If this is your first time running Cadence, a “Welcome” menu appears – close it. A new window will appear, hopefully saying that the simulation was successful, and providing a brief summary of the simulation convergence. [s]4.If everything went well, go to the Simulation Window, and select “Results > Annotate >DC Node Voltages”[d]. Note that the voltages at each terminal of each device are now marked on the schematic. Now go to “Results > Annotate > DC Operating Point”[D]. Note that important voltages and currents are now marked on each device. You can quicklysee whether the devices are biased properly. You can remove this annotation by using “Results > Annotate >Design Defaults”[^d].5.You should see a problem with the node voltages. The node “vout” should be about 2.4V. Thismeans that the top pMOST is operating in triode, and this amplifier will not work properly. You’ll now fix this using a DC sweep to find the correct bias point.6.Go back to the Simulation Window, and select “Analyses > Choose...” [a]. Under “SweepVariable” on the DC Analysis Form, select “Component Parameter”. The form will become larger.7.On the expanded form, click the “Select Component” button. You will be prompted to selecta component on the schematic. Select the “vsin” symbol at the nMOST input. A new window willappear, and you should select “dc” as the parameter you wish you vary, then click “OK” in the new window.8.Fill in the rest of the form so that the voltage is swept from 0 to 2.5V. Set the sweep type to“Linear”, and set the number of points to be plotted to 500. When you’re done, click “OK” on the Choose Analyses window.9.Now you need to select an output to plot. To plot a voltage, use the following procedure:10.Go to “Outputs > To Be Saved > Select on Schematic” in the SimulationWindow. Left-click on the “vout” and “vin” nets in the schematic window, and then press “ESC”. This step is typically not done as you can simply click on the nodes you want to plot after the simulation is complete. However, go ahead and try it this time.11.Go to “Outputs > Setup...”. In the Setting Outputs window, click on the “vout” line onthe right hand side. Then select the “Plotted” button, and press “Apply”. Do the same for the “vin” line. Then click “OK” in the Setting Outputs window.12.Finally, we can perform the DC Sweep. Press the green traffic light. The Waveform Window withthe simulation results should appear.13.We need to find the input voltage which will place our output bias at roughly Vdd/2. Move yourcursor over the waveform plot of “vout”. You’ll see the x and y coordinates at the top of the window. Using this method, select the DC value of “vin” which will give an output of approximately 1.25V. You should get about 550mV. Update the “vsin” symbol with this new DC offset voltage.14.Repeat the DC simulation, and verify from the annotated voltages that your output is now roughlyat Vdd/2. If so, you’re ready to move on to the next simulation.15.But first, unless you like to repeat things, you should learn how to save the simulation state.Go to“Session > Save State...”, and you’ll be prompted to save your current state. Enter the name of a state of your choosing, or just stick with the default. This state can be reloaded later (using “Session > Load State...”, and you won’t have to enter all of the setup data again.Performing a Transient AnalysisIn this section, we’ll look at the amplifier’s large signal response to a sinusoidal input signal at 100kHz.1.First, turn off the DC Sweep analysis by bringing up the choose Analysis window and unselectingthe “Enabled” box at the bottom of the form.2.Select the “tran” button. Enter “100u” in the “Stop Time” field. If you want, you can alsoclick the “moderate” button, but this is not necessary. It is recommended by Cadence you never click the other two.3.Click the “Options” button. A new dialog box appears. In this Transient Options window,change the following attributes: “step” to 10n, “maxstep” to 10n, then press “OK”. These options make sure that enough points are taken during the transient analysis. They will be different for other simulations in this class, and you’ll need to experiment with them. Typically, you can leave this field blank and see how well the transient results look. If they seem “choppy,” go ahead and enter a number here. Refer to the Cadence documentation for more information on the other parameters on this form.4.You’re now ready to simulate, and you haven’t changed the schematic, so you can press the yellowtraffic light to simply run the simulation.5.After a few moments, the waveform window should appear with a nice sinusoid. You can removethe input sinusoid (we know it’s just a 2mV peak-to-peak wave) to get a better view of the output.Go to “Curves > Edit” in the Waveform Window, and turn off the “vin” waveform or click on the waveform and press “del”.6.To measure the peak-to-peak amplitude of the output, use the “Markers” {a},{b} menu to placemarkers A and B at the highest and lowest points of “vout”. From the display at the bottom of the window which will appear after you have done this, you should find the peak-to-peak amplitude to be about 63mV, meaning the circuit has a gain of about 30.Performing an AC AnalysisIn this section, we’ll look at the amplifier’s frequency response. Hopefully you’re becoming proficient with Cadence now, so not as much detail about the individual steps will be provided.1.Bring up the Choosing Analyses window, and disable the transient simulation, and the sweepportion of the DC simulation. Then click the “ac” button, and set up this simulation to sweep frequency from 100Hz to 1GHz, with 100 points per decade. You will need to change the sweep type to “logarithmic”.list and Run the simulation (or just run it, if your schematic is unchanged). [s]3.In the schematic window, we will now create a Bode plot. The easy way to do this is to go to“Axes” and change the scale of the y-axis to be logarithmic. We’ll use a different approach, usingthe Waveform Calculator, an important Cadence tool.(a)First, add a new subwindow to plot our new graph in. Do this by going to the “Window >Subwindows...” menu option, or by clicking on the subwindow icon on the left-handside of the Waveform Window{S}. Make sure that the new subwindow is active by left-clicking in its area. Now click on the calculator icon on the left side of the waveformwindow. The calculator will appear. By default, the calculator uses RPN (Reverse PolishNotation), but this can be changed in the “Options” menu item, if you’d like. For thefollowing, I assume you’re using RPN.(b)Click on the “wave” button in the calculator. You will be prompted to click on a wave -select the “vout” waveform. The expression for this wave will appear in the calculatorwindow.(c)You want to plot 20*log10(vout). To do this in RPN, now click on the “log10” button,then enter “20” on the keypad, then press the multiply button. You should see thecalculation take place in the calculator window. If you prefer, you can simply type “*20”at the end of the expression in the calculator window. – in other words, use it as a normalcalculator.(d)Now press the calculator “plot” button. The new wave will appear in the subwindow.4.You can also make measurements with the calculator. If you click and hold the “SpecialFunctions” button, you will see a list of functions. Select “bandwidth”. A form will come up, and you can click “OK”. Then press the “print” button on the calculator. This will bring up a window with the measured 3-db bandwidth of your circuit.5.You’re done with the AC Analysis now. We’ve only scratched the surface of what can be donewith the Waveform Calculator. Feel free to experiment more with it if you wish. Then go to the next section.Performing a Parametric SweepSometimes it’s important to perform sweeps of two variables simultaneously. This section shows you how to do this. We will sweep the nMOST bias voltage over a few values, and plot the frequency response of the amplifier for each value. This will demonstrate how drastically the bias point (which determines whether transistors are saturated) can affect circuit performance.1.For a parametric analysis, you must first define the variable to be parameterized (the one whichtakes on discrete values). In our case, this will be the offset voltage of the “vsin” symbol. Go to this symbol and edit its properties. In place of the number which you currently have entered in the “Offset voltage” field, enter “vgs”. Then click “OK”. Check and save.2.Go to the Simulator Window and select “Variables > Copy From Cellview”. You willnotice that “vgs” appears in the Design Variables subwindow.3.Go to “Variables > Edit...” (or use the shortcut) and set the value of “vgs to the bias voltage youfound during the DC Sweep portion of the tutorial.4.Next, you will need to re-enable the DC simulation. To do so, go back to the analysis chooser andselect the DC analysis button. Choose to enable this simulation; however, make sure you disable the “component parameter” sweep.5.Now netlist the schematic. (You can find the option to just netlist under “Simulation”, or youcan just netlist and run. It doesn’t make any difference. We just need to netlist somehow.) This is a critical step. If you forget to do this, the parametric analysis will seem to do nothing.6.In the Simulation Window, go to “Tools > Parametric Analysis...”. Set up the formso that “vgs” is swept from 0.4V to 0.8V in 9 total steps. In the same form, go to “Analysis > Start” to begin the analysis.7.When the Waveform window comes back, it should have multiple distinct curves, showing thefrequency response for each value of vgs. Notice how dramatically the gain drops off away from the correct bias point!A Note on Measuring CurrentsYou select a current to be plotted in much the same way as you select a voltage. When selecting outputs to be plotted (see the beginning of “Analyzing the Design”), click on the terminal of adevice rather than a wire. A circle should surround the terminal to show that the current flowing INTO this terminal will be plotted. A few caveats: first, sometimes it can be very difficult to select a node - you may have to click on the center of the symbol at which you want to measure current, which will select all nodes of that symbol, and then delete the currents you don’t want in the Simulation Window. Second, the transistor symbols used for the class don’t allow their currents to be plotted for some reason. Remember, you can always put in a zero-volt voltage source if you need some usable terminals for measuring current!A Note on Printing/PlottingSome information on customizing printing was given earlier in this tutorial. In order to actually bring up a plotting dialog box, you can go to “Design > Plot > Submit..” in the Schematic Window, or “Window > Hardcopy” in the Waveform Window. You’ll have to experiment with the forms to get what you want. The forms are quite versatile. Keep in mind you can print to a postscript file as well as directly to a printer.When printing, it is suggested that you do the following:(a)Unselect the [Plot with] “Header” button.(b)On the Plot options page:i.Unselect the “Mail Log to” button.ii.Select the “Center plot” button. [Not available when printing waveforms]iii. Select the “Fit to page” button. [Not available when printing waveforms]iv. Check that the correct printer is selected (or)v. If you want to print to a postscript file, select the “Send plot only tofile” button.If you decide to print to a file, the output will be a postscript file. This may be inconvenient for some students. If this is the case, you can run “ps2pdf <filename.ps>” to convert the postscript file to a PDF. This program, however, is not available in your path, by default. You will need to add it to your path before ps2pdf will work. To do so, at the UNIX command prompt (not the CIW!), type:set path = ( $path /software/common/ghostscript-8.0.0/bin )Note: Due to a “bug” in Cadence, waveforms are printed as they appear on the screen. In other words, if the waveform window is small, on the screen, the printout will be equally small. It is suggested that you make the waveform windows large to get the clearest printouts.。

cadence培训

cadence培训

Design path Setup 很多人在设置Allegro库的路径时,一直有无法修改的 问题.解决方法如下.在Cadence的安装目录下, 如:D:\Cadence15.2\SPB_15.2\share\pcb\text,找到 ENV文件,在文件的最后键入 Set PSMPATH = Set PADPATH = Set DEVPATH = 指定库的路径即可.
Ref定义在components
2) 快捷键设置 用惯PADS的人改用Allegro布线的话,刚开始会很不习惯 的,Allegro的走线方式和PADS完全两样。不过我们可 以在env文件中设置相应的快捷键,以提高布线速度以 下是我的设置方式及和PADS命令的对照表,以供参考: 大家可根据自 己的习惯设置.
- 项目管理工具 设计工具管理器, 由此可以启动设计的所有模块
2 ) -Concept HDL - 原理图设计工具.
界面如下:
3 )Allegro Expert-- PCB设计专家.
三. 设计的文件结构
文件结构目录及构成如图 (具体操作演示)
四. 创建新的项目
创建过程 1.首先创建一个自己的工作 文件夹,用于存放所有的设 计文件,例如D:\working. 2.启动项目管理器,选择新建 3.输入项目名称,location中 输入D:\working 4.添加LIB 5.输入设计单板名 6.结束
从setup\constraints或点击图标 Set Standards Values… 进入板的缺省间距的设置
(edit/property)
3.Physical rule setup:(设定线宽和选用的via) 1)点击Set Value如右图: 在圈出的地方可以设定 rule name,”add”就ok了 再输入最小线宽,最大 线宽等,选择你需要的Via 点击“ok”即可. 之后就可以布线了.

cadence_tutorial8

cadence_tutorial8

Cadence Tutorial 4Simulating a Schematic with Verilog-XLEE577b Spring2000In this tutorial, you will run a Verilog simulation on the schematic cellview of adder8.1. Tutorial Setup1. Finish the cadence tutorial 3 before you start this tutorial.2. Invoke "icfb".2. Open the 8-bit Adder Schematic Cellview1. From the Library Manager, read the adder8 schematic cellview from the Adder8 library.The adder8 schematic cellview is displayed.3. Initializing Verilog Integration1. Start Verilog integration by selecting sch :Tools->Simulation->Verilog-XL from the adder8schematic cellview.The Verilog-XL Setup Environment window is displayed.2. In the Verilog-XL Setup Environment window, enter adder8.run2 for the run directory. All otherdefault values are correct.3. Click on OK.The Verilog-XL Integration control window is opened. The adder8.run2 run directory iscreated and the environment is initialized.4. Setting the Netlist and Waveform Options1. In the Verilog-XL window, set the Netlisting Options by selecting Setup->Netlist.The Netlisting Options form is displayed.2. In the Netlisting Option window, set Netlist These Views list to:verilog schematic symbol3. Click on More>>Additional netlisting options are added to the form.4. Define Stop Netlisting at Views as:verilog symbol5. Click on Generate Pin Map to turn it on.6. Click on OK.5. Creating the Stimulus FileThe test fixture file used in the previous tutorial is used for this tutorial as well.1. Create a Test Fixture (Stimulus) file by selectingStimulus->Verilog2. Click on No on the dialog box that appears to copy test fixture file on adder8.run1.3. Select testfixture.verilog file of adder8.run1 in Copy From and click copy on Mode.4. Type testfixture.verilog in Copy To.5. Click OK.These steps are for copying testfixture.verilog of adder8.run1 to adder8.run2.6. Select testfixture.verilog by Stimulus->Verilog again.Click testfixture.verilog and click on Select at Mode.6. SimulationAll simulation steps are same as the previous tutorial.For the compilation of verilog netlist from schematic, you need to include all netlist files in "ihnl" subdirectory. If you finish the generation of netlist from schematic, you should have 8 subdirectoriesunder "ihnl".In testfixture.template file, please add the lines as follows (modify it according to your running directory).`include "/home/scf-12/jsmoon/cds/adder8.run2/hdlFilesDir/cds_globals.v"`include "/home/scf-12/jsmoon/cds/adder8.run2/ihnl/cds0/netlist"`include "/home/scf-12/jsmoon/cds/adder8.run2/ihnl/cds1/netlist"`include "/home/scf-12/jsmoon/cds/adder8.run2/ihnl/cds2/netlist"`include "/home/scf-12/jsmoon/cds/adder8.run2/ihnl/cds3/netlist"`include "/home/scf-12/jsmoon/cds/adder8.run2/ihnl/cds4/netlist"`include "/home/scf-12/jsmoon/cds/adder8.run2/ihnl/cds5/netlist"`include "/home/scf-12/jsmoon/cds/adder8.run2/ihnl/cds6/netlist"cds_globals.v file is necessary because it has the definition of vdd and gnd.If you get the following error message when you initiate verilog-xl interactive,ERROR: hnlCellExtractedC -- Netlister: the cell adder8 was modified since last extraction.Check & Save the schematic from bottom cell to top-most .. then startverilog-xl again.7. Netlist FilesTake a look at the netlist Þles in ihnl/cds0directory. You can see how transistor schematic is netlisted in verilog code.。

cadence详细教程(模拟电路)

cadence详细教程(模拟电路)

cadence详细教程(模拟电路)⽬录1.Cadence系统编辑环境 (2)实验1:Cadence系统编辑环境设置与基本操作 (2)2.电路图设计⼯具-Schematic (8)实验2:⼆与⾮门电路原理图设计 (8)实验3:数、模混合集成电路原理图设计 (14)3.电路仿真⼯具-ADE (18)实验4:ADE环境设置 (18)实验5:差分放⼤器电路仿真 (23)4.版图设计⼯具-Layout Editor (30)实验6:Layout Editor环境设置 (30)实验7:MOS管版图设计 (35)实验8:BJT管版图设计 (38)实验9:CMOS反相器版图设计 (42)实验10:Pcells版图设计 (46)实验11:pk44chip芯⽚版图综合设计 (53)5.版图验证⼯具-Diva (57)实验12:版图验证 (57)实验13:版图识别 (66)实验14:版图改错 (71)6.设计性实验 (73)实验15:RS触发器设计 (73)实验16:静态存储器设计 (76)实验17:三态与⾮门设计 (79)实验18:基准电压源设计 (81)实验19:CMOS放⼤器设计 (83)实验20:异或门设计 (84)Lab 1 Cadence系统环境设置与基本操作1.实验⽬的熟悉Cadence系统环境了解CIW窗⼝的功能掌握基本操作⽅法2.实验原理系统启动Cadence系统包含有许多⼯具(或模块),不同⼯具在启动时所需的License 不同,故⽽启动⽅法各异。

⼀般情况下涉及到的启动⽅式主要有以下⼏种,本实验系统所⽤到的有icms、icfb、layoutPlus等。

①前端启动命令:表1.1 前端启动命令命令规模功能icde s 基本数字模拟设计输⼊icds s icde以及数字设计环境icms s 前端模拟、混合、微波设计icca xl 前端设计加布局规划②版图⼯具启动命令表1.2 版图⼯具启动命令命令规模功能Layout s 基本版图设计(具有交互DRC功能)layoutPlus m 版图设计(具有⾃动化设计⼯具和交互验证功能)③系统级启动命令表1.3 系统级启动命令命令规模功能swb s PCB设计msfb l 混合型号IC设计icfb xl 前端到后端⼤多数⼯具CIW窗⼝Cadence系统启动后,⾃动弹出“what’s New…”窗⼝和命令解释窗⼝CIW (Command Interpreter Window)。

cadence教程-IC设计工具原理共页课件 (二)

cadence教程-IC设计工具原理共页课件 (二)

cadence教程-IC设计工具原理共页课件 (二) - Cadence教程-IC设计工具原理共页课件
1. 什么是Cadence?
Cadence是一家专门从事电子设计自动化软件的公司。

其产品涵盖了芯片设计、系统设计、封装设计和PCB设计等领域。

Cadence的软件被广泛应用于半导体、通信、计算机、消费电子等行业。

2. Cadence的主要产品
Cadence的主要产品包括Virtuoso、Allegro、OrCAD、Sigrity等。

其中,Virtuoso是一款用于模拟、布局和验证芯片的工具;Allegro是
一款用于PCB设计的工具;OrCAD是一款用于电路设计的工具;
Sigrity则是一款用于信号完整性分析的工具。

3. Cadence的应用领域
Cadence的软件被广泛应用于各种电子产品的设计和制造中,如手机、平板电脑、笔记本电脑、服务器、网络设备、汽车电子、医疗设备等。

在半导体行业中,Cadence的软件被用于设计各种芯片,如处理器、存储器、模拟集成电路、射频集成电路等。

4. Cadence的优势
Cadence的软件具有高度的可靠性、灵活性和易用性。

其产品支持多种操作系统,如Windows、Linux、Solaris等。

此外,Cadence还提供了丰富的教程和技术支持,帮助用户更好地使用其软件。

5. Cadence的未来发展
随着电子行业的不断发展,Cadence的软件也在不断升级和改进。

未来,Cadence将继续加强与各大芯片厂商和设备厂商的合作,开发出更加先进和适用的软件,为电子行业的发展做出更大的贡献。

cadence入门教程

cadence入门教程

cadence入门教程(一)linux常用命令1、cd“cd FileName”是进入FileName文件夹。

“cd..”是进入上一层目录,主要那里是两个点。

2、ls这是最基本的文件命令,用以显示某一个目录中的文件。

可以在ls后加上所要观察的目录名称或文件的名称,如果你在下ls命令后没有接任何的目录名,它将会显示出目前目录中所有文件。

ls可以带一些参数,给予用户更多相关的信息:-a:在UNIX中若一个目录或文件名字的第一个字元为".",该文件为隐藏文件,使用ls将不会显示出这个文件的名字。

如cshell的初始化文件.cshrc,如果我们要察看这类文件,则必须加上参数-a。

-l:这个参数代表使用ls的长(long)格式,可以显示更多的信息,如文件存取权,文件拥有者(owner),文件大小,文件更新日期,或者文件链接到的文件、文件夹。

-F:给目录、可执行文件、符号链接以特殊的标记,在可执行文件后面加“*”、目录后面加“/”、符号连接后面加“@”,以方便用户区别。

3、cpcp命令用于将一个或多个文件复制成另一个文件或者是将其复制到另一个目录去。

cp有三种基本格式如下:cp source target将文件名为source的文件复制一份为文件名为target的文件。

如果target文件不存在,则产生文件名为target的文件,如果target文件存在,缺省时自动覆盖该文件。

cp file1file2…dir将文件file1file2...都以相同的文件名复制一份放到目录dir里面。

cp-r source target拷贝整个目录,将source目录下的所有文件和文件夹复制到target目录下。

cp命令常用的选项参数有:-i:交互(interactive)模式,当文件名为target的文件存在时,缺省情况下该命令会自动将原来target的内容覆盖掉,加上改选项将询问用户是否覆盖。

用户输入y(yes)则执行复制的动作,否则放弃复制。

Cadence 手册详细图解 英文版

Cadence 手册详细图解 英文版

Cadence IC Design ManualFor EE5518ZHENG Huan QunLin Long YangRevised onMay 2017Department of Electrical & Computer EngineeringNational University of SingaporeContents1 INTRODUCTION (4)1.1 Overview of Design Flow (4)1.2 Getting Started with Cadence (6)1.3 Using Online Help (8)1.4 Exit Cadence (8)2 SCHEMATIC ENTRY (9)2.1 Creating a New Design Library (9)2.2 Creating a Schematic Cellview (10)2.3 Adding Components to Schematic (11)2.4 Adding Pins to Schematic (12)2.5 Adding Wires to Schematic (13)2.6 Saving Your Design (14)3 SYMBOL AND TEST CIRCUIT CREATION (15)3.1 Creating Symbol (15)3.2 Editing Symbol (16)3.3 Building Test Bench (18)4 SIMULATING YOUR CIRCUIT (21)4.1 Start the Simulation Environment (21)4.2 Selecting Project Directory (21)4.3 Setup Model Library (22)4.4 Choosing the Desired Analysis (22)4.5 Setup Variables (23)4.6 Saving Simulation Data (24)4.7 Saving Output for Plotting (24)4.8 Viewing the Netlists (25)4.9 Running the Simulation (25)5 PHYSICAL LAYOUT (28)5.1 Layout vs Symbol of CMOS Devices (28)5.2 Starting Layout Editor (29)5.3 Vias (31)5.4 Changing the Grid (33)5.5 Inserting and Editing Instances (34)5.6 Drawing Shapes / Paths (35)5.7 Creating Pins (36)6 DESIGN VERIFICATION: DRC AND LVS (38)6.1 Performing DRC (38)6.2 Performing LVS (40)6.3 Performing PEX (41)7 POST‐LAYOUT SIMULATION (45)7.1 Simulation the Extracted Cell View (45)8 CONCLUSION (46)1INTRODUCTIONThis manual describes how to use Cadence IC design tools. It covers the whole design cycle, from the front-end to the back-end, i.e., from the pre-layout design to the post-layout design.The manual aims to provide a guide for fresh users. Following the manual, users can start doing analog IC design even though the users don’t have any knowledge of the tools.An inverter is used to illustrate the whole cycle of analog IC design, and Cadence Generic 45nm (cg45nm) kit is the technology library used for implementing the inverter. The method stated in the manual can be applied to other type of analog circuit design.1.1Overview of Design FlowFigure 1 shows a typical analog IC design flow.The design flow starts from schematic entry with the Cadence schematic capture tool –Schematic Editor. Devices or cells from the cg45nm or other libraries are used to build your circuit. Your design is hierarchical; therefore higher level schematics also incorporate cells which you have already developed. The schematics which you enter at this stage therefore typically consist of a number of base library cells and also lower level cells designed yourself.These are described in Sections 2 and 3 of the manual.When you have finished designing a particular circuit, you need to simulate it to ensure that it works as expected. It would be unlikely that your circuit works as expected at the first time so you have to repeat the cycle to improve the circuit, as shown in Figure 1, until the circuit works satisfactorily. This must be done for each sub-circuit of your design and then for the top level design. How to simulate and view the performance of simulation results are presented in Sections 4 of the manual.When the performance of the circuit is satisfactory, it is ready to start the physical design or layout of the circuit. The layout starts with the cell or device placement. Once the cells have been placed, routing can be carried out. Routing connects the cells/device of the design.After finishing placement and routing, the layout has to go through the Design Rule Check (DRC) with rule decks provided by PDK provider, to ensure that there is no design rule violation in the layout. The layout has to be rectified accordingly to the rules’ requirement till it passes DRC.Upon a successful DRC, it is Layout-versus-Schematic (LVS) check, to assure that all connections in the layout are correct. The layout has to be amended accordingly to the schematic If LVS doesn’t pass. DRC has to be done whenever layout is changed. The process is repeated until the LVS passes.Figure 1. Analog IC Design FlowThe next step is parasitic extraction (PEX) to get the extracted view of the circuit, which is used for post–layout simulation. The extracted view includes the parasitic effects in both the instances/devices and the required wiring interconnects of the circuit.Following DRC, LVS and PEX, it is post-layout simulation. The post-layout simulation is essential to make sure that the circuit with the extra parasitic parameters functions well and still meet the design specifications. If the performance of the post-layout simulation is not acceptable, back to the stage of schematic entry to check the circuit. Basically, re-design the circuit is necessary. Repeat the whole flow until the results of the post-layout simulation meet the design specifications.If everything is satisfactory, the next stage is GDSII Generation. It generates a file which depicts the low level geometry of layout. GDSII format is industry standard format suitable fora semiconductor company to fabricate and manufacture the chip of layout. This is briefed inthe last section of the manual.1.2Getting Started with CadenceUpon logging into your account, you will be brought to the Linux Desktop Environment.Right click on the desktop and click Open Terminal to open a “window” on the desktop. This window is the Linux command line prompt at which you can run Linux commands. After running a Linux command, this window also shows the output of the command.The following steps show how to start Cadence with cg45nm kit.A.Create a working directory - project (it can be any name as you like) with thecommand:mkdir projectwhere mkdir is Linux command and the project is the directory name;B.Enter the working directory with the command:cd projectwhere the cd is the Linux command;C.Type the followings commands to do the environment setup for using Cadence Generic45nm PDK.cp /app11/cg45nm/USERS/cds.lib .cp /app11/cg45nm/USERS/assura_tech.lib .cp /app11/cg45nm/USERS/pvtech.lib .D.Start cadence in the working directory – project with the following command:virtuoso &where virtuoso is the command to start Cadence IC design tool.Now, Cadence tools are successfully started. Keeps only the Command Input Window (CIW) which is shown in Figure 2.Figure 2. CIW WindowDo not close this CIW and try to keep it in view whenever you are using Cadence. Error messages and output from some of the tools are always sent to the CIW. If something doesn't appear to be working, always check the CIW for error messages. In addition, the CIW allows the user great control over Cadence by interpreting skill commands which are typed into it.E.In the CIW, select Tools Library Manager. The Library Manager pop up as inFigure 3. The Library Manager is where you create, add, copy, delete and organizeyour libraries and cell views.Figure 3. Library Manager WindowYou can see that the library gpdk045 appears in the Library column of the librarymanager.Now, you have started Cadence tool and loaded the cg45nm kit successfully. There are some documents in /app11/cg45nm/ gpdk045_v4_0/docs, and you can always refer to these documents for the information such as devices, device models, DRC rules and others related to cg45nm kit.Next time, you need only to repeat the steps B and D, for launching Cadence virtuoso and doing your project.1.3Using Online HelpCadence provides a comprehensive online manuals for all Cadence tools. You can launch the online help by typing the following command at the Linux prompt.cdnshelpThis invokes the online software manuals. Alternately, there is a help menu on each Cadence window. Manual which is related to that window related will pop-up once clicking on the help button.1.4Exit CadenceTo exit Cadence, just click on the cross sign X or File Exit in CIW. It is necessary to exit Cadence when it is not in use. Your library file would be locked or cannot edited next time if Cadence was not exited properly.2SCHEMATIC ENTRYNow that Cadence is running, you are almost ready to start entering schematics. However, you must first create a library which will be used to store all the parts of your design. Then, schematic can be created in the library.2.1Creating a New Design LibraryA.In the Library Manager window, select File→New→Library. New Library formpops up as shown in Figure 4.B.In the New Library form referring to Figure 4, key in your design library name(example: test) in the field of Name, and then click Ok.C.Click Ok in the pop-up window - the Technology File for New Library, referring toFigure 5.D.Choose gpdk045 in the Attach Library to Technology Library form, referring toFigure 6, and then click Ok.Figure 4. New Library FormFigure 5. Technology File for New Library FormFigure 6. Attach Library to Technology File FormA new library, named test, should appear in your Library Manager window.2.2 Creating a Schematic CellviewA.In Library Manager, select the Library where you would like to create a schematic. Then,select File→New→Cell View.B.Set up the New File form as Figure 7Figure 7. Create CellViewC.Click OK when done. A blank schematic window for the "inv" (your cell name)schematic appears.Explore the functions available by putting your mouse over the toolbar and fixed menu icons.In addition, note that some of the menu selections have alphabets listed to the right of them. These are bind-key or shortcut-key definitions which are very useful in the long run.Test them out during the schematic drawing in subsequent steps.2.3Adding Components to SchematicFigure 8 shows the schematic which you are going to patch, and the property of each component is listed in Table 1.Figure 8. Inverter CircuitTabel 1. Component Properties of Figure 8: Inverter CircuitComponents Library Name Cell Name PropertiesPMOS gpdk045 pmos1v l:45nm w:120nm (default size)NMOS gpdk045 nmos1v l:45nm w:120nm (default size)Here is the example on how to add component instances by placing cell views from libraries. Type “i” bind-key or select Create Instance in the schematic window or click on the menu bar to display Add Instance form. Then in the Add Instance window, select gpdk045as Library, choose the NMOS transistor by selecting nmos1v in Cell and also choose symbol as View, as shown in Figure 9.Figure 9. Add Instance FormSimilarly, add the pmos1v into the schematic. As an example, here we just keep all theparameters as default.If you place a component with the wrong parameter values, select the component and type “q” bindkey or use the Edit→Properties→Objects command to change the parameters. Use the Edit→Move command or type “m” if you place components in the wrong location.2.4Adding Pins to SchematicYou must place I/O pins in your schematic to identify the inputs and the outputs. A pin can be an input, output or an input-output (bi-directional) pin.Type “p” or select Add →Pin from inv Schematic Window or click the Pin fixed menuicon in the schematic window. The Add Pin form appears as Figure 10.Figure 10. Add Pin FormClick Hide and move you cursor to the Schematic Window. Place pins at the correct places and click right mouse key to rotate the pin if necessary.Add pins according to Table 2, paying attention to the direction.Table 2. Pin Names and Direction of invPin Names DirectionVin InputVout OutputVDD, GND Input-OutputCaution: Do not use the add component form to place schematic pins.2.5 Adding Wires to SchematicAdd wires to connect the components and pins in the design.A.Type “w” or select Add →Wire (narrow) in Schematic Window or click (narrow)fixed menu icon.B.In the schematic window, click on a pin of one of your components as the first pointfor your wiring. A diamond shape appears over the starting point of this wire.C.Follow the prompts at the bottom of the design window and click left mouse key onthe destination point for your wire.D.Continue wiring the schematic. When done wiring, press Esc with your cursor in theschematic window to cancel wiring.2.6Saving Your DesignCheck the design to ensure that it is correct and save the design.A.Click the Check and Save icon in the schematic window.B.Observe the CIW output area, for the information of the check and save action.3SYMBOL AND TEST CIRCUIT CREATIONSymbols are useful when creating designs as it is impractical to show every transistor on the top level schematic. Instead, the symbols of cells are created in order to instantiate them in the higher level schematics and make them more readable (i.e. hierarchical designs). Create a symbol for your design so you can place it in a test circuit for simulation.3.1Creating SymbolA.In the inv schematic window, select Create → Cellview → From Cellview. CellviewFrom Cellview pops up as shown in Figure 11.Figure 11. Cellview From Cellview FormB.Click OK in the Cellview From Cellview form. The Symbol Generation Options formappears as Figure 12. Enter the information listed in Table 3 for the symbol.Table 3: Pin SpectificationsLeft Pins : VinRight Pins : VoutTop Pins: VDDBottom Pins: GNDFigure 12. Symbol Generation Options FormC.Click OK in the Symbol Generation Options form. A window with a symbol createdautomatically by the tools pops up, referring to Figure 13.Figure 13. Symbol Generated AutomaticallyD.Observe the CIW output pane and note the messages stating Adding ‘CDFinformation ...’.3.2Editing SymbolYou can modify the symbol to have a more meaningful shape for easy recognition.A.Move your cursor over the symbol, until the entire green rectangle is highlighted. Clickleft to select it.B.Click Delete icon in the symbol window to delete the green rectangle.C.Select Create→Shape→Polygon. Follow the prompts at the bottom of the symbol, anddraw the triangle shown in Figure 14.D.Type “m” or click Move icon in the symbol window, move the pins to the finaldestination.E.Select [@partName], and use Edit→Properties→Object to change it to inverter asshown in Figure 14.Figure 14. Edit Object Properties FormF.Save your edited symbol view. The final symbol is shown in Figure 15.Figure 15. Symbol of inv3.3Building Test BenchTo test the inverter that you have just built, you need to create a test bench. This test bench will also be used during the post-layout simulation.Creating an inv_test schematic cellview with the below information, following the steps listed in Section 2 – SCHEMATIC ENTRY. The test bench is as shown in Figure 17.Library Name : testCell Name : inv_testView Name : schematicLibrary Name Cell Name Propertiestest inv_testanalogLib Vdc VDDanalogLib vpulse Referring to Figure 16analogLib gnd GNDanalogLib cap 1f FFigure 16. Vpulse FormFigure 17. Test Bench – inv_test for inv CircuitNote:There are wire names Vin and Vout in Figure 17. These can be created by clicking on Create Wire Name on the inv_test schematic window. Key in Vin Vout in the Names field of the Add Wire Name form, and then click Hide. Moving your mouse to the schematic window, click the wire where you want it to be named in the same sequence as typing the names in the Names field.4SIMULATING YOUR CIRCUITBefore starting the simulation, make sure that the schematic (inv_test) is open, then perform the following steps.4.1Start the Simulation EnvironmentIn your schematic window, select Launch →ADE L. The Analog Design Environment (ADE) window appears as shown in Figure 18.Figure 18. ADE Window4.2Selecting Project DirectoryIn the ADE window, select Setup→Simulator/ Directory/ Host. A Choosing Simulator form appears as Figure 19. In the Project Directory blank, type in /var/tmp/(desired folder name) to save your simulation files in the /var/tmp directory on the local server. Click OK to confirm.Figure 19. Choosing Simulator/Directory/Host FormAs each user account has a limited quota, this helps to conserve memory space in your account and prevents you from exceeding your account quota. However, note that contents in this folder is deleted periodically every 30 days automatically.4.3Setup Model LibraryIn the ADE window, select Setup Model Libraries. The Model Library setup form appears. Double click the column of section, and then click the down arrow to choose tt which is typical N and P model parameters. The model library setup for the inv_test circuit is shown in Figure 20. Click ok on the setup form to finish the settings.The information of models can be found in/app11/cg45nm/gpdk045_v4_0/docs/gpdk045_pdk_referenceManual.pdf.Figure 20. Model Library Setup for inv_test4.4Choosing the Desired AnalysisIn the ADE window, click the Choose Analyses icon . The Choosing Analyses form appears. Cadence ADE is able to run several types of simulations consecutively. You are then able to view the signals from different simulations at the same time. In this example, we will do transient analysis, so we shall setup transient analyses through the ADE as Figure 21.Figure 21. Setup for Transient Analyses4.5Setup VariablesThere is a variable, VDD, in the inv_test circuit. We need to set a value to it before starting simulation.In the ADE window, click Variables. Enter the name as the variable name VDD, then set the valueas 1.1, and finally click Ok. Please take note that 1.1v is the nominal voltage for this technology.Figure 22. Editing Design Variables4.6Saving Simulation DataThe simulation environment is configured to save all node voltages in the design by default. In larger designs, where saving all of the data requires too much disk space, you can select a specific set of node to save. Following steps show you how to select terminals to save.A.In the ADE window, select Outputs→Save All.B.The Keep Options form appears. Do not modify the form at this time. However, if youneed to save less data, under the first option “Select signals to output”, Click “selected”.4.7Saving Output for PlottingSelect the signals that you would like to observe.A.Select Outputs→To Be Plotted→Select On Design.B.Note that if you click on wires / nets, voltage signals are selected. If you click onconnection nodes, currents flowing through that note and into the component are saved.C.Follow the prompts at the bottom of the schematic window. Click on the output wireslabeled with Vout and Vin (select the wire that you want to monitor).D.Press Esc with your cursor in the schematic window when finished.Now you have set up the simulation environment which as shown in Figure 23. You can save the simulation state. This saves all the information such as the Model Path, outputs, analyses, environment options, and variables so that you do not need to set these parameters the next time again.Figure 23. ADE window with completed settingsIn the ADE window, select Session→Save State. Tick Cellview and then click OK. You can recall your settings by selecting Session→Load State.4.8Viewing the NetlistsSometimes, you need to view the netlist of your circuit or design. You can do so through the ADE, select Simulation→Netlist→Create / Display / Recreate.If there are any errors encountered during this step, check the messages in the CIW and retrace your steps to see that all data was entered properly.4.9Running the SimulationSelect Simulation→Netlist and Run to start the simulation or click on the Run Simulation icon in the Simulation Window. After the simulation is done, a waveform window will pop up showing the simulation results as Figure 24.Click on the waveform window to separate Vin and Vout.You can create a horizontal or vertical marker by clicking Marker on the waveform window. For example, creating a horizontal marker on Figure 24 with put Y Postion at 0.5*VDD=550mV, and then zoom in. The waveform window will look like Figure 25. Delays of the inverter could be found from the reading on the marker.Figure 24. Output of SimulationFigure 25. Waveform with Marker.Explore the icons on the toolbar as well as the various items on the menu. Try to add markers as that is something that will be used often during your simulations. You can also update the titles and labels on your plot to make them easy to read or more meaningful, if necessary.*Quick Tip : Shortcuts “a” and “b” to place a delta marker where you observe the difference between two points. What does shortcuts “v” and “h” do?There are many other functions available in the calculator tool, explore and play around with them.By now, you have finished pre-layout simulation (schematic level simulation). Next, you need to draw the layout of the inverter circuit and then do post-layout simulation to check your circuitperformance.5 PHYSICAL LAYOUTBy now, you should know how to create and simulate your circuit. Once the performance of your design is satisfactory, the next step in the process of making an integrated circuit chip is to create a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices.Before we get into the layout, first you need to understand the design rules for layout. Design rules give guidelines for generating layouts. They dictate spaces between wells, sizes of contacts, minimum spacing between a poly and a metal, and many other similar rules.Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. Note that the layout is very much process dependent, since every process has a certain fixed number of available masks for layout and fabrication.You may find more details on the Design Rules Manual (DRM):/app11/cg45nm/gpdk045_v_4_0/docs/gpdk045_drc.pdf5.1 Layout vs Symbol of CMOS DevicesIn this section, we look at only three devices: nmos1v and pmos1v. Check the process document, you can find the information for other devices.Figure 26 shows the nmos1v device. From layout view, you can see that the terminal B is the black background of the layout window.Figure 26. Layout vs Symbol of NMOSFigure 27 shows the pmos1v device, which looks similar to NMOS device but with P type implant (orange-stripe layer) and N-well (purple surrounding layer). G D SBFigure 27. Layout vs Symbol of PMOS5.2Starting Layout EditorNow we are going to create a new layout in the cell “inv” in “test” library.A.In Library Manager, select File→New→Cellview ... A Create New File form pops up.B.Select "test" as Library Name; enter "inv" as Cell Name, "layout" as View Name.C.Choose Open with Layout XL, and then click OK.Figure 28. Create Cellview – LayoutUseful layerselectionfeatureFigure 29. Layout WindowCell "inv" with "layout" view in library "test" will be created. It is opened up automatically, followed by inv schematic window, as shown in Figure 29. The layout editor contains two main sub-windows, namely the Layers sub-window on the left and Layout Editing window on the right. Notice the Layers sub-window on the left side of the layout view. This sub-window displays the fabrication layers defined in the technology. You can find the cross sectional profile in the process documents.Each layer is represented by a different color and pattern for easier differentiation. The black background on the right can be interpreted as the p-substrate of the wafer.To hide a layer, use the middle scroll button to click on a layer. To disable a layer from use, use the right mouse button.You might notice that some layer names appear more than once in the Layers sub-window. For example, Metal1 appears two times: one as Metal1 drawing, the other as Metal1 pin. Metal1 drawing is a layer with drawing purpose, and such layers with drawing purposes will be fabricated in the mask. The pin layers are symbolic layers and serve to indicate position of I/O pins and define net names. Such layers are not part of the mask layout and will not be fabricated.5.3ViasVias are used to connect between layers, much like those used in PCB design.There are different types of vias for different layer pairs. Normally a via is only for connecting two successive layers, e.g., Metal 1 and Metal 2. In case there is a metal jump between more than two layers, via stacking is required.In the layout window, click Create→Via or type “o” to bring up the via menu. Place the vias on the layout editing window, you can observe the layers that are involved in each type of via. Experiment with the different modes and configurations in the via menu to create arrays and stacks of vias as well. For example,A.Click on Create→Via, the Create Via window pops up as figure 30 shows.B.Choose M1_PO under Via Definition, and click on the layout window to place it andthen press Esc button to stop the placing. You can change the number of Rows and Columns on the Create Via form.C.To view the layers of M1_PO, click to select it first and then press Shift + f key. Observethe via appears different.D.To check the layers used in via M1_PO, select it and then click Edit→Hierarchy→Flatten as shown in figure 31. Click OK on the pop-up form shown in Figure 32.E.Now, you can separate the layers and check layers’ property to find out the layers’ name.Via M1_PO connects layers Metal 1 and Poly as shown in Figure 33.Try to explore different options (Rows, Columns, Stack, etc.) under via menu by yourself, this will be very helpful for layout drawing.Figure 30. Create Via windowsFigure 31. Edit ViaFigure 32. Flatten FormFigure 33. Via M1_POThe M1_PSUB and M1_NWELL contacts are substrate and n-well contacts that are used to connect the bulks of the NMOS and PMOS respectively. For the inverter circuit used in this manual, the bulks of the NMOS and PMOS need to be connected to ground (GND) and VDD respectively.5.4Changing the GridIn Figure 29, the black window on the right is the layout editing window. The position of the cursor in layout editing window is indicated by the coordinate showed on the top right corner of the window after X: and Y:. The unit here is "µm". Move your cursor around the editing window and see the X: Y: values change with step size 0.1. Change the step size to 0.005 as that is the minimum step size for this technology.From Layout Editing window pull down menu, select Options →Display... change "X Snap Spacing" and "Y Snap Spacing" to 0.005 then click on "OK". Now move the cursor around the editing window again, you will see the X: Y: values change with step size 0.005.There are raw grid and fine grid (as small dots) on the window background. If you cannot clearly see the raw grids, from pull down menu select Window →Zoom out by 2In addition to pull down menu and bind key "z", "Zoom Out" is also listed in the picture tool bar to the left of the window. Find it and try it out.Also you may use up, down, left, and right arrows to move around the design window. You will need to use "Zoom in" and "Zoom out" and those arrows many times throughout your design process. So it's not a bad idea to practice them a little bit now.To save and close the cell view, from Virtuoso Editing window, Select Design →Save.。

cadence 教程

cadence 教程

cadence 教程Cadence 是一种电子设计自动化工具,常用于模拟、验证和布局设计。

它可以帮助工程师在各种电子系统中设计和验证电路,从而提高电路设计的效率和可靠性。

下面将介绍一些 Cadence 的基本使用方法和技巧。

1. 创建新项目要使用 Cadence,首先需要创建一个新项目。

可以通过菜单栏上的"File" -> "New"来创建新项目。

然后输入项目名称、路径等信息,并选择适当的项目类型。

2. 添加电路在 Cadence 中,可以通过绘制电路原理图来添加电路。

可以使用"Create Schematic"工具来创建新的电路原理图。

在绘制电路原理图时,注意使用正确的元件符号和连线方式。

3. 设置仿真参数在进行电路仿真之前,需要设置仿真参数。

可以通过菜单栏上的"Simulator" -> "Edit Simulation"来打开仿真设置窗口。

在仿真设置窗口中,可以设置仿真类型(如DC、AC、Transient 等)、仿真时间范围、仿真步长等参数。

4. 运行仿真设置好仿真参数后,可以通过菜单栏上的"Simulator" -> "Run Simulation"来运行仿真。

运行仿真后,可以查看仿真结果,如电压波形、电流波形等。

5. 进行验证在验证电路设计时,可以使用 Cadence 提供的调试工具和验证功能。

可以通过菜单栏上的"Debug" -> "Start Debugging"来启动调试。

在调试过程中,可以查看电路元件的属性、信号的波形等信息,以发现和解决问题。

6. 进行布局设计在电路设计完成后,可以进行布局设计。

可以使用 Cadence 提供的布局工具来布局电路版图。

布局时,要注意合理安排电路元件的位置和走线方式,以满足电路设计的要求。

cadence Tutorial

cadence Tutorial

Schematic Layout
Figure 20: PPART Partitioning
Schematic Layout


Click “Place Partitioning”, which pops up a window shown in Figure 20. This is used to create partitions. In the section “Choose or type a Partition name”, type the name of the partition one would like to create for e.g. PPART/NPART and click on “Create Partition”. Click on the “Link to design” which turns into “Unlink”. Choose “Softfence (SoftFnc dg) from the LSW window (Figure 21). Create a rectangle (“Create Rectangle”) inside the Boundary area of the Design (between Vdd and Gnd). Click on “Attach Shape” and click on the rectangle drawn on the layout window. If the shape is attached the “Detach Shape” will be activated. (Incase this doesn't happen just check whether the “Link to Design” button is showing "Unlink", otherwise click on "Link to Design".)

Cadence Tutorial(Cadence 教程)

Cadence Tutorial(Cadence 教程)

Cadence TutorialCadence ICFB (IC Front to Back environment) is a software package used for Integrated Circuit design and simulation. This software features a complete suite of tools including schematic capture, simulation, layout, and extraction. Several simulation engines are available: spice, hspice, spectre, etc. These engines require model files that specify the device modeling parameters, such as oxide thickness ( Tox ) and electron mobility ( Uo ).1.We will be using the TSMC 0.3d (L=0.25um) process availablein the NCSU Design Kit.2.We will also be using spectre for simulation.The following tutorial will guide you through the basic setup and operationof Cadence ICFB. You will build a schematic and perform several analyses.Quick TipsI. Should the Schematic not display correct, selectWindow -> Redraw from the Schematic menuII. Schematic view has many editing operations that are very helpful. For example copy, paste, undo, rotate.III. These operations are accessible through any of the following: the Edit menu, the side bar buttons, and shortcut keys.IV. IMPORTANT : Hit the “Esc” key to exit an operation.Contents:1. Cadence Startup42.Startup Screens53.Create A New Library74.Create A New Schematic85.Adding Components to the Schematic106.Connecting Components in the Schematic147.Simulator Setup168.DC Analysis189.Transient Analysis2010. AC Analysis2311. Parametric Analysis2612. Saving State of the Analog Design Environment2813.Plotting VI Characteristics2914.Plotting DC Transfer Characteristics3415. Plotting Rin and Rout361.Cadence Startup:a.Cadence is started from a terminali. To open a terminal: right click on the desktop and select“new Terminal”.Or, press “Ctrl”+”t” on the keyboardb.Running Cadenceii.Change the directory to “cadence5”by executing the followingcommand: % cd cadence5iii. The following command should be executed to source cadence.source /usr/local/cadence/NCSU_151/ncsu.cshrciv. Executeicfb: % icfb&2. Startup Screens:W hen ICFB starts, two windows appear: the ICBF Log window (Figure 1) and the Library Manager (Figure 2). The Log window is the main window for ICFB. User preferences and other options are accessed through its menus. The Log window also displays useful output, such as if a simulation run completes successfully or unsuccessfully.Figure 1. The ICFB Log WindowThe Library Manager provides organization for components and design files. Cadence files are organized into “Libraries.” Cadence files are structured objects called “Cells”. Each “Cell” can have several different “Views”. These “Views” are associated with a particular Cadence tool, such as the Layout editor and the Schematic editor.Figure 2. The Library Manager Window3. Create A New Library:a. Select File -> New -> Library ...in the either the Library manager or Log window. The CreateLibrary window appears.Figure 3 Create Library Window*b.Enter a library name.c.Choose “ Attach to existing tech library ”underTechnology library.d.Choose “NCSU_Techlib_tsmc_03d” for the library. This isthe process we will be using for this class.(By attaching a tech library to our library, all the cells we will createin our library will be associated with this 0.3d process.)e. Click the “ OK ” button. Your new library will be added to the list in theLibrary Manager.*Please do not refer to the library name in the figure; only follow instructions above.4.Create A New Schematic:a. Click on the name of the library you just created. We will now add a newcell to this library.b.Select File -> New -> Cell View ...in the Library Manager. The Create New File window appears.Figure 4. Create New File Windowc.Enter the schematic name in “ Cell Name ”.d.Choose Tool “ Composer-Schematic ”.e.The View Name should be “ schematic ”, which associates this cellview with the Schematic editor.f.The Library Name should be the name of the library you created.a. If not, click the “-“ next to the Library Name and select your libraryfrom the list.g.Click “ OK ”. The Composer-Schematic Window will appear.Figure 5. Composer-Schematic Window5.Adding Components to the Schematic:a. Select Add –> Instance from the schematic menu. The ComponentBrowser and Add Instance windows will appear.1)There are many shortcut keys to menu items. Usually it is fasterto use the shortcut keys instead of using the menus.2)Press the “i” key to add an instanceb. Choose the “ NCSU_Analog_Parts ” library.Figure 6. Component Browser and Add Instance Windowsc.Select “ N_Transistors ” from the list.1)Click on “ nmos4 ”2)Switch to the Schematic Window and place the transistorby clicking somewhere on the schematic.d.Press the “Esc” key to stopping adding instances.e.Click on the nmos component you just placed. The component willbe surrounded by a white border, when it is highlighted.f.Press the “q” key to edit the component properties.g.Change the Width to 10u (it will be set to 9.975u, which is the closestmultiple of 0.3). In this example, leave the Length at the processminimum. But, in your design you may want to change the length also.Figure 7. Add Instance Windowh.Press “i” on the keyboard to add more components.i.Select “ R_L_C ” from the list to place resistors, inductors, and capacitors.1)Add a 50k resistor (“res”) to your schematic.2)To change the component values , click on the part in theschematic and press “q”. Remember to press “Esc” on thekeyboard to stop adding instances.j.Select “ Voltage_Sources ” from the list.1)Add a “vsin” sourcei.Set the “AC Magnitude” to 1. This value is used inAC (Frequency Domain) Simulations.ii.Set the “Amplitude” to 2m and the “Frequency” 10k. These values are used in Transient (Time Domain) Simulations.iii.Apply a gate voltage: set the “DC Voltage” to 0.52)Add a “vdc” source with a 2.5 “DC Voltage”k.Select “Supply_Nets”from the list. These components allow us to connect nodes (nets) together without drawing lines.1)Add “gnd” and “vdd” components to the schematic.l.Hit the “Esc” key in the Schematic Window, when you are finished placing components.6. Connecting Components in the Schematic:Connect the component with wires.a.You can add wires by selecting Add -> Wire , then left click where youwant you end points. Hit “Esc” when you are finished adding your wire.b.It is much easier to just left click and drag the component’s node (thered squares) to form lines.c.Connect the components as shown in Figure 8.Figure 8. Common Source Amplifierd.You can label “in” and “out”, by selecting Add -> Wire Namee.Remember to connect the bulk to the source.f. Save your work by selecting Design -> Check and Save****NOTE: It is important to “Check and Save” every time you make a change to the schematic. If you don’t, the simulator will not complete successfully until the schematic is “Checked”. There are design rules for schematic entry. When you perform a “Check”, your schematic is compared with the design rules.7. Simulator Setup:a. From the Schematic menu selectTools -> Analog Environment . The Analog DesignEnvironment window will appear as shown in Figure 9.Figure 9. Analog Design Environment Windowb.Select Setup –> Simulator/Directory/Host ... in the AnalogEnvironment window.c.Choose spectre and click OK.Figure 10. Choosing a Simulator Windowd.Select Setup –> Model Librariese.Add the TSMC 0.3d model files for NMOS and PMOS devices./usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dN.m/usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dP.mFigure 11. Add Model Library File Window**Please do not refer to the names of the model files in the figure; only follow instructions above.8.DC Analysis:a. Select Analyses –> Choose in the Analog Environment window.b.Click on “dc”c.Select “Save DC Operating Point”.Figure 12. Analyses Setup Windowd.Click “OK”e.Select Simulation -> Run in the Analog Design Environment windowf.Once the simulation is complete click onResults -> Annotate -> DC Node Voltages andResults -> Annotate -> DC Operating Points . Now the DCvoltages, currents and other information will appear on the schematic.NOTE: If the Annotate section is not highlighted, then the simulation was unsuccessful. Look in the ICFB Log window for more information about the reason for the failure.Make sure that the DC conditions of the circuit are correct, beforeperforming other analyses.9.Transient Analysis:a. Select Analyses -> Choose … in the Analog Environment window.b. Click on “ tran ” and enter the stop time for the simulation.c.Click OKd.Make sure you have entered the Amplitude 10m and Frequnecy 10Kfor the vsin source in the schematic. These values are used in the Transient Analysis.e.Select Outputs -> To Be Plotted -> Select on Schematic .f.Return to the Schematic editor, and select the desired outputs.1)Click on a wire or a wire name to choose a voltage.2)Click on a node (the red squares) to select a current.3)When you are done press the “Esc” key.g.Select the input voltage and the output voltage.h.The outputs will appear under the “Outputs” section in the Analog DesignEnvironment window.Figure 13. Outputs added to Analog EnvironmentNote: The input and output nodes are named as “in” and “out” in the schematic for convenience. Otherwise, you would get the default net names.i.Click on Simulation -> Run .j.The Waveform window will appear.k. Select Axis -> Strips to view the plots on separate axes.Figure 15. Transient Waveforms Strips10.AC Analysis:a. Select Analyses -> Chooseb. Disable the Transient analysis and choose AC analysis.c.Enter the Sweep Range (100 to 1M).d.Make sure you have entered AC Magnitude for the AC source as 1.This means the output AC Magnitude will be the gain of the circuit.e.Select Simulation -> Runf. If you still have the outputs selected, then the voltage magnitude will beplotted:Figure 16. AC Voltage Magnitude, Frequency Responseg.We can also plot the Magnitude in dB. Select Results -> DirectPlot -> dB20 Magnitude in the Analog Environment Window.h.Click on the output wire and then press the “Esc” key.i.The Magnitude in dB is plotted.Figure 17. AC Magnitude dB, Frequency Response11. Parametric Analysis:We can also assign a variable to component parameter, such as the resistance value of a resistor. Then, we can use the Parametric Analysis tool to change the variable value and run a simulation of each value.a.Change the value of Rd to “my_Rd_variable” on the schematic.b.Select Variables -> Copy From Cellview in the AnalogEnvironment window. The variable “my_Rd_variable” should show up in the list of Design Variables. To assign a value, double click the“my_Rd_variable” in the list.c. Select Tools -> Parametric Analysis ... from the AnalogEnvironment menu.d.Enter the Variable Name “my_Rd_variable”.e.Choose a Range from 10k to 50k with 5 total steps.f.Select Analysis -> Start in the Parametric Analysis window.g.Plot the Magnitude as performed in the AC Analysis section.Figure 18. AC Simulation Using Parametric Analysis12. Saving State of the Analog Design Environment:We can also save the current state of the Analog Design Environment.This will save all the settings, such as the simulator and model library files selected. It will also retain the analyses, variables, and outputs selected. Then, the state can be reloaded at a later time, and all of the savedsettings will return. You can continue working exactly where you left off without having to choose the settings again.a. Select Session -> Save State in the Analog Design Environmentb.Now “state1” will be associated with this current design. The next timeyou open this design schematic you can reload this state.c.Do so by selecting Session -> Load State in the Analog DesignEnvironment13. Plotting VI Characteristics:Use the following procedure to generate VI plots for a transistor. This can be accomplished by doing a DC sweep of the voltage across drain and source.a. Build the following schematicb.Open the Analog Design Environment. Select the spectre simulatorand add the model library file.c.Choose a DC analysisd.Select “Component Parameter” from the “Sweep Variable” section,as shown above.e.Press the “Select Component” button.f.Then return to the Schematic Editor and click on the DC voltagesource connected to the drain.g.Select the DC voltage from the “Select Component Parameter”window, shown above. Click “OK”.h.The Component Name and Parameter Name will appear in theChoosing Analys is window.i.Enter a Sweep Range from 0 to 2.5. And, click “OK” to close the ChoosingAnalys is windowj. In the Analog Design Environment, select Outputs -> To be Plotted -> Select on Schematick.Return to the Schematic Editor, and click the drain node (red square) to select the drain current as the output. Press “Esc”.l.In the Analog Design Environment, the drain current node will appearin the Outputs section.m. Then run the simulation.Figure 20. VI Characteristic for Single VGSn. We can also perform a Parametric Analysis sweep on the value of VGS.a. In the Schematic Editor, change the value of the DC source to avariable, “my_VGS”b. Add the variable to the Analog Design Environment, Variable ->Copy from Cellviewc. Open the Parametric Analysis toold.Enter the variable name and the sweep rangee.Select Analysis -> RunFigure 21. VI Characteristics for Several VGS14. Plotting DC Transfer Characteristics:Use the following procedure to generate the DC Transfer Characteristic of an amplifier. This can be accomplished by doing a DC sweep of the input voltage. The DC Transfer Curve provides a lot of information about the amplifier: input/output dynamic ranges and gain.a. Consider the CS Amplifier belowb.Setup a DC Sweep Analysis for the DC voltage of the input source.c.Plot the output of the amplifier (in this case labeled “out”).Figure 22. DC Transfer Characteristic15. Plotting Rin and Rout:Use the following procedure to plot the input and output impedances of an amplifier. This can be accomplished by doing a AC sweep of the input or output Magnitude.a. Consider the circuit below for Rin:b. Setup an AC Analysis that sweeps the Magnitude of the AC input source.36c.Specify the Frequency of the signal (10k), and enter the Sweep Range.d.Click “OK”.e.In the Analog Design Environment, select Outputs -> Save Allf.We need to save the AC currents, so select “yes” for “Select ACterminal currents (useprobes)”. Click “OK”g.Setup the drain node as an output by selecting it on the schematic.h.Run the simulation.Figure 23. Slope = 1/Rini.You can quickly measure the slope of the plot by using the DeltaTool: select Trace -> Delta from the menu.j.Rout can be found in a similar fashion. Consider the circuit belowk. Setup the analysis like we did for Rin, but sweep the AC Magnitude of the AC source at the output.l. Run the simulationFigure 24. Slope = 1/Rout。

CadenceAllegroSI培训课件Lesson

CadenceAllegroSI培训课件Lesson
set on the DiffPair itself. Pre-defined DiffPair constraints cannot be added on any other
object type. If the (X)nets of a DiffPair reference different ECSets with different
In the Constraint Manager: DiffPairs are treated as Objects. DiffPair constraints are considered as “electrical”.
Pre-defined (DRCs) User-defined (custom measurements)
Differential Pair Analysis in Constraint Manager From the Constraint Manager, select
Nets > Routing > Differential Pair spreadsheet.
Defined rule on a selected Object
Constraints in the differential pair topology with only legal pins/parts. Alternatively, you can create differential pair ECSets for these rules in the
The differential pairs created using Allegro or the Constraint Manager are physical assignment only. To extract the differential pair topology, the differential pair signal model with mating pin specifications needs to be assigned. If a signal model is not assigned for the differential pair, the simulation will be single-Xnet-based .

cadence教程轻松学3

cadence教程轻松学3
6
IC设计基础
CADENCE
• 避免集成电路设计中出现错误措施有:
(1)在芯片中设置容错电路,使芯片具有一定的修正功 能。
(2)借助计算机辅助设计工具(EDA工具)对设计的每 个阶段进行反复验证和检查,并对物理因素与电学性 能的交织问题进行考虑,以保证设计的正确性。
7
IC设计基础
CADENCE
• 设计信息描述:
集成电路设计信息描述主要有设计图和语言描述方式。 与设计层次相对应的设计描述主要有功能描述、逻辑描 述、电路描述、版图描述。
功能和逻辑描述可用设计图和语言实现。 逻辑描述用逻辑图和逻辑语言实现。 电路描述用电路图实现。 版图描述采版图实现
8
IC设计基础
CADENCE
• IC设计流程:
9
IC设计基础
10
ICቤተ መጻሕፍቲ ባይዱ计基础
CADENCE
• 典型的实际分层次设计流程:
11
IC设计基础
CADENCE
• 分层次设计流程主要适用于数字系统设 计,模拟IC设计基本上是手工设计。
• 即便是数字IC设计,也需要较多的人工 干预。
12
IC设计基础
CADENCE
• IC设计方法
(1)全定制设计 (2)半定制设计
通道门阵列法 门海法
2
IC设计基础
CADENCE
• 集成电路制造过程示意图:
3
IC设计基础
CADENCE
• 集成电路设计域主要包括三个方面: 行为设计(集成电路的功能设计) 结构设计(逻辑和电路设计) 物理设计(光刻掩模版的几何特性和物 理特性的具体实现)
4
IC设计基础
CADENCE
• 集成电路设计层次主要包括五个层次:

Cadence Layout Tutorial

Cadence Layout Tutorial

ELEC 301Lab 5: Cadence Layout Tutorial 1Revision: 2.0Date: July 98OverviewThis lab shows you how to layout a simply inverter using Virtuoso Layout Editor. Virtuoso provides a hierarchical I.C. layout and verification environment that supports all I.C. design techniques, from hand crafting, to automatic placement and routing. This tutorial will take you step-by-step through the process of handcrafting a simple inverter and perform the design rule checking (DRC) to verify the correctness of the physical design. This layout will correspond to the schematic, which has been created in lab2. Learning the command in Virtuoso Layout EditorIn virtuoso, you can always seek help from the OpenBook whenever you faced any difficulty. To begin this lab, you are required to familiar with the virtuoso command, which will be frequently used in the following sections, by going through the OpenBook. To start the OpenBook, type “openbook” in the command window. Then select IC Tools – Layout Design – Virtuoso Layout editor help. Spend at least 15 mins to go thought all 4 topics (Cellviews, The LSW, Creating Objects and the Editing Objects).Setting Virtuoso Layout Editor EnvironmentBefore you can draw the layout in Virtuoso, you must first create a cellview (view name layout in cell inv) to contain the layout data. This is done using the same procedures you used previously to create the schematic cellview.Step 1.Open inv layout in edit mode.1.1.When you open a layout cellview, you see both the cellview and Layer andSelection Window (LSW). The LSW will appear first along the left side ofthe screen. Next an empty Virtuoso window will appear.At this point, you may find that the CIW window is overlapped by theEditing window. You should move the windows around so that you have agood view of the LSW window, the Editing window and the CIW. Keep youreye on the CIW messages and the status banner at the top of the Editingwindow.1.2The Layer and Selection Window (LSW) allow you to choose the layer onwhich you draw objects (called the “drawing” or “entry” layer).layer Name Descriptionnwell This is the well put down ina P-type wafer to provide atub for the PMOS transistorsactive Thin oxide region whichidentify active region fortransistors.poly Polysilicon. Used to makethe gate of the MOS devicepselect P-type implant masknselect N-type implant maskcp Contact cut between polyand metal1metal1First level metal. Used forhorizontal routing. E.g.Power and Ground of cellsvia First to second level metalcontact cutmetal2Second level metal. Used forvertical routing. Eg I/O pinof signal.ca Contact cut between activeand metal1.text Label for parts.dg Drawing for a layerpn Label the metal which isused as a I/O pin.It can also be used to set the layers to selectable or visible. The detailedprocedure will be given in the following.1.3.You will notice that there are fourquadrants in your screen. You will want todraw you layouts in the quadrant as figure.There is no specific reason for this otherthan that you will be more comfortableworking with a positive coordinate system.The spacing between the snap points is exactly 0.2u because all of our layoutfor fabrication can have no finer resolution than 0.2um.1.4Before creating transistors layout, you may need to zoom out to givenecessary space for drawing. In Virtuoso, you can find command Zoom underthe menu Window.of 2.Refer to OpenBook for details of command Zoom.Creating pmso Transistors LayoutThis part covers the basic steps used to layout a pmos transistor. You'll use polygons to describe most of the transistor geometric. The given geometry dimensions are based on the MOSIS scalable and generic CMOS design rule with lambda = 0.4 micron. You may need to refer to the design rule during design processYou will start by drawing the polysilicon gate layer for the pmos transistor. The gate should be 21λ (8.4u) in width and 2λ (0.8u) in length.Step 2.In the LSW, click on the active (dg) box.This refers to the Active Area drawing layer. (dg stands for drawing). Noticethat the top of the LSW now displays the selected layer name. We say thatany geometry you draw will be drawn with the selected drawing layer. Youcan change the selected drawing layer by clicking left on any of the layers inthe LSW menu.2.1Click on the Rectangle icon from the left menu (short cut icon),OR - Select Create - Rectangle from the pull-down menu.2.2 Drawing a rectangle 16λ (6.4u) in width and 21λ (8.4u) in height asfollowing figure. Remind that each snap point on the layout is 0.2um. To do so, you may want to use a ruler.In Virtuoso, Select Misc – Ruler . Click on mouse left button to start a ruler and move the cursor. The end of the ruler gives you the current length. Click again to complete the ruler.Anytime, you can press the Escape <ESC> key to terminate any drawing command including Ruler .To clear the ruler, select Misc-Clear Ruler .If you have make any mistake, you can delete the unwanted object, highlight the unwanted object and then select Edit – Delete . In addition, you can stretch the object if the size is incorrect. Select Edit-Stretch . Click on the edge of the object you want to stretch, you will see the edge is highlighted. Then click again on the new position where the gate width is 4.4u. Hit <ESC> to exit creates rectangle mode.2.3.Next, click left on the poly (dg) box in the LSW window, and using Create->Rectangle , draw a poly rectangle with dimension as shown in figure below,such that it is centered on the active rectangle. (It should overlap this rectangle by 7λ (2.8u) on each side, and the active rectangle should overlap it by 2λ (0.8u) on the top and bottom... this is to satisfy our MOSIS design rules). Congratulations! You have just created your first transistor.Confused? Right now you are probably thinking to yourself "I don't know all those rules, and it takes forever to look them all up". Don't worry about them,Cadence is nice enough to check our design rules for us, as we will see later.Fixing most mistakes is fairly easy. For drawing, a good rule of thumb seems to be that most spacing rules are 0.8um (for example, overlaps, spacing between object of the same shape, etc.). Fixing design rule violations is normally fairly easy.2.4. By now, we have finished drawing a transistor, however, we haven’tspecified that it is P-Type. To do so, draw a rectangle using pselect (dg),which overlapped the active of the top transistor by 2λ(0.8u). And then, draw 8.4u (gate width)2.8u0.8u 6.4uanother nwell (dg) overlapped the pselect. The overlap rule for this is that nwell should overlap active by 6λ (2.4u) as figure.2.5. We need to connect nwell to vdd!. To do so, we draw a plug for our Nwell.First, draw a 4λ x 4λ (1.6u) active rectangle. Then, place a nselect (since weare plugging an Nwell) region around the active which will overlap it by 2λ(0.8u) on all sides. Move the well plus to the position as following. StretchNwell to overlap it as figure shown.Performing a Design Rule Check (DRC)Although our inverter is not yet done, let’s perform a design rule check. It’s always a good practice to perform DRC periodically so that you won't finish a large design with many errors.Step 3.To do a DRC choose Verify-DRC , the DRC form will appear. Click on "OK ".Look in the CIW, you should see all the design rules scroll by as they are checked. When it is done you will see something like:******* Summary of rule violation for cell "inv layout" *******# errors Violated Rules4 Active overlap of gate must be at least 32 Poly separation to active must be at least 16 Total errors foundIf you look at your layout, you will see these errors flagged and highlight parts.Lets fix these errors now by referring to the appendix A for detail debugging.3.1.Re-run the DRC, and make sure your design is correct. Save your design.WellplugnwellCross sectionWiring the TransistorYou now have finished a pmos transistor, which are design rule passed. As from the schematic, the pmos transistor of our inverter is connected to the power and ground lines, and the well plugs.4.2.Let’s first create the output node. We cannot connect N-active and P-activedirectly, so we need to use metal1 to connect them.•To do so, we need to create 8 active contacts for PMOS and then connect those contacts with metal1. We also will route our power/ground lines inmetal1. Refer to figure for detailed position.•To drawing an active contact, first draw a 2λ x 2λ (0.8u) rectangle of ca (dg), ca standing for contact for active.•Instead of drawing 8 contacts by hand, lets draw one then copy it. To do so, select the contact and issue menu command Edit - Cop y. Repeat copycommand for another contacts. Notice that the spacing between contactsshould be 1.2u.•These are your contacts. MOSIS rules say that contact to metal needs to be surrounded by metal1 and active by 2λ (0.8u). Create two metal1 (dg)rectangles, which surrounds the ca (dg) on both sides of PMOS. Run aDRC to ensure this.•For the well plug we need to add a contact also, copy and move it into the active of well plus. It should be overlapped by 1λ (0.4u) on each side withactive.4.4.Draw the metal1 rectangles for the Power, which should be 5u in height and atleast 10u length. Place it at the upper side of the inverter.4.5.Stretch the metal1 to touch the power as figure and merge the two metal1.Refer to OpenBook for detail usage of merge.4.6.By now, you have finished the upper part of the transistor, run a DRC to checkit. The complete view should be as following figure:Creating nmos Transistor LayoutYou have just finished the pmos part of the inv. Now, you need to go on finished the nmos part also. The procedure is similar to the pmos one.Step 5Using the same procedure as drawing pmos transistors, draw another nmos transistor and put in below the pmos transistor with some spaces betweenthem. The gate width of nmos transistor should be 11λ (4.4u) as followingfigure.5.1To specify that this transistor is N-type. Draw a nselect (dg) rectangle(instead of the pselect and nwell) around the transistor. Again there shouldbe a 2λ (0.8um) overlap of the active.5.2Similar to well plus to the Pmos transistor, we need to connect p-typesubstrate contact to gnd!. You may want to copy the well plug you created(including the select area)and then change the nselect rectangle to pselectrantangle.Highlight the nselect rectangle and choose Edit - Properties. The editproperties form appear.Notice that one property of the rectangle is its layer, in the Layer field,hold down your mouse button, and choose pselect . Click OK .5.3Finished wiring the nmos transistor as in pmso one and run DRC again toensure that there is no error.Wiring the InverterYou have now finished the two transistors for the inv . The next step is to finished the internal and external connection for the inv .Input connectionStep 6Connect the two transistors’ poly to become the inverter input. To do so,we can stretch either transistor’s poly to touch the other’s one. Refer to thefollowing figure as the guideline.6.1In virtuoso, the two-touched poly will already be considered to be one longpoly. However, you may want to merge them to give better appearance.First click on the poly(dg) box in LSW window, highlight the long poly,then select Edit - Other - Merge . The two rectangles will now becomeone.6.2Create Input terminal (Signal name "A"). For external connection point,we want to using metal2 so that it can be accessed in both upward anddownward direction. Since we can’t connect poly and metal2 directly, weneed to connect poly to metal1 by using cp (dg) first and then connectmetal1 to metal2 by using via (dg)• Draw a 0.8u x 0.8u poly contact in cp (dg). Place it between two transistors.• Draw a poly which overlap cp 0.8u on each sides.4.4ucp(dg)via(dg)Metal1+Metal2+Metal1•Draw a 0.8u x 0.8u via (dg) on the leftside of cp, then place a metal2 (dg)which overlap via 0.4u.•Connecting both via and cp you justcreated by metal1. It should have 0.8uoverlapping to both. Run a DRC toensure this.Output Connection6.3.Create the output node. Draw a rectangle in metal1 (dg) which overlapsthe two metal1 on right side of transistors. Refer to following figure fordetails.6.4Create Output terminalAgain, create an external connection point using metal2 and via at theoutput node.Labeling6.4.Create Power and Ground labels for identification.In LSW, select text (dg).Click on Create - Label.Fill in "vdd!" as the label name, then place it on the top metal1 line asshown in page.Create "gnd!" for the lower metal1 line by the same procedures.6.5.Create labels "A" and "Out" as mentioned above. Refer to the figure forlabel position.6.6.Run a final DRC, and save your design.The complete inverter layout should resemble the following diagram:Setting Layer Visibility using the LSWAfter step 6. You are basically finished the inv layout. However, you may want to check the transistor design in each layer. The layer and Selection Window (LSW) allow you to set particular layers selectable and visible.Step 7.Move the cursor over the cp (dg) layer in the LSW and click the middlemouse button.The middle mouse button toggles layer visibility. It also automatically setsinvisible layers to be unselectable.metal1activeviametal2nwellcontactPowerlabelPNP Transistor NPNTransistor InputTerminalPartname Layer name Figure 1The contact layer colour disappears to show that the layer is invisible, and the layer name turns gray to show that the layer is not selectable.7.1.Select Window - Redraw in the inv window.The inv layout is displayed without contacts, since they are drawn on the cp layer.7.2.Click on the AV (All Visible) button in the LSW.The coloured square showing the contact layer colour reappears, and the shading on the layer name disappears.7.3.Select Window - Redrew in the inv window.The inv layout is re-displayed with cp (dg).You must redraw the window to see the effect of LSW changes. This way you can make several changes before you take the time to redraw a complex design.7.4 Show you layout to T.A7.5.Click on Window - Close, the inv layout will be closed.End of LabAppendix A: Design Rule Check (DRC) DebuggingIf you find that there are lots of error appear, don’t be panics. Virtuoso provides an easy environment to fixe the errors. Most common errors are design rule violations, which can be fixed by checking the CIW window.Step 1.Look at the CIW windows for the errors.2. Look at the Editing window for the corresponding error parts. Here, there are2 errors in contact spacing on same active. The space should be 3λ (1.2u).From the editing windows, the space between two ca (dg) is highlight that should correspond to the error.3 In addition, you can select Verify-markers-find to find the error marker. Pressapplyto get the first error marker and so on.Error typedescriptionSpace rule inλ4Select verify-markers-Explain to check for error explanation. User mouse to click on the error marker that you want it to be explained.5Correct the error and re-run the DRC, make sure your design is correct. Save your design.。

cadence软件基本原理图设计指导培训

cadence软件基本原理图设计指导培训

9、INDUCTOR(电感) 10、MEMORY(存储器) 11、MICROPROCESSOR(微处理器) 12、OPTICAL_TRANSMITTER_MODULE(光传
输模块) 13、OPTOISOLATOR(光电耦合器) 14、POWER(电源模块) 15、RELAY(继电器) 16、RESISTOR(电阻)
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创建proБайду номын сангаасect
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一、Cadence软件介绍 二、原理图设计基本流程 三、典型project的目录结构 四、原理图库相关 五、原理图设计相关(before/after) 六、原理图设计技巧及常见问题解决
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1、PARTCODE--物料号 2、PARTVALUE--器件型号 3、 JEDEC_TYPE--器件封装 4、 $LOCATION--器件位号 5、 GROUP --器件分组属性 6、 DESCRIPTION--器件描述(封装类型/器件
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set_var SG_SPICE_SIMPLIFY true - This setting will put SignalStorm into "SIMPLE" mode for the purposes of inferring logic in your transistor structures. set_var SG_HALF_WIDTH_HOLD_FLAG true
These settings will setup SignalStorm to run its simulation processes on the local machine using LSF (Load Sharing Facility) as opposed to using the distibuted server-farm (cluster) approach.
syn2tlf std_cells.lib -format 4.3 -ir 50 -if 50 -dr 50 -df 50 -sr 10 -sf 10 -tr 90 -tf 90 -slew_measure_lower_rise 20 -slew_measure_lower_fall 20 slew_measure_upper_rise 80 -slew_measure_upper_fall 80 -o std_cells.tlf
Charles Lamech
Page 1
Cadence ELC Tutorial Then generate the extracted netlist from Simulation Netlist Create as shown in the screenshot. Save this netlist file to your working directory with some preferred name (Eg: sLC Configuration file
The configuration file has a set of commands that does some configurations for the ELC. Some of the examples are:
This converts the Liberty file which is the output of the previous step to TLF file which is the cell library specification for Encounter Place & Route tool. Timing Library Format (.tlf) file will have the Timing and power parameters associated with the standard cells. Raise and Fall time delay & Power parameters in table format. Also has some I/O pin details If you open and read the .tlf file, you can understand the rise & fall time and power analysis values. Unfortunately ELC doesn’t give layout area information????
Step 5: Run ELC
Now we can run the ELC with the following command and its parameters:
elc -L test.log -C test_cmd.log -S cmd_file
Runs the ELC tool with the commands in cmd_file, test.log will have execution log test_cmd.log will have command log
Charles Lamech
Page 2
Cadence ELC Tutorial We will also specify the characterization inputs like subcircuit name, model file (this comes with the PDK) and the setup file (which is explained in the next section)
Step 6: Convert Liberty file to Cadence Timing file
Now we can convert the Liberty file to Cadence timing file (.tlf) which will be used by Encounter tool.
Steps for Running Encounter Library Characterizer
Step 1: Create Extracted Netlist
To characterize standard cells we need the extracted views of the standard cells. Let us create a subdirectory for the ELC under cadence working directory. Now create a schematic which contains an instance of all of your cells without connecting them. Then start ADE tool from there. Since we want extracted netlist with parasitics specify the extracted view in Setup Environment as shown in the screenshot below. (It can be extracted/analog_extracted/caliber depends on your simulator)
Step 3: Create ELC Setup file
The setup file defines some setup required for the simulation. It defines the following: Defines the Voltage, Temperature & Vth for typical, best and worst case Defines also Resistance, transient time to simulate etc... Save it with the file name under the ELC subdirectory with the name setup.ss. Please refer the attached setup file.
Cadence ELC Tutorial
Cadence Encounter Library Characterizer – Tutorial
Abstract
This tutorial explains characterizing the Standard Cells using Cadence Encounter Library Characterizer (ELC) tool. It explains the flow of ELC tool which converts extracted version of standard cells to Liberty (.lib) or Cadence Encounter place and route tool’s input file format (.tlf).
set_var SG_SIM_TYPE "spectre" set_var SG_SIM_NAME "spectre"
These settings will setup spectre as the simulation environment as opposed to HSPICE which is used by default. If you're wondering why the default simulator in a Cadence produce is HSPICE (a Synopsys product) rather than Spectre (a Cadence product). Please refer the attached sample configuration file.
Step 4: Create Command file
You can start ELC by typing “elc” and then run it by typing a series of commands to run the simulation or can put those commands in a file called command file and run with a single command. I prefer creating a command file and running with a single command. This file essentially will have the following commands: db_open std_cells Opens the working library db_prepare –f db_spice –s spectre –keep_log This command will launch the simulation processes db_output –lib std_cells.lib – process typical – state saves output in Liberty file format db_close exit
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