AT24C04的原理与应用

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AT24C04的原理与应用

4.2 I2C器件AT24C04的原理与应用I2C(Inter－Integrated Circuit)总线是一种由PHILIPS公司开发的两线式串行总线，用于连接微控制器及其外围设备。

I2C总线产生于上世纪80年代，最初为音频和视频设备开发，如今主要在服务器管理中使用，其中包括单个组件状态的通信。

I2C总线最主要的优点是其简单性和有效性。

由于接口直接在组件之上，因此I2C 总线占用的空间非常小，减少了电路板的空间和芯片管脚的数量，降低了互联成本。

总线的长度可高达25英尺，并且能够以10Kbps的最大传输速率支持40个组件。

I2C总线的另一个优点是，它支持多主控(multimastering)，其中任何能够进行发送和接收的设备都可以成为主总线。

一个主控能够控制信号的传输和时钟频率。

当然，在任何时间点上只能有一个主控。

4.2.21 I2C总线的构成和信号类型一、I2C总线的构成I2C总线是由数据线SDA和时钟SCL构成的串行总线，可发送和接收数据。

在CPU 与被控IC之间、IC与IC之间进行双向传送，最高传送速率100kbps，采用7位寻址，但是由于数据传输速率和应用功能的迅速增加，I2C总线也增强为快速模式（400Kbits/s）和10位寻址以满足更高速度和更大寻址空间的需求。

各种被控制电路均并联在这条总线上，但就像电话机一样只有拨通各自的号码才能工作，所以每个电路和模块都有唯一的地址。

在信息的传输过程中，I2C总线上并接的每一模块电路既是主控器（或被控器），又是发送器（或接收器），这取决于它所要完成的功能。

CPU发出的控制信号分为地址码和控制量两部分，地址码用来选址，即接通需要控制的电路，确定控制的种类；控制量决定该调整的类别（如对比度、亮度等）及需要调整的量。

这样，各控制电路虽然挂在同一条总线上，却彼此独立，互不相关。

二、I2C总线的信号类型I2C总线在传送数据过程中共有三种类型信号，它们分别是：起始信号、终止信号和应答信号。

铁电存储器FM24C04原理及应用

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AT24C04的原理与应用

4.2 I2C器件AT24C04的原理与应用I2C(Inter－Integrated Circuit)总线是一种由PHILIPS公司开发的两线式串行总线，用于连接微控制器及其外围设备。

I2C总线产生于上世纪80年代，最初为音频和视频设备开发，如今主要在服务器管理中使用，其中包括单个组件状态的通信。

I2C总线最主要的优点是其简单性和有效性。

由于接口直接在组件之上，因此I2C 总线占用的空间非常小，减少了电路板的空间和芯片管脚的数量，降低了互联成本。

总线的长度可高达25英尺，并且能够以10Kbps的最大传输速率支持40个组件。

I2C总线的另一个优点是，它支持多主控(multimastering)，其中任何能够进行发送和接收的设备都可以成为主总线。

一个主控能够控制信号的传输和时钟频率。

当然，在任何时间点上只能有一个主控。

4.2.21 I2C总线的构成和信号类型一、I2C总线的构成I2C总线是由数据线SDA和时钟SCL构成的串行总线，可发送和接收数据。

各种被控制电路均并联在这条总线上，但就像电话机一样只有拨通各自的号码才能工作，所以每个电路和模块都有唯一的地址。

在信息的传输过程中，I2C总线上并接的每一模块电路既是主控器（或被控器），又是发送器（或接收器），这取决于它所要完成的功能。

这样，各控制电路虽然挂在同一条总线上，却彼此独立，互不相关。

二、I2C总线的信号类型I2C总线在传送数据过程中共有三种类型信号，它们分别是：起始信号、终止信号和应答信号。

24C04中文资料

24C02串行E2PROM的读写I2C总线是一种用于IC器件之间连接的二线制总线。

它通过SDA（串行数据线）及SCL（串行时钟线)两根线在连到总线上的器件之间传送信息，并根据地址识别每个器件：不管是单片机、存储器、LCD驱动器还是键盘接口。

1．I2C总线的基本结构采用I2C总线标准的单片机或IC器件，其内部不仅有I2C接口电路，而且将内部各单元电路按功能划分为若干相对独立的模块，通过软件寻址实现片选，减少了器件片选线的连接。

CPU不仅能通过指令将某个功能单元电路挂靠或摘离总线，还可对该单元的工作状况进行检测，从而实现对硬件系统的既简单又灵活的扩展与控制。

I2C总线接口电路结构如图1所示。

2．双向传输的接口特性传统的单片机串行接口的发送和接收一般都各用一条线，如MCS51系列的TXD和RXD，而I2C 总线则根据器件的功能通过软件程序使其可工作于发送或接收方式。

当某个器件向总线上发送信息时，它就是发送器(也叫主器件)，而当其从总线上接收信息时，又成为接收器(也叫从器件)。

主器件用于启动总线上传送数据并产生时钟以开放传送的器件，此时任何被寻址的器件均被认为是从器件。

I2C总线的控制完全由挂接在总线上的主器件送出的地址和数据决定。

在总线上，既没有中心机，也没有优先机。

总线上主和从(即发送和接收)的关系不是一成不变的，而是取决于此时数据传送的方向。

SDA和SCL均为双向I/O线，通过上拉电阻接正电源。

当总线空闲时，两根线都是高电平。

连接总线的器件的输出级必须是集电极或漏极开路，以具有线“与”功能。

I2C总线的数据传送速率在标准工作方式下为100kbit/s，在快速方式下，最高传送速率可达400kbit/s。

3．I2C总线上的时钟信号在I2C总线上传送信息时的时钟同步信号是由挂接在SCL时钟线上的所有器件的逻辑“与”完成的。

SCL线上由高电平到低电平的跳变将影响到这些器件，一旦某个器件的时钟信号下跳为低电平，将使SCL线一直保持低电平，使SCL线上的所有器件开始低电平期。

I2C之AT24C04总结

I2C之AT24C04总结济南职业学院电子工程系朱志强1、AT24C04介绍2、AT24C04之准备工作3、AT24C04之小试牛刀4、对应源程序2010年7月28日1、AT24C04介绍关于I2C的介绍，这里就不用说了，直接介绍24C04了。

24C04是4K位串行CMOS E2PROM。

引脚的认识：SCL 串行时钟引脚SDA 串行数据/地址A0、A1、A2 器件地址输入端WP 写保护（WP 管脚连接到Vcc，所有的内容都被写保护（只能读）。

当WP 管脚连接到Vss 或悬空，允许器件进行正常的读/写操作。

）2、AT24C04之准备工作首先，我们先查看一下实验板上面的接线图。

如图1所示。

图1 24c04连接图我们要注意的第一点是器件地址全部是0，即接地处理。

第二点是读写保护WP接地，意味着我们可以随意存取。

第三点是我们要用到的引脚连接到了P3^6和P3^7上。

在这里还要提醒一下，就是引脚上一定要有上拉电阻！阻值在470~1k 都可以的，具体的数值可以参考相关的手册。

在程序里我们需要先做以下定义：sbit AT24C04_SCL=P3^7;sbit AT24C04_SDA=P3^6;在写这个程序的时候，要使用到键盘，不用太多按键，我们暂时只用四个。

把实验板上面的跳线JP8接到“-”端上，使第一行的按键变为独立键盘就可以了。

线路图如图2所示。

图2 键盘部分电路图键盘这部分我就不说了吧，直接附上我用到的这部分程序，在我的程序中，并没有判断按键是否松开，而是使用的延时，这样的好处是一直按着按键，数据会一直在变化，要不然，频繁的按真的很累人。

转到按键程序对于里面用到的延时函数，一个是US级延时函数，一个是ms级延时函数，分别调用一下是延时2us和1ms。

对于显示部分吧，使用的就是LCD1602显示了。

这部分程序参见这里。

显示程序说完了这些，准备的就差不多了，我们可以对着PDF写AT24C04程序了。

3、AT24C04之小试牛刀我们打破PDF中的介绍顺序，按照实际写程序时的顺序分开分析。

单片机学习项目 (11) I2C总线器件AT24C04及其应用

单片机学习项目项目11-I2C总线器件AT24C04及其应用一：电路原理电路在LED流水灯电路基础上设计，单片机的P2.6连接AT24C04的SDA端口，P3.7连接SCL，为保证数据传输正确，端口接上拉电阻。

电路见5-8所示。

二：程序设计主程序调用AT24C04子程序，在程序运行之前，需对AT24C04初始化。

程序清单如下：/*预处理*/#include<reg51.h>#include”AT24C04.c” //主程序包含AT24C04子程序/*延时函数*/void delay(unsigned int x){while(x--);}/*主函数*/void main(void){init_24c04();while(1){write_add_dat_24c04(1,0x0f); //地址1保存数据0x0fdelay(300);write_add_dat_24c04(2,0xf0); //地址2保存数据0xf0delay(300);P0 = read_add_dat_24c04(1); //读地址1保存数据0x0f，并在P0口显示 delay(50000);P0 = read_add_dat_24c04(2); //读地址2保存数据0xf0，并在P0口显示 delay(50000);}}/*结束*/三、24C04驱动#include<intrins.h>#define uchar unsigned char#define nop _nop_()sbit sda = P1^7;sbit scl = P1^1;/*I2C总线启动*/void start_24c04(void){sda = 1;nop;scl = 1;nop;sda = 0;nop;scl = 0;}/*I2C总线停止*/void stop_24c04(void){sda = 0;nop;scl = 1;nop;sda = 1;nop;}/*应答程序*/void ack_24c04(void){uchar i = 255;scl = 1;nop;while(sda && i--);scl = 0;nop;}/*I2C总线初始化*/void init_24c04(void)//该函数可以省去{sda = 1;nop;//常态scl = 0;nop;//常态}/*读取一个字节*/uchar read_onebyte_24c04(void){uchar i,dat;sda = 1; // 释放总线for(i = 0;i < 8;i++){scl = 1;dat = dat << 1;if(sda)dat = dat | 0x01;//先读取数据的高位，放到dat的低位 scl = 0;}sda = 1;scl = 0;return(dat);}/*写入一个字节*/void write_onebyte_24c04(uchar dat){uchar i;for(i = 0;i < 8;i++){sda = (bit)(dat & 0x80);//先发送数据的高位dat = dat << 1;scl = 1;scl = 0;}sda = 1;scl = 0;}/*对某个地址写一个字节的数据*/void write_add_dat_24c04(uchar add,uchar dat){start_24c04();write_onebyte_24c04(0xa0);ack_24c04();write_onebyte_24c04(add);ack_24c04();write_onebyte_24c04(dat);ack_24c04();stop_24c04();}/*读取某个地址一个字节的数据*/uchar read_add_dat_24c04(uchar add){uchar dat;start_24c04();write_onebyte_24c04(0xa0);ack_24c04();write_onebyte_24c04(add);ack_24c04();start_24c04();write_onebyte_24c04(0xa1);ack_24c04();dat = read_onebyte_24c04();stop_24c04();return(dat);}/*结束*/四、仿真运行本例程序Proteus仿真结果见图5-9所示，图中LED连接采用网络标号。

24c04的使用说明

24c04的使用说明1．引脚(见: 硬件接法)读写命令1 0 1 0 A2 A1 A0 R\w “1001”是AT24cxx 类型识别符(着种芯片的地址)A2 A1 A0 挂在总线上不同芯片的地址（片选）W/R 0写;1 读2．引脚说明：A0~A2: 芯片的地址SCL：时钟信号线用于产生器件所有数据发送或接收的时钟在写方式,SCL为高电平时, 数据必须保持稳定.且下降沿送数.SDA：数据信号线用于传送地址和所有数据的发送和接受仅仅在SCL为低时数据才可以改变;WP：写保护接+5V时只能读;接GND时即能写也能读;3．时序开始信号SCL为高电平时，SDA由高变底停止信号SCL为高电平时，SDA由低变高应答信号接收数据的IC在接到第8BIT后(“写”)，发出特定的低电平脉冲,表示受到数据操作步骤：(1)”写”启动总线(I方C)—发送器件寻址字节—应答—发送数据寻址地址—回答—发送第一个数据—应答--………….发送第N个数据—应答—停止总线; 写地址可以指定第一个数据地址后连续送数。

“写”分为字节写和页写两种方式.(2)”读”所有的操作几乎一样.只是在读完8位数据以后,.从设备不是发出ACK(低电平),而是直接给SETB SDA ,然后发出停止总线信号即可结束本次读.读也分为当前地址读随机读和顺序读.硬件接法P1.0 接scl(6脚);p1.1接sda(5脚);4脚为GND;8脚为VCC;剩下的A2(3脚)A1(2脚) A0(1脚),T通过接VCC或GND以确定硬件的地址.功能：显示60H~63H中的数显示24c04(60h~63h)读到单片机60h~63h中显示。

代码VSDA BIT P1.0VSCL BIT P1.1org 0000hmov 60h,#00hmov 61h,#00hmov 62h,#00hmov 63h,#00hstart: LCALL DISPLAYLCALL DLE1mov 60h,#01hmov 61h,#02hmov 62h,#03hmov 63h,#04hlcall writelcall delcall readlcall display;############# 问题asd: ajmp asd;#############ajmp startSTA: SETB VSDA SETB VSCLNOPnopnopnopCLR VSDANOPclr vsdanopnopnopnopCLR VSCLRETSTOP: clr vsda setb vsclnopnopsetb vsdaRETWRBYT: MOV 17h,#08H;上升沿WLP: RLC AJC WR1AJMP WR0WLP1: DJNZ 17h,WLP NOPNOPSETB VSCLNN: MOV C,VSDAJC NNCLR VSCL;call deRETWR1: setb vsdasetb vsclNOPNOPnopnopclr VSCLclr vsdaAJMP WLP1WR0: CLR vsdasetb vsclNOPNOPnopnopclr vsclAJMP WLP1rdbyt : mov 10h,#08h rlp: setb vsda setb vsclmov c,vsdarlc aclr vscldjnz 10h,rlpnopsetb vsdanopnopsetb vsclretWRITE: mov 15h,#4 mov 16h,#50hmov r0,#60hlcall stamov a,#0a0hlcall wrbytmov a,16hlcall wrbytwda: mov a,@r0lcall wrbyt;lcall deinc r0djnz 15h,wdalcall stopretread: mov 15h,#4mov 16h,#50hmov r0,#60hok: lcall stamov a,#0a0hlcall wrbytmov a,16hlcall wrbytlcall stamov a,#0a1hlcall wrbytnoplcall rdbytlcall stopmov @r0,ainc r0inc 16hdjnz 15h,okretmack: clr vsdasetb vsclnopnopclr vsclsetb vsdaretmnack: setb vsdasetb vsclnopnopclr vsdaclr vsclretdisplay:mov dptr,#tab1 mov a,60h;4movc a,@a+dptrmov 13h,amov dptr,#tab1mov a,61h;3movc a,@a+dptrmov 12h,amov dptr,#tab1mov a,62h;2movc a,@a+dptrmov 11h,amov dptr,#tab1mov a,63h;高movc a,@a+dptrmov 10h,aACALL DISPRETdisp: clr p1.5clr p1.4MOV 16H,#4mov r1,#13hdir1x:acall shift;senddata dec r1djnz 16H,dir1xsetb p1.5;first finishnopNOPclr p1.5RETshift: mov a,@r1;mov 15H,#08hacall ywRETyw: RRC AMOV P1.3,CSETB P1.4NOPNOPNOPCLR P1.4DJNZ 15H,ywMOV 15H,#08HRETtab1: db 0fch,60h,0dah,0f2h,66h,0b6h,0beh,0e0h,0feh,0f6h DE: MOV 40H,#08HDE3: MOV 41H,#0a0HDE2: MOV 42H,#01HDE1: DJNZ 42H,DE1DJNZ 41H,DE2dJNZ 40H,DE3RETDLE1: MOV 40H,#08HDE31: MOV 41H,#0FFHDE21: MOV 42H,#0FFHDE11: DJNZ 42H,DE11DJNZ 41H,DE21dJNZ 40H,DE31RETEND。

EEPROM---AT24Cxx应用介绍

EEPROM---AT24Cxx应⽤介绍结论：1、读写AT24CXX芯⽚，根据容量有多种⽅式：⼀、容量为AT24C01~AT24C16，⾸先发送设备地址（8位地址），再发送数据地址（8位地址），再发送或者接受数据。

⼆、AT24C32/AT24C64~AT24C512，⾸先发送设备地址（8位地址），再发送⾼位数据地址，再发送地位数据地址，再发送或者接受数据。

三、容量AT24C1024的芯⽚,是把容量⼀和容量⼆的⽅法结合，设备地址中要⽤⼀位作为数据地址位，存储地址长度是17位。

2、它的设备地址根据容量不同有区别： 1）、AT24C01~AT24C16：这⼀类⼜分为两类，分别为AT24C01/AT24C02和AT24C04~AT24C16;他们的设备地址为⾼7位，低1位⽤来作为读写标⽰位，1为读，0为写。

*1*、AT24C01/AT24C02。

AT24C01/AT24C02的A0、A1、A2引脚作为7位设备地址的低三位，⾼4为固定为1010B，低三位A0、A1、A2确定了AT24CXX的设备地址，所以⼀根I2C线上最⼤可以接8个AT24CXX，地址为1010000B~1010111B。

*2*、AT24C04~AT24C16的 A0、A1、A2只使⽤⼀部分，不⽤的悬空或者接地（数据⼿册中写的是悬空不接）。

举例：AT24C04只⽤A2、A1引脚作为设备地址，另外⼀位A0不⽤悬空，发送地址中对应的这位（A0）⽤来写⼊页寻址的页⾯号,⼀根I2C线上最⼤可以接4个，地址为101000xB~101011xB 2）、AT24C32/AT24C64:和AT24C01/AT24C02⼀样，区别是，发送数据地址变成16位。

注意事项：对AT24C32来说，WP置⾼，则只有四分之⼀受保护，即0x0C00－0x0FFF。

也就是说保护区为1KBytes。

对于低地址的四分之三，则不保护。

所以，如果数据较多时，可以有选择地存储。

ATMEL AT24C04的官方PDF资料

1Features•Write Protect Pin for Hardware Data Protection –Utilizes Different Array Protection Compared to the AT24C02/04•Low-voltage and Standard-voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Internally Organized 256 x 8 (2K), 512 x 8 (4K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•100 kHz (1.8V) and 400 kHz (2.5V , 2.7V , 5V) Clock Rate •8-byte Page (2K), 16-byte Page (4K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms Max)•High Reliability–Endurance: One Million Write Cycles –Data Retention: 100 Years•Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free Devices Available•8-lead PDIP , 8-lead JEDEC SOIC, 8-lead MAP , 8-lead TSSOP and 8-ball dBGA2 Packages •Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers.DescriptionThe AT24C02A/04A provides 2048/4096 bits of serial electrically erasable and program-mable read-only memory (EEPROM) organized as 256/512 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C02A/04A is available in space-saving 8-lead PDIP , 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP pack-ages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.Table 1. Pin ConfigurationPin Name Function A0–A2Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NCNo-connect2AT24C02A/04A0976Q–SEEPR–8/05Figure 1. Block DiagramPin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under Device Addressing, page 8).Absolute Maximum Ratings*Operating T emperature ........................................−40°C to +85°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature .........................................−65°C to +150°C Voltage on Any Pinwith Respect to Ground ........................................−1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C02A/04A0976Q–SEEPR–8/05The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no-connect.WRITE PROTECT (WP): The AT24C02A/04A have a WP pin that provides hardware data protection. The WP pin allows normal read/write operations when connected to ground (GND). When the WP pin is connected to V CC , the write protection feature is enabled and operates as shown.Table 2. Write ProtectMemory OrganizationAT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8bytes each. Random word addressing requires an 8-bit data word address.AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16bytes each. Random word addressing requires a 9-bit data word address.Note:1.This parameter is characterized and is not 100% tested.WP Pin Status Part of the Array Protected24C02A 24C04A At V CC Upper Half (1K) ArrayUpper Half (2K) ArrayAt GNDNormal Read/Write OperationsTable 3. Pin Capacitance (1)Applicable over recommended operating range from T AI = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0V4AT24C02A/04A0976Q–SEEPR–8/05Note:1.V IL min and V IH max are reference only and are not tested.Table 4. DC CharacteristicsApplicable over recommended operating range from: T AI = −40°C to +85°C, V CC = +1.8V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.5 5.5V V CC 3Supply Voltage 2.7 5.5V V CC4Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.03.0mA I SB1Standby Current V CC = 1.8V V IN = V CC or V SS 0.63.0µA I SB2Standby Current V CC = 2.5V V IN = V CC or V SS 1.4 4.0µA I SB 3Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB4Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.103.0µA I LO Output Leakage Current V OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)−0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V5AT24C02A/04A0976Q–SEEPR–8/05Note:1.This parameter is characterized and is not 100% tested.Table 5. AC CharacteristicsApplicable over recommended operating range from T AI = −40°C to +85°C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and 100pF (unless otherwise noted)Symbol Parameter1.8-volt2.5, 2.7, 5.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 100400kHz t LOW Clock Pulse Width Low 4.7 1.2µs t HIGH Clock Pulse Width High 4.00.6µs t I Noise Suppression Time (2)10050ns t AA Clock Low to Data Out Valid 0.1 4.50.10.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.7 1.2µs t HD.ST A Start Hold Time 4.00.6µs t SU.ST A Start Set-up Time 4.70.6µs t HD.DA T Data In Hold Time 00µs t SU.DAT Data In Set-up Time 200100ns t R Inputs Rise Time (1) 1.00.3µs t F Inputs Fall Time (1)300300ns t SU.STO Stop Set-up Time 4.70.6µs t DH Data Out Hold Time 10050ns t WRWrite Cycle Time 55ms Endurance (1) 5.0V , 25°C, Page Mode1M 1MWrite Cycles6AT24C02A/04A0976Q–SEEPR–8/05Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below.Figure 2. Data ValiditySTART CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 3).Figure 3. Start and Stop DefinitionSTOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.. The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode that is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the com-pletion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles2.Look for SDA high in each cycle while SCL is high3.Create a start condition as SDA is high.7AT24C02A/04A0976Q–SEEPR–8/05Figure 4. Bus TimingFigure 5. Write Cycle TimingNotes:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.8AT24C02A/04A0976Q–SEEPR–8/05Device AddressingThe 2K and 4K EEPROM devices require an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in Figure 7.Figure 7. Device AddressThe device address word consists of a mandatory “1”, “0” sequence for the first fourmost significant bits as shown. This is common to all the EEPROM devices.The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM.These three bits must compare to their corresponding hardwired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hardwired input pins. The A0 pin is no-connect.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high, and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time,the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete, see Figure 8 on page 8.Figure 8. Byte WritePAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K device is capable of 16-byte page writes.9AT24C02A/04A0976Q–SEEPR–8/05A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K) more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition, see Figure 9.Figure 9. Page WriteThe data word address lower three (2K) or four (4K) bits are internally incremented fol-lowing the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, inter-nally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K) data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0” allowing the read or write sequence to continue.10AT24C02A/04A0976Q–SEEPR–8/05Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input “0” but does generate a following stop condition, see Figure 10.Figure 10. Current Address ReadRANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition, see Figure 11.Figure 11. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-11AT24C02A/04A0976Q–SEEPR–8/05tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition,see Figure 12.Figure 12.Sequential Read12AT24C02A/04A0976Q–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C02A Ordering Information (1)Ordering Code Package Operation Range A T24C02A-10PI-2.7A T24C02AN-10SI-2.7A T24C02A-10TI-2.78P 38S18A2Industrial T emperature (−40°C to 85°C)A T24C02A-10PI-1.8A T24C02AN-10SI-1.8A T24C02A-10TI-1.88P 38S18A2Industrial T emperature (−40°C to 85°C)A T24C02A-10PU-2.7(2)A T24C02A-10PU-1.8(2)A T24C02AN-10SU-2.7(2)A T24C02AN-10SU-1.8(2)A T24C02A-10TU-2.7(2)A T24C02A-10TU-1.8(2)A T24C02AY1-10YU-1.8(2)A T24C02AU 3-10UU-1.8(2)8P 38P 38S18S18A28A28Y18U 3-1Lead-free/Halogen-free/Industrial T emperature (−40°C to 85°C)A T24C02A-W2.7-11(3)A T24C02A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8U3-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)13AT24C02A/04A0976Q–SEEPR–8/05Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C04A Ordering Information (1)Ordering Code Package Operation Range A T24C04A-10PI-2.7A T24C04AN-10SI-2.7A T24C04A-10TI-2.78P 38S18A2Industrial T emperature (−40°C to 85°C)A T24C04A-10PI-1.8A T24C04AN-10SI-1.8A T24C04A-10TI-1.88P 38S18A2Industrial T emperature (−40°C to 85°C)A T24C04A-10PU-2.7(2)A T24C04A-10PU-1.8(2)A T24C04AN-10SU-2.7(2)A T24C04AN-10SU-1.8(2)A T24C04A-10TU-2.7(2)A T24C04A-10TU-1.8(2)A T24C04AY1-10YU-1.8(2)A T24C04AU 3-10UU-1.8(2)8P 38P 38S18S18A28A28Y18U 3-1Lead-free/Halogen-free/Industrial T emperature (−40°C to 85°C)A T24C04A-W2.7-11(3)A T24C04A-W1.8-11(3)Die Sale Die SaleIndustrial T emperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8U3-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)14AT24C02A/04A0976Q–SEEPR–8/05Packaging Information8P3 – PDIP15AT24C02A/04A0976Q–SEEPR–8/058S1 – JEDEC SOIC16AT24C02A/04A0976Q–SEEPR–8/058A2 – TSSOP17AT24C02A/04A0976Q–SEEPR–8/058U3-1 – dBGA218AT24C02A/04A0976Q–SEEPR–8/058Y1 – MAP19AT24C02A/04A0976Q–SEEPR–8/05Y5 – MAP0976Q–SEEPR–8/05Disclaimer: The information in this document is provided in connection with Atmel products. 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AT24C1024介绍

AT24C1024介绍AT24C10242 线串⾏EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8 位=1M2 线串⾏接⼝施密特触发器，噪声抑制滤波输⼊双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V) 硬件写保护引脚和软件数据保护256 字节页写模式(允许部分页⾯写⼊)随机和顺序读写模式⾃定义写周期(5ms)⾼可靠性：耐久⼒：写周期/页100,000 次数据保留：40 年8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装描述AT24C1024 提供1,048,567 位的串⾏可电擦除和可编程只读存储器（EEPROM），它的每8 位组成⼀个字节，共131,072 个字节。

该设备的级联功能允许多达2 个设备共亨同⼀条2- 线总线。

该设备适合⽤于许多⼯业和商业，应⽤必要的低功耗和低电压的操作。

该器件可提供节省空间的8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装。

另外，这⼀系列产品允许在2.7V（2.7V~5.5V）下⼯作。

绝对最⼤额定值：⼯作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最⼤⼯作电压：6.25V 直流输出电流：5.0mA注意：强制⾼出“绝对最⼤额定值”可能导致设备的永久损坏。

设备的压⼒等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。

长时间⼯作在绝对最⼤额定值的条件下可能影响设备的可靠性。

引脚描述：串⾏时钟（SCL）：SCL 的输⼊是在时钟的上升沿数据进⼊每个EEPROM 设备和下降沿数据输出每个设备。

串⾏数据（SDA）：SDA 引脚是双向串⾏数据传输的。

这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。

器件/ 页地址（A1 ）：A1 引脚是设备的输⼊地址，它能够通过导线与不兼容的设备AT24C128/256/512 连接。

I2C之AT24C04总结

I2C之A T24C04总结-标准化文件发布号：（9556-EUATWK-MWUB-WUNN-INNUL-DDQTY-KIII2C之AT24C04总结济南职业学院电子工程系朱志强1、AT24C04介绍2、AT24C04之准备工作3、AT24C04之小试牛刀4、对应源程序2010年7月28日1、AT24C04介绍关于I2C的介绍，这里就不用说了，直接介绍24C04了。

24C04是4K位串行CMOS E2PROM。

引脚的认识：SCL 串行时钟引脚SDA 串行数据/地址A0、 A1、 A2 器件地址输入端WP 写保护（WP 管脚连接到Vcc，所有的内容都被写保护（只能读）。

当WP 管脚连接到Vss 或悬空，允许器件进行正常的读/写操作。

）2、AT24C04之准备工作首先，我们先查看一下实验板上面的接线图。

如图1所示。

图1 24c04连接图我们要注意的第一点是器件地址全部是0，即接地处理。

第二点是读写保护WP接地，意味着我们可以随意存取。

第三点是我们要用到的引脚连接到了P3^6和P3^7上。

在这里还要提醒一下，就是引脚上一定要有上拉电阻！阻值在470~1k都可以的，具体的数值可以参考相关的手册。

在程序里我们需要先做以下定义：sbit AT24C04_SCL=P3^7;sbit AT24C04_SDA=P3^6;在写这个程序的时候，要使用到键盘，不用太多按键，我们暂时只用四个。

把实验板上面的跳线JP8接到“-”端上，使第一行的按键变为独立键盘就可以了。

线路图如图2所示。

转到按键程序对于里面用到的延时函数，一个是US级延时函数，一个是ms级延时函数，分别调用一下是延时2us和1ms。

对于显示部分吧，使用的就是LCD1602显示了。

ARM嵌入式系统应用技术笔记—基于LPC2400(上册)

第1章SmartARM2400工控开发平台1.1 功能特点1.2 硬件电路分析1.2.1 电路原理图SmartARM2400工控开发平台的核心板电路原理图和底板电路原理图见产品光盘“SmartARM2400开发板硬件参考资料\开发板原理图”内。

1.2.2 核心板原理图说明1．核心板电源电路2．看门狗复位电路由于ARM芯片的高速、低功耗、低工作电压等特性导致其噪声容限低，对电源的纹波、瞬态响应性能、时钟源的稳定性、电源监控可靠性等诸多方面也提出了更高的要求。

核心板上使用了专用微处理器电源监控芯片SP706S以提高系统的可靠性，同时该芯片还带有硬件看门狗电路。

如图1.1所示，在电路中已经将看门狗复位信号输出脚（WDO）通过R47连接到 SP706S 的手动复位输入脚（MR）上，信号RST连接到CPU的复位脚RESET。

CPU通过定时翻转P3.22脚电平来喂狗，一旦CPU在1.6秒内未翻转P3.22的电平，则SP706S内部的看门狗溢出，WDO脚输出低电平，MR脚被WDO脚拉低为低电平，导致SP706S 在RST脚输出200ms的复位脉冲令CPU复位，同时SP706S内部清零看门狗让其重新计数。

图1.1 系统复位和ISP电路注：喂狗信号引脚为P3.22。

信号SYS_RST被连接到核心板CON2接口的第48脚上，此管脚连接到底板上的系统复位按键（RST键）上。

当复位按键RST按下时，SP706S的RST脚输出低电平复位系统。

注：若CPU未在1.6秒内喂狗一次，则看门狗将会溢出导致CPU复位，从而中止程序调试或者ISP过程。

因此在程序调试阶段和ISP阶段，用户应该将R47焊掉，断开WDO与MR之间的连接。

看门狗功能是预留功能，因此SmartARM2400的核心板上的R47出厂时是没有焊接的，看门狗不起复位作用。

若用户需要使用看门狗溢出复位功能，则需要自行焊接R47（该器件在核心板的正面）。

3．时钟系统、RTC时钟电路4．JTAG接口电路采用ARM公司提出的标准20脚JTAG仿真调试接口，JTAG信号的定义及与LPC2400系列ARM的连接如图1.2所示。

串行E~2PROM-AT24CXX的原理及应用

串行E~2PROM-AT24CXX的原理及应用预览说明:预览图片所展示的格式为文档的源格式展示,下载源文件没有水印,内容可编辑和复制- 42 -●新特器件应用《国外电子元器件》1997 年第 8 期 1997 年 8 月串行 E 2P RO M A T24CXX 的原理及应用孔令成王华摘要 : 本文分析了美国爱特梅尔 (A TM EL ) 公司生产的最新二线式串行 CMO SE 2PROM 芯片 A T24C01/ 02/ 04/ 08/ 16 的内部结构、性能特点、读写时序 ,并说明了使用方法。

关键词 : E 2PROM 串行读写地址数据如图 1 所示 ,各管脚功能如表 1 所示 ,内部结1 、引言串行 E 2PROM 芯片 A T24C01/ 02/ 04/ 08/ 16 是美国爱特梅尔 (A TM EL ) 公司最新生产的二线式串行 IC 卡芯片 , 小巧 , 可靠性高 ,具有保护性能 ,速度快 ,安全稳定 ,因此在设计 IC 卡等领域中得到了广泛的应用。

2 、A T24CXX 性能特点A T24CXX 系列芯片主要有 A T24C01 ,A T24C02 , A T24C04 , A T24C08 , A T24C16 等型号 ,其区别主要是容量不同 ,分别为 1k , 2k , 4k , 8k 和 16k 比特。

其内部组合分别为128 ×8 位、256 ×8 位、512 ×8 位、1024 ×8 位和2048 ×8 位 ,并允许部分页面写入功能。

并有多种工作电压可供不同用户选择。

它采用低功耗、高速度和高密度 CMO S 工艺 , 可擦写 10 万次以上 , 数据保存 100 年有效 , 为双线串行接口。

存储在芯片中的数据 , 可通过软件的方法利用各种加密算法进行处理 , 从而确保其安全性。

芯片引脚和外形封装形式表 1 管脚功能表管脚功能构框图如图 2 所示。

24c04a中文介绍

24c04a资料一、概述1.1 特征•低功率CMOS技术•硬件写保护* 两线串行接口总线，与I2CTM兼容•5V电源条件下，系统正常工作•自定时写周期（包括自动擦除）•自定时写周期（包含自动擦除）•16个字节的页面写缓冲器•1,000,000擦/写周期（典型值）•8脚DIP/SOIC封装•提供很宽的温度适用范围商用：0℃~+70℃工业用：-40℃~+85℃汽车：-40℃~+125℃2.1描述Microchip公司的24c04a是4K位可擦除PROM。

芯片由2个或4个256*8位存储器块构成，并具有标准的两线串行接口。

可在电源电压低到2.5V的条件下工作，等待电流和额定电流分别仅为5uA和1mA。

24c04a具有8B页面写能力。

的24c04a已经一4页写能力高到八字节，和了到四24c04a设备也许连接到相同的两线总线。

2.2 引脚排列引脚说明1.SDA串行地址/数据输入/输出端这是一个双向传输端，用于传送地址和数据进入器件或从器件发出数据。

它是一个漏极开路端，因此要求接一个上拉电阻到Vcc端（典型值如下：100kHz时为10KΩ，400kHz 时为1KΩ）这对一般的数据传输，只有在SCL为低电平期间，SDA才允许变化。

在SCL为高电平期间SDA的变化，留给指示开始和停止条件。

2. SCL串行时钟端次输入端用于同步传输进入和发出器件的数据3. WP端此端必须接到Vss或者Vcc如果此端接到Vss，一般存储器操作使能（读/写整个存储器）如果此端接到Vcc，写操作禁止。

整个存储器是写保护的。

读操作不受到影响。

当WP被使能（连接到Vcc），允许用户可将24c04a用作串行ROM4.A0、A1、A2端这些端没有被24c04a使用。

它们可以不用连接，或者连接到Vss、Vcc2.3电子特性Vcc——————————————————7.0V输入和输出关于VSS———-0.6V ~ VCC + 1.0V存储温度———————————-65℃~ + 150℃使用环境温度—————————-65℃~ +1 25℃焊接口通导温度————————————+300℃引脚的ESD保护————————————4kV 名称功能A0A1、A2 Vss SDA SCL WP Vcc 不工作（必须与Vcc、Vss连接）芯片地址输入接地串行地址/数据I\O串行时钟写保护输入端+5V电源端三、功能说明24c04a支持双向两线总线和数据传输规程。

AT4(CC04)-四线模拟载波中继板

1
C&C08 数字程控交换系统单板手册
AT4
载波中继信令采用 2600Hz 脉冲方式。AT4 板的 2600Hz 信号的发送和接收由数字信号处理器（DSP）完成，不同的线路信令由不同的单频脉冲组合构成，如“占用”：发 2600Hz 持续 150ms；“重复拆线”：发 150ms，断 300ms，再发 600ms。
发送线路信令由单片机控制编译码电路切割信号形成；接收时，单片机定时读取数字信号处理器的处理结果，对数字信号处理器上报的结果进行时间处理，即可知道从线路上收到何种线路信令，并通过上行口上报主机。在某些专网中，还采用单频脉冲收发方式。所以，AT4 还具有脉冲收发码的功能，以适用于专网。
编译码器完成模拟信号与数字信号之间的转换。
四线载波中继板主要功能如下：
(1) 完成四线载波中继线上带内单频脉冲信令的发送与接收。 (2) 完成外部模拟信号与交换机内部 PCM 数字信号的转换。 (3) 通过串行口接收主机命令，上报状态。 (4) 配合测量台完成载波中继内、外线测试。 (5) 提供 8 路 4 线载波中继接口。四线载波中继板原理如图 1所示：
四线载波中继板原理如图1所示保护保护测试测试隔离隔离编解码器数器dsp控路abcd内测外测uhwdhw至图1cc04at4单板原理框图外线经保护电路进入模拟载波中继保护电路主要由压敏电阻和热敏电阻构成用于防止外线雷击等异常电压电流进入交换机
C&C08 数字程控交换系统单板手册
目录
目录
CC04AT4 四线模拟载波中继板 .................................................................................................. 1 功能及原理 .................................................................................................................................. 1 面板及指示灯说明 ....................................................................................................................... 2 开关及跳线说明........................................................................................................................... 4 外部配线...................................................................................................................................... 4

常用EEPROM存储器

常用EEPROM存储器电路EEPROM存储器AT24C01低压和标准电压工作(Vcc=1.8V—5.5V)，128x8（1k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。

Bi方向传输协议，100kHz （1.8V,2.5V,2.7V）和400kHz（5V）兼容传输速率。

，硬件数据写保护引脚，8位页写模式，允许局部页写操作，器件内部写周期最大10ms，高可靠性，1万次的写周期，100年的保存时间。

8pinPDIP、8pinJEDEC SOIC、8pinMAP和8pinTSSOP等四种封装形式。

AT24C01数据手册[Datasheet]供此芯片，需要请联系我们EEPROM存储器AT24C02低压和标准电压工作(Vcc=1.8V—5.5V)，256x8（2k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。

Bi方向传输协议，100kHz （1.8V,2.5V,2.7V）和400kHz（5V）兼容传输速率。

，硬件数据写保护引脚，8位页写模式，允许局部页写操作，器件内部写周期最大10ms，高可靠性，1万次的写周期，100年的保存时间。

8pinPDIP、8pinJEDEC SOIC、8pinMAP和8pinTSSOP 等四种封装形式。

AT24C02数据手册[Datasheet]供此芯片，需要请联系我们EEPROM存储器AT24C04低压和标准电压工作(Vcc=1.8V—5.5V)，512x8（4k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。

Bi方向传输协议，100kHz （1.8V,2.5V,2.7V）和400kHz（5V）兼容传输速率。

，硬件数据写保护引脚，8位页写模式，允许局部页写操作，器件内部写周期最大10ms，高可靠性，1万次的写周期，100年的保存时间。

8pinPDIP、8pinJEDEC SOIC、8pinMAP和8pinTSSOP 等四种封装形式。

AT24C04数据手册[Datasheet]供此芯片，需要请联系我们EEPROM存储器AT24C08低压和标准电压工作(Vcc=1.8V—5.5V)，1024x8（8k）存储空间，2线串行总线，斯密特触发，噪声抑制滤波输入。

AT24C04中文资料

Maplead MCU Development Board24. AT24C04 芯片的 I2C 总线读写4K（512×8）AT24C04 E2PEOMAT24C04 是 ATMEL 公司生产的 4K bit（512Bytes）E2PROM 芯片，该芯片采用 I2C 总线设计，主要性能指标与 AT24C02 类似，不同点为：容量为 AT24C02 的两倍，分为两部分存储空间，每部分 256bytes。

有 2 个器件地址选择脚，一个 I2C 总线最多能够挂接 4 个 AT24C04 器件。

32 页，每页 16 字节，每次可连续写入 16 字节数据。

WP 引脚为高电平时，AT24C04 的 0~255 地址空间的数据被写保护。

需要 9 位的地址进行数据寻址。

AT24C04 的引脚定义图 24-1 AT24C02 引脚定义表 24-1 AT24C02 引脚定义引脚定义 1. A0 2. A1,A2 3. GND 4. SDA 5. SCL 6. WP 7. VCC 空引脚。

器件地址设定引脚。

电源地。

数据口。

同步时钟口。

写保护口。

电源。

说明A0 为空引脚，A1,A2 口为器件地址设定口，通过 A1,A2 口来设定 AT24C04 的器件地址 WP 口接低电平时，可以对整个 AT24C04 器件的 512 个字节进行读写操作。

当 WP 口接高电平后，器件前 256 个地址的数据被保护，只能读，不可写入，后 256 个字节数据可进行读写操作。

172Maplead MCU Development BoardAT24C04 的从器件寻址图 24-2 AT24C04 的器件及数据空间地址 AT24C04 的器件地址由两个引脚决定，分别为 A1,A2 引脚。

AT24C04 的数据空间由 P0 位决定，如图 24-2 所示，当 P0 为“0”时，将对 AT24C04 的 0~255 空间的数据进行操作；当当 P0 为“1”时，将对 AT24C04 的 256~511 空间的数据进行操作。

浅谈AT24C04在电子设计中的作用

图２ — １ＡＴ２４Ｃ０４￣Ｉ脚分布图
Ａ１、Ａ２为芯片的引脚地址，ＳＣＬ和ＳＤＡ为Ｉ２Ｃ总线接口的串行时钟线与数据线。ＷＰ为写保护引脚，当芯片写保护时，ＷＰ为高电平，智能对器读操作，不能改写内部数据，从而起到硬件保护作用，当ＷＰ为低电平时，才能实现对器件的写操作。芯片引脚少，外围电路简单，减少了布局布线空间。
～
在简易时钟电路设计中，由于时钟芯片掉电时时间信息会丢失，重新上电后，芯片复位，内部数据清零，因此无法掉电保存数据。使用ＡＴ２４ｃ０４配合掉电管理，系统工作时，时间信息实时显示的同事，处理器同时将此刻数据写入至ＡＴ２４ＣＯ４，掉电后，ＡＴ２４Ｃ０４保存了掉电时刻的数据。重新上电时，可由单片机控制器件读取掉电时的时间信息。
ＡＴ２４Ｃ０４，其中，单片机作为数据交互与处理的中间桥梁，数据存２ＡＴ２４Ｃ０４的基本介绍
ＡＴ２４Ｃ０４是Ａｔｍｅｌ公司的一款Ｉ２Ｃ串行ＥＥＰＲＯＭ，其工作电压范围宽，ｖＣＣ工作在１．７．５．５伏，兼容５１单片机的ＴＴＬ电平。芯片引脚分布图如图２．１所示：
图４ — １系统框图

at24c04数据手册

1Features•Low-voltage and Standard-voltage Operation –2.7(V CC =2.7V to 5.5V)–1.8(V CC =1.8V to 5.5V)•Internally Organized 128x 8(1K),256x 8(2K),512x 8(4K),1024x 8(8K)or 2048x 8(16K)•2-wire Serial Interface•Schmitt Trigger,Filtered Inputs for Noise Suppression •Bi-directional Data Transfer Protocol•100kHz (1.8V,2.5V,2.7V)and 400kHz (5V)Compatibility •Write Protect Pin for Hardware Data Protection•8-byte Page (1K,2K),16-byte Page (4K,8K,16K)Write Modes •Partial Page Writes are Allowed •Self-timed Write Cycle (10ms max)•High-reliability–Endurance:1Million Write Cycles –Data Retention:100Years•Automotive Grade and Extended Temperature Devices Available•8-lead PDIP ,8-lead JEDEC SOIC,8-lead MAP,8-lead TAP and 8-lead TSSOP PackagesDescriptionThe AT24C01A/02/04/08/16provides 1024/2048/4096/8192/16384bits of serial elec-trically erasable and programmable read-only memory (EEPROM)organized as 128/256/512/1024/2048words of 8bits each.The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.The AT24C01A/02/04/08/16is available in space-saving 8-pin PDIP ,8-lead JEDEC SOIC,8-lead MAP ,8-lead TAP and 8-lead TSSOP packages and is accessed via a 2-wire serial interface.In addition,the entire family is available in 2.7V (2.7V to 5.5V)and 1.8V (1.8V to 5.5V)versions.Pin Configurations8-lead SOIC8-pin PDIP8-lead TSSOP8-lead MAP/TAP2AT24C01A/02/04/08/160180G –SEEPR –02/02Block DiagramAbsolute Maximum Ratings*NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings ”may cause permanent dam-age to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3AT24C01A/02/04/08/160180G –SEEPR –02/02Pin DescriptionSERIAL CLOCK (SCL):The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA):The SDA pin is bi-directional for serial data transfer.This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2,A1,A0):The A2,A1and A0pins are device address inputs that are hard wired for the AT24C01A and the AT24C02.As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04uses the A2and A1inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system.The A0pin is a no connect.The AT24C08only uses the A2input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system.The A0and A1pins are no connects.The AT24C16does not use the device address pins,which limits the number of devices on a single bus to one.The A0,A1and A2pins are no connects.WRITE PROTECT (WP):The AT24C01A/02/04/16has a Write Protect pin that provides hardware data protection.The Write Protect pin allows normal read/write operations when connected to ground (GND).When the Write Protect pin is connected to V CC ,the write protection feature is enabled and operates as shown in the following table.Memory OrganizationAT24C01A,1K SERIAL EEPROM:Internally organized with 16pages of 8bytes each,the 1K requires a 7-bit data word address for random word addressing.AT24C02,2K SERIAL EEPROM:Internally organized with 32pages of 8bytes each,the 2K requires an 8-bit data word address for random word addressing.AT24C04,4K SERIAL EEPROM:Internally organized with 32pages of 16bytes each,the 4K requires a 9-bit data word address for random word addressing.AT24C08,8K SERIAL EEPROM:Internally organized with 64pages of 16bytes each,the 8K requires a 10-bit data word address for random word addressing.AT24C16,16K SERIAL EEPROM:Internally organized with 128pages of 16bytes each,the 16K requires an 11-bit data word address for random word addressing.4AT24C01A/02/04/08/160180G –SEEPR –02/02IL IH Pin Capacitance (1)DC CharacteristicsApplicable over recommended operating range from:T AI =-40°C to +85°C,V CC =+1.8V to +5.5V,T AC =0°C to +70°C,5AT24C01A/02/04/08/160180G –SEEPR –02/02AC CharacteristicsApplicable over recommended operating range from T A =-40°C to +85°C,V CC =+1.8V to +5.5V,CL =1TTL Gate and6AT24C01A/02/04/08/160180G –SEEPR –02/02Device OperationCLOCK and DATA TRANSITIONS:The SDA pin is normally pulled high with an exter-nal device.Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram).Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION:A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION:A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence,the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE:All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.The EEPROM sends a zero to acknowledge that it has received each word.This happens during the ninth clock cycle.STANDBY MODE:The AT24C01A/02/04/08/16features a low-power standby mode which is enabled:(a)upon power-up and (b)after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET:After an interruption in protocol,power loss or system reset,any 2-wire part can be reset by following these steps:1.Clock up to 9cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C01A/02/04/08/160180G –SEEPR –02/02Bus TimingSCL:Serial Clock,SDA:Serial Data I/OWrite Cycle TimingSCL:Serial Clock,SDA:Serial Data I/ONote:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/writecycle.8AT24C01A/02/04/08/160180G –SEEPR –02/02Data ValidityStart and Stop DefinitionOutputAcknowledge9AT24C01A/02/04/08/160180G –SEEPR –02/02Device AddressingThe 1K,2K,4K,8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1).The device address word consists of a mandatory one,zero sequence for the first four most significant bits as shown.This is common to all the EEPROM devices.The next 3bits are the A2,A1and A0device address bits for the 1K/2K EEPROM.These 3bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2and A1device address bits with the third bit being a memory page address bit.The two device address bits must compare to their corre-sponding hard-wired input pins.The A0pin is no connect.The 8K EEPROM only uses the A2device address bit with the next 2bits being for memory page addressing.The A2bit must compare to its corresponding hard-wired input pin.The A1and A0pins are no connect.The 16K does not use any device address bits but instead the 3bits are used for mem-ory page addressing.These page addressing bits on the 4K,8K and 16K devices should be considered the most significant bits of the data word address which follows.The A0,A1and A2pins are no connect.The eighth bit of the device address is the read/write operation select bit.A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address,the EEPROM will output a zero.If a compare is not made,the chip will return to a standby state.Write OperationsBYTE WRITE:A write operation requires an 8-bit data word address following the device address word and acknowledgment.Upon receipt of this address,the EEPROM will again respond with a zero and then clock in the first 8-bit data word.Following receipt of the 8-bit data word,the EEPROM will output a zero and the addressing device,such as a microcontroller,must terminate the write sequence with a stop condi-tion.At this time the EEPROM enters an internally timed write cycle,t WR ,to the nonvolatile memory.All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE:The 1K/2K EEPROM is capable of an 8-byte page write,and the 4K,8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write,but the microcontroller does not send a stop condition after the first data word is clocked in.Instead,after the EEPROM acknowledges receipt of the first data word,the microcontroller can transmit up to seven (1K/2K)or fifteen (4K,8K,16K)more data words.The EEPROM will respond with a zero after each data word received.The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3).The data word address lower three (1K/2K)or four (4K,8K,16K)bits are internally incremented following the receipt of each data word.The higher data word address bits are not incremented,retaining the memory page row location.When the word address,internally generated,reaches the page boundary,the following byte is placed at the beginning of the same page.If more than eight (1K/2K)or sixteen (4K,8K,16K)data words are transmitted to the EEPROM,the data word address will “roll over ”and previ-ous data will be overwritten.10AT24C01A/02/04/08/160180G –SEEPR –02/02ACKNOWLEDGE POLLING:Once the internally timed write cycle has started and the EEPROM inputs are disabled,acknowledge polling can be initiated.This involves sending a start condition followed by the device address word.The read/write bit is representative of the operation desired.Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one.There are three read operations:current address read,random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation,incremented by one.This address stays valid between operations as long as the chip power is maintained.The address “roll over ”during read is from the last byte of the last memory page to the first byte of the first page.The address “roll over ”during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM,the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condi-tion (refer to Figure 4).RANDOM READ:A random read requires a “dummy ”byte write sequence to load in the data word address.Once the device address word and data word address are clocked in and acknowledged by the EEPROM,the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high.The EEPROM acknowledges the device address and serially clocks out the data word.The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (refer to Figure 5).SEQUENTIAL READ:Sequential reads are initiated by either a current address read or a ran-dom address read.After the microcontroller receives a data word,it responds with an acknowledge.As long as the EEPROM receives an acknowledge,it will continue to increment the data word address and serially clock out sequential data words.When the memory address limit is reached,the data word address will “roll over ”and the sequential read will con-tinue.The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6).11AT24C01A/02/04/08/160180G –SEEPR –02/02Figure 1.Device AddressFigure 2.Byte WriteFigure 3.Page Write(*=DON ’T CARE bit for1K)12AT24C01A/02/04/08/160180G –SEEPR –02/02Figure 4.Current Address ReadFigure 5.Random Read(*=DON ’T CARE bit for 1K)Figure 6.SequentialRead13AT24C01A/02/04/08/160180G –SEEPR –02/02AT24C01A Ordering Information14AT24C01A/02/04/08/160180G –SEEPR –02/02AT24C02Ordering Information15AT24C01A/02/04/08/160180G –SEEPR –02/02AT24C04Ordering Information16AT24C01A/02/04/08/160180G –SEEPR –02/02AT24C08Ordering Information17AT24C01A/02/04/08/160180G –SEEPR –02/02AT24C16Ordering Information18AT24C01A/02/04/08/160180G –SEEPR –02/02Packaging Information8P3–PDIP19AT24C01A/02/04/08/160180G –SEEPR –02/028S1–JEDEC SOIC20AT24C01A/02/04/08/160180G –SEEPR –02/028A2–TSSOP21AT24C01A/02/04/08/160180G –SEEPR –02/028Y1–MAP22AT24C01A/02/04/08/160180G –SEEPR –02/028Y3–TAPon recycled paper.©Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products,other than those expressly contained in the Company ’s standard warranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site.The Company assumes no responsibility for any errors which may appear in this document,reserves the right to change devices or specifications detailed herein at any time without notice,and does not make any commitment to update the information contained herein.No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products,expressly or by implication.Atmel ’s products are not authorized for use as critical components in life support devices or systems.Atmel HeadquartersAtmel OperationsCorporate Headquarters2325Orchard Parkway San Jose,CA 95131TEL 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