M27W202-200F6TR资料

M27W202 2Mbit(128Kb x16)Low Voltage UV EPROM and OTP EPROM s 2.7V to3.6V SUPPLY VOLTAGE in READ
OPERATION
s ACCESS TIME:
–80ns at V CC=3.0V to3.6V
–100ns at V CC=2.7V to3.6V
s LOW POWER CONSUMPTION:
–Active Current20mA at5MHz
–Standby Current15µA
s PIN COMPATIBLE with M27C202
s PROGRAMMING TIME:100µs/word
s HIGH RELIABILITY CMOS TECHNOLOGY
–2,000V ESD Protection
–200mA Latchup Protection Immunity
s ELECTRONIC SIGNATURE
–Manufacturer Code:0020h
–Device Code:001Ch
DESCRIPTION
The M27W202is a low voltage2Mbit EPROM of-
fered in the two range UV(ultra violet erase)and OTP(one time programmable).It is ideally suited
for microprocessor systems requiring large data or program storage and is organised as131,072by 16bits.
The M27W202operates in the read mode with a
supply voltage as low as2.7V at–40to85°C tem-perature range.The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery re-charges.
The FDIP40W(window ceramic frit-seal package)
has a transparent lid which allows the user to ex-pose the chip to ultraviolet light to erase the bit pat-tern.A new pattern can then be written to the device by following the programming procedure. For application where the content is programmed only one time and erasure is not required,the M27W201is offered in PDIP40,PLCC44and TSOP40(10x14mm)packages.Figure1.Logic Diagram
AI02730
17
A0-A16
P
Q0-Q15
V PP
V CC
M27W202
G
E
V SS
16
1
40
1
40
PDIP40(B)
PLCC44(K)TSOP40(N)
10x14mm
FDIP40W(F)
1/15
April2000
M27W202
2/15
Figure 2B.LCC Connections
AI02732
A 14
A11A7A 323
Q6Q5Q4
Q 3Q 2N C A 2Q12Q8V SS NC Q11Q1012
A 15A91Q 15V SS A12Q 13A5
44
N C A 16M27W202
Q 14A13A 4
NC A634
Q 1Q9A10A8Q7Q 0G A 0A 1V P P E P V C C Figure 2A.DIP Connections
Q6Q5Q4Q11Q8V SS Q7Q10Q9A12A8A11A10A6A13A9V SS A7A2Q1Q0A0
G
A1A5A16P E Q12V PP V CC
Q15AI02731
M27W202812345679101112131415163231
30292827262524232221
20191817Q3Q2Q14Q13A4A34039383736353433A14A15Figure 2C.TSOP Connections
DQ6DQ3DQ2DQ13DQ8
DQ7DQ10DQ9A14A8A11A10A4A15A9G A7A2DQ1DQ0A0A1A3A16P E DQ14V PP V CC DQ15AI02733
M27W202 (Normal)
101
11
2021
30
3140
V SS
A12A6A13A5DQ12DQ4DQ11DQ5V SS Table 1.Signal Names
A0-A16Address Inputs Q0-Q15Data Outputs E Chip Enable G Output Enable P Program V PP Program Supply V CC Supply Voltage V SS Ground
NC
Not Connected Internally
M27W202
Table2.Absolute Maximum Ratings(1)
Symbol Parameter Value Unit T A Ambient Operating Temperature(3)–40to125°C T BIAS Temperature Under Bias–50to125°C T STG Storage Temperature–65to150°C V IO(2)Input or Output Voltage(except A9)–2to7V V CC Supply Voltage–2to7V V A9(2)A9Voltage–2to13.5V V PP Program Supply Voltage–2to14V Note: 1.Except for the rating”Operating Temperature Range”,stresses above those listed in the Table”Absolute Maximum Ratings”may cause permanent damage to the device.These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.Exposure to Absolute Maximum Rating condi-tions for extended periods may affect device reliability.Refer also to the STMicroelectronics SURE Program and other relevant qual-ity documents.
2.Minimum DC voltage on Input or Output is–0.5V with possible undershoot to–2.0V for a period less than20ns.Maximum DC
voltage on Output is V CC+0.5V with possible overshoot to V CC+2V for a period less than20ns.
3.Depends on range.
Table3.Operating Modes
Mode E G P A9V PP Q15-Q0 Read V IL V IL V IH X V CC or V SS Data Output Output Disable V IL V IH X X V CC or V SS Hi-Z Program V IL X V IL Pulse X V PP Data Input Verify V IL V IL V IH X V PP Data Output Program Inhibit V IH X X X V PP Hi-Z Standby V IH X X X V CC or V SS Hi-Z Electronic Signature V IL V IL V IH V ID V CC Codes Note:X=V IH or V IL,V ID=12V±0.5V.
Table4.Electronic Signature
Identifier A0Q7Q6Q5Q4Q3Q2Q1Q0Hex Data Manufacturer’s Code V IL0010000020h Device Code V IH000111001Ch Note:Outputs Q15-Q8are set to’0’.
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M27W202
4/15
Table 5.AC Measurement Conditions
High Speed
Standard Input Rise and Fall Times ≤10ns ≤20ns Input Pulse Voltages
0to 3V 0.4V to 2.4V Input and Output Timing Ref.Voltages
1.5V
0.8V and 2V
Figure 3.AC Testing Input Output Waveform
AI01822
3V
High Speed
0V
1.5V
2.4V
Standard 0.4V
2.0V 0.8V
Figure 4.AC Testing Load Circuit
AI01823B
1.3V
OUT
C L
C L =30pF for High Speed C L =100pF for Standard C L includes JIG capacitance
3.3k Ω
1N914
DEVICE UNDER TEST
Table 6.Capacitance (1)(T A =25°C,f =1MHz)
Note: 1.Sampled only,not 100%tested.
Symbol Parameter
Test Condition
Min
Max Unit C IN Input Capacitance V IN =0V 6pF C OUT
Output Capacitance
V OUT =0V
12
pF
DEVICE OPERATION
The operating modes of the M27W202are listed in the Operating Modes table.A single power supply is required in the read mode.All inputs are TTL levels except for V PP and 12V on A9for Electronic Signature.Read Mode
The M27W202has two control functions,both of which must be logically active in order to obtain data at the outputs.Chip Enable (E)is the power control and should be used for device selection.Output Enable (G)is the output control and should be used to gate data to the output pins,indepen-dent of device selection.Assuming that the ad-dresses are stable,the address access time
(t AVQV )is equal to the delay from E to output (t ELQV ).Data is available at the output after a delay of t OE from the falling edge of G,assuming that E has been low and the addresses have been stable for at least t AVQV -t GLQV .Standby Mode
The M27W202has a standby mode which reduc-es the supply current from 15mA to 15µA with low voltage operation V CC â3.6V,see Read Mode DC Characteristics table for details.
The M27W202is placed in the standby mode by applying a TTL high signal to the E input.When in the standby mode,the outputs are in a high imped-ance state,independent of the G input.
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M27W202
Table 7.Read Mode DC Characteristics (1)
(T A =–40to 85°C;V CC =2.7V to 3.6V;V PP =V CC )
Note: 1.V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .
2.Maximum DC voltage on Output is V CC +0.5V.
Symbol Parameter
Test Condition Min
Max Unit I LI Input Leakage Current 0V ≤V IN ≤V CC ±10µA I LO Output Leakage Current 0V ≤V OUT ≤V CC ±10µA I CC Supply Current
E =V IL ,G =V IL ,I OUT =0mA,f =5MHz
V CC ≤ 3.6V
20mA I CC1Supply Current (Standby)TTL E =V IH 1mA I CC2Supply Current (Standby)CMOS E >V CC –0.2V V CC ≤ 3.6V 15µA I PP Program Current V PP =V CC
10µA V IL Input Low Voltage –0.60.2V CC V V IH (2)Input High Voltage 0.7V CC V CC +0.5
V V OL Output Low Voltage I OL =2.1mA 0.4
V V OH
Output High Voltage TTL
I OH =–400µA
2.4
V
Two Line Output Control
Because OTP EPROMs are usually used in larger memory arrays,this product features a 2line con-trol function which accommodates the use of mul-tiple memory connection.The two line control function allows:
a.the lowest possible memory power dissipation,
plete assurance that output bus contention will not occur.
For the most efficient use of these two control lines,E should be decoded and used as the prima-ry device selecting function,while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus.This ensures that all deselect-ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices.The supply current,I CC ,has three seg-ments that are of interest to the system designer:the standby current level,the active current level,and transient current peaks that are produced by the falling and rising edges of E.The magnitude of transient current peaks is dependent on the ca-pacitive and inductive loading of the device at the output.The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors.It is recommended that a 0.1µF ceram-ic capacitor be used on every device between V CC and V SS .This should be a high frequency capaci-tor of low inherent inductance and should be placed as close to the device as possible.In addi-tion,a 4.7µF bulk electrolytic capacitor should be used between V CC and V SS for every eight devic-es.The bulk capacitor should be located near the power supply connection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.
M27W202
6/15
Table 8.Read Mode AC Characteristics (1)
(T A =–40to 85°C;V CC =2.7V to 3.6V;V PP =V CC )
Note: 1.V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .
2.Sampled only,not 100%tested.
3.Speed obtained with High Speed AC measurement conditions.
Symbol
Alt
Parameter
Test Condition
M27W202
Unit
-100(3)
-120(-150/-200)
V CC =3.0V to 3.6V V CC =2.7V to 3.6V V CC =2.7V to 3.6V Min
Max Min
Max Min
Max t AVQV t ACC Address Valid to Output Valid E =V IL ,G =V IL 80100120ns t ELQV t CE Chip Enable Low to Output Valid G =V IL 80100120ns t GLQV t OE Output Enable Low to Output Valid E =V IL 50
6070ns t EHQZ (2)t DF Chip Enable High to Output Hi-Z G =V IL 050060070ns t GHQZ (2)t DF Output Enable High to Output Hi-Z E =V IL 050
060
070
ns t AXQX
t OH
Address Transition to Output Transition
E =V IL ,G =V IL
00ns
Figure 5.Read Mode AC Waveforms
AI01818B
tAXQX
tEHQZ
A0-A16
E
G
Q0-Q15
tAVQV
tGHQZ
tGLQV
tELQV
VALID Hi-Z
VALID
7/15
M27W202
Table 9.Programming Mode DC Characteristics (1)
(T A =25°C;V CC =6.25V ±0.25V;V PP =12.75V ±0.25V)
Note: 1.V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .
Table 10.Programming Mode AC Characteristics (1)(T A =25°C;V CC =6.25V ±0.25V;V PP =12.75V ±0.25V)
Note: 1.V CC must be applied simultaneously with or before V PP and removed simultaneously or after V PP .
2.Sampled only,not 100%tested.
Symbol Parameter
Test Condition Min
Max Unit I LI Input Leakage Current 0≤V IN ≤V IH
±10µA I CC Supply Current 50mA I PP Program Current E =V IL
50mA V IL Input Low Voltage –0.30.8V V IH Input High Voltage 2
V CC +0.5
V V OL Output Low Voltage I OL =2.1mA 0.4
V V OH Output High Voltage TTL I OH =–400µA
2.4V V ID
A9Voltage
11.5
12.5
V
Symbol Alt Parameter
Min Max
Unit t AVPL t AS Address Valid to Program Low 2µs t QVPL t DS Input Valid to Program Low 2µs t VPHPL t VPS V PP High to Program Low 2µs t VCHPL t VCS V CC High to Program Low 2µs t ELPL t CES Chip Enable Low to Program Low 2µs t PLPH t PW Program Pulse Width
95105µs t PHQX t DH Program High to Input Transition 2µs t QXGL t OES Input Transition to Output Enable Low 2
µs t GLQV t OE Output Enable Low to Output Valid 100ns t GHQZ (2)t DFP Output Enable High to Output Hi-Z 0130ns t GHAX
t AH
Output Enable High to Address Transition
0ns
Programming
When delivered,all bits of the M27W202are in the ’1’state.Data is introduced by selectively pro-gramming ’0’s into the desired bit locations.Al-though only ’0’s will be programmed,both ’1’s and ’0’s can be present in the data word.The
M27W202is in the programming mode when V PP input is at 12.75V,E is at V IL and P is pulsed to V IL .The data to be programmed is applied to 16bits in parallel,to the data output pins.The levels re-quired for the address and data inputs are TTL.V CC is specified to be 6.25V ±0.25V.
M27W202
8/15
Figure 6.Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00706
A0-A15
Q0-Q15
V PP
V CC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM VERIFY
Figure 7.Programming Flowchart
AI02734
n =0
Last Addr
VERIFY
P =100µs Pulse
++n =25++Addr
V CC =6.25V,V PP =12.75V
FAIL
CHECK ALL WORDS 1st:V CC =5V 2nd:V CC =2.7V
YES NO
YES
NO
YES
NO PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-gramming of the whole array with a guaranteed margin,in a typical time of 13seconds.Program-ming with PRESTO II consists of applying a se-quence of 100µs program pulses to each word until a correct verify occurs (see Figure 7).During programming and verify operation,a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin.No overprogram pulse is applied since the verify in MARGIN MODE at V CC much higher than 3.6V,provides necessary margin to each programmed cell.Program Inhibit
Programming of multiple M27W202s in parallel with different data is also easily accomplished.Ex-cept for E,all like inputs including G of the parallel M27W202may be common.A TTL low level pulse applied to a M27W202’s P input,with E low and V PP at 12.75V,will program that M27W202.A high level E input inhibits the other M27W202s from be-ing programmed.Program Verify
A verify (read)should be performed on the pro-grammed bits to determine that they were correct-ly programmed.The verify is accomplished with E and G at V IL ,P at V IH ,V PP at 12.75V and V CC at 6.25V.
M27W202
On-Board Programming
The M27W202can be directly programmed in the application circuit.See the relevant Application Note AN620.
Electronic Signature
The Electronic Signature(ES)mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type.This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the25°C±5°C am-bient temperature range that is required when pro-gramming the M27W202.To activate the ES mode,the programming equipment must force 11.5V to12.5V on address line A9of the M27W202with V PP=V CC=5V.Two identifier bytes may then be sequenced from the device out-puts by toggling address line A0from V IL to V IH.All other address lines must be held at V IL during Electronic Signature mode.Byte0(A0=V IL)rep-resents the manufacturer code and byte1 (A0=V IH)the device identifier code.For the STMicroelectronics M27W202,these two identifier bytes are given in Table4and can be read-out on outputs Q7to Q0.ERASURE OPERATION(applies to UV EPROM) The erasure characteristics of the M27W201are
such that erasure begins when the cells are ex-posed to light with wavelengths shorter than ap-
proximately4000Å.It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the3000-4000Årange.Data shows that constant exposure to room level fluo-rescent lighting could erase a typical M27W201in about3years,while it would take approximately1 week to cause erasure when exposed to direct sunlight.If the M27W201is to be exposed to these types of lighting conditions for extended periods of time,it is suggested that opaque labels be put over the M27W201window to prevent unintentional erasure.The recommended erasure procedure for the M27W201is exposure to short wave ultraviolet light which has wavelength of2537Å.The inte-grated dose(i.e.UV intensity x exposure time)for erasure should be a minimum of15W-sec/cm2. The erasure time with this dosage is approximate-ly15to20minutes using an ultraviolet lamp with 12000µW/cm2power rating.The M27W201 should be placed within2.5cm(1inch)of the lamp tubes during the erasure.Some lamps have a filter on their tubes which should be removed before erasure.
9/15
M27W202
10/15
Table 11.Ordering Information Scheme
Note: 1.
High Speed,see AC Characteristics section for further information.2.This speed also guarantees 80ns access time at V CC =3.0V to 3.6V.3.These speeds are replaced by the 120ns.
4.Packages option available on request.Please contact STMicroelectronics local Sales Office.
For a list of available options (Speed,Package,etc...)or for further information on any aspect of this de-vice,please contact the STMicroelectronics Sales Office nearest to you.Example:M27W202
-100K
6
TR
Device Type M27
Supply Voltage W =2.7V to 3.6V Device Function
202=2Mbit (128Kb x16)Speed
-100(1,2)=100ns -120=120ns
Not For New Design (3)-150=150ns -200=200ns Package F =FDIP40W (4)B =PDIP40K =PLCC44
N =TSOP40:10x 14mm (4)Temperature Range 6=–40to 85°C
Options
TR =Tape &Reel Packing
Table 12.Revision History
Date Revision Details
November 1998First Issue
04/19/00
From Product Preview to Data Sheet FDIP40W Package added I CC2Stanbdy current changed
Table13.FDIP40W-40lead Ceramic Frit-seal DIP with window,Package Mechanical Data
Symbol
mm inches
Typ Min Max Typ Min Max
A 5.720.225
A10.51 1.400.0200.055 A2 3.91 4.570.1540.180 A3 3.89 4.500.1530.177 B0.410.560.0160.022 B1 1.45––0.057––C0.230.300.0090.012 D51.7952.60 2.039 2.071 D248.26–– 1.900––E15.24––0.600––E113.0613.360.5140.526
e 2.54––0.100––
eA14.99––0.590––eB16.1818.030.6370.710 L 3.18 4.100.1250.161 S 1.52 2.490.0600.098∅8.13––0.320––α4°11°4°11°N4040
Figure8.FDIP40W-40lead Ceramic Frit-seal DIP with window,Package Outline
Drawing is not to scale.
FDIPW-a
A3
A1
A
L
B1B e
D
S
E1E
N
1
C
α
eA
D2
∅
eB
A2
11/15
Table14.PDIP40-40pin Plastic DIP,600mils width,Package Mechanical Data
Symbol
mm inches
Typ Min Max Typ Min Max
A 4.45––0.175––
A10.640.38–0.0250.015–A2 3.56 3.910.1400.154 B0.380.530.0150.021 B1 1.14 1.780.0450.070 C0.200.310.0080.012 D51.7852.58 2.039 2.070 D248.26–– 1.900––E14.8016.260.5830.640 E113.4613.990.5300.551 e1 2.54––0.100––eA15.24––0.600–
eB15.2417.780.6000.700 L 3.05 3.810.1200.150 S 1.52 2.290.0600.090α0°15°0°15°N4040
Figure9.PDIP40-40lead Plastic DIP,600mils width,Package Outline
Drawing is not to scale.
PDIP
A2
A1
A
L
B1B e1
D
S
E1E
N
1
C
α
eA
eB
D2
12/15
13/15
Table 15.PLCC44-44lead Plastic Leaded Chip Carrier,Package Mechanical Data
Symbol
mm
inches Typ
Min Max Typ
Min Max A 4.20 4.700.1650.185A1 2.29 3.040.0900.120A2–0.51–0.020B 0.330.530.0130.021B10.660.810.0260.032D 17.4017.650.6850.695D116.5116.660.6500.656D214.9916.000.5900.630E 17.4017.650.6850.695E116.5116.660.6500.656E214.9916.000.5900.630e 1.27
––0.050––F 0.000.250.0000.010R 0.89––
0.035––
N 44
44
CP
0.100.004Figure 10.PLCC44-44lead Plastic Leaded Chip Carrier,Package Outline
Drawing is not to scale.
PLCC
D Ne
E1E
1N
D1
Nd
CP
B
D2/E2
e
B1
A1
A
R
0.51(.020)
1.14(.045)
F A2
14/15
Table 16.TSOP40-40lead Plastic Thin Small Outline,10x 14mm,Package Mechanical Data
Symbol
mm
inches Typ
Min
Max Typ
Min
Max A 1.200.0472A10.050.150.00200.0059A20.95 1.050.03740.0413B 0.170.270.00670.0106C 0.100.210.00390.0083D 13.8014.200.54330.5591D112.3012.500.48430.4921E 9.9010.100.38980.3976e 0.50
––0.0197
––L 0.500.700.01970.0276α0°5°
0°5°
N 40
40
CP
0.10
0.0039
Figure 11.TSOP40-40lead Plastic Thin Small Outline,10x 14mm,Package Outline
Drawing is not to scale.
TSOP-a
D1E
1
N
CP
B
e
A2
A
N/2
D
DIE
C
L
A1α
Information furnished is believed to be accurate and reliable.However,STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specifications mentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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