Addressing Modes
instruction (1)
Procedure returns Case / switch statements Virtual functions or methods High-order functions or function pointers Dynamically shared libraries
Half word add?
Optional saturating arithmetic. Up to 10 instructions can be replaced by HADD.
19
Instructions for Control Flow
Four basic types:
Conditional branches Jumps (unconditional) Procedure calls Procedure returns
R[3]R[3]+M[R[1]+R[A2r]]ray Access
Hale Waihona Puke R[1]R[1]+M[1001] Static Data
R[1]R[1]+M[M[R[3]]*]p (Ptr Address)
R[1]R[1]+M[R[2]]
Array in a Loop
R[2]R[2]+d R[2]R[2] – d R[1]R[1]+M[R[2]] R[1]R[1]+M[100+R[2]+R[3]*d]
Instructions for Control Flow
Instruction Format
The Role of Compilers
大学计算机组织与结构习题
前二章作业1.计算机的四个基本功能（Functions）是什么？2.在计算机的top-level structure view中，四个structural components 是什么？3.谁提出了store-program concept ?你能用汉语简单地描述这个存储程序的概念吗？4.CPU的英文全称是什么？汉语意义是什么？5.ALU的英文全称是什么？汉语意义是什么？6.V on Neumann 的IAS机的五大部件都是什么？7.在第一章中我们认识到的四个结构性部件（第2题）与V on Neumann的IAS机（第6题）中部件有本质差别吗？8.Fundamental Computer Elements 有哪几个？它们与计算机的四个基本功能的关系是什么？9.Moore’s Law在中文翻译为什么？它描述了什么事物的一般规律？10.本书的次标题和第二章第二节标题均为“Designing forPerformance”,Performance 主要指什么？Performance Balance的（balance）平衡要平衡什么？11.本书作者将他要研究的范围局限在“desktop, workstation , server“中，它们的中文名称是什么？各自的工作范围是什么？Chapter 3Homework1.PC means _________.A. personal computerB. programming controllerC. program counterD. portable computer2. PC holds _______________ .A. address of next instructionB. next instructionC. address of operandD. operand3. At the end of fetch cycle, MAR holds _____.A. address of instructionB. instructionC. address of operandD. operand4. Interrupt process steps are __________.A. suspending , resuming , branching & processingB. branching , suspending , processing & resumingC. suspending , branching , processing & resumingD. processing , branching , resuming & suspending5. A unsigned binary number is n bits, so it is can represent a value in the range between _________ .A. 0 to n-1B. 1 to nC. 0 to 2n-1D. 1 to 2n6.The length of the address code is 32 bits, so addressing range (or the range of address) is ________________.A. 4GB.from –2G to 2GC.4G-1D. from 1 to 4G7.There are three kinds of BUSes. Which is not belong to them?A. address busB. system busC. data busD. control busQuestions1.Translate the following terms (Note: function)PC, MAR, MBR, IR, AC, bus, system bus, data bus , address bus , control bus , handler*, opcode, Bus arbitrate* , multiplexed bus* , interrupt, ISR, Instruction cycle , fetch cycle , execute cycle(带“*”为选做题)2.Page90 problems3.1What general categories of functions are specified by computer instruction?3. Describe simply the operations of PC and IR in an instruction cycle.4.Suppose the length of word is n-bit, describe simply operand(操作数) format and instruction format.5. Describe simply the procedure of the interruption6. Describe simply the types and functions of the BUS.一：选择题1.The computer memory system refers to _________A.RAMB.ROMC.Main memoryD.Register , main memory, cache, external memory2.If the word of memory is 16 bits, which the following answer is right ?A.The address width is 16 bitsB.The address width is related with 16 bitsC.The address width is not related with 16 bitsD.The address width is not less than 16 bits3.The characteristics of internal memory compared to external memoryA.Big capacity, high speed, low costB.Big capacity, low speed, high costC.small capacity, high speed, high costD.small capacity, high speed, low cost4．On address mapping of cache, any block of main memory can be mapped toany line of cache, it is ___________ .A) Associative Mapping B) Direct MappingC) Set Associative Mapping D) Random Mapping5. Cache’s write-through polity means write operation to main memory _______.A)as well as to cacheB)only when the cache is replacedC)when the difference between cache and main memory is foundD)only when direct mapping is used6.Cache’s write-back polity means write operation to main memory ______________.a)as well as to cacheb)only when the relative cache is replacedc)when the difference between cache and main memory is foundd)only when using direct mapping7. On address mapping of cache, the data in any block of main memory can be mapped to fixed line of cache, it is _________________.associative mapping B) direct mappingC)set associative mapping D) random mapping8.On address mapping of cache, the data in any block of main memory can be mapped to fixed set any line(way) of cache, it is _________________.associative mapping B) direct mappingD)set associative mapping D) random mapping二：计算题(from page 126)Problem 4.1 , Problem 4.3 , Problem 4.4 , Problem 4.5 , , Problem 4.7, Problem 4.10第五章作业1.which type of memory is volatile?A.ROMB. E2PROMC. RAMD. flash memory2.which type of memory has 6-transistor structure?A. DRAMB. SRAMC. ROMD. EPROMing hamming code, its purpose is of one-bit error.A. detecting and correctingB. detectingC. correctingD. none of all4.Flash memory is .A. read-only memoryB. read-mostly memoryC. read-write memoryD. volatile5.Which answer about internal memory is not true?A. RAM can be accessed at any time, but data would be lost when power down..B. When accessing RAM, access time is non-relation with storage location.C. In internal memory, data can’t be modified.D. Each addressable location has a unique address.Page161 Problems: 5.4 5.5 5.6 5.7 5.8第六章作业一、选择题1. RAID levels_________make use of an independent access technique.A. 2B. 3C. 4D. all2. In RAID 4, to calculate the new parity, involves _________reads.A. oneB. twoC. threeD.four3. During a read/write operation, the head is ___________A. movingB. stationaryC. rotatingD. above all4. On a movable head system, the time it takes to position the head at the track is know as______.A. seek timeB. rotational delayC. access timeD. transfer time5. RAID makes use of stored______information that enable the recovery of data lost due to a disk failure.A. parityB. user dataC. OSD. anyone6. Recording and retrieval via _________called a headA. conductive coilB. aluminiumC. glassD. Magnetic field7.In Winchester disk track format, _________is a unique identifier or address used to locate a particular sector.A. SYNCHB. GapC. ID fieldD. Data field8. Data are transferred to and from the disk in ________.A. trackB. sectorC. gapD. cylinder9. In _________, each logical strip is mapped to two separate physical disk.A. RAID 1B. RAID 2C. RAID 3D. RAID 410. With _________, the bits of an error correcting code are stored in the corresponding bit position on multiple parity disk.A. RAID 1B. RAID 2C. RAID 3D. RAID 411. The write-once read-many CD, known as ________.A. CD-ROMB. CD-RC. CD-R/WD. DVD二、How are data written onto a magnetic disk?三、In the context of RAID, what is the distinction between parallel access and independent access?Homework in Chapter 71.“When the CPU issues a command to the I/O module, it must wait until the I/Ooperation is complete”. It is programmed I/O , the word “wait”means ___________________.a. the CPU stops and does nothingb. the CPU does something elsec. the CPU periodically reads & checks the status of I/O moduled. the CPU wait the Interrupt Request Signal2.See Figure 7.7. To save (PSW & PC) and remainder onto stack, why theoperations of restore them is reversed? Because the operations of stack are ________________.a. first in first outb. randomc. last in first outd. sequenceding stack to save PC and remainder, the reason is ____________________ .a.some information needed for resuming the current program at the point ofinterruptb.when interrupt occurs, the instruction is not executed over, so the instructionat the point of interrupt must be executed once againc.the stack must get some information for LIFOd.the start address of ISR must transfer by stack4.The signals of interrupt request and acknowledgement exchange between CPUand requesting I/O module. The reason of CPU’s acknowledgement is ________________a.to let the I/O module remove request signalb. to let CPU get the vectorfrom data busc.both a & bd. other aims5.In DMA , the DMA module takes over the operations of data transferring fromCPU, it means _________________________a.the DMA module can fetch and execute instructions like CPU doesb.the DMA module can control the bus to transfer data to or from memoryusing stealing cycle techniquec.the DMA module and CPU work together(co-operate) to transfer data into orfrom memoryd.when DMA module get ready, it issues interrupt request signal to CPU forgetting interrupt service6.Transfer data with I/O modules, 3 types of techniques can be used. Which one isnot belong them?a. Interrupt-driven I/Ob. programmed I/Oc. direct I/O accessd. DMA7.Think 2 types of different data transferring, to input a word from keyboard and tooutput a data block of some sectors to harddisk. The best choice is to use ___________.a. interrupt-driven I/O and DMAb. DMA and programmed I/O C. both interrupt-driven I/Os d. both DMAsparing with interrupt-driven I/O, DMA further raises the usage rate of CPUoperations, because __________a. it isn’t necessary for CPU to save & restore sceneb. it isn’t necessary for CPU to intervene the dada transferc. it isn’t necessary for CPU to read & check status repeatedlyd. both a and b9.Simply script the all actions when using Interrupt-driven I/O technique totransferring data with I/O module.(please insert the “vector “at step3 & step5)10.See Figure 7.7 & 7.8. Redraw figure 7.8, and mark the sequence numberaccording to Figure 7.7, to indicate the sequence of the information flowing.11. According to DMA technique, write all information of CPU sending to DMA module, and write at which time the DMA module issues interrupt request signal to CPU and why the INTR is issued ?.Chapter9 homework1.Suppose bit long of two’s complement is 5 bits, which arithmetic operation brings OVERFLOW?A. 5+8B. (-8)+(-8)C. 4-(-12)D.15-72.Overflow occurs sometime in ______arithmetic operation.A. addB. subtractC. add and subtractD. multiply3. In twos complement, two positive integers are added, when does overflow occurs?A. There is a carryB. Sign bit is 1C. There is a carry, and sign bit is 0D. Can’t determine4. An 8-bit twos complement 1001 0011 is changed to a 16-bit that equal to____.A.1000 0000 1001 0011B. 0000 0000 1001 0011C.1111 1111 1001 0011D.1111 1111 0110 1101 115. An 8-bit twos complement 0001 0011 is changed to a 16-bit that equal to____.A. 1000 0000 1001 0011B. 0000 0000 0001 0011C. 1111 1111 0001 0011D. 1111 1111 1110 11016.Booth’s algorithm is used for Twos complement ______.A. additionB. subtractionC. multiplicationD. division7. In floating-point arithmetic, addition can divide to 4 steps: ______.A. load first operand, add second operand, check overflow and store resultB. compare exponent, shift significand, add significands and normalizeC. fetch instruction, indirectly address operand, execute instruction and interruptD. process scheduling states: create, get ready, is running and is blocked8. In floating-point arithmetic, multiplication can divide to 4 steps: ______.A. load first operand, add second operand, check overflow and store resultB. fetch instruction, indirectly address operand, execute instruction and interruptC. process scheduling states: create, get ready, is running and is blockedD. check for zero, add exponents, multiply significands, normalize, and round.9.The main functions of ALU are?A. LogicB. ArithmeticC. Logic and arithmeticD. Only addition10. Which is true?A. Subtraction can not be finished by adder and complement circuits in ALUB. Carry and overflow are not sameC.In twos complement, the negation of an integer can be formed with thefollowing rules: bitwise not (excluding the sign bit), and add 1.D. In twos complement, addition is normal binary addition, but monitor sign bit foroverflowPage326：9.4, 9.5 and 9.7(其中9.4选作)To prove: in twos complement, sign-extension rule (converting between different bit length) and negation rule ( (-X)补= X补+ 1).Chapter 10 and Chapter 111: In instruction, the number of addresses is 0, the operand(s)’address is implied, which is(are) in_______.A. accumulatorB. program counterC. top of stackD. any register2: Which the following addressing mode can achieve the target of branch in program?A.Direct addressing modeB.Register addressing modeC.Base-register addressing modeD.Relative addressing mode （有问题）3: In index-register addressing mode , the address of operand is equal toA.The content of base-register plus displacementB.The content of index-register plus displacementC.The content of program counter plus displacementD.The content of AC plus displacement4: The address of operand is in the instruction, it is_________ ?A.Direct addressing modeB.Register indirect addressing modeC.Stack addressing modeD.Displacement addressing mode5: Which the following is not the area that the source and result operands can be stored in ?A.Main or virtual memoryB.CPU registerC.I/O deviceD.Instruction6: Compared with indirect addressing mode , the advantage of register indirect addressing mode isrge address spaceB.Multiple memory referenceC.Limit address spaceD.Less memory access7:With base-register ADDRESSING , the ______________ register can be used.A. BASEB. INDEXC. PCD. ANY8:The disadvantage of INDIRECT ADDRESSING is ____________.A. large addressing rangeB. no memory accessC. more memory accessD. large value range9:Which is not an advantage with REGISTER INDIRECT?A. just one times of operand’s accessB. large memory spaceC. large value rangeD. no memory reference10:The REGISTER ADDRESSING is very fast, but it has _________________.A. very less value rangeB. very less address spaceC. more memory accessD. very complex address’ calculating11:The disadvantage of IMMEDIATE ADDRESSING is ___________.A. limited address rangeB. more memory accessC. limit value rangeD. less memory access12:In instruction, the number of addresses is 2, one address does double duty both _______________.A. a result and the address of next instructionB.an operand and a resultC.an operand and the address of next instructionD.two closed operands13.In instruction, the number of addresses is 3, which are _______________.A. two operands and one resultB. two operands and an address of next instructionC. one operand, one result and an address of next instructionD. two operands and an address of next instruction14.The address is known as a type of data, because it is represented by __________.A. a number of floating pointB. a signed integerC. an unsigned integerD. a number of hexadecimal15.Which is not a feature of Pentium .A. complex and flex addressingB. abundant instruction setC. simple format and fixed instruction lengthD. strong support to high language16. Which is not a feature of Power PC .A. less and simple addressing modeB. basic and simple instruction setC. variable instruction length and complex formatD. strong support to high languageChapter 12 and Chapter 181. After the information flow of fetch subcycle, the content of MBR is_____________.A.oprandB.address of instructionC. instructionD. address of operand2. After the information flow of instruction subcycle, the content of MBR is_____________.A.oprandB.address of instructionC. instructionD. address of operand3. The worse factor that limits the performance of instruction pipeline is _________________.A.conditional branch delaying the operation of target addressB. the stage number of pipeline c an’t exceed 6C. two’s complement arithmetic too complexD. general purpose registers too few4.The most factor to affect instruction pipeline effectiveness is __________.A. The number of stagesB. the number of instructionC. the conditional branch instructionD. the number of pipelines5. RISC rejects ______.A. few, simple addressing modesB. a limited and simple instruction setC. few, simple instruction formatsD. a few number of general purpose registers6. RISC rejects ______.A.a large number of general-purpose registersB. indirect addressingC. a single instruction sizeD. a small number of addressing mode7. Which is NOT a characteristic of RISC processor.A. a highly optimized pipeline.B. Register to registeroperationsC. a large number of general-purpose registersD. a complexed instructionformat8.Control unit use some input signals to produce control signals that open the gatesof information paths and let the micro-operations implement. Which is NOT the input signals of control unit/A.clock and flagsB.instruction registerC.interrupt request signalD.memory read or write9.Control unit use some output signals to cause some operations. Which is notincluded in the output signals?A.signals that cause data movementB.signals that a ctivate specific functions(e.g. add/sub/…)C.flagsD.read or write or acknowledgement10. Symmetric Multi-Processor (SMP) system is tightly coupled by _______.A. high-speed data-link and distributed memoryB. shared RAIDs and high-speed data-linkC. distributed caches and shared memoryD. interconnect network and distributed memory11. The SMP means __________.A.Sharing Memory ProcessesB.Split Memory to PartsD.Stack and Memory Pointer D.Symmetric Multi-Processo r12.The “MESI” means states of ____________ .A.Modified, Exclusive, Stored and InclusiveB.Modified, Expected, Shared and InterruptedC.Modified, Exclusive, Shared and InvalidD.Moved, Exchanged, Shared and Invalid13.The protocol “MESI” is also called __________.A. write back policyB. write-update protocolC. write-invalidate protocolD. write through policyChapter 121.Which register is user –visible but is not directly operated in 8086 ?A. DSB. SPC. IPD. BP2.The indirect sub-cycle is occurred _____________ ?A. before fetch sub-cycleB. after execute sub-cycleC. after interrupt sub-cycleD. after fetch sub-cycle and before execute sub-cycle3.Within indirect sub-cycle , the thing the CPU must do is ______________?A. fetch operand or store resultB. fetch operand’s address from memoryC. fetch next instruction from memoryD. nothing4.In general, which register is used for relative addressing ---- the content inthis register plus the A supplied by instruction to make a target address in branch or loop instructions.A. SPB. IRC. BRD. PC5.The Memory Address Register connects to ____________ BUS .A. systemB. addressC. dataD. control6.The Memory Buffer Register links to ________ BUS.A. systemB. addressC. dataD. control7.After Indirect cycle , there is a ______________ cycle .A. FetchB. IndirectC. ExecuteD. Interrupt8.The Interrupt cycle is __________ ______ Execute cycle .A. always afterB. never afterC. sometime afterD. maybe before9.The correct cycle sequence is _________________ .A. Fetch , Indirect , Execute and InterruptB. Fetch , Execute , Indirect and InterruptC. Fetch , Indirect , Interrupt and ExecuteD. Indirect , Fetch , Execute and Interrup10.The aim of the indirect cycle is to get __________________.A. an operandB. an instructionC. an address of an instructionD. an address of an operand11.Which is not in the ALU ?A. shifterB. adderC. complementerD. accumulator12.The registers in the CPU is divided _____registers and ________registers .A. general purpose , user-visibleB. user-visible , control and statusC. data , addressD. general purpose , control and status13.The Base register is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control14.The Instruction Pointer is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control15.The Index register is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control16.The Stack Pointer is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control17.The Accumulator is a(n) __________ register in 8086.A. general purposeB. dataC. addressD. control18.The Programming Status W ord is a(n) __________ register .A. general purposeB. dataC. addressD. controlShow all the micro-operations and control signals for the following instruction:1. ADD AX, X; —The contents of AC adds the contents of location X, result is stored to AC.2. MOV AX, [X];—Operand pointed by the content of location X is moved to AX, that means ((X))->AX—[ ] means indirect addressing.3. ADD AX, [BX];—Operand pointed by the content of Register BX is added to AX, that means (AX)+((BX))->AX—[ ] means register indirect addressing.4. JZ NEXT1; —If (ZF)=0,then jump to (PC)+ NEXT1.5. CALL X; —Call x function, save return address on the top of stack.6. RETURN; —From top of stack return to PC.。
绿色物流可持续发展外文翻译(节选)
绿色物流可持续发展外文翻译(节选)中文2600字，1600单词，9500英文字符文献出处：Fransoo J C. Green Logistics: Enablers for Sustainable Development [J]. Supply chain management: an international journal, 2021, 8(2): 122-131.原文GREEN LOGISTICS: ENABLERS FOR SUSTAINABLEDEVELOPMENTJan C. Fransoo1 INTRODUCTIONLogistics is the backbone of industry and commerce. As a discipline, it describes the management and coordination of activities along supply chains. These activities include freight transport, storage, inventory management, materials handling and related information processing. A large part oflogistics activities are often outsourced to specialized providers thatprovide cost- effective services. Research has shown that, at least in high income economies, the value of services is not assessed in monetary andservice quality terms alone. In making decisions, logistics professionals are increasingly taking into consideration external effects such as emissions, pollution, noise, and accidents.The last LPI report release in 2021, for instance, pointed out that in shipments to OECD countries, environmentally friendly solutions are considered far more often than elsewhere. Mounting regulatory pressure, together with changes in customer preferences, are the main drivers of this phenomenon. Oneof the more widely used terms to describe this set of preferences is green Logistics, especially when the activities of logistics service providers are concerned.Research, including a recent book by Alan McKinnon, has established that green Logistics is an emerging concern of private operators and providers and users of logistics. From a policy standpoint, and especially for the global environment, green Logistics is potentially a major topic as well: estimates vary, but about 15% of global greenhouse gas emissions (GHG) can be traced to logistics activities.Green Logistics may not be an independent policy area. Rather, the supply chain perspective provides a framework to understand and deal with issues that are separate.but ultimately interrelated. Importantly, looking at supply chains helps policy makers understand the interests and actions of private sector operators. Green Logistics may therefore propose a number of tools and identify emerging sustainable solutions contributing to the overarching objective of green Growth.From a policy perspective, logistics cut across several areas and sectors. The performance of supply chains depends on areas or activities where government as regulator or catalyst of investment is critical, such as:Transport infrastructure: road and rail corridors, ports and airportsThe efficiencies of logistics services: services include not only modal freight transport, but also warehousing and intermediary services, such as brokers and forwarders, and related information-flow management. In modern economies, the trend is towards integration in multi-activity logistics providers (3PLs, 4PLs) to which industrial and commercial firms outsourcetheir supply chain activities. Understanding the regulatory dimension of services is becoming increasingly critical to the development of effective policies in areas such as:professional and operational standards, regulation of entry in market and professions, competition, enforcement.Procedures applying to the merchandise, such as trade procedures (customs and other controls).The soft infrastructure that supports information or financial flow associated with the physical movements along supply chains: IT infrastructure, payment systems.The concept of national logistics performance capturing the outcome of these policies is widely recognized by policy makers and the private sector worldwide as a critical contribution to national competitiveness. A key question for sustainable development is how to integrate supply chain participants concern with environmental sustainability with the concept of national logistics performance.Within logistics, transport creates the largest environmental footprint. But the volume of emissions can vary greatly, depending on the mode oftransport. The volume of emission per ton per km increases by an order of magnitude from maritime to land transportation and to air transportation. This is a key environmental aspect of logistics that is not taken into consideration by most supply chain operators. Logisticsexperts typically integrate freight modes and other related activities so that the transport and distribution network is used in the most efficient manner, which is important for keeping emissions in check, as well. Depending on the type of industry and geographical region, supply chain operators can place varying emphasis on the reliability of supply chains, as well. In summary, supply chain choices typically include multiple criteria and trade-offs, and this makes an analysis of their environmental impact complex; the most environmentally friendly choices do not only depend on mode of transportation, but also on other elements, such as efficiency and reliability.To reduce the environmental footprint of a supply chain, the focus should be on several dimensions and should select the best mode of transport,efficient movements, and innovation. Comprehensive work on greening individual modes of transportation is already available. Here, the key drivers have been energy efficiency and the urge to diminish various types of emission. Given the integrated nature of supply chains, however, the manner in which price signals and incentives catalyze supply chain structure is a rather intricate problem: lower- emission modes of transport (maritime, e.g.) are typically also less reliable or have other limitations (such as maritime access to a landlocked country). Such limitations may include the cost of such technologies, the temperature range within which they can be used or the availability of certain types of fuel. It is therefore critical to complement the current knowledge about emissions produced by different modes of transportation with an understanding of what drives the demand for Green Logistics within supply chains.The emerging response is likely to take the form of top-down policy, such as measures in the form of standards or taxes addressing emissions (GHG, SO2, NOx) by mode of freight. For instance, a cap on SO2 emissions on major maritime routes will go into effect at the end of 20212. At least as important is the response from the bottom up. These are supply-chain strategies coming from the private sector in response to policy or price changes, but also demand from consumers, clients and stake-holders. Green Supply Chain management has to be taken seriously by policy makers.An exclusive focus on price mechanism (including taxes), as is the current tendency, may miss some of the major driver of changes in supply chain management. Another complication, at least in the context of international trade, is that the focus on the impact on international logistics does not capture the footprint of production processes. These processes may have different impact than the supply chain itself, as in the case of food production.There is also evidence that much of the environmental footprint of logistics operations is tied to short distances and distribution. Green Logistics is intimately linked with concerns such as urban congestion, and innovations in Logistics are critical to sustainable supply chains. Grassroots innovations in Logistics have recently flourished, often producing win-win solutions in terms of jobs and the environment. More generally, there is increasing awareness that green supply chains can be also competitive, either because the awareness of the environment helps productivity or because consumers expect it, particularly in wealthy countries.A concrete case in point is also the so-called sculpture emission regulation by IMO that enters into force on January 1, 2021 in most of North Sea, Baltic Sea and along west and east coasts of US & Canada (bar Alaska). Ships have to go over from fuel with 1.5 % sculpture to 0.1 % sculpture or invest in so-called scrubbers, that absorb the sculpture from exhaust gases; technology that is still nascent in the maritime context. Scrubber investment per cargo ship is USD 2 million and no with multiples as the ship engine size increases, with annual maintenance cost approx..7-10 % of investment. This seemingly innocent and rather technical change is going to have a huge impact on shipping and the spillover effect to other modes & Supply chains are going to be significant Green Logistics also encompasses potentially longer-term concerns. A green focus within logistics analysis could examine a supply chain vulnerability to climate events or to large swings in the price of transport inputs, for instance. A recent volcanic episode in Iceland showed the vulnerability of one specific supply chain that relies heavily on air freight fresh produce coming from Africa spoiled when flights were cancelled because of the volcanic ash. Resilience concerns and other form of uncertainty are likely to shape supply chain choices by regional and global operators.Given the importance of trade in components and intra-firm trade, how large operators develop green supply chain strategies will have profound economic impact. Resilient and greener supply chains are likely to be lessextended and leaner, for example, though the consequences for trade and integration of low income economies cannot be treated fully here.Policy makers should be concerned by both the supply and demand aspects of logistics environmental dimensions. So far, the policy focus has been on modal footprint and has not taken into account a supply chain perspective. There have not been major initiatives in Green Logistics, even in the countries most sensitive to the issue, such as those in Northern Europe. Rather the most important changes have occurred as a combination of largely uncoordinated public and private initiatives: voluntary behavior by shippers, innovation in terms of technology, information (environmental logistics dashboard) or services, or common public-private objectives such as in modal shifts.2 DEFINING GREEN LOGISTICS AND GREEN SUPPLY CHAIN MANAGEMENTThere are many variations in the terminology regarding green logistics and green supply chain management. This section aims at providing a brief overview on some of the key terms used in the literature.Green logistics refers mainly to environmental issues related to transportation, material handling and storage, inventory control, warehousing, packaging, and facility location allocation decisions (Min & Kim, 2021). Gonzalez-Benito and Gonzalez-Benito (2021) use the term environmentallogistics to describe logistics practices that are divided intosupply/purchasing, transportation, warehousing and distribution, and reverse logistics and waste management. Although distribution is considered to be one of the interrelated areas of supply chain management, the term green distribution has also been used to describe the whole process of integrating environmental concerns into transportation, packaging, labeling and reverse logistics (Shi et al., 2021).Reverse logistics is often used as a synonym to efforts to reduce the environmental impact of the supply chain by recycling, reusing and remanufacturing.译文绿色物流:促进可持续发展贾恩. 法兰斯1. 引言物流是工商业的支柱。
S3F9498中文资料
8-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 1
元器件交易网
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. S3C9498/F9498 8-Bit CMOS Microcontroller User's Manual, Revision 1 Publication Number: 21-S3-C9498/F9498-102004 © 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: FAX: (82)-(031)-209-1934 (82) (331) 209-1889 "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.
Introduction toProgramming
Do not confuse assembly and assembler
5
Source code, object code, and machine code
The translation of the source code into machine code is usually done in two steps. 1. The Assembler translate the source code into relocatable object format 2. Then another special program called a Linker, produce the final sequence of bytes that can be loaded into memory (machine code). Line assemblers translate each line of source directly into machine language. The line assemblers (a.k.a. debuggers, command line assemblers, and interactive assemblers) translate each line of source after it is entered.
… LDAA $32 BCLR 10,#5 …
23
Direct Addressing Example
24
Extended Addressing
The operand is an address not the data itself. The operand is two byte only. With a 16-bit address it is possible to access the space from $0000 to $FFFF (which is the complete microcontroller addressing space) … LDAA $1005 STAA $6D00 …
68000指令集
instruction encoding have been omitted (i.e., the actual op-code bit patterns).
ADD Add binary
Operation: [destination] ← [source] + [destination]
Syntax: ADD <ea>,Dn
ADD Dn,<ea>
LOOP ABCD -(A0),-(A1) Add a pair of digits
DBRA D0,LOOP Repeat until 9 digits added
Attributes: Size = byte, word, longword
Description: Add the source operand to the destination operand and store the
The 68000's Instruction Set
We have included this appendix to save you the task of having to turn to secondary
material when writing 68000 assembly language programs. Since most
* The bit is set or cleared according to the outcome of the instruction.
Unless an addressing mode is implicit (e.g., NOP, RESET, RTS, etc.), the legal
微控制器(MicroController)
其后16个数据单元（Bit Addressable Area: 20H～2FH）
既可作为一般的数据单元使用，也可按位对每个单元进行操作 又称为位寻址区：共计128位，其位地址为00H～0FH bits 0-7 can also be referred to as bits 20.0-20.7, and bits 8FH are the same as 21.0-21.7 and so on.
Direct addresses higher than 7FH access one memory space, and indirect addresses higher than 7FH access a different memory space. Thus the Upper 128 and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities.
MOV One-byte addresses are often used in conjunction with one or more other I/O lines to page the RAM. Two-byte addresses can also be used, in which case the high address byte is emitted at Port 2.
8位 微控制器
16位 微控制器 32位 微控制器
8051系列
Intel公司于1980年开始推出MCS-51系列单片机 Siemens、Philips和Fujitsu等公司也相继推出与之兼容的单片
c51 指令二进制
c51 指令二进制## English Answer:C51 Instruction Set.The C51 instruction set is a set of instructions used by the 8051 microcontroller. It is a reduced instruction set computer (RISC) architecture, which means that it has a small number of instructions that are designed to be executed quickly. The C51 instruction set is divided into three types:Data manipulation instructions These instructions are used to perform operations on data, such as adding, subtracting, multiplying, and dividing.Control flow instructions These instructions are used to control the flow of execution of a program, such as branching, looping, and returning from a subroutine.Input/output instructions These instructions are used to transfer data between the microcontroller and the outside world, such as reading from a port or writing to a display.The C51 instruction set is a powerful set of instructions that can be used to implement a wide variety of applications. It is a popular choice for embedded systems because of its small size, low power consumption, and high performance.Instruction Format.The C51 instructions are all 8 bits wide. The first 4 bits of an instruction specify the opcode, which is the operation that the instruction will perform. The remaining 4 bits of an instruction specify the operands, which are the data that the instruction will operate on.Addressing Modes.The C51 instruction set supports a variety ofaddressing modes, which allow instructions to access datain different ways. The most common addressing modes are:Register addressing This addressing mode allows instructions to access data in the microcontroller's registers.Immediate addressing This addressing mode allows instructions to access data that is specified in the instruction itself.Direct addressing This addressing mode allows instructions to access data in the microcontroller's memory.Indirect addressing This addressing mode allows instructions to access data in the microcontroller's memory through a pointer.Example Instructions.The following are some examples of C51 instructions:MOV A, R0 This instruction moves the contents of register R0 to register A.ADD A, #5 This instruction adds the value 5 to the contents of register A.JMP 0x1000 This instruction jumps to the address0x1000.MOVX @DPTR, A This instruction moves the contents of register A to the memory location pointed to by the DPTR register.Conclusion.The C51 instruction set is a powerful set of instructions that can be used to implement a wide variety of applications. It is a popular choice for embedded systems because of its small size, low power consumption, and high performance.## 中文回答：C51 指令集。
1559S
1FeaturesGeneral•High-performance,Low-power AVR ®(AVR3Core)Enhanced RISC Architecture –133Powerful Instructions (Most Executed in a Single Clock Cycle)•Low-power Idle and Power-down Modes•Bond Pad Locations Conforming to ISO 7816-2•ESD Protection to ±6000V •Operating Ranges:–ISO Mode:2.7V to 5.5V;PC Industry Compliant–USB Mode:3.6V to 5.5V;Compliant with USB Specification V1.1•Available in Wafers,Modules and Industry-standard PackagesMemory•64K Bytes of EEPROM,Including 64-byte OTP Area and 64-byte Bit-addressable Area–1to 128-byte Program/Erase –2ms Program,2ms Erase–Typically More than 500,000Write/Erase Cycles –10Years Data Retention•64K Bytes of Flash Program Memory–128-byte Page Programming–Minimum 10,000Write/Erase Cycles –10Years Data Retention •3K Bytes of RAMPeripherals•Two I/O Ports (Configurable to Support Communication Protocols Including ISO 7816-3and 2-wire Interfaces)•USB Interface (4Endpoints)–USB V1.1Full-speed (12Mbps)Certified,Suspend/Resume Modes Supported –3Configurable Endpoints in Addition to Endpoint EP0–2Endpoints with Double-buffering Capability (Ping-pong Mode)–Dynamic Pull-up Attachment •DMA Controller•Automatic USB/ISO Interface Detection Circuitry •Two 16-bit Timers•Random Number Generator (FIPS 140-1)•2-level,8-vector Interrupt Controller•Hardware DES and Triple DES DPA Resistant •Checksum Accelerator •Crypto-coprocessor–Pre-programmed Functions for Cryptography and Authentication Including RSA,DSA,Key Generation,ECCSecurity•Dedicated Hardware for Protection Against SPA/DPA Attacks •Advanced Protection Against Physical Attack •Environmental Protection Systems •Voltage and Frequency Monitors•Secure Memory Management/Access Protection (Supervisor Mode)Development Tools•Hardware Development Support on Voyager Emulation Platform (ATV1)Note:This is a summary document.A complete document is available under NDA.For more information,please contact your local Atmel sales office.2AT90SC6464C-USB1559BS–8/02DescriptionThe AT90SC6464C-USB is a low-power,high-performance,8-bit microcontroller,based on the new AVR3enhanced RISC architecture,featuring Flash program memory,EEPROM data memory and a 16-bit crypto-coprocessor dedicated to per-forming fast encryption and authentication functions.The new AVR3core allows linear addressing of up to 8M bytes of code and up to 16M bytes of data,and provides a num-ber of new functional and security features.This new core executes powerful instructions in a single clock cycle,and allows the AT90SC6464C-USB to achieve throughputs close to 1MIPS per MHz.The Harvard architecture includes 32general-purpose working registers directly connected to the ALU,allowing two independent registers to be accessed in one single instruction executed in one clock cycle.The AT90SC6464C-USB includes 128K bytes of Atmel’s high density,nonvolatile memory.The on-chip downloadable Flash allows the program memory to be reprogrammed in-system.This technology combined with the versatile 8-bit CPU on a monolithic chip provides a highly flexible and cost-effective solution to many smart card applications.Additional security features include power and frequency protection logic,logical scrambling on program data and addresses,Power Analysis countermeasures and memory accesses controlled by a supervisor mode.Pin ConfigurationThe AT90SC6464C-USB pinout conforms to the ISO 7816-2and USB Full-speed V1.1Interface specifications (the USB interface requires the addition of an external 4MHz clock signal or 4MHz crystal).A second I/O port is also provided,.Note:By convention RST corresponds to RST in the ISO Interface protocol.RST in all cases,however,remains active low.Architectural OverviewThe AT90SC6464C-USB is based on the AVR (core #3)enhanced RISC architecture (see Figure 1).The fast-access register file contains 32x 8-bit general-purpose working registers,each of which can be accessed in a sin-gle clock cycle.Furthermore,the high-performance ALU (Arithmetic Logic Unit)operates directly on the 32general-purpose working registers.This allows the processor to execute a complete ALU operation in a single clock cycle—two operands are output from the register file,the operation is executed,and the result is stored back in the register file,all in the same clock cycle.The ALU operations are divided into three main categories:arithmetic,logical and bit-functions.3AT90SC6464C-USB1559BS–8/02Six of the 32general-purpose registers can be used as three 16-bit indirect address register pointers X,Y ,and Z,for addressing data space and allowing efficient address calculations.As the A T90SC6464C-USB has more than 64K bytes of data space to address,registers RAMPX,RAMPY and RAMPZ are concatenated with the X,Y and Z registers respectively for indirect addressing.RAMPD is concatenated with a part of the instruction word to enable direct addressing of 16M bytes of data (using LDS or STS).EIND is concatenated with register Z to enable extended indirect jumps and calls on 4M words of code (using EIJMP or EICALL).Figure 1.The AT90SC6464C-USB AVR Enhanced RISC ArchitectureThe ALU performs arithmetic and logical operations on the contents of single registers,pairs of registers and between reg-isters and constant values.Conventional memory addressing modes can be used to access the register file,as these registers are assigned to the 32lowermost data space addresses.The I/O memory space contains 64addresses for CPU peripheral functions such as control registers,timer/counters,inter-nal and external interrupts,serial pins,and other I/O functions.The I/O memory space can be accessed directly,or as data space locations.One hundred and sixty additional peripherals registers are available.The AVR3core uses a Harvard architecture,with separate address spaces for program memory and data memory.Differ-ent addresses are used by the same memory block if used for program or data.The FLASH program memory is accessed with single level pipelining;while one instruction is being executed,the next instruction is pre-fetched from the program memory.This mechanism allows each instruction to be executed in a single clock cycle.The EEPROM includes 64bytes of bit-addressable memory and 64bytes of OTP (One Time Programmable)memory.The 22-bit Program Counter (PC)on AT90SC6464C-USB can address 4M words (8M bytes)of program memory.Most AVR instructions have a single 16-bit word format.Every program memory address contains a 16-bit or 32-bit instruc-tion.The 3K bytes of data RAM can be accessed easily through the five different addressing modes supported in the AVR architecture.©Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products,other than those expressly contained in the Com-pany’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site.The Company assumes no responsibility for any errors which may appear in this document,reserves the right to change devices or specifications detailed herein at any time without notice,and does not make any commitment to update the information contained herein.No licenses to patents or other intellectual property of Atmel are granted by the Com-pany in connection with the sale of Atmel products,expressly or by implication.Atmel’s products are not authorized for use as critical compo-nents in life support devices or systems.Corporate Headquarters,2325Orchard Parkway,San Jose,CA 95131,TEL (408)441-0311,FAX (408)487-2600Atmel Colorado Springs,1150E.Cheyenne Mtn.Blvd.,Colorado Springs,CO 80906,TEL (719)576-3300,FAX (719)540-1759Atmel Grenoble,Avenue de Rochepleine,BP 123,38521Saint-Egreve Cedex,France,TEL (33)4-7658-3000,FAX (33)4-7658-3480Atmel Heilbronn,Theresienstrasse 2,POB 3535,D-74025Heilbronn,Germany,TEL (49)7131672594,FAX (49)7131672423Atmel Nantes,La Chantrerie,BP 70602,44306Nantes Cedex 3,France,TEL (33)024*******,FAX (33)024*******Atmel Rousset,Zone Industrielle,13106Rousset Cedex,France,TEL (33)4-4253-6000,FAX (33)4-4253-6001Atmel Smart Card ICs,Scottish Enterprise Technology Park,East Kilbride,Scotland G750QR,TEL (44)1355-357-000,FAX (44)1355-242-743on recycled paper.A flexible interrupt controller has its control registers in the I/O space with an additional global interrupt enable bit in the sta-tus register.Each of the interrupts has a separate interrupt vector in the interrupt vector table at the beginning of the program memory.The different interrupts are prioritized according to their programmed priority level.When two interrupts with the same priority are detected at the same time,the interrupt with the lower source number is serviced first.USB Module Functional DescriptionUSB Hardware BlockThe USB interface consists of a Serial Interface Engine (SIE)and a Universal Function Interface (UFI).The SIE performs clock/data separation,NRZI encoding and decoding,bit stuffing,CRC generation and checking,and serial-parallel data conversion.The UFI connects the USB interface to the AVR.It consists of a protocol engine and provides four configurable data trans-fer endpoints,each with its own DPRAM in the memory area.The data transfer type for each endpoint is configured by software.The table below indicates the size of each endpoint.Note:Ping-pong (double-buffering)mode is a special proprietary feature,transparent to the user,that allows software to read data from one bank while the hardware fills another bank,thereby saving processing and transaction time.The bus controller manages the device addresses,monitors the status of the transaction,manages the DPRAMs and com-municates with the AVR through a set of status and control registers,the UFI registers.USB Software BlockThe function controller must be implemented in the firmware of the microcontroller.This software must comply with Chapter 9of the USB specifications V1.1.Enumerating and executing functions should be done using USB interrupts (polling is possible but is more complicated to manage).1559BS–8/02ATMEL ®and AVR ®are the registered trademarks of Atmel Corporation.Other terms and product names may be the trademark of others.。
instruction(完成)
– One operand can be memory.
Load-store architectures
– All operands are registers (except for load/store) 3
Four Architecture Classes
Instructions for Control Flow
Instruction Format
The Role of Compilers
The MIPS Architecture
Conclusion
CDA 5155 – Spring 2012
Copyright © 2012 Prabhat Mishra
Some architectures support a decimal format
Packed decimal or binary-coded decimal (BCD)
Why?
(0.10)10 = (?)2 Answers
0.10 0.0001 0.1010 0.000110011
Some decimal fractions does not have exact representation in binary.
SPEC CPU2000 on Alpha
Sign bit is not counted
© 2003 Elsevier Science (USA). All rights reserved.
12
Addressing Mode for FFT
FFTs start or end their processing with data shuffled in a particular order.
MSP430单片机课件
5
MSP430 main characteristics (2/3)
UBI
On-chip analogue features: 10/12/16-bit Analogue-to-Digital Converter (ADC); 12-bit dual Digital-to-Analogue Converter (DAC); Comparator-gated timers; Operational Amplifiers (Op Amps); Supply Voltage Supervisor (SVS). 16 bit RISC CPU: Compact core design reduces power consumption and cost; 16-bit data bus; 27 core instructions; 7 addressing modes; Extensive vectored-interrupt capability.
>> Contents
Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt
3
Microcontroller characteristics
UBI
Integration: Able to implement a whole design onto a single chip. Cost: Are usually low-cost devices (a few $ each); Clock frequency: Compared with other devices (microprocessors and DSPs), MCUs use a low clock frequency: MCUs today run up to 100 MHz/100 MIPS (Million Instructions Per Second). Power consumption: Low power (battery operation); Bits: 4 bits (older devices) to 32 bits devices; Memory: Limited available memory, usually less than 1 MByte;
IA-32指令集汇编语言说明书
for (j=0; j<4; j++) printf("Byte %d: %x\n", j, p[j]);
}
Byte 0: ff"
Output on a
Byte 1: 77"
little-endian
Byte 2: 33"
machine
Byte 3: 0"
6
IA-32 General Purpose Registers"
char i; … if (i > 5) {
i++; else
i--; }
cmpb $5, %al jle else incb %al jmp endif else: decb %al endif:
8
C Example: Four-Byte Data"
Global int variable i is in %eax, the full 32 bits of the “A” register.
• Character: 1 byte! • Short, int, and long: varies, depending on the computer! • Float and double: varies, depending on the computer! • Pointers: typically 4 bytes!
• Register addressing!
• Example: movl %edx, %ecx" • Choice of register(s) embedded in the instruction! • Copy value in register EDX into register ECX!
AppJ
J-2 J-3 J-45 J-65 J-83 J-90
J
Survey of Instruction Set Architectures
RISC: any computer announced after 1985.
Steven Przybylski
A Designer of the Stanford MIPS
J-2
I
Appendix J Survey of Instruction Set Architectures
J.1
Introduction
This appendix covers 13 instruction set architectures, some of which remain a vital part of the IT industry and some of which have retired to greener pastures. We keep them all in part to show the changes in fashion of instruction set architecture over time. We start with ten RISC architectures. There are billions of dollars of computers shipped each year for ARM (including Thumb), MIPS (including MIPS16), Power, and SPARC. Indeed, ARM dominates embedded computing. However, the Digital Alpha and HP PA-RISC were both shoved aside by Itanium, and they remain primarily of historical interest. The 80x86 remains a dominant ISA, dominating the desktop and the low-end of the server market. It has been extended more than any other ISA in this book, and there are no plans to stop it soon. Now that it has made the transition to 64-bit addressing, we expect this architecture to be around longer than your authors. The VAX typifies an ISA where the emphasis was on code size and offering a higher level machine language in the hopes of being a better match to programming languages. The architects clearly expected it to be implemented with large amounts of microcode, which made single chip and pipelined implementations more challenging. Its successor was the Alpha, which had a short life. The vulnerable IBM 360/370 remains a classic that set the standard for many instruction sets to follow. Among the decisions the architects made in the early 1960s were:
11_ Instruction Sets addressing modes汇总
18
Indexed Addressing • • • • A = base R = displacement EA = A + R Good for accessing arrays
—EA = A + R —R++
19
Combinations • Postindex • EA = (A) + (R) • Preindex • EA = (A+(R)) • (Draw the diagrams)
— Starting address plus offset gives linear address — This goes through page translation if paging enabled
• 12 addressing modes available
— Immediate — Register operand — Displacement — Base — Base with displacement — Scaled index with displacement — Base with index and displacement — Base scaled index with displacement — Relative
• Arithmetic
— Operands in registers or part of instruction — Floating point is register only
24
PowerPC Memory Operand Addressing Modes
25
Instruction Formats
Memory Pointer to operand
现代计算机体系结构--CPU(英文版)(ppt 31页)PPT学习课件
–PowerPC指令功能强，灵活，甚至有点象CISC
9
2 Instruction pipeline
• Most instructions are register to register • Two phases of execution
– I: Instruction fetch – E: Execute
• ALU operation with register input and output
• For load and store
– I: Instruction fetch – E: Execute
• Calculate memory address
– D: Memory
• Register to memory or memory to register operation
12
Normal and Delayed Branch
Address
Hale Waihona Puke Normal Branch
Delayed Branch
Optimized Delayed Branch
100
LOAD X, rA
LOAD X, rA
LOAD X, rA
101
ADD 1, rA
ADD 1, rA
JUMP 105
102
2
1 CISC & RISC
• Why CISC (1)? • Compiler simplification?
– Disputed… – Complex machine instructions harder to exploit – Optimization more difficult
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Addressing Modes
The addressing modes in the MCS-51 instruction set are as follows
●DIRECT ADDRESSING
In direct addressing, the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRS can be directly addressed.
●INDIRECT ADDRESSING
In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit “data pointer” register, DPTR.
●REGISTER INSTRUCTIONS
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction.
Instructions that access the registers this way are code efficient, since this mode eliminated an address byte. When the instruction is executed one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW.
●REGISTER-SPECIFIC INSTRUCTIONS
Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode itself does that. Instructions that refer to the Accumulator as A assemble as accumulator-specific opcodes.
●IMMEDIATE CONSTANTS
The value of a constant can follow the opcode in Program Memory. For example,
MOV A, # 100
loads the Accumulator with the decimal number 100.
The same number could be specified in hex digits as 64H.
●INDEXED ADDRESSING
Only Program Memory can be accessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program
A 16-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is setup with the table entry number. The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer.
Another type of indexed address ing is used in the “case jump” instruction. In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data.
●RELATIVE ADDRESSING & RELATIVE OFFSET
The destination address for these jumps is specified to the assembler by a label or by an actual address in Program Memory. However, the destination address assembles to a relative offset byte. This is a signed (two’s complement) of fset byte which is added to the PC in two’s complement arithmetic if the jump is executed.
The range of the jump is therefore -128 to + 127 Program Memory bytes relative to the first byte following the instruction.
●Boolean Instructions
MCS-51 devices contain a complete Boolean (single-bit) processor. The internal RAM contains 128 addressable bits, and the SFR space can support up to 128 other addressable bits. All of the port lines are bit-addressable and each one can be treated as a separate single bit port.
The instructions that access these bits are not just conditional branches, but a complete menu of move, set, clear, complement, OR and AND instructions.
These kinds of bit operations are not easily obtained in other architectures with any amount of byte-Oriented Software.。