ASIC第二次作业

完整程序 证明：
P _ odd [n 1] P _ odd [n] ^ D _ in[n]; P _ odd [n] P _ odd [n 1] ^ D _ in[n 1]; P _ odd [1] P _ odd [0] ^ D _ in[0]=0^D _ in[0] D _ in[0]; P _ odd [2] P _ odd [1] ^ D _ in[1] D _ in[0] ^ D _ in[1]; P _ odd [n] P _ odd [n 1] ^ D _ in[n 1] D _ in[0] ^ D _ in[1] ^ D _ in[n 1];
5-15. 设计并验证符合下面规范的4位二进制同步计数
器的Verilog模型：下降沿同步、同步装载与复位、数 据并行装载和低有效使能计数。
输入：时钟，使能，复位，装载 输出：计数
`timescale 1ns / 1ps module ch5_15( input clk, input reset, input enable, input load, input [3:0]loadData, output reg [3:0]Count ); always @ (negedge clk) if(reset)begin Count <= 0; end else if(enable) if(load)begin Count <= loadData; end else begin Count <= Count + 1'b1; end else begin Count <= Count; end endmodule
`timescale 1ns / 1ps module ch5_14( ); reg clk; reg D_in; reg reset; wire tempD; reg P_odd; always @ (posedge clk) if(reset)begin P_odd <= 0; end else begin P_odd <= tempD; end assign tempD = P_odd^D_in; //test always @(posedge clk) if(reset)begin D_in <= 1'b0; end else D_in <=$random; always #5 clk = ~clk; initial begin reset =0; clk =0; #20 reset = 1; forever #30 reset =0; end endmodule
initial begin clk =0; forever #10 clk = ~clk; end initial begin reset =0; #15 reset=1; forever #70 reset =0; end initial begin enable =1; # 200 enable =0; forever #30 enable =1; end initial begin load =0; #300 load=1; forever #20 load=0; end initial begin loadData =0; #300 loadData =7; forever #20 loadData =0; end endmodule
设计 模块
测试 模块
`timescale 1ns / 1ps module test( ); reg clk,reset,enable,load; reg [3:0]loadData; wire [3:0]Count; ch5_15 ut( .clk(clk), .reset(reset), .enable(enable), .load(load), .loadData(loadData), .Count(Count) );
设计 模块
ቤተ መጻሕፍቲ ባይዱ
测试 模块
`timescale 1ns / 1ps module test( ); reg clk,reset,enable,load; reg [3:0]loadData; wire [3:0]Count; ch5_15 ut( .clk(clk), .reset(reset), .enable(enable), .load(load), .loadData(loadData), .Count(Count) );
initial begin clk =0; forever #10 clk = ~clk; end initial begin reset =0; #15 reset=1; forever #70 reset =0; end initial begin enable =1; # 200 enable =0; forever #30 enable =1; end initial begin load =0; #300 load=1; forever #20 load=0; end initial begin loadData =0; #300 loadData =5; forever #20 loadData =0; end endmodule
ASIC第二次作业
（参考答案）
5-14. 编写图P5.14所示电路的Verilog描述，证明：
如果D_in的连续取样值具有奇数个1，那么电路的输出 P_odd有效。
wire tempD; always @ (posedge clk) if(reset) begin P_odd <= 0; end else begin P_odd <= tempD; end assign temp = P_odd^D_in; endmodule
5-19. 设计并验证模6计数器的Verilog模型。
为了方便，直接在第15题的基础上修改 那么需要思考，模6的位置放在那里？
`timescale 1ns / 1ps module ch5_19( input clk, input reset, input enable, input load, input [2:0]loadData, output reg [2:0]Count ); always @ (negedge clk) if(reset)begin Count <= 0; end else if(enable) if(load)begin Count <= loadData; end else begin if(Count==5)begin Count <=0; end else begin Count <= Count + 1'b1; end end else begin Count <= Count; end endmodule