AT24C1024
AT24系列的读写注意事项
AT24系列的读写注意事项AT24系列的读写注意事项所看过的对24系列I2C读写时序描述最准确最容易理解的资料，尤其是关于主从器件的应答描述和页写描述，看完后明白了很多。
关于页写的描述，网络上绝大部分范程都没提到页写时的数据地址必须是每页的首地址才能准确写入，而且如果写入超过一页的数据会循环覆盖当前页的数据。
关于IIC总线I2C总线：i2c总线是Philips 公司首先推出的一种两线制串行传输总线。
它由一根数据线（SDA）和一根时钟线（SDL）组成。
i2c总线的数据传输过程如图3所示，基本过程为：1、主机发出开始信号。
2、主机接着送出1字节的从机地址信息，其中最低位为读写控制码（1为读、0为写），高7位为从机器件地址代码。
3、从机发出认可信号。
4、主机开始发送信息，每发完一字节后，从机发出认可信号给主机。
5、主机发出停止信号。
I2C总线上各信号的具体说明：开始信号：在时钟线（SCL）为高电平其间，数据线（SDA）由高变低，将产生一个开始信号。
停止信号：在时钟线（SCL）为高电平其间，数据线（SDA）由低变高，将产生一个停止信号。
应答信号：既认可信号，主机写从机时每写完一字节，如果正确从机将在下一个时钟周期将数据线（SDA）拉低，以告诉主机操作有效。
在主机读从机时正确读完一字节后，主机在下一个时钟周期同样也要将数据线（SDA）拉低，发出认可信号，告诉从机所发数据已经收妥。
（注：读从机时主机在最后1字节数据接收完以后不发应答，直接发停止信号）。
注意：在I2C通信过程中，所有的数据改变都必须在时钟线SCL 为低电平时改变,在时钟线SCL为高电平时必须保持数据SDA信号的稳定,任何在时钟线为高电平时数据线上的电平改变都被认为是起始或停止信号。
作为一种非易失性存储器（NVM），24系列EEPROM使用的很普遍，一般作为数据量不太大的数据存储器。
下面总结一下其应用的一些要点。
从命名上看，24CXX中XX的单位是kbit，如24C08，其存储容量为8k bit，即1k Byte＝1024 Byte。
串行EEPROM AT24CXX芯片资料
串行EEPROM AT24CXX芯片资料AT24CXX是美国ATMEL公司的低功耗CMOS串行EEPROM，典型的型号有AT24C01A/02/04/08/16等5种，它们的存储容量分别是1024/2048/4096/8192/16384位；也就是128/256/512/1024/2048字节；使用电压级别有5V，2.7V,2.5V,1.8V;本文主要介绍常用的AT24C02即256字节存储器的使用；它具有工作电压宽（2.5～5.5V）、擦写次数多（大于10000次）、写入速度快（小于10ms）等特点。
外行如图：AT24C02的1、2、3脚是三条地址线，用于确定芯片的硬件地址（实验板中直接接地只有一块器件）；第8脚和第4脚分别为正、负电源。
第5脚SDA为串行数据输入/输出，数据通过这条双向I2C总线串行传送，SDA和SCL都需要和正电源间各接一个5.1K的电阻上拉。
第7脚为WP写保护端，接地时允许芯片执行一般的读写操作。
接电源端时不允许对器件写。
24C02中带有片内地址寄存器。
每写入或读出一个数据字节后，该地址寄存器自动加1，以实现对下一个存储单元的读写。
所有字节均以单一操作方式读取。
为降低总的写入时间，一次操作可写入多达8个字节的数据。
;这是将0100H地址中以下的8个数据写到24C02的01H为首址单元中去的汇编程序可直接在实验板上实验。
ORG 0000HSCL BIT P3.7;定义24C02的串行时钟线SDA BIT P3.6;定义24C02的串行数据线LJMP STARTSTART:LCALL STAR;调用MOV R2,#08H;一个数据有8位MOV DPTR,#0100H;定义源数据的位置LOOP:MOV A,#00HMOVC A,@A+DPTRLCALL SDATALCALL ACKJC LOOPINC DPTRDJNZ R2,LOOPLCALL STOP;调用停止子程序STAR:SETB SDASETB SCLNOPNOPNOPNOPCLR SDANOPNOPNOPNOPCLR SCLRETSDATA:MOV R0,#08HLOOP0:RLC AMOV SDA,CNOPNOPSETB SCLNOPNOPNOPCLR SCLDJNZ R0,LOOP0 RETACK:SETB SDA NOPNOPSETB SCL NOPNOPNOPNOPMOV C,SDA CLR SCLRETSTOP:CLR SDA NOPNOPNOPNOPSETB SCL NOPNOPNOPNOPSETB SDANOPNOPNOPRETORG 0100HDB 0A0H,10H,01H,02H,03H,04H,05H,06HEND读写子程序如下：;写串行E2PROM子程序XEPR; R3=10100000（命令1010+器件3位地址+读/写。
串行eepromat24cxx芯片资料
串行EEPROM AT24CXX芯片资料AT24CXX是美国ATMEL公司的低功耗CMOS串行EEPROM，典型的型号有AT24C01A/02/04/08/16等5种，它们的存储容量分别是1024/2048/4096/8192/16384位；也就是128/256/512/1024/2048字节；使用电压级别有5V，2.7V,2.5V,1.8V;本文主要介绍常用的AT24C02即256字节存储器的使用；它具有工作电压宽（2.5～5.5V）、擦写次数多（大于10000次）、写入速度快（小于10ms）等特点。
外行如图：AT24C02的1、2、3脚是三条地址线，用于确定芯片的硬件地址（实验板中直接接地只有一块器件）；第8脚和第4脚分别为正、负电源。
第5脚SDA为串行数据输入/输出，数据通过这条双向I2C总线串行传送，SDA和SCL 都需要和正电源间各接一个5.1K的电阻上拉。
第7脚为WP写保护端，接地时允许芯片执行一般的读写操作。
接电源端时不允许对器件写。
24C02中带有片内地址寄存器。
每写入或读出一个数据字节后，该地址寄存器自动加1，以实现对下一个存储单元的读写。
所有字节均以单一操作方式读取。
为降低总的写入时间，一次操作可写入多达8个字节的数据。
;这是将0100H地址中以下的8个数据写到24C02的01H为首址单元中去的汇编程序可直接在实验板上实验。
ORG 0000HSCL BIT P3.7;定义24C02的串行时钟线SDA BIT P3.6;定义24C02的串行数据线LJMP STARTSTART:LCALL STAR;调用MOV R2,#08H;一个数据有8位MOV DPTR,#0100H;定义源数据的位置LOOP:MOV A,#00HMOVC A,@A+DPTRLCALL SDATALCALL ACKJC LOOPINC DPTRDJNZ R2,LOOPLCALL STOP;调用停止子程序STAR:SETB SDASETB SCLNOPNOPNOPNOPCLR SDANOPNOPNOPNOPCLR SCLRETSDATA:MOV R0,#08HLOOP0:RLC AMOV SDA,CNOPNOPSETB SCLNOPNOPNOPCLR SCLDJNZ R0,LOOP0 RETACK:SETB SDA NOPNOPSETB SCL NOPNOPNOPNOPMOV C,SDA CLR SCLRETSTOP:CLR SDA NOPNOPNOPNOPSETB SCL NOPNOPNOPNOPSETB SDANOPNOPNOPRETORG 0100HDB 0A0H,10H,01H,02H,03H,04H,05H,06HEND读写子程序如下：;写串行E2PROM子程序XEPR; R3=10100000（命令1010+器件3位地址+读/写。
四片AT24C1024组成的存储器
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AT24C1024介绍
AT24C10242 线串行EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8 位=1M2 线串行接口施密特触发器，噪声抑制滤波输入双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V) 硬件写保护引脚和软件数据保护256 字节页写模式(允许部分页面写入)随机和顺序读写模式自定义写周期(5ms)高可靠性：耐久力：写周期/页100,000 次数据保留：40 年8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚无铅阵列和8 引脚球状dBGA 封装描述AT24C1024 提供1,048,567 位的串行可电擦除和可编程只读存储器（EEPROM），它的每8 位组成一个字节，共131,072 个字节。
该设备的级联功能允许多达2 个设备共亨同一条2- 线总线。
该设备适合用于许多工业和商业，应用必要的低功耗和低电压的操作。
该器件可提供节省空间的8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚无铅阵列和8 引脚球状dBGA 封装。
另外，这一系列产品允许在2.7V（2.7V~5.5V）下工作。
绝对最大额定值：工作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最大工作电压：6.25V 直流输出电流：5.0mA注意：强制高出“绝对最大额定值”可能导致设备的永久损坏。
设备的压力等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。
长时间工作在绝对最大额定值的条件下可能影响设备的可靠性。
引脚描述：串行时钟（SCL）：SCL 的输入是在时钟的上升沿数据进入每个EEPROM 设备和下降沿数据输出每个设备。
串行数据（SDA）：SDA 引脚是双向串行数据传输的。
这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。
器件/ 页地址（A1 ）：A1 引脚是设备的输入地址，它能够通过导线与不兼容的设备AT24C128/256/512 连接。
AT24C1024W-10SU-2.7;AT24C1024Y4-10YU-2.7;AT24C1024W-10SU-2.7 SL383;中文规格书,Datasheet资料
1Features•Low-voltage Operation –2.7 (V CC = 2.7V to 5.5V)•Internally Organized 131,072 x 8•Two-wire Serial Interface•Schmitt Triggers, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•400 kHz (2.7V) and 1 MHz (5V) Clock Rate•Write Protect Pin for Hardware and Software Data Protection •256-byte Page Write Mode (Partial Page Writes Allowed)•Random and Sequential Read Modes •Self-timed Write Cycle (5 ms Typical)•High Reliability–Endurance: 100,000 Write Cycles/Page –Data Retention: 40 Years•8-lead PDIP , 8-lead EIAJ SOIC, 8-lead LAP and 8-lead SAP Packages •Die Sales: Wafer Form, Waffle Pack and Bumped DieDescriptionThe AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to two devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applicationswhere low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead PDIP , 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V)versions.Table 1. Pin ConfigurationsPin Name Function A1Address Input SDA Serial Data SCL Serial Clock Input WP Write Protect NCNo Connect8-lead PDIP8-lead Leadless ArrayBottom View 8-lead SOIC8-lead SAPBottom View2AT24C10241471O–SEEPR–3/07Figure 1. Block DiagramAbsolute Maximum Ratings*Operating Temperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage..........................................6.25V DC Output Current........................................................5.0 mA3AT24C10241471O–SEEPR–3/07Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/ADDRESSES (A1): The A1 pin is a device address input that can be hardwired or left not connected for hardware compatibility with other AT24Cxx devices. When the A1 pin is hardwired, as many as two 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the A1 pin is left floating, the A1 pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the A1 pin to GND.WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to V CC , all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recom-mends connecting the pin to GND. Switching WP to V CC prior to a write operation creates a software write-protect function.MemoryOrganizationAT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address.4AT24C10241471O–SEEPR–3/07Table 2. Pin Capacitance (1)Table 3. DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 1, SCL)6pFV IN = 0VApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +2.7V to +5.5V, T AC = 0°C to +70°C,V CC = +2.7V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC Supply Voltage 2.75.5V I CC Supply Current V CC = 5.0V READ at 400 kHz 2.0mA I CC Supply Current V CC = 5.0V WRITE at 400 kHz 5.0mA I SB Standby Current V CC = 2.7V V IN = V CC or V SS3.0µA V CC = 5.5V 6.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL Output Low LevelV CC = 3.0VI OL = 2.1 mA0.4V5AT24C10241471O–SEEPR–3/07Table 4. AC Characteristics (1)R L (connects to V CC ): 1.3 k Ω (2.7V, 5V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤50 nsInput and output timing reference voltages: 0.5 V CC 2.This parameter is ensured by characterization only.Applicable over recommended operating range from T A = –40°C to +85°C, V CC = +2.7V to +5.5V, C L = 100 pF (unless otherwise noted)Symbol ParameterTest Conditions MinMax Units f SCL Clock Frequency, SCL 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 1000400kHz t LOW Clock Pulse Width Low 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.41.3µs t HIGH Clock Pulse Width High 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.40.6µs t AA Clock Low to Data Out Valid4.5V ≤ V CC ≤5.5V 2.7V ≤ V CC ≤ 5.5V 0.050.050.550.9µs t BUF Time the bus must be free before a new transmission can start (2) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.51.3µs t HD.STA Start Hold Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.250.6µs t SU.STA Start Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t HD.DAT Data In Hold Time 0µs t SU.DAT Data In Setup Time 100ns t R Inputs Rise Time (2)0.3µs t F Inputs Fall Time (2) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 100300ns t SU.STO Stop Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t DH Data Out Hold Time 50ns t WRWrite Cycle Time10ms Endurance (2) 5.0V, 25°C, Page Mode 100KWrite Cycles6AT24C10241471O–SEEPR–3/07Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)upon power-up and b)after the receipt of the stop bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.Device Power Up And Power Down RecommendationPOWER UP: It is recommended to power up from 0V to full VCC in less than 1ms and then hold for at least 100µs at full VCC level before first operation.POWER DOWN: It is recommended to power down from full VCC to 0V in less than 1ms and then hold at 0V for at least 0.5s before power up. It is not recommended to VCC power down to non-zero volt and then slowly go to zero volt.7AT24C10241471O–SEEPR–3/07Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O ®)Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4.Data Validity8AT24C10241471O–SEEPR–3/07Figure 5. Start and Stop DefinitionFigure 6. Output AcknowledgeDevice AddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7 on page 11). The device address word consists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all two-wire EEPROM devices.The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state.DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC.9AT24C10241471O–SEEPR–3/07WriteOperationsBYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0 bit of the device address, then the most significant word address followed by the least significant word address (see Figure 8 on page 11)A write operation requires the P 0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, T WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11).PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (see Figure 9 on page 11).The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “rollover” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.10AT24C10241471O–SEEPR–3/07ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover”during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 11).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 12).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (see Figure 12 on page 12).分销商库存信息:ATMELAT24C1024W-10SU-2.7AT24C1024Y4-10YU-2.7AT24C1024W-10SU-2.7SL383。
基于Proteus的IIC器件AT24C1024的应用
关 键 词 ：ｒｔ ｓＥ Ｐ Ｏ Ｄ １ｂ ０ 温 度 传感 器 Ｐｏｅ ； Ｅ Ｒ Ｍ； Ｓ ８ ２ ； ｕ
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由软件对其内容进行随机读写， 又可在芯片断电的 情况 下长时 间保存 信息， 因此 兼备 了 Ｒ Ｍ 和 Ｒ Ａ ＯＭ 的特点。Ｅ Ｐ ＯＭ有串行和并行 两大类 ，并行 ＥＲ Ｅ ＰＯ Ｅ Ｒ Ｍ存储容量较大， 读写方法简单， 但价格较 高适 用于信息量较多的场合。串行 Ｅ Ｐ ＯＭ结构 ＥＲ 简单紧凑＇ 价格低廉担 其读写方法复杂存 储单元较 小 般用于掉电情况下需要保存或一些数据需要 在线修改的场合这 类数据不多却很重要若使 用常 规的 Ｒ Ｍ芯片， Ａ 就必须附带一套性能可靠的掉电 保护系统这不仅增加了线路设计的复杂性同 时也 给设备的运行和维护带来了诸多不便。同时 Ｐｏ ｒ— ｔｕ 软件是一款单片机软硬件设计仿真平台， ｅｓ 能实 时仿 真 多种 单 片机 芯片 ，如 ５ 单 片 机 系列 、 Ｖ １ ＡＲ 单 片 机 系列 、Ｉ 片 机 系列 及 Ａｍ 单 片 机 系列 ＰＣ单 ｒ 等 ， 少 学 习单片 机 的成 本 ， 可达 到 良好 的学 可减 又 习效 果 。 １ ４ ２Ｃ系列 串行 Ｅ Ｐ Ｏ Ｅ Ｒ Ｍ介 绍 ２Ｃ系列 串行 Ｅ Ｐ Ｏ 除具 有一 般 串行 ４ ＥＲ Ｍ ＥＰ Ｏ Ｅ Ｒ Ｍ的体积小 、 功耗低 、 工作电压允许范围宽 等特 点外ｊ 具有 型号多 、 大 、 总线 协议 、 丕 容量 二 占用 ０口线少 、 容量扩展配置极其灵活方便、 读写操作 相对简单等特点 。本 系统 中使用的是 ２ Ｃ ０ ４ ４ １２ （ ２ ｋ）生产 工艺 是 Ｃ Ｓ 艺 作 电压 在 １ ～ １ ４ｂ， ０ ＭＯ Ｔ ． ８ ５ Ｖ之间２ Ｃ系列有两种封装形式： ． ５ ４ ８脚封装和 １ ４ 脚封装 。 国 目前开发 用量最 多的封装 形式 是 ８ 我 脚 ＰＩ Ｄ Ｐ封装，脚 Ｐ Ｉ ８ ＤＰ封装中 Ａ Ａ１、２为器件地 ０、 Ａ 址选择位这 ３个引脚配置成不同的编码直在同一 串行总线上最多可扩展 ８片同一容量或不同容量 的 ２ Ｃ系列串行 Ｅ Ｐ ＯＭ芯片。ＷＰ Ｅ ￣ 为硬 ４ ＥＲ ｆ Ｓ 件写保护控制端（ 测试端） 个引脚， 这 各个公 司生产 的有所不同洧 的公司将其定义为脉冲的上升沿将 数据写入 Ｅ Ｐ 下降沿将数据从 Ｅ Ｐ Ｏ Ｅ ＲＯ Ｅ Ｒ Ｍ中 读出。Ｓ Ａ为串行数据输入输出端 漏极开路驱动， Ｄ 容量扩展时， 可以将多片 ２ Ｃ系列 Ｓ Ａ引脚直接 ４ Ｄ 相连，实际使用时要加一个上拉电阻－Ｃ Ｖ Ｃ和 Ｇ Ｄ Ｎ 分别是 电源和地 。 ２ Ｔ ４ ２ ２ Ｃ ０ ４硬件 电路 的应用 设计 Ａ １ 系统应用电路如图 １ 所示， 时钟芯片接 Ｐ 端 ｌ 口的 Ｐ ． Ｐ ．和 Ｐ ． １、１ ０ １ １ ２引脚 ， 提供实时时间； 温度传 感器接 Ｐ 端 口的 Ｐ ．， ｌ １ 测量外界的温度； ７ 由于 ５ １ 单片机没有 Ｉ Ｉ 口，可以利用单片机的 Ｐ 端口 Ｃ接 ３
基于Proteus的IIC器件AT24C1024的应用
基于Ｐｒｏｔｅｕｓ的ＩＩＣ器件ＡＴ２４Ｃ１０２４的应用作者：袁易君来源：《中国新技术新产品》2008年第24期摘要：本文采用软件仿真平台Proteus介绍了AT24C1024 EEPROM的使用及其特点,以及在具有DS1302时钟芯片、DS18b20温度传感器的具体应用系统中的使用，本系统对每隔一段时间的温度进行了存储。
关键词：Proteus；EEPROM；DS18b20；温度传感器电可擦除可编程EEPROM 在应用系统中既可由软件对其内容进行随机读写,又可在芯片断电的情况下长时间保存信息, 因此兼备了RAM 和ROM 的特点。
EEPROM 有串行和并行两大类，并行EEPROM 存储容量较大,读写方法简单,但价格较高,适用于信息量较多的场合。
串行EEPROM结构简单紧凑,价格低廉,但其读写方法复杂,存储单元较小,一般用于掉电情况下需要保存或一些数据需要在线修改的场合,这类数据不多却很重要,若使用常规的RAM芯片,就必须附带一套性能可靠的掉电保护系统,这不仅增加了线路设计的复杂性,同时也给设备的运行和维护带来了诸多不便。
同时Proteus软件是一款单片机软硬件设计仿真平台，能实时仿真多种单片机芯片，如51单片机系列、AVR单片机系列、PIC单片机系列及Arm单片机系列等，可减少学习单片机的成本，又可达到良好的学习效果。
124C系列串行EEPROM介绍24C系列串行EEPROM除具有一般串行EEPROM 的体积小、功耗低、工作电压允许范围宽等特点外,还具有型号多、容量大、二总线协议、占用I/ O 口线少、容量扩展配置极其灵活方便、读写操作相对简单等特点。
本系统中使用的是24C1024(1024kb) ,生产工艺是CMOS 工艺,工作电压在1.8～5.5V 之间,24C系列有两种封装形式:8 脚封装和14 脚封装。
我国目前开发用量最多的封装形式是8脚PDIP 封装,8 脚PDIP封装中A0 、A1 、A2 为器件地址选择位,这3 个引脚配置成不同的编码值,在同一串行总线上最多可扩展8 片同一容量或不同容量的24C 系列串行EEPROM 芯片。
AT24C1024W-10SI-2.7中文资料
1Features•Low-voltage Operation –2.7 (V CC = 2.7V to 5.5V)•Internally Organized 131,072 x 8•2-wire Serial Interface•Schmitt Triggers, Filtered Inputs for Noise Suppression •Bi-directional Data Transfer Protocol•400 kHz (2.7V) and 1 MHz (5V) Clock Rate•Write Protect Pin for Hardware and Software Data Protection •256-byte Page Write Mode (Partial Page Writes Allowed)•Random and Sequential Read Modes •Self-timed Write Cycle (5 ms Typical)•High Reliability–Endurance: 100,000 Write Cycles/Page –Data Retention: 40 Years•8-lead PDIP , 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGA TM PackagesDescriptionThe AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-ball dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.Pin ConfigurationsPin Name Function A1Address Input SDA Serial Data SCL Serial Clock Input WPWrite Protect NCNo Connect8-lead PDIP8-lead Leadless ArrayBottom View8-lead SOIC8-ball dBGABottom View2AT24C10241471H–SEEPR–03/03Block DiagramAbsolute Maximum Ratings*Operating Temperature..................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................-65°C to +150°C Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C10241471H–SEEPR–03/03Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A1): The A1 pin is a device address input that can be hard-wired or left not connected for hardware compatibility with AT24C128/256/512. When the A1pin is hardwired, as many as two 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pin is not hardwired, the default A1 is zero.WRITE PROTECT (WP): The hardware Write Protect pin is useful for protecting the entire contents of the memory from inadvertent write operations. The write-protect input, when tied to GND, allows normal write operations. When WP is tied high to V CC , all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to V CC prior to a write operation creates a software write-protect function.Memory OrganizationAT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address.4AT24C10241471H–SEEPR–03/03Pin Capacitance (1)Note:1.This parameter is characterized and is not 100% tested.DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 1, SCL)6pFV IN = 0VApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +2.7V to +5.5V, T AC = 0°C to +70°C,V CC = +2.7V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC Supply Voltage 2.75.5V I CC Supply Current V CC = 5.0V READ at 400 kHz 2.0mA I CC Supply Current V CC = 5.0V WRITE at 400 kHz 5.0mA I SB Standby Current V CC = 2.7V V IN = V CC or V SS3.0µA V CC = 5.5V 6.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)-0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL Output Low LevelV CC = 3.0VI OL = 2.1 mA0.4V5AT24C10241471H–SEEPR–03/03AC Characteristics2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.7V , 5V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤50 nsInput and output timing reference voltages: 0.5 V CCApplicable over recommended operating range from T A = -40°C to +85°C, V CC = +2.7V to +5.5V, C L = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.Symbol ParameterTest Conditions MinMax Units f SCL Clock Frequency, SCL 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 1000400kHz t LOW Clock Pulse Width Low 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.41.3µs t HIGH Clock Pulse Width High 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.40.6µs t AA Clock Low to Data Out Valid4.5V ≤ V CC ≤5.5V 2.7V ≤ V CC ≤ 5.5V 0.050.050.550.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.51.3µs t HD.STA Start Hold Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.250.6µs t SU.STA Start Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t HD.DAT Data In Hold Time 0µs t SU.DA T Data In Setup Time 100ns t R Inputs Rise Time (1)0.3µs t F Inputs Fall Time (1) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 100300ns t SU.STO Stop Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t DH Data Out Hold Time 50ns t WRWrite Cycle Time10ms Endurance (1) 5.0V , 25°C, Page Mode100KWrite Cycles6AT24C10241471H–SEEPR–03/03Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)upon power-up and b)after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles,2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C10241471H–SEEPR–03/03Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.8AT24C10241471H–SEEPR–03/03Data ValidityStart and Stop DefinitionOutput Acknowledge9AT24C10241471H–SEEPR–03/03DeviceAddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word con-sists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2-wire EEPROM devices.The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state.DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC .WriteOperationsBYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0 bit of the device address, then the most significant word address followed by the least significant word address (refer to Figure 2)A write operation requires the P 0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, T WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (refer to Figure 3).The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “rollover” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.10AT24C10241471H–SEEPR–03/03ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover”during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (refer to Figure 4).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (refer to Figure 6).11AT24C10241471H–SEEPR–03/03Figure 1. Device AddressFigure 2. Byte WriteFigure 3. Page WriteFigure 4.Current Address Read12AT24C10241471H–SEEPR–03/03Figure 5. Random ReadFigure 6.Sequential Read13AT24C10241471H–SEEPR–03/03Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.Ordering InformationOrdering CodePackage Operation RangeA T24C1024-10CI-2.7A T24C1024C1-10CI-2.7A T24C1024-10PI-2.7A T24C1024W-10SI-2.7A T24C1024-10UI-2.78CN38CN18P38S28U8Industrial (-40°C to 85°C)Package Type8CN38-lead, 0.230" Wide, Leadless Array Package (LAP)8CN18-lead, 0.300" Wide, Leadless Array Package (LAP)8P38-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)8S28-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)8U88-ball, die Ball Grid Array Package (dBGA)Options-2.7Low Voltage (2.7V to 5.5V)14AT24C10241471H–SEEPR–03/03Packaging Information8CN3 – LAP15AT24C10241471H–SEEPR–03/038CN1 – LAP16AT24C10241471H–SEEPR–03/038P3 – PDIP17AT24C10241471H–SEEPR–03/038S2 – EIAJ SOIC18AT24C10241471H–SEEPR–03/038U8 – dBGA1471H–SEEPR–03/03xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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EEPROM---AT24Cxx应用介绍
EEPROM---AT24Cxx应⽤介绍结论：1、读写AT24CXX芯⽚，根据容量有多种⽅式：⼀、容量为AT24C01~AT24C16，⾸先发送设备地址（8位地址），再发送数据地址（8位地址），再发送或者接受数据。
⼆、AT24C32/AT24C64~AT24C512，⾸先发送设备地址（8位地址），再发送⾼位数据地址，再发送地位数据地址，再发送或者接受数据。
三、容量AT24C1024的芯⽚,是把容量⼀和容量⼆的⽅法结合，设备地址中要⽤⼀位作为数据地址位，存储地址长度是17位。
2、它的设备地址根据容量不同有区别： 1）、AT24C01~AT24C16：这⼀类⼜分为两类，分别为AT24C01/AT24C02和AT24C04~AT24C16;他们的设备地址为⾼7位，低1位⽤来作为读写标⽰位，1为读，0为写。
*1*、AT24C01/AT24C02。
AT24C01/AT24C02的A0、A1、A2引脚作为7位设备地址的低三位，⾼4为固定为1010B，低三位A0、A1、A2确定了AT24CXX的设备地址，所以⼀根I2C线上最⼤可以接8个AT24CXX，地址为1010000B~1010111B。
*2*、AT24C04~AT24C16的 A0、A1、A2只使⽤⼀部分，不⽤的悬空或者接地（数据⼿册中写的是悬空不接）。
举例：AT24C04只⽤A2、A1引脚作为设备地址，另外⼀位A0不⽤悬空，发送地址中对应的这位（A0）⽤来写⼊页寻址的页⾯号,⼀根I2C线上最⼤可以接4个，地址为101000xB~101011xB 2）、AT24C32/AT24C64:和AT24C01/AT24C02⼀样，区别是，发送数据地址变成16位。
注意事项：对AT24C32来说，WP置⾼，则只有四分之⼀受保护，即0x0C00－0x0FFF。
也就是说保护区为1KBytes。
对于低地址的四分之三，则不保护。
所以，如果数据较多时，可以有选择地存储。
AT24C1024介绍
AT24C1024介绍AT24C10242 线串⾏EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8 位=1M2 线串⾏接⼝施密特触发器，噪声抑制滤波输⼊双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V) 硬件写保护引脚和软件数据保护256 字节页写模式(允许部分页⾯写⼊)随机和顺序读写模式⾃定义写周期(5ms)⾼可靠性：耐久⼒：写周期/页100,000 次数据保留：40 年8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装描述AT24C1024 提供1,048,567 位的串⾏可电擦除和可编程只读存储器（EEPROM），它的每8 位组成⼀个字节，共131,072 个字节。
该设备的级联功能允许多达2 个设备共亨同⼀条2- 线总线。
该设备适合⽤于许多⼯业和商业，应⽤必要的低功耗和低电压的操作。
该器件可提供节省空间的8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装。
另外，这⼀系列产品允许在2.7V（2.7V~5.5V）下⼯作。
绝对最⼤额定值：⼯作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最⼤⼯作电压：6.25V 直流输出电流：5.0mA注意：强制⾼出“绝对最⼤额定值”可能导致设备的永久损坏。
设备的压⼒等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。
长时间⼯作在绝对最⼤额定值的条件下可能影响设备的可靠性。
引脚描述：串⾏时钟（SCL）：SCL 的输⼊是在时钟的上升沿数据进⼊每个EEPROM 设备和下降沿数据输出每个设备。
串⾏数据（SDA）：SDA 引脚是双向串⾏数据传输的。
这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。
器件/ 页地址（A1 ）：A1 引脚是设备的输⼊地址，它能够通过导线与不兼容的设备AT24C128/256/512 连接。
AT24C
1Features•Low-voltage and Standard-voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms max)•High-reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years •Automotive Devices Available•8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages•Die Sales: Wafer Form, Waffle Pack and Bumped WafersDescriptionThe AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP ,8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23(AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. Table 1. Pin ConfigurationPin Name Function A0 - A2Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect GND Ground VCCPower Supply8-lead SOIC 8-lead PDIP8-lead Ultra Thin Mini-MAP(MLP 2x3)Bottom View 5-lead SOT238-ball dBGA2Bottom View 8-lead TSSOP2AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 1. Block DiagramAbsolute Maximum RatingsOperating Temperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage..........................................6.25V DC Output Current........................................................5.0 mA3AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground.The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground.WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal Read/Write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown in Table 2.Table 2. Write ProtectMemory OrganizationAT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,the 1K requires a 7-bit data word address for random word addressing.AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,the 2K requires an 8-bit data word address for random word addressing.AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,the 4K requires a 9-bit data word address for random word addressing.AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.WP Pin Status Part of the Array Protected24C01A 24C0224C0424C08A 24C16A At V CC Full (1K) ArrayFull (2K) ArrayFull (4K) ArrayFull (8K) ArrayFull (16K) ArrayAt GNDNormal Read/Write Operations4AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Note:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Table 3. Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VTable 4. DC CharacteristicsApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC =+1.8V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.7 5.5V V CC3Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current V CC = 1.8V V IN = V CC or V SS 0.6 3.0µA I SB2Standby Current V CC = 2.5V V IN = V CC or V SS 1.4 4.0µA I SB3Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB4Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V5AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Note:1.This parameter is characterized.Table 5. AC CharacteristicsApplicable over recommended operating range from T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC = +2.7V to +5.5V,CL = 1 TTL Gate and 100pF (unless otherwise noted)Symbol Parameter1.8-volt2.7, 5.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 100400kHz t LOW Clock Pulse Width Low 4.7 1.2µs t HIGH Clock Pulse Width High 4.00.6µs t I Noise Suppression Time (1)10050ns t AA Clock Low to Data Out Valid 0.1 4.50.10.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.7 1.2µs t HD.STA Start Hold Time 4.00.6µs t SU.STA Start Setup Time 4.70.6µs t HD.DAT Data In Hold Time 00µs t SU.DAT Data In Setup Time 200100ns t R Inputs Rise Time (1) 1.00.3µs t F Inputs Fall Time (1)300300ns t SU.STO Stop Setup Time 4.70.6µs t DH Data Out Hold Time 10050ns t WRWrite Cycle Time 55ms Endurance (1) 5.0V, 25°C, Byte Mode1M 1MWrite Cycles6AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Bus TimingFigure 2. SCL: Serial Clock, SDA: Serial Data I/O ®Write Cycle TimingFigure 3. SCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4.Data Validity8AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 5. Start and Stop DefinitionFigure 6.Output Acknowledge9AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Device AddressingThe 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for mem-ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows.The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11).PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 11).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ-ous data will be overwritten.10AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page.The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 12).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 12).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).11AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 7. Device AddressFigure 8. Byte WriteFigure 9. Page Write(* = DON’T CARE bit for 1K)12AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 10. Current Address ReadFigure 11. Random Read(* = DON’T CARE bit for 1K)Figure 12.Sequential Read13AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.This device is not recommended for new design. Please refer to AT24C01B datasheet. For2.7V devices used in the 4.5V to5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Pleasecontact Serial EEPROM Marketing.AT24C01A Ordering Information (1)Ordering CodePackage Operation RangeAT24C01A-10PU-2.7(2)AT24C01A-10PU-1.8(2)AT24C01A-10SU-2.7(2)AT24C01A-10SU-1.8(2)AT24C01A-10TU-2.7(2)AT24C01A-10TU-1.8(2)AT24C01A-10TSU-1.8(2)AT24C01AU3-10UU-1.8(2)AT24C01AY1-10YU-1.8(2) (Not recommended for new design)AT24C01AY6-10YH-1.8(3)8P38P38S18S18A28A25TS18U318Y18Y6Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)AT24C01A-W1.8-11(4)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)14AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.This device is not recommended for new design. Please refer to AT24C02B datasheet. For2.7V devices used in the 4.5V to5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C02 Ordering Information (1)Ordering Code Package Operation RangeAT24C02-10PU-2.7(2)AT24C02-10PU-1.8(2)AT24C02N-10SU-2.7(2)AT24C02N-10SU-1.8(2)AT24C02-10TU-2.7(2)AT24C02-10TU-1.8(2)AT24C02Y1-10YU-1.8(2)AT24C02-10TSU-1.8(2)AT24C02U3-10UU-1.8(2)8P38P38S18S18A28A28Y15TS18U3-1Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)AT24C02-W2.7-11(3)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)15AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.AT24C04 Ordering Information (1)Ordering CodePackage Operation RangeAT24C04-10PU-2.7(2)AT24C04-10PU-1.8(2)AT24C04N-10SU-2.7(2)AT24C04N-10SU-1.8(2)AT24C04-10TU-2.7(2)AT24C04-10TU-1.8(2)AT24C04Y1-10YU-1.8(2) (Not recommended for new design)AT24C04Y6-10YH-1.8(3)AT24C04-10TSU-1.8(2)AT24C04U3-10UU-1.8(2)8P38P38S18S18A28A28Y18Y65TS18U3-1Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)AT24C04-W1.8-11(4)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)16AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.AT24C08A Ordering Information (1)Ordering CodePackage Operation RangeAT24C08A-10PU-2.7(2)AT24C08A-10PU-1.8(2)AT24C08AN-10SU-2.7(2)AT24C08AN-10SU-1.8(2)AT24C08A-10TU-2.7(2)AT24C08A-10TU-1.8(2)AT24C08AY1-10YU-1.8(2) (Not recommended for new design)AT24C08AY6-10YH-1.8(3)AT24C08AU2-10UU-1.8(28P38P38S18S18A28A28Y18Y68U2-1Lead-free/Halogen-free/Industrial Temperature (−40°C to 85°C)AT24C08A-W1.8-11(4)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)17AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.This device is not recommended for new design. Please refer to AT24C16B datasheet. For2.7V devices used in the 4.5V to5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Pleasecontact Serial EEPROM Marketing.AT24C16A Ordering Information (1)Ordering CodePackage Operation RangeAT24C16A-10PU-2.7(2)AT24C16A-10PU-1.8(2)AT24C16AN-10SU-2.7(2)AT24C16AN-10SU-1.8(2)AT24C16A-10TU-2.7(2)AT24C16A-10TU-1.8(2)AT24C16AY1-10YU-1.8(2) (Not recommended for new design)AT24C16AY6-10YH-1.8(3)AT24C16AU2-10UU-1.8(2)8P38P38S18S18A28A28Y18Y68U2-1Lead-free/Halogen-free/Industrial Temperature (−40°C to 85°C)AT24C16A-W1.8-11(3)Die SaleIndustrial Temperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)18AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Packaging Information8P3 – PDIP19AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068S1 – JEDEC SOIC20AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068A2 – TSSOP21AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068Y1 – MAP22AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068Y6 − Mini-MAP (MLP 2x3 mm)23AT24C01A/02/04/08A/16A0180Z–SEEPR–11/065TS1 – SOT2324AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068U2 – dBGA225AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068U3-1 – dBGA20180Z–SEEPR–11/06Disclaimer: The information in this document is provided in connection with Atmel products. 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Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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AT24c1024 LPC23XX驱动 i2c
void I2CSendByte(unsigned char ch)//写一个字节数据
{
unsigned char Byte_count=8;
SDA_out;
while(Byte_count--)
{
FIO0CLR=SD2401_SCL;
I2CWait(50);
//延时大约8uS
//sramadd_lo:每块内的EE字节地址,
//sramdata:数据
unsigned char I2CReadEEram(unsigned char page,unsigned int sramadd_lo)
{
unsigned char ddata=0;
I2CStart();
if(page==0)I2CSendByte(0xA0);
unsigned char Byte_count=8; unsigned char ddata=0; SDA_in;
第2页
AT24c1024 LPC23XX驱动
FIO0SET=SD2401_SDA;
while (Byte_count--)
{
ddata<<=1;
FIO0CLR=SD2401_SCL;
I2CWait(50);
//延时大约8uS
FIO0SET=SD2401_SCL;
I2CWait(50);
//延时大约8uS
if(FIO0PIN&SD2401_SDA)ddata=ddata|1;
}
FIO0CLR=SD2401_SCL;
return ddata;
}
//page:00：选择块0,01：选择块1，
(完整word版)AT24Cxx中文数据手册
AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位,以及由每8位组成一个字节的可编程只读存储器（EEPROM）,其分别提供128/256/512/1024/2048个字节.该设备适用在许多低功耗和低电压操作的工业和商业应用中。
1引脚描述1.1串行时钟（SCL）SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。
1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。
该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或.1.3设备/页地址（A2,A1，A0）对于AT24C01A和AT24C02,A2、A1和A0引脚是配置器件的硬件地址输入。
一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）.AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。
A0引脚没有连接。
AT24C08A只使用A2引脚作为硬件地址输入,在一根总线上有2个8K 的设备可用来寻址.A0和A1引脚没有连接。
AT24C16A不使用设备地址引脚,这限制了一根总线上只能挂一个设备。
A0、A1和A2引脚没有连接。
1.4写保护(WP）AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。
写保护引脚允许正常读/写操作时连接到GND。
当写保护引脚连接到VCC,写保护功能启用和操作如下表所示.2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高.SDA引脚上的数据只能在SCL低时间段内更改,而启动条件或停止条件在SCL 为高时进行。
2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。
2.3停止条件SDA由低变为高，且SCL为高。
在读取序列之后,执行停止命令后EEPROM进入备用电源模式.2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。
I2C程序(AT24C1024)测试通过的
_nop_();
}
//*********************************************
//从机接收一位数据应答0
//*********************************************
voidACK(void)
{
SDA=0;
_nop_();
void write_byte(uchar ch)
{
uchar i, n=8;//向SDA发送一个字节数据，8位
for(i=0;i<n;i++)
{
if((ch&0x80)==0x80)
{//若要发送的位为1，则SDA=1
SDA=1;
SCL=1;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
SCL=1;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
SCL=0;
_nop_();
_nop_();
_nop_();
SDA=1;
_nop_();
}
//*********************************************
{
receive_data[i]=read_byte();//读出来的数据存到receivedata[]数组中
if(i==15)//是否读完，未读完全部数据，则应答0
NoACK();
else
ACK();
}//停止总线
stop();
}
void main()
24C1024中文资料
1Features•Low-voltage Operation –2.7 (V CC = 2.7V to 5.5V)•Internally Organized 131,072 x 8•2-wire Serial Interface•Schmitt Triggers, Filtered Inputs for Noise Suppression •Bi-directional Data Transfer Protocol•400 kHz (2.7V) and 1 MHz (5V) Clock Rate•Write Protect Pin for Hardware and Software Data Protection •256-byte Page Write Mode (Partial Page Writes Allowed)•Random and Sequential Read Modes •Self-timed Write Cycle (5 ms Typical)•High Reliability–Endurance: 100,000 Write Cycles/Page –Data Retention: 40 Years•8-lead PDIP , 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGA TM PackagesDescriptionThe AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-ball dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.Pin ConfigurationsPin Name Function A1Address Input SDA Serial Data SCL Serial Clock Input WPWrite Protect NCNo Connect8-lead PDIP8-lead Leadless ArrayBottom View8-lead SOIC8-ball dBGABottom View2AT24C10241471H–SEEPR–03/03Block DiagramAbsolute Maximum Ratings*Operating Temperature..................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................-65°C to +150°C Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C10241471H–SEEPR–03/03Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A1): The A1 pin is a device address input that can be hard-wired or left not connected for hardware compatibility with AT24C128/256/512. When the A1pin is hardwired, as many as two 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pin is not hardwired, the default A1 is zero.WRITE PROTECT (WP): The hardware Write Protect pin is useful for protecting the entire contents of the memory from inadvertent write operations. The write-protect input, when tied to GND, allows normal write operations. When WP is tied high to V CC , all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to V CC prior to a write operation creates a software write-protect function.Memory OrganizationAT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address.4AT24C10241471H–SEEPR–03/03Pin Capacitance (1)Note:1.This parameter is characterized and is not 100% tested.DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 1, SCL)6pFV IN = 0VApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +2.7V to +5.5V, T AC = 0°C to +70°C,V CC = +2.7V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC Supply Voltage 2.75.5V I CC Supply Current V CC = 5.0V READ at 400 kHz 2.0mA I CC Supply Current V CC = 5.0V WRITE at 400 kHz 5.0mA I SB Standby Current V CC = 2.7V V IN = V CC or V SS3.0µA V CC = 5.5V 6.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)-0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL Output Low LevelV CC = 3.0VI OL = 2.1 mA0.4V5AT24C10241471H–SEEPR–03/03AC Characteristics2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.7V , 5V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤50 nsInput and output timing reference voltages: 0.5 V CCApplicable over recommended operating range from T A = -40°C to +85°C, V CC = +2.7V to +5.5V, C L = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.Symbol ParameterTest Conditions MinMax Units f SCL Clock Frequency, SCL 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 1000400kHz t LOW Clock Pulse Width Low 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.41.3µs t HIGH Clock Pulse Width High 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.40.6µs t AA Clock Low to Data Out Valid4.5V ≤ V CC ≤5.5V 2.7V ≤ V CC ≤ 5.5V 0.050.050.550.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.51.3µs t HD.STA Start Hold Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.250.6µs t SU.STA Start Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t HD.DAT Data In Hold Time 0µs t SU.DA T Data In Setup Time 100ns t R Inputs Rise Time (1)0.3µs t F Inputs Fall Time (1) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 100300ns t SU.STO Stop Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t DH Data Out Hold Time 50ns t WRWrite Cycle Time10ms Endurance (1) 5.0V , 25°C, Page Mode100KWrite Cycles6AT24C10241471H–SEEPR–03/03Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)upon power-up and b)after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles,2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C10241471H–SEEPR–03/03Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.8AT24C10241471H–SEEPR–03/03Data ValidityStart and Stop DefinitionOutput Acknowledge9AT24C10241471H–SEEPR–03/03DeviceAddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word con-sists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2-wire EEPROM devices.The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state.DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC .WriteOperationsBYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0 bit of the device address, then the most significant word address followed by the least significant word address (refer to Figure 2)A write operation requires the P 0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, T WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (refer to Figure 3).The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “rollover” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.10AT24C10241471H–SEEPR–03/03ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover”during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (refer to Figure 4).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (refer to Figure 6).11AT24C10241471H–SEEPR–03/03Figure 1. Device AddressFigure 2. Byte WriteFigure 3. Page WriteFigure 4.Current Address Read12AT24C10241471H–SEEPR–03/03Figure 5. Random ReadFigure 6.Sequential Read13AT24C10241471H–SEEPR–03/03Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.Ordering InformationOrdering CodePackage Operation RangeA T24C1024-10CI-2.7A T24C1024C1-10CI-2.7A T24C1024-10PI-2.7A T24C1024W-10SI-2.7A T24C1024-10UI-2.78CN38CN18P38S28U8Industrial (-40°C to 85°C)Package Type8CN38-lead, 0.230" Wide, Leadless Array Package (LAP)8CN18-lead, 0.300" Wide, Leadless Array Package (LAP)8P38-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)8S28-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)8U88-ball, die Ball Grid Array Package (dBGA)Options-2.7Low Voltage (2.7V to 5.5V)14AT24C10241471H–SEEPR–03/03Packaging Information8CN3 – LAP15AT24C10241471H–SEEPR–03/038CN1 – LAP16AT24C10241471H–SEEPR–03/038P3 – PDIP17AT24C10241471H–SEEPR–03/038S2 – EIAJ SOIC18AT24C10241471H–SEEPR–03/038U8 – dBGA1471H–SEEPR–03/03xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80e-mailliterature@Web Site© Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof, are the registered trademarks, and dBG A ™ is the trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.。
DSP中i2c存储eeprom实例分析
1.示例程序中几种状态说明第一次看i2c_eeprom示例程序，对程序中的MsgStatus信息状态切换非常懵懂，为什么要有这几个状态？状态切换顺序如何安排？一大堆的状态，让人有些摸不着头脑。
先把程序中的头文件涉及的7种状态分析一下。
// I2C Message Commands for I2CMSG struct#define I2C_MSGSTAT_INACTIVE 0x0000 //未激活状态：一般成功发送数据或者//接受数据后可以设置信息状态为此状态，告诉用户可进行下一次的写数据或读数据。
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 //发送带停止位数据：这是为写数据而设///的状态，写入地址和数据之后发个停止位告诉存储器数据写入完毕。
#define I2C_MSGSTAT_WRITE_BUSY 0x0011 //写数据忙状态：在将待写的数据放入//缓存后，就可以使能IIC传输数据了，然后把信息状态设为该状态，意在告诉用户：数据//已经在传送过程中。
当然是否传送完毕，还需要通过查询SCD位来判断。
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020//发送无停止位数据：这个状态是为了读//取数据而设的，有查阅过AT24C1024EEPROM存储器使用手册的读者知道，在读数据之前//要发送数据的地址，发完地址不能产生停止位，这是存储器硬件设计决定的。
设为这个状//态意在告诉读者，可以发送要读取的数据的地址了。
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021//发送无停止位数据忙状态：这个状态是//为了读取数据而设的,似于I2C_MSGSTAT_WRITE_BUSY，说明地址数据已经在传送过程中。
//传送是否成功，还要看ARDY的状态。
#define I2C_MSGSTAT_RESTART 0x0022//重发开始位状态：这个状态也是为读取////数据而设。
AT24C1024 中文说明书
AT24C10242线串行EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8位=1M2线串行接口施密特触发器，噪声抑制滤波输入双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V)硬件写保护引脚和软件数据保护256字节页写模式(允许部分页面写入)随机和顺序读写模式自定义写周期(5ms)高可靠性：耐久力：写周期/页100,000次数据保留：40年8引脚PDIP，8引脚有铅SOIC封装，8引脚无铅阵列和8引脚球状dBGA封装描述AT24C1024提供1,048,567位的串行可电擦除和可编程只读存储器（EEPROM），它的每8位组成一个字节，共131,072个字节。
该设备的级联功能允许多达2个设备共亨同一条2-线总线。
该设备适合用于许多工业和商业，应用必要的低功耗和低电压的操作。
该器件可提供节省空间的8引脚PDIP，8引脚有铅SOIC封装，8引脚无铅阵列和8引脚球状dBGA封装。
另外，这一系列产品允许在2.7V（2.7V~5.5V）下工作。
绝对最大额定值：工作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最大工作电压：6.25V直流输出电流：5.0mA注意：强制高出“绝对最大额定值”可能导致设备的永久损坏。
设备的压力等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。
长时间工作在绝对最大额定值的条件下可能影响设备的可靠性。
引脚描述：：引脚描述串行时钟（SCL）：SCL的输入是在时钟的上升沿数据进入每个EEPROM设备和下降沿数据输出每个设备。
串行数据（SDA）：SDA引脚是双向串行数据传输的。
这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。
器件/页地址（A1）：A1引脚是设备的输入地址，它能够通过导线与不兼容的设备AT24C128/256/512连接。
当A1通过硬件连接时，2个以上的1024K设备可以在同一条系统总路线上寻址（下面会详细谈论设备的地址选择）。
at24-c1024_read_write
///////////////////////////////
//从addr读一个数据
unsigned char Read24c1024_OneByte(unsigned char addrh,unsigned char addrl)
{
uchar temp;
Start();
{uchar count;
for(count=0;count!=8;count++)
{
CLK(0); DelayMs(2);
if(Xdata&0x80)
IO(1);
else
IO(0);
DelayMs(2);
CLK(1); DelayMs(2);
{
uchar count;
uchar temp;
uchar value=0;
DDRD&=~0x04;//设置为输入
for(count=0;count!=8;count++)
{
value<<=1;
CLK(1); DelayMs(2);
temp=PIND;//读引脚
else PORTD&=~0x04;//IO置0
}
/////////////////////////////////
//IIC
//*******************Start条件****************//
void Start(void)
{
CLK(0);DelayMs(2);
CLK(0);DelayMs(2);
return value;
基于C8051F060单片机的AT24C1024芯片应用
基于C8051F060单片机的AT24C1024芯片应用本文介绍了I2C总线的原理以及2线制串行E2PROM 存储芯片AT24C1024的时序结构，结合C8051F060单片机的特点，给出了单片机与存储芯片硬件连接结构及软件模拟I2C总线的程序设计。
标签：C8051F060；AT24C1024；I2C1 引言随着电子技术的发展，越来越多的手持设备得到了广泛的应用。
因此，人们对设备的功耗和存储空间提出了更高的要求。
AT24C1024是24C系列E2PROM 存储器中存储容量最大的一种，具有I2C总线接口功能、功耗小、电源电压宽（2.7～5.5v）、工作电流和静态电流小等特点，其存储容量为1M位。
C8051F060单片机是美国Silabs公司生产的系统级芯片，它具有与8051兼容的高速CIP-51内核，指令系统与MCS-51指令集完全兼容，低功耗等优点[1]。
本文设计的以C8051F060单片机核心的AT24C1024存储芯片应用，具有结构简单、存储速度快、扩充空间方便等优点，现已在多个手持式设备上得到了广泛的应用。
2 AT24C1024芯片介绍2.1 芯片引脚AT24C1024提供1，048，567位的串行可电擦除和可编程只读存储器，它的每8位组成一个字节，共131，072个字节，内部有512页，每页有256个字节。
随机访问一个字地址数据需要17位数据的字地址。
AT24C1024共有6个有效引脚：VCC、GND、SCL、SDA、A1、WP。
其引脚如图1所示[2]：2.2 器件写操作（1）器件寻址：对于AT24C1024来说，8 位地址的高5 位被固定为10100，A1 为器件引脚的连接信息，若A1接高电平时，相应软件中的位为l，A1 接地时，相应位为0。
P0为页地址信息，P0为0 时是对前256页操作，为1时是对后256页操作。
R/W表示对从器件的读/写操作，l为读，0为写。
（2）字节写：单片机发送两个8 位地址字写入AT24C1024的地址指针，在收到AT24C1024的应答信号后，再发送数据到被寻址的存储单元。
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1Features•Low-voltage Operation –2.7(V CC =2.7V to 5.5V)•Internally Organized 131,072x 8•2-wire Serial Interface•Schmitt Triggers,Filtered Inputsfor Noise Suppression •Bi-directional Data Transfer Protocol•400kHz (2.7V)and 1MHz (5V)Clock Rate•Write Protect Pinfor Hardware and Software Data Protection •256-byte Page Write Mode (Partial Page Writes Allowed)•Random and Sequential Read Modes •Self-timed WriteCycle (5ms Typical)•High Reliability–Endurance:100,000Write Cycles/Page –Data Retention:40Years•8-lead PDIP ,8-lead EIAJ SOIC,8-lead LAP and 8-ball dBGA TM PackagesDescriptionThe AT24C1024provides 1,048,576bits of serial electrically erasable and program-mable readonly memory (EEPROM)organized as 131,072words of 8bits each.The device’s cascadable feature allows up to 2devices to share a common 2-wire bus.The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.The devices are available in space-saving 8-lead PDIP ,8-lead EIAJ SOIC,8-lead Leadless Array (LAP),and 8-ball dBGA packages.In addition,the entire family is available in 2.7V (2.7V to 5.5V)versions.Pin Configurations8-lead PDIP8-lead Leadless ArrayBottom View8-lead SOIC8-ball dBGA Bottom View2AT24C10241471F–SEEPR–03/02Block DiagramAbsolute Maximum Ratings**NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings”may cause permanent dam-age to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.3AT24C10241471F–SEEPR–03/02Pin DescriptionSERIAL CLOCK (SCL):The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA):The SDA pin is bi-directional for serial data transfer.This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A1):The A1pin is a device address input that can be hard-wired or left not connected for hardware compatibility with AT24C128/256/512.When the A1pin is hardwired,as many as two 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).When the pin is not hardwired,the default A1is zero.WRITE PROTECT (WP):The hardware Write Protect pin is useful for protecting the entire contents of the memory from inadvertent write operations.The write-protect input,when tied to GND,allows normal write operations.When WP is tied high to V CC ,all write operations to the memory are inhibited.If left unconnected,WP is internally pulled down to GND.Switching WP to V CC prior to a write operation creates a software write-protect function.MemoryOrganizationAT24C1024,1024K SERIAL EEPROM:The 1024K is internally organized as 512pages of 256bytes each.Random word addressing requires a 17-bit data word address.4AT24C10241471F–SEEPR–03/02Pin Capacitance (1)DC CharacteristicsIL IH Applicable over recommended operating range from:T AI =-40°C to +85°C,V CC =+2.7V to +5.5V,T AC =0°C to +70°C,5AT24C10241471F–SEEPR–03/02AC Characteristics2.AC measurement conditions:R L (connects to V CC ):1.3k Ω(2.7V ,5V)Input pulse voltages:0.3V CC to 0.7V CC Input rise and fall times:≤50nsInput and output timing reference voltages:0.5V CCApplicable over recommended operating range from T A =-40°C to +85°C,V CC =+2.7V to +5.5V,C L =100pF (unless6AT24C10241471F–SEEPR–03/02Device OperationCLOCK and DATA TRANSITIONS:The SDA pin is normally pulled high with an external device.Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram).Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION:A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION:A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence,the Stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE:All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE:The AT24C1024features a low-power standby mode which is enabled:a)upon power-up and b)after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET:After an interruption in protocol,power loss or system reset,any 2-wire part can be reset by following these steps:1.Clock up to 9cycles,2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C10241471F–SEEPR–03/02Bus Timing (SCL:Serial Clock,SDA:Serial Data I/O)Write Cycle Timing (SCL:Serial Clock,SDA:Serial Data I/O)Note:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/writecycle.8AT24C10241471F–SEEPR–03/02Data ValidityStart and Stop DefinitionOutputAcknowledge9AT24C10241471F–SEEPR–03/02DeviceAddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1).The device address word con-sists of a mandatory one,zero sequence for the first five most significant bits as shown.This is common to all 2-wire EEPROM devices.The 1024K uses the one device address bit,A1,to allow up to two devices on the same bus.The A1bit must compare to the corresponding hardwired input pin.The A1pin uses an inter-nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0)of the device address is a memory page address bit.This memory page address bit is the most significant bit of the data word address that follows.The eighth bit of the device address is the read/write operation select bit.A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address,the EEPROM will output a zero.If a compare is not made,the device will return to a standby state.DATA SECURITY:The AT24C1024has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC .WriteOperationsBYTE WRITE:To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0bit of the device address,then the most significant word address followed by the least significant word address (refer to Figure 2)A write operation requires the P 0bit and two 8-bit data word addresses following the device address word and acknowledgment.Upon receipt of this address,the EEPROM will again respond with a zero and then clock in the first 8-bit data word.Following receipt of the 8-bit data word,the EEPROM will output a zero.The addressing device,such as a microcontroller,then must terminate the write sequence with a stop condition.At this time the EEPROM enters an internally timed write cycle,T WR ,to the nonvolatile memory.All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE:The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write,but the microcontroller does not send a stop condition after the first data word is clocked in.Instead,after the EEPROM acknowledges receipt of the first data word,the microcontroller can transmit up to 255more data words.The EEPROM will respond with a zero after each data word received.The microcontroller must ter-minate the page write sequence with a stop condition (refer to Figure 3).The data word address lower 8bits are internally incremented following the receipt of each data word.The higher data word address bits are not incremented,retaining the memory page row location.When the word address,internally generated,reaches the page boundary,the following byte is placed at the beginning of the same page.If more than 256data words are transmitted to the EEPROM,the data word address will “roll over”and previous data will be overwritten.The address “rollover”during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING:Once the internally timed write cycle has started and the EEPROM inputs are disabled,acknowledge polling can be initiated.This involves sending a start condition followed by the device address word.The read/write bit is representative of the operation desired.Only if the internal write cycle has completed will the EEPROM respond with a zero,allowing the read or write sequence to continue.10AT24C10241471F–SEEPR–03/02ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one.There are three read operations:current address read,random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation,incremented by one.This address stays valid between operations as long as the chip power is maintained.The address “rollover”during read is from the last byte of the last memory page,to the first byte of the first page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM,the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condi-tion (refer to Figure 4).RANDOM READ:A random read requires a “dummy”byte write sequence to load in the data word address.Once the device address word and data word address are clocked in and acknowledged by the EEPROM,the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high.The EEPROM acknowledges the device address and serially clocks out the data word.The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (refer to Figure 5).SEQUENTIAL READ:Sequential reads are initiated by either a current address read or a ran-dom address read.After the microcontroller receives a data word,it responds with an acknowledge.As long as the EEPROM receives an acknowledge,it will continue to increment the data word address and serially clock out sequential data words.When the memory address limit is reached,the data word address will “roll over”and the sequential read will con-tinue.The sequential read operation is terminated when the microcontroller does not respond with a zero,but does generate a following stop condition (refer to Figure 6).11AT24C10241471F–SEEPR–03/02Figure 1.Device AddressFigure 2.Byte WriteFigure 3.Page WriteFigure 4.Current AddressRead12AT24C10241471F –SEEPR –03/02Figure 5.Random ReadFigure 6.SequentialRead13AT24C10241471F –SEEPR –03/02Ordering Information14AT24C10241471F –SEEPR –03/02Packaging Information8CN3–LAP15AT24C10241471F –SEEPR –03/028CN1–LAP16AT24C10241471F –SEEPR –03/028P3–PDIP17AT24C10241471F –SEEPR –03/028S2–EIAJ SOIC18AT24C10241471F –SEEPR –03/028U8–dBGAon recycled paper.©Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products,other than those expressly contained in the Company ’s standard warranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site.The Company assumes no responsibility for any errors which may appear in this document,reserves the right to change devices or specifications detailed herein at any time without notice,and does not make any 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