格雷码和二进制的相互转换-vhdl程序剖析

1.B2G_converter
1)Screenshot of iSim simulation results:
note: from the beginning point at 1,000ns, input(i5binary) changes every other 50ns
a)i5binary input from 0 to 6
b)i5binary input from 7 to 13
c)i5binary input from 14 to 20
d)i5binary input from 21 to 27
e)i5binary input from 28 to 31
2)VHDL for Binary-to-Gray-Code converter:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:02:37 09/15/2015
-- Design Name:
-- Module Name: b2g_converter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity b2g_converter is
Port ( i5Binary : in STD_LOGIC_VECTOR (4 downto 0);
o5GrayCode : out STD_LOGIC_VECTOR (4 downto 0));
end b2g_converter;
architecture Behavioral of b2g_converter is
signal gbuffer: std_logic_vector (4 downto 0);
begin
o5GrayCode<=gbuffer;
gbuffer(4)<=i5Binary(4);
label1:
for i in 3 downto 0 generate
gbuffer(i)<= i5Binary(i+1) xor i5Binary(i);
end generate;
end Behavioral;
2.G2B_converter
1)Gray-code-to-Binary conversion
From the combinational logic described for gray-code-to-binary conversion, we obtain:
Thus, for a n-bit graycode number g, g=g(n-1)g(n-2)…g(2)g(1)g(0), the corresponding n-bit binary number b, b=b(n-1)b(n-2)…b(2)b(1)b(0) is computed using the following description:
b(n-1)=g(n-1) for the MSB, and
b(i)= g(i) b(i+1) for bits in position 0 to n-2
2)Screenshot of iSim simulation results:
note: from the beginning point at 1,000ns, input(i5graycode) changes every other 50ns
a)i5graycode input from 0 to 6
b)i5graycode input from 7 to 13
c)i5graycode input from 14 to 20
d)i5graycode input from 21 to 27
e)i5graycode input from 28 to 31
3)VHDL for Gray-Code-to-Binary converter:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:20:03 09/15/2015
-- Design Name:
-- Module Name: g2b_converter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
---------------------------------------------------------------------------------- library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity g2b_converter is
Port ( i5GrayCode : in STD_LOGIC_VECTOR (4 downto 0);
o5Binary : out STD_LOGIC_VECTOR (4 downto 0)); end g2b_converter;
architecture Behavioral of g2b_converter is
signal bbuffer: std_logic_vector (4 downto 0);
begin
o5Binary <= bbuffer;
bbuffer(4)<= i5GrayCode(4);
label1:
for i in 3 downto 0 generate
bbuffer(i)<= bbuffer(i+1) xor i5GrayCode(i); end generate;
end Behavioral;。