SGS-THOMSON STP80N05-09 说明书

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STP80N05-09
N -CHANNEL ENHANCEMENT MODE
”ULTRA HIGH DENSITY”POWER MOS TRANSISTOR
s ULTRA HIGH DENSITY TECHNOLOGY s TYPICAL R DS(on)=7m Ω
s AVALANCHE RUGGED TECHNOLOGY s LOW GATE CHARGE
s HIGH CURRENT CAPABILITY
s
175o
C OPERATING TEMPERATURE
APPLICATIONS
s SYNCROUNOUS RECTIFIERS
s HIGH CURRENT,HIGH SPEED SWITCHING s DC-DC &DC-AC CONVERTER ABSOLUTE MAXIMUM RATINGS
INTERNAL SCHEMATIC DIAGRAM
March 1997
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Value Unit V DS Drain-source Voltage (V GS =0)50V V DGR Drain-gate Voltage (R GS =20k Ω)50V V GS Gate-source Voltage
±20V I D Drain Current (continuous)at T c =25o C 80A I D Drain Current (continuous)at T c =100o C 60A I DM (•)Drain Current (pulsed)320A P tot
Total Dissipation at T c =25o C 150W Derating Factor
1W/o C dV/dt(1)Peak Diode Recovery voltage slope 5V/ns
T stg Storage Temperature
-65to 175o C T j
Max.Operating Junction Temperature
175
o
C (•)Pulse width limited by safe operating area
(1)I SD ≤60A,di/dt ≤200A/ms,V DD ≤V (BR)DSS ,T J ≤T JMAX
TYPE V DSS R DS(on)I D STP80N05-09
50V
<0.009Ω
80A
1
2
3
TO-220
1/9
THERMAL DATA
R thj-case R thj-amb R thc-sink
T l Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Thermal Resistance Case-sink Typ
Maximum Lead Temperature For Soldering Purpose
1
62.5
0.5
300
o C/W
o C/W
o C/W
o C
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I AR Avalanche Current,Repetitive or Not-Repetitive
(pulse width limited by T j max,δ <1%)
60A
E AS Single Pulse Avalanche Energy
(starting T j=25o C,I D=I AR,V DD=25V)
600mJ
ELECTRICAL CHARACTERISTICS(T case=25o C unless otherwise specified)
OFF
Symbol Parameter Test Conditions Min.Typ.Max.Unit V(BR)DSS Drain-source
Breakdown Voltage
I D=250µA V GS=050V
I DSS Zero Gate Voltage
Drain Current(V GS=0)V DS=Max Rating
V DS=Max Rating T c=125o C
1
10
µA
µA
I GSS Gate-body Leakage
Current(V DS=0)
V GS=±20V±100nA ON(∗)
Symbol Parameter Test Conditions Min.Typ.Max.Unit V GS(th)Gate Threshold Voltage V DS=V GS I D=250µA234V R DS(on)Static Drain-source On
Resistance
V GS=10V I D=40A0.0070.009Ω
I D(on)On State Drain Current V DS>I D(on)x R DS(on)max
V GS=10V
80A DYNAMIC
Symbol Parameter Test Conditions Min.Typ.Max.Unit
g fs(∗)Forward
Transconductance
V DS>I D(on)x R DS(on)max I D=40A25S
C iss C oss C rss Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS=25V f=1MHz V GS=05900
900
230
pF
pF
pF
STP80N05-09 2/9
ELECTRICAL CHARACTERISTICS(continued)
SWITCHING ON
Symbol Parameter Test Conditions Min.Typ.Max.Unit
t d(on) t r Turn-on Time
Rise Time
V DD=30V I D=40A
R G=4.7ΩV GS=10V
(see test circuit,figure3)
32
160
42
200
ns
ns
(di/dt)on Turn-on Current Slope V DD=48V I D=80A
R G=50ΩV GS=10V
(see test circuit,figure5)
240A/µs
Q g Q gs Q gd Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V DD=40V I D=80A V GS=10V230
30
60
280nC
nC
nC
SWITCHING OFF
Symbol Parameter Test Conditions Min.Typ.Max.Unit
t r(Voff) t f t c Off-voltage Rise Time
Fall Time
Cross-over Time
V DD=48V I D=40A
R G=4.7ΩV GS=10V
(see test circuit,figure5)
35
175
240
46
230
300
ns
ns
ns
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min.Typ.Max.Unit
I SD I SDM(•)Source-drain Current
Source-drain Current
(pulsed)
80
320
A
A
V SD(∗)Forward On Voltage I SD=80A V GS=0 1.5V
t rr Q rr I RRM Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD=80A di/dt=100A/µs
V R=30V T j=150o C
(see test circuit,figure5)
125
0.6
10
ns
µC
A
(∗)Pulsed:Pulse duration=300µs,duty cycle1.5%
(•)Pulse widthlimited by safe operating area
Safe Operating Area Thermal Impedance
STP80N05-09
3/9
Derating Curve
Transfer Characteristics
Static Drain-source On Resistance Output Characteristics Transconductance
Gate Charge vs Gate-source Voltage
STP80N05-09 4/9
Capacitance Variations
Normalized On Resistance vs Temperature Turn-off Drain-source Voltage Slope Normalized Gate Threshold Voltage vs Temperature
Turn-on Current Slope
Cross-over Time
STP80N05-09
5/9
Switching Safe Operating Area
Source-drain Diode Forward Characteristics Fig.1:Unclamped Inductive Load Test Circuit Accidental Overload Area
Fig.2:Unclamped Inductive Waveform
STP80N05-09 6/9
Fig.3:Switching Times Test Circuits For Resistive Load
Fig.5:Test Circuit For Inductive Load Switching And DIode Recovery Times Fig.4:Gate Charge test Circuit
STP80N05-09
7/9
DIM.mm
inch MIN.TYP.
MAX.MIN.TYP.
MAX.A 4.40 4.600.1730.181C 1.23 1.320.0480.051D 2.40
2.72
0.094
0.107
D1 1.27
0.050
E 0.490.700.0190.027
F 0.610.880.0240.034F1 1.14 1.700.0440.067F2 1.14 1.700.0440.067
G 4.95 5.150.1940.203G1 2.4 2.70.0940.106H210.0
10.40
0.393
0.409
L216.4
0.645
L413.014.00.5110.551L5 2.65 2.950.1040.116L615.2515.750.6000.620L7 6.2 6.60.2440.260L9 3.5 3.930.1370.154DIA.
3.75 3.85
0.147
0.151
L6
A
C
D
E
D 1
F
G
L7
L2
Dia.
F 1
L5
L4
H 2
L9
F 2
G 1
TO-220MECHANICAL DATA
P011C
STP80N05-09
8/9
STP80N05-09 Information furnished is believed to be accurate and reliable.However,SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patent s or other rights of third parties which may results from its use.No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specifications mentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectroni c s product s are not autho rized for use as critical components in life suppor t devices or systems without expre ss written approval of SGS-THOMSON Microelectonics.
©1996SGS-THOMSON Microelectroni c s-Printed in Italy-All Rights Reserved
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