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Lenovo Storage D1224 Drive Enclosure for SAP HANA
Lenovo Storage D1224 Drive Enclosure for SAP HANA Product GuideLenovo Storage D1224 Drive Enclosure models for SAP HANA provide additional required disk storage capacity for certain SAP HANA X6 systems with large memory configurations. They are designed specifically for SAP HANA certified appliance requirements and are supported on SAP HANA X6 systems. The D1224 for SAP HANA is a 2U rack-mount enclosure that has 24 SFF hot-swap drive bays and is attached to SAP HANA X6 systems via the ServeRAID M5225 RAID adapter. All D1224 models for SAP HANA contain single Environmental Service Module (ESM) with 3x 12 Gbps SAS x4 ports for direct-attach host connectivity.The D1224 for SAP HANA is shown in the following figure.Figure 1. Lenovo Storage D1224 Disk Expansion Enclosure for SAP HANADid you know?The D1224 expansion enclosures for SAP HANA offer flexible hybrid storage configurations with enterprise SAS hard disk drives (HDDs) and high performance SAS solid-state drives (SSDs).The D1224 expansion units for SAP HANA support 12 Gbps SAS connectivity, which doubles the data transfer rate compared to 6 Gb SAS solutions to maximize performance of storage I/O-intensive applications.Click here to check for updatesFigure 2. Front view of the D1224 drive enclosure for SAP HANAFigure 3. Rear view of the D1224 drive enclosure for SAP HANANote: The ESM (shown in Figure 4) has additional service ports with a specialized connector, and these ports are reserved for use by a Lenovo service technician.System specificationsThe following table lists the D1224 for SAP HANA system specifications.Table 1. System specificationsAttribute SpecificationDrivesThe following table lists drive options for the D1224 drive enclosure for SAP HANA. Table 4. SFF drive optionsDescription Part number FeaturecodeMaximumquantity perone D12242.5-inch SAS hot-swap HDDsLenovo Storage 300GB 15K 2.5" SAS HDD01DC197AU1J24 Lenovo Storage 600GB 10K 2.5" SAS HDD01DC427AU1Q24 Lenovo Storage 600GB 15K 2.5" SAS HDD01DC192AU1H24 Lenovo Storage 900GB 10K 2.5" SAS HDD01DC417AU1N24 Lenovo Storage 900GB 15K 2.5" SAS HDD01KP040AVP524 Lenovo Storage 1.2TB 10K 2.5" SAS HDD01DC407AU1L24 Lenovo Storage 1.8TB 10K 2.5" SAS HDD01DC402AU1K24 Lenovo Storage 2.4TB 10K 2.5" SAS HDD4XB7A09101B10324 2.5-inch NL SAS hot-swap HDDsLenovo Storage 1TB 7.2K 2.5" NL-SAS HDD01DC442AU1S24 Lenovo Storage 2TB 7.2K 2.5" NL-SAS HDD01DC437AU1R24 2.5-inch SAS hot-swap SED HDDsLenovo Storage 1.2TB 10K 2.5" SAS HDD (SED)01DC412AU1M24 2.5-inch SAS hot-swap SSDs (10 DWD)Lenovo Storage 400GB 10DWD 2.5" SAS SSD01DC462AUDK24 Lenovo Storage 800GB 10DWD 2.5" SAS SSD01DC452AUDH24 Lenovo Storage 1.6TB 10DWD 2.5" SAS SSD01DC447AUDG24 2.5-inch SAS hot-swap SSDs (3 DWD)Lenovo Storage 400GB 3 DWD 2.5" SAS SSD01DC482AU1V24 Lenovo Storage 800GB 3DWD 2.5" SAS SSD01DC477AU1U24 Lenovo Storage 1.6TB 3DWD 2.5" SAS SSD01DC472AU1T24 2.5-inch SAS hot-swap SSDs (1 DWD)Lenovo Storage 3.84TB 1DWD 2.5" SAS SSD (1200.2)01CX632AV2F24 Lenovo Storage 3.84TB 1DWD 2.5" SAS SSD (PM1633a)01KP065AVPA24 Lenovo Storage 7.68TB 1DWD 2.5" SAS SSD01KP060AVP924 Lenovo Storage 15.36TB 1DWD 2.5" SAS SSD4XB7A08817B10424 2.5-inch SAS hot-swap SED SSDs (10 DWD)Lenovo Storage 800GB 10DWD 2.5" SAS SSD (SED)01DC457AUDJ24 Power cablesPower cablesThe D1224 for SAP HANA ships standard with two 1.5m, 10A/100-250V, C13 to IEC 320-C14 rack power cables. Other power cable options are also available, and the part numbers and feature codes to order the power cables are listed in the following table (two power cables are required per each D1224 for SAP HANA).Table 5. Power cable optionsDescription PartnumberFeaturecodeRack power cables1.2m, 10A/100-250V, 2 Short C13s to Short C14 Rack Power Cable47C2487A3SS 1.2m, 16A/100-250V, 2 Short C13s to Short C20 Rack Power Cable47C2491A3SW1.5m, 10A/100-250V, C13 to IEC 320-C14 Rack Power Cable39Y793762012.5m, 10A/100-250V, 2 Long C13s to Short C14 Rack Power Cable47C2488A3ST 2.5m, 16A/100-250V, 2 Long C13s to Short C20 Rack Power Cable47C2492A3SX 2.8m, 10A/100-250V, 2 Short C13s to Long C14 Rack Power Cable47C2489A3SU 2.8m, 10A/100-250V, C13 to IEC 320-C14 Rack Power Cable None*6311 2.8m, 10A/100-250V, C13 to IEC 320-C20 Rack Power Cable39Y79386204 2.8m, 16A/100-250V, 2 Short C13s to Long C20 Rack Power Cable47C2493A3SY 4.1m, 10A/100-250V, 2 Long C13s to Long C14 Rack Power Cable47C2490A3SV 4.1m, 16A/100-250V, 2 Long C13s to Long C20 Rack Power Cable47C2494A3SZ 4.3m, 10A/100-250V, C13 to IEC 320-C14 Rack Power Cable39Y79326263 Line cords10A/125V C13 to NEMA 5-15P 4.3m line cord39Y79316207 10A/250V C13 to NEMA 6-15P 2.8m line cord46M2592A1RF Argentina 10A/250V C13 to IRAM 2073 2.8m line cord39Y79306222 Australia/NZ 10A/250V C13 to AS/NZ 3112 2.8m line cord39Y79246211 Brazil 10A/250V C13 to NBR 14136 2.8m line cord69Y19886532 China 10A/250V C13 to GB 2099.1 2.8m line cord39Y79286210 Denmark 10A/250V C13 to DK2-5a 2.8m line cord39Y79186213 European 10A/230V C13 to CEE7-VII 2.8m line cord39Y79176212 India 10A/250V C13 to IS 6538 2.8m line cord39Y79276269 Israel 10A/250V C13 to SI 32 2.8m line cord39Y79206218 Italy 10A/250V C13 to CEI 23-16 2.8m line cord39Y79216217 Japan 12A/125V C13 to JIS C-8303 2.8m line cord46M2593A1RE Korea 12A/250V C13 to KETI 2.8m line cord39Y79256219 South Africa 10A/250V C13 to SABS 164 2.8m line cord39Y79226214 Switzerland 10A/250V C13 to SEV 1011-S24507 2.8m line cord39Y79196216 Taiwan 15A/125V C13/CNS 10917 2.8m line cord00CG2676402 United Kingdom 10A/250V C13 to BS 1363/A 2.8m line cord39Y79236215Physical specificationsInteroperabilityLenovo provides end-to-end storage compatibility testing to deliver interoperability throughout the network. For end-to-end storage configuration support, refer to the Lenovo Storage Interoperation Center (LSIC): https:///us/en/lsicUse the LSIC to select the known components of your configuration and then get a list all other supported combinations, with details about supported hardware, firmware, operating systems, and drivers, plus any additional configuration notes. View results on screen or export them to Excel.Rack cabinetsThe following table lists the supported rack cabinets.Table 7. Rack cabinetsPart number Description93072RX25U Standard Rack (1000mm)93072PX25U Static S2 Standard Rack (1000mm)7D6DA007WW ThinkSystem 42U Onyx Primary Heavy Duty Rack Cabinet (1200mm)7D6DA008WW ThinkSystem 42U Pearl Primary Heavy Duty Rack Cabinet (1200mm)93604PX42U 1200mm Deep Dynamic Rack93614PX42U 1200mm Deep Static Rack93634PX42U 1100mm Dynamic Rack93634EX42U 1100mm Dynamic Expansion Rack93074RX42U Standard Rack (1000mm)7D6EA009WW ThinkSystem 48U Onyx Primary Heavy Duty Rack Cabinet (1200mm)7D6EA00AWW ThinkSystem 48U Pearl Primary Heavy Duty Rack Cabinet (1200mm)For specifications about these racks, see the Lenovo Rack Cabinet Reference, available from:https:///lp1287-lenovo-rack-cabinet-referenceFor more information, see the list of Product Guides in the Rack cabinets category:https:///servers/options/racksPower distribution unitsThe following table lists the power distribution units (PDUs) that are offered by Lenovo.Table 8. Power distribution unitsPart number Feature code Description 0U Basic PDUs00YJ776ATZY 0U 36 C13/6 C19 24A 1 Phase PDU N Y Y N N N N N N Y Y Y N 00YJ777ATZZ 0U 36 C13/6 C19 32A 1 Phase PDU Y Y N Y Y Y Y Y Y N N Y Y 0U Switched and Monitored PDUs00YJ783AU040U 12 C13/12 C19 Switched and Monitored48A 3 Phase PDUN N Y N N N Y N N Y Y Y N 00YJ781AU030U 20 C13/4 C19 Switched and Monitored 24A 1 Phase PDUN N Y N Y N Y N N Y Y Y N1U Switched and Monitored PDUs 4PU7A81117BNDV 1U 18 C19/C13 switched and monitored 48A 3P WYE PDU - ETLN N N N N N N N N N N Y N 4PU7A77467BLC41U 18 C19/C13 Switched and Monitored 80A 3P Delta PDUN N N N N N N N N Y N Y N 4PU7A77469BLC61U 12 C19/C13 switched and monitored 60A 3P Delta PDUN N N N N N N N N N N Y N 4PU7A77468BLC51U 12 C19/C13 switched and monitored 32A 3P WYE PDUY Y Y Y Y Y Y Y Y N Y Y Y 4PU7A81118BNDW1U 18 C19/C13 switched and monitored 48A 3P WYE PDU - CEY Y Y Y Y Y Y Y Y N Y N Y1U Ultra Density Enterprise PDUs (9x IEC 320 C13 + 3x IEC 320 C19 outlets)71763NU 6051Ultra Density Enterprise C19/C13 PDU 60A/208V/3PHN N Y N N N N N N Y Y Y N 71762NX6091Ultra Density Enterprise C19/C13 PDU ModuleY Y Y Y Y Y Y Y Y Y Y Y Y1U C13 Enterprise PDUs (12x IEC 320 C13 outlets)39Y89416010DPI C13 Enterprise PDU Module (WW)Y Y Y Y Y Y Y Y Y Y Y Y Y 1U Front-end PDUs (3x IEC 320 C19 outlets)39Y89386002DPI Single-phase 30A/120V Front-end PDU (US)Y Y Y Y Y Y Y Y Y Y Y Y Y 39Y89396003DPI Single-phase 30A/208V Front-end PDU (US)Y Y Y Y Y Y Y Y Y Y Y Y Y 39Y89346005DPI Single-phase 32A/230V Front-end PDU (International)Y Y Y Y Y Y Y Y Y Y Y Y Y 39Y89406004DPI Single-phase 60A/208V Front-end PDU (US)Y N Y Y Y Y Y N N Y Y Y N 39Y89356006DPI Single-phase 63A/230V Front-end PDU (International)Y Y Y Y Y Y Y Y Y Y Y Y Y1U NEMA PDUs (6x NEMA 5-15R outlets)39Y89055900DPI 100-127V NEMA PDUY Y Y Y Y Y Y Y Y Y Y Y YA N Z A S E A NB r a z i lE E T M E AR U C I S W E H T KI N D I A J A P A NL A N A P R CLine cords for 1U PDUs that ship without a line cord40K96116504 4.3m, 32A/380-415V, EPDU/IEC 309 3P+N+G 3ph wye (non-US) Line CordY Y Y Y Y Y Y Y Y Y Y Y Y 40K96126502 4.3m, 32A/230V, EPDU to IEC 309 P+N+G (non-US) Line CordY Y Y Y Y Y Y Y Y Y Y Y Y 40K96136503 4.3m, 63A/230V, EPDU to IEC 309 P+N+G (non-US) Line CordY Y Y Y Y Y Y Y Y Y Y Y Y40K96146500 4.3m, 30A/208V, EPDU to NEMA L6-30P (US)Line CordY Y Y Y Y Y Y Y Y Y Y Y Y 40K96156501 4.3m, 60A/208V, EPDU to IEC 309 2P+G (US)Line CordN N Y N N N Y N N Y Y Y N 40K96176505 4.3m, 32A/230V, Souriau UTG Female to AS/NZ 3112 (Aus/NZ) Line CordY Y Y Y Y Y Y Y Y Y Y Y Y40K961865064.3m, 32A/250V, Souriau UTG Female to KSC 8305 (S. Korea) Line CordY Y Y Y Y Y Y Y Y Y Y Y Y Part number Feature code Description For more information, see the Lenovo Press documents in the PDU category:https:///servers/options/pduUninterruptible power supply unitsA N Z A S E A NB r a z i lE E T M E AR U C I S W E H T KI N D I AJ A P A NL A N A P R CUninterruptible power supply unitsThe following table lists the uninterruptible power supply (UPS) units that are offered by Lenovo.Table 9. Uninterruptible power supply unitsPart number Description55941AX RT1.5kVA 2U Rack or Tower UPS (100-125VAC)55941KX RT1.5kVA 2U Rack or Tower UPS (200-240VAC)55942AX RT2.2kVA 2U Rack or Tower UPS (100-125VAC)55942KX RT2.2kVA 2U Rack or Tower UPS (200-240VAC)55943AX RT3kVA 2U Rack or Tower UPS (100-125VAC)55943KX RT3kVA 2U Rack or Tower UPS (200-240VAC)55945KX RT5kVA 3U Rack or Tower UPS (200-240VAC)55946KX RT6kVA 3U Rack or Tower UPS (200-240VAC)55948KX RT8kVA 6U Rack or Tower UPS (200-240VAC)55949KX RT11kVA 6U Rack or Tower UPS (200-240VAC)55948PX RT8kVA 6U 3:1 Phase Rack or Tower UPS (380-415VAC)55949PX RT11kVA 6U 3:1 Phase Rack or Tower UPS (380-415VAC)55943KT†ThinkSystem RT3kVA 2U Standard UPS (200-230VAC) (2x C13 10A, 2x GB 10A, 1x C19 16A outlets)55943LT†ThinkSystem RT3kVA 2U Long Backup UPS (200-230VAC) (2x C13 10A, 2x GB 10A, 1x C19 16A outlets)55946KT†ThinkSystem RT6kVA 5U UPS (200-230VAC) (2x C13 10A outlets, 1x Terminal Block output) 5594XKT†ThinkSystem RT10kVA 5U UPS (200-230VAC) (2x C13 10A outlets, 1x Terminal Block output)† Only available in China and the Asia Pacific market.For more information, see the list of Product Guides in the UPS category:https:///servers/options/upsLenovo Financial ServicesTrademarksLenovo and the Lenovo logo are trademarks or registered trademarks of Lenovo in the United States, other countries, or both. A current list of Lenovo trademarks is available on the Web athttps:///us/en/legal/copytrade/.The following terms are trademarks of Lenovo in the United States, other countries, or both:Lenovo®ServeRAIDSystem x®ThinkSystem®The following terms are trademarks of other companies:Linux® is the trademark of Linus Torvalds in the U.S. and other countries.Excel® is a trademark of Microsoft Corporation in the United States, other countries, or both.Other company, product, or service names may be trademarks or service marks of others.。
NuMicro N9H30系列开发板用户手册说明书
NuMicro®FamilyArm® ARM926EJ-S BasedNuMaker-HMI-N9H30User ManualEvaluation Board for NuMicro® N9H30 SeriesNUMAKER-HMI-N9H30 USER MANUALThe information described in this document is the exclusive intellectual property ofNuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.Nuvoton is providing this document only for reference purposes of NuMicro microcontroller andmicroprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.All data and specifications are subject to change without notice.For additional information or questions, please contact: Nuvoton Technology Corporation.Table of Contents1OVERVIEW (5)1.1Features (7)1.1.1NuMaker-N9H30 Main Board Features (7)1.1.2NuDesign-TFT-LCD7 Extension Board Features (7)1.2Supporting Resources (8)2NUMAKER-HMI-N9H30 HARDWARE CONFIGURATION (9)2.1NuMaker-N9H30 Board - Front View (9)2.2NuMaker-N9H30 Board - Rear View (14)2.3NuDesign-TFT-LCD7 - Front View (20)2.4NuDesign-TFT-LCD7 - Rear View (21)2.5NuMaker-N9H30 and NuDesign-TFT-LCD7 PCB Placement (22)3NUMAKER-N9H30 AND NUDESIGN-TFT-LCD7 SCHEMATICS (24)3.1NuMaker-N9H30 - GPIO List Circuit (24)3.2NuMaker-N9H30 - System Block Circuit (25)3.3NuMaker-N9H30 - Power Circuit (26)3.4NuMaker-N9H30 - N9H30F61IEC Circuit (27)3.5NuMaker-N9H30 - Setting, ICE, RS-232_0, Key Circuit (28)NUMAKER-HMI-N9H30 USER MANUAL3.6NuMaker-N9H30 - Memory Circuit (29)3.7NuMaker-N9H30 - I2S, I2C_0, RS-485_6 Circuit (30)3.8NuMaker-N9H30 - RS-232_2 Circuit (31)3.9NuMaker-N9H30 - LCD Circuit (32)3.10NuMaker-N9H30 - CMOS Sensor, I2C_1, CAN_0 Circuit (33)3.11NuMaker-N9H30 - RMII_0_PF Circuit (34)3.12NuMaker-N9H30 - RMII_1_PE Circuit (35)3.13NuMaker-N9H30 - USB Circuit (36)3.14NuDesign-TFT-LCD7 - TFT-LCD7 Circuit (37)4REVISION HISTORY (38)List of FiguresFigure 1-1 Front View of NuMaker-HMI-N9H30 Evaluation Board (5)Figure 1-2 Rear View of NuMaker-HMI-N9H30 Evaluation Board (6)Figure 2-1 Front View of NuMaker-N9H30 Board (9)Figure 2-2 Rear View of NuMaker-N9H30 Board (14)Figure 2-3 Front View of NuDesign-TFT-LCD7 Board (20)Figure 2-4 Rear View of NuDesign-TFT-LCD7 Board (21)Figure 2-5 Front View of NuMaker-N9H30 PCB Placement (22)Figure 2-6 Rear View of NuMaker-N9H30 PCB Placement (22)Figure 2-7 Front View of NuDesign-TFT-LCD7 PCB Placement (23)Figure 2-8 Rear View of NuDesign-TFT-LCD7 PCB Placement (23)Figure 3-1 GPIO List Circuit (24)Figure 3-2 System Block Circuit (25)Figure 3-3 Power Circuit (26)Figure 3-4 N9H30F61IEC Circuit (27)Figure 3-5 Setting, ICE, RS-232_0, Key Circuit (28)Figure 3-6 Memory Circuit (29)Figure 3-7 I2S, I2C_0, RS-486_6 Circuit (30)Figure 3-8 RS-232_2 Circuit (31)Figure 3-9 LCD Circuit (32)NUMAKER-HMI-N9H30 USER MANUAL Figure 3-10 CMOS Sensor, I2C_1, CAN_0 Circuit (33)Figure 3-11 RMII_0_PF Circuit (34)Figure 3-12 RMII_1_PE Circuit (35)Figure 3-13 USB Circuit (36)Figure 3-14 TFT-LCD7 Circuit (37)List of TablesTable 2-1 LCD Panel Combination Connector (CON8) Pin Function (11)Table 2-2 Three Sets of Indication LED Functions (12)Table 2-3 Six Sets of User SW, Key Matrix Functions (12)Table 2-4 CMOS Sensor Connector (CON10) Function (13)Table 2-5 JTAG ICE Interface (J2) Function (14)Table 2-6 Expand Port (CON7) Function (16)Table 2-7 UART0 (J3) Function (16)Table 2-8 UART2 (J6) Function (16)Table 2-9 RS-485_6 (SW6~8) Function (17)Table 2-10 Power on Setting (SW4) Function (17)Table 2-11 Power on Setting (S2) Function (17)Table 2-12 Power on Setting (S3) Function (17)Table 2-13 Power on Setting (S4) Function (17)Table 2-14 Power on Setting (S5) Function (17)Table 2-15 Power on Setting (S7/S6) Function (18)Table 2-16 Power on Setting (S9/S8) Function (18)Table 2-17 CMOS Sensor Connector (CON9) Function (19)Table 2-18 CAN_0 (SW9~10) Function (19)NUMAKER-HMI-N9H30 USER MANUAL1 OVERVIEWThe NuMaker-HMI-N9H30 is an evaluation board for GUI application development. The NuMaker-HMI-N9H30 consists of two parts: a NuMaker-N9H30 main board and a NuDesign-TFT-LCD7 extensionboard. The NuMaker-HMI-N9H30 is designed for project evaluation, prototype development andvalidation with HMI (Human Machine Interface) function.The NuMaker-HMI-N9H30 integrates touchscreen display, voice input/output, rich serial port serviceand I/O interface, providing multiple external storage methods.The NuDesign-TFT-LCD7 can be plugged into the main board via the DIN_32x2 extension connector.The NuDesign-TFT-LCD7 includes one 7” LCD which the resolution is 800x480 with RGB-24bits andembedded the 4-wires resistive type touch panel.Figure 1-1 Front View of NuMaker-HMI-N9H30 Evaluation BoardNUMAKER-HMI-N9H30 USER MANUAL Figure 1-2 Rear View of NuMaker-HMI-N9H30 Evaluation Board1.1 Features1.1.1 NuMaker-N9H30 Main Board Features●N9H30F61IEC chip: LQFP216 pin MCP package with DDR (64 MB)●SPI Flash using W25Q256JVEQ (32 MB) booting with quad mode or storage memory●NAND Flash using W29N01HVSINA (128 MB) booting or storage memory●One Micro-SD/TF card slot served either as a SD memory card for data storage or SDIO(Wi-Fi) device●Two sets of COM ports:–One DB9 RS-232 port with UART_0 used 75C3232E transceiver chip can be servedfor function debug and system development.–One DB9 RS-232 port with UART_2 used 75C3232E transceiver chip for userapplication●22 GPIO expansion ports, including seven sets of UART functions●JTAG interface provided for software development●Microphone input and Earphone/Speaker output with 24-bit stereo audio codec(NAU88C22) for I2S interfaces●Six sets of user-configurable push button keys●Three sets of LEDs for status indication●Provides SN65HVD230 transceiver chip for CAN bus communication●Provides MAX3485 transceiver chip for RS-485 device connection●One buzzer device for program applicationNUMAKER-HMI-N9H30 USER MANUAL●Two sets of RJ45 ports with Ethernet 10/100 Mbps MAC used IP101GR PHY chip●USB_0 that can be used as Device/HOST and USB_1 that can be used as HOSTsupports pen drives, keyboards, mouse and printers●Provides over-voltage and over current protection used APL3211A chip●Retain RTC battery socket for CR2032 type and ADC0 detect battery voltage●System power could be supplied by DC-5V adaptor or USB VBUS1.1.2 NuDesign-TFT-LCD7 Extension Board Features●7” resolution 800x480 4-wire resistive touch panel for 24-bits RGB888 interface●DIN_32x2 extension connector1.2 Supporting ResourcesFor sample codes and introduction about NuMaker-N9H30, please refer to N9H30 BSP:https:///products/gui-solution/gui-platform/numaker-hmi-n9h30/?group=Software&tab=2Visit NuForum for further discussion about the NuMaker-HMI-N9H30:/viewforum.php?f=31 NUMAKER-HMI-N9H30 USER MANUALNUMAKER-HMI-N9H30 USER MANUAL2 NUMAKER-HMI-N9H30 HARDWARE CONFIGURATION2.1 NuMaker-N9H30 Board - Front View Combination Connector (CON8)6 set User SWs (K1~6)3set Indication LEDs (LED1~3)Power Supply Switch (SW_POWER1)Audio Codec(U10)Microphone(M1)NAND Flash(U9)RS-232 Transceiver(U6, U12)RS-485 Transceiver(U11)CAN Transceiver (U13)Figure 2-1 Front View of NuMaker-N9H30 BoardFigure 2-1 shows the main components and connectors from the front side of NuMaker-N9H30 board. The following lists components and connectors from the front view:NuMaker-N9H30 board and NuDesign-TFT-LCD7 board combination connector (CON8). This panel connector supports 4-/5-wire resistive touch or capacitance touch panel for 24-bits RGB888 interface.Connector GPIO pin of N9H30 FunctionCON8.1 - Power 3.3VCON8.2 - Power 3.3VCON8.3 GPD7 LCD_CSCON8.4 GPH3 LCD_BLENCON8.5 GPG9 LCD_DENCON8.7 GPG7 LCD_HSYNCCON8.8 GPG6 LCD_CLKCON8.9 GPD15 LCD_D23(R7)CON8.10 GPD14 LCD_D22(R6)CON8.11 GPD13 LCD_D21(R5)CON8.12 GPD12 LCD_D20(R4)CON8.13 GPD11 LCD_D19(R3)CON8.14 GPD10 LCD_D18(R2)CON8.15 GPD9 LCD_D17(R1)CON8.16 GPD8 LCD_D16(R0)CON8.17 GPA15 LCD_D15(G7)CON8.18 GPA14 LCD_D14(G6)CON8.19 GPA13 LCD_D13(G5)CON8.20 GPA12 LCD_D12(G4)CON8.21 GPA11 LCD_D11(G3)CON8.22 GPA10 LCD_D10(G2)CON8.23 GPA9 LCD_D9(G1) NUMAKER-HMI-N9H30 USER MANUALCON8.24 GPA8 LCD_D8(G0)CON8.25 GPA7 LCD_D7(B7)CON8.26 GPA6 LCD_D6(B6)CON8.27 GPA5 LCD_D5(B5)CON8.28 GPA4 LCD_D4(B4)CON8.29 GPA3 LCD_D3(B3)CON8.30 GPA2 LCD_D2(B2)CON8.31 GPA1 LCD_D1(B1)CON8.32 GPA0 LCD_D0(B0)CON8.33 - -CON8.34 - -CON8.35 - -CON8.36 - -CON8.37 GPB2 LCD_PWMCON8.39 - VSSCON8.40 - VSSCON8.41 ADC7 XPCON8.42 ADC3 VsenCON8.43 ADC6 XMCON8.44 ADC4 YMCON8.45 - -CON8.46 ADC5 YPCON8.47 - VSSCON8.48 - VSSCON8.49 GPG0 I2C0_CCON8.50 GPG1 I2C0_DCON8.51 GPG5 TOUCH_INTCON8.52 - -CON8.53 - -CON8.54 - -CON8.55 - -NUMAKER-HMI-N9H30 USER MANUAL CON8.56 - -CON8.57 - -CON8.58 - -CON8.59 - VSSCON8.60 - VSSCON8.61 - -CON8.62 - -CON8.63 - Power 5VCON8.64 - Power 5VTable 2-1 LCD Panel Combination Connector (CON8) Pin Function●Power supply switch (SW_POWER1): System will be powered on if the SW_POWER1button is pressed●Three sets of indication LEDs:LED Color DescriptionsLED1 Red The system power will beterminated and LED1 lightingwhen the input voltage exceeds5.7V or the current exceeds 2A.LED2 Green Power normal state.LED3 Green Controlled by GPH2 pin Table 2-2 Three Sets of Indication LED Functions●Six sets of user SW, Key Matrix for user definitionKey GPIO pin of N9H30 FunctionK1 GPF10 Row0 GPB4 Col0K2 GPF10 Row0 GPB5 Col1K3 GPE15 Row1 GPB4 Col0K4 GPE15 Row1 GPB5 Col1K5 GPE14 Row2 GPB4 Col0K6GPE14 Row2GPB5 Col1 Table 2-3 Six Sets of User SW, Key Matrix Functions●NAND Flash (128 MB) with Winbond W29N01HVS1NA (U9)●Microphone (M1): Through Nuvoton NAU88C22 chip sound input●Audio CODEC chip (U10): Nuvoton NAU88C22 chip connected to N9H30 using I2Sinterface–SW6/SW7/SW8: 1-2 short for RS-485_6 function and connected to 2P terminal (CON5and J5)–SW6/SW7/SW8: 2-3 short for I2S function and connected to NAU88C22 (U10).●CMOS Sensor connector (CON10, SW9~10)–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11)–SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensorconnector (CON10)Connector GPIO pin of N9H30 FunctionCON10.1 - VSSCON10.2 - VSSNUMAKER-HMI-N9H30 USER MANUALCON10.3 - Power 3.3VCON10.4 - Power 3.3VCON10.5 - -CON10.6 - -CON10.7 GPI4 S_PCLKCON10.8 GPI3 S_CLKCON10.9 GPI8 S_D0CON10.10 GPI9 S_D1CON10.11 GPI10 S_D2CON10.12 GPI11 S_D3CON10.13 GPI12 S_D4CON10.14 GPI13 S_D5CON10.15 GPI14 S_D6CON10.16 GPI15 S_D7CON10.17 GPI6 S_VSYNCCON10.18 GPI5 S_HSYNCCON10.19 GPI0 S_PWDNNUMAKER-HMI-N9H30 USER MANUAL CON10.20 GPI7 S_nRSTCON10.21 GPG2 I2C1_CCON10.22 GPG3 I2C1_DCON10.23 - VSSCON10.24 - VSSTable 2-4 CMOS Sensor Connector (CON10) FunctionNUMAKER-HMI-N9H30 USER MANUAL2.2NuMaker-N9H30 Board - Rear View5V In (CON1)RS-232 DB9 (CON2,CON6)Expand Port (CON7)Speaker Output (J4)Earphone Output (CON4)Buzzer (BZ1)System ResetSW (SW5)SPI Flash (U7,U8)JTAG ICE (J2)Power ProtectionIC (U1)N9H30F61IEC (U5)Micro SD Slot (CON3)RJ45 (CON12, CON13)USB1 HOST (CON15)USB0 Device/Host (CON14)CAN_0 Terminal (CON11)CMOS Sensor Connector (CON9)Power On Setting(SW4, S2~S9)RS-485_6 Terminal (CON5)RTC Battery(BT1)RMII PHY (U14,U16)Figure 2-2 Rear View of NuMaker-N9H30 BoardFigure 2-2 shows the main components and connectors from the rear side of NuMaker-N9H30 board. The following lists components and connectors from the rear view:● +5V In (CON1): Power adaptor 5V input ●JTAG ICE interface (J2) ConnectorGPIO pin of N9H30Function J2.1 - Power 3.3V J2.2 GPJ4 nTRST J2.3 GPJ2 TDI J2.4 GPJ1 TMS J2.5 GPJ0 TCK J2.6 - VSS J2.7 GPJ3 TD0 J2.8-RESETTable 2-5 JTAG ICE Interface (J2) Function●SPI Flash (32 MB) with Winbond W25Q256JVEQ (U7); only one (U7 or U8) SPI Flashcan be used●System Reset (SW5): System will be reset if the SW5 button is pressed●Buzzer (BZ1): Control by GPB3 pin of N9H30●Speaker output (J4): Through the NAU88C22 chip sound output●Earphone output (CON4): Through the NAU88C22 chip sound output●Expand port for user use (CON7):Connector GPIO pin of N9H30 FunctionCON7.1 - Power 3.3VCON7.2 - Power 3.3VCON7.3 GPE12 UART3_TXDCON7.4 GPH4 UART1_TXDCON7.5 GPE13 UART3_RXDCON7.6 GPH5 UART1_RXDCON7.7 GPB0 UART5_TXDCON7.8 GPH6 UART1_RTSCON7.9 GPB1 UART5_RXDCON7.10 GPH7 UART1_CTSCON7.11 GPI1 UART7_TXDNUMAKER-HMI-N9H30 USER MANUAL CON7.12 GPH8 UART4_TXDCON7.13 GPI2 UART7_RXDCON7.14 GPH9 UART4_RXDCON7.15 - -CON7.16 GPH10 UART4_RTSCON7.17 - -CON7.18 GPH11 UART4_CTSCON7.19 - VSSCON7.20 - VSSCON7.21 GPB12 UART10_TXDCON7.22 GPH12 UART8_TXDCON7.23 GPB13 UART10_RXDCON7.24 GPH13 UART8_RXDCON7.25 GPB14 UART10_RTSCON7.26 GPH14 UART8_RTSCON7.27 GPB15 UART10_CTSCON7.28 GPH15 UART8_CTSCON7.29 - Power 5VCON7.30 - Power 5VTable 2-6 Expand Port (CON7) Function●UART0 selection (CON2, J3):–RS-232_0 function and connected to DB9 female (CON2) for debug message output.–GPE0/GPE1 connected to 2P terminal (J3).Connector GPIO pin of N9H30 Function J3.1 GPE1 UART0_RXDJ3.2 GPE0 UART0_TXDTable 2-7 UART0 (J3) Function●UART2 selection (CON6, J6):–RS-232_2 function and connected to DB9 female (CON6) for debug message output –GPF11~14 connected to 4P terminal (J6)Connector GPIO pin of N9H30 Function J6.1 GPF11 UART2_TXDJ6.2 GPF12 UART2_RXDJ6.3 GPF13 UART2_RTSJ6.4 GPF14 UART2_CTSTable 2-8 UART2 (J6) Function●RS-485_6 selection (CON5, J5, SW6~8):–SW6~8: 1-2 short for RS-485_6 function and connected to 2P terminal (CON5 and J5) –SW6~8: 2-3 short for I2S function and connected to NAU88C22 (U10)Connector GPIO pin of N9H30 FunctionSW6:1-2 shortGPG11 RS-485_6_DISW6:2-3 short I2S_DOSW7:1-2 shortGPG12 RS-485_6_ROSW7:2-3 short I2S_DISW8:1-2 shortGPG13 RS-485_6_ENBSW8:2-3 short I2S_BCLKNUMAKER-HMI-N9H30 USER MANUALTable 2-9 RS-485_6 (SW6~8) FunctionPower on setting (SW4, S2~9).SW State FunctionSW4.2/SW4.1 ON/ON Boot from USB SW4.2/SW4.1 ON/OFF Boot from eMMC SW4.2/SW4.1 OFF/ON Boot from NAND Flash SW4.2/SW4.1 OFF/OFF Boot from SPI Flash Table 2-10 Power on Setting (SW4) FunctionSW State FunctionS2 Short System clock from 12MHzcrystalS2 Open System clock from UPLL output Table 2-11 Power on Setting (S2) FunctionSW State FunctionS3 Short Watchdog Timer OFFS3 Open Watchdog Timer ON Table 2-12 Power on Setting (S3) FunctionSW State FunctionS4 Short GPJ[4:0] used as GPIO pinS4Open GPJ[4:0] used as JTAG ICEinterfaceTable 2-13 Power on Setting (S4) FunctionSW State FunctionS5 Short UART0 debug message ONS5 Open UART0 debug message OFFTable 2-14 Power on Setting (S5) FunctionSW State FunctionS7/S6 Short/Short NAND Flash page size 2KBS7/S6 Short/Open NAND Flash page size 4KBS7/S6 Open/Short NAND Flash page size 8KBNUMAKER-HMI-N9H30 USER MANUALS7/S6 Open/Open IgnoreTable 2-15 Power on Setting (S7/S6) FunctionSW State FunctionS9/S8 Short/Short NAND Flash ECC type BCH T12S9/S8 Short/Open NAND Flash ECC type BCH T15S9/S8 Open/Short NAND Flash ECC type BCH T24S9/S8 Open/Open IgnoreTable 2-16 Power on Setting (S9/S8) FunctionCMOS Sensor connector (CON9, SW9~10)–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11).–SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensorconnector (CON9).Connector GPIO pin of N9H30 FunctionCON9.1 - VSSCON9.2 - VSSCON9.3 - Power 3.3VCON9.4 - Power 3.3V NUMAKER-HMI-N9H30 USER MANUALCON9.5 - -CON9.6 - -CON9.7 GPI4 S_PCLKCON9.8 GPI3 S_CLKCON9.9 GPI8 S_D0CON9.10 GPI9 S_D1CON9.11 GPI10 S_D2CON9.12 GPI11 S_D3CON9.13 GPI12 S_D4CON9.14 GPI13 S_D5CON9.15 GPI14 S_D6CON9.16 GPI15 S_D7CON9.17 GPI6 S_VSYNCCON9.18 GPI5 S_HSYNCCON9.19 GPI0 S_PWDNCON9.20 GPI7 S_nRSTCON9.21 GPG2 I2C1_CCON9.22 GPG3 I2C1_DCON9.23 - VSSCON9.24 - VSSTable 2-17 CMOS Sensor Connector (CON9) Function●CAN_0 Selection (CON11, SW9~10):–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11) –SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensor connector (CON9, CON10)SW GPIO pin of N9H30 FunctionSW9:1-2 shortGPI3 CAN_0_RXDSW9:2-3 short S_CLKSW10:1-2 shortGPI4 CAN_0_TXDSW10:2-3 short S_PCLKTable 2-18 CAN_0 (SW9~10) Function●USB0 Device/HOST Micro-AB connector (CON14), where CON14 pin4 ID=1 is Device,ID=0 is HOST●USB1 for USB HOST with Type-A connector (CON15)●RJ45_0 connector with LED indicator (CON12), RMII PHY with IP101GR (U14)●RJ45_1 connector with LED indicator (CON13), RMII PHY with IP101GR (U16)●Micro-SD/TF card slot (CON3)●SOC CPU: Nuvoton N9H30F61IEC (U5)●Battery power for RTC 3.3V powered (BT1, J1), can detect voltage by ADC0●RTC power has 3 sources:–Share with 3.3V I/O power–Battery socket for CR2032 (BT1)–External connector (J1)●Board version 2.1NUMAKER-HMI-N9H30 USER MANUAL2.3 NuDesign-TFT-LCD7 -Front ViewFigure 2-3 Front View of NuDesign-TFT-LCD7 BoardFigure 2-3 shows the main components and connectors from the Front side of NuDesign-TFT-LCD7board.7” resolution 800x480 4-W resistive touch panel for 24-bits RGB888 interface2.4 NuDesign-TFT-LCD7 -Rear ViewFigure 2-4 Rear View of NuDesign-TFT-LCD7 BoardFigure 2-4 shows the main components and connectors from the rear side of NuDesign-TFT-LCD7board.NuMaker-N9H30 and NuDesign-TFT-LCD7 combination connector (CON1).NUMAKER-HMI-N9H30 USER MANUAL 2.5 NuMaker-N9H30 and NuDesign-TFT-LCD7 PCB PlacementFigure 2-5 Front View of NuMaker-N9H30 PCB PlacementFigure 2-6 Rear View of NuMaker-N9H30 PCB PlacementNUMAKER-HMI-N9H30 USER MANUALFigure 2-7 Front View of NuDesign-TFT-LCD7 PCB PlacementFigure 2-8 Rear View of NuDesign-TFT-LCD7 PCB Placement3 NUMAKER-N9H30 AND NUDESIGN-TFT-LCD7 SCHEMATICS3.1 NuMaker-N9H30 - GPIO List CircuitFigure 3-1 shows the N9H30F61IEC GPIO list circuit.Figure 3-1 GPIO List Circuit NUMAKER-HMI-N9H30 USER MANUAL3.2 NuMaker-N9H30 - System Block CircuitFigure 3-2 shows the System Block Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-2 System Block Circuit3.3 NuMaker-N9H30 - Power CircuitFigure 3-3 shows the Power Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-3 Power Circuit3.4 NuMaker-N9H30 - N9H30F61IEC CircuitFigure 3-4 shows the N9H30F61IEC Circuit.Figure 3-4 N9H30F61IEC CircuitNUMAKER-HMI-N9H30 USER MANUAL3.5 NuMaker-N9H30 - Setting, ICE, RS-232_0, Key CircuitFigure 3-5 shows the Setting, ICE, RS-232_0, Key Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-5 Setting, ICE, RS-232_0, Key Circuit3.6 NuMaker-N9H30 - Memory CircuitFigure 3-6 shows the Memory Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-6 Memory Circuit3.7 NuMaker-N9H30 - I2S, I2C_0, RS-485_6 CircuitFigure 3-7 shows the I2S, I2C_0, RS-486_6 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-7 I2S, I2C_0, RS-486_6 Circuit3.8 NuMaker-N9H30 - RS-232_2 CircuitFigure 3-8 shows the RS-232_2 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-8 RS-232_2 Circuit3.9 NuMaker-N9H30 - LCD CircuitFigure 3-9 shows the LCD Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-9 LCD Circuit3.10 NuMaker-N9H30 - CMOS Sensor, I2C_1, CAN_0 CircuitFigure 3-10 shows the CMOS Sensor,I2C_1, CAN_0 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-10 CMOS Sensor, I2C_1, CAN_0 Circuit3.11 NuMaker-N9H30 - RMII_0_PF CircuitFigure 3-11 shows the RMII_0_RF Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-11 RMII_0_PF Circuit3.12 NuMaker-N9H30 - RMII_1_PE CircuitFigure 3-12 shows the RMII_1_PE Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-12 RMII_1_PE Circuit3.13 NuMaker-N9H30 - USB CircuitFigure 3-13 shows the USB Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-13 USB Circuit3.14 NuDesign-TFT-LCD7 - TFT-LCD7 CircuitFigure 3-14 shows the TFT-LCD7 Circuit.Figure 3-14 TFT-LCD7 CircuitNUMAKER-HMI-N9H30 USER MANUAL4 REVISION HISTORYDate Revision Description2022.03.24 1.00 Initial version NUMAKER-HMI-N9H30 USER MANUALNUMAKER-HMI-N9H30 USER MANUALImportant NoticeNuvoton Products are neither intended nor warranted for usage in systems or equipment, anymalfunction or failure of which may cause loss of human life, bodily injury or severe propertydamage. Such applications are deemed, “Insecure Usage”.Insecure usage includes, but is not limited to: equipment for surgical implementation, atomicenergy control instruments, airplane or spaceship instruments, the control or operation ofdynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all typesof safety devices, and other applications intended to support or sustain life.All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claimsto Nuvoton as a result of customer’s Insecure Usage, custome r shall indemnify the damagesand liabilities thus incurred by Nuvoton.。
新核心网开站步骤(精)
关于阿朗CDMA的IPBH基站的整合步骤主要目的:因目前新局使用的基站使用IPBH和以前的frame relay方式不同,添加了阿朗的路由交换机7750设备代替了5E同基站连接。
根据新局现场(软件是R31版)的测试经验,总结基站部分的内容,方便SUB-C工程师查阅和尽快上手,也为客户准备技术文档。
步骤简介:根据IPBH基站的特点,主要三个部分步骤:一,基站硬件安装调测二,基站和7750确认传输路由的配合步骤三,基站的数据添加一,基站硬件安装调测1)基站硬件安装完毕2) 基站用RMT调测基站背板参数,把Frame 转为PPP模式,主要是在RMT/boot memory parameter窗口中/trunk group controller parameter简称TGCP和initial link configuration parameter简称ILCP/ recall成RMT自带的配置文件/自己电脑中的RMT目录/config/1bts/IEH/BMP/中根据URC功能配置分1X和EVDO两种:1X的URC是/Voice/URC-URCII/E1/IPBH-Voice/CDM has its owner E1s/TGCP-CDM(1-5-9-13)-IPBH-E1-v4和/Voice/URC-URCII/E1/IPBH-Voice/CDM has its owner E1s/ILCP-CDM(1-5-9-13)-IPBH-E1-v4EVDO的URCII是EVDO/URC-URCII/E1/PPP-EVDO/CDM has its owner E1s/TGCP-CDM(2-6-10-14)-PPP-E1-v4和EVDO/URC-URCII/E1/PPP-EVDO/CDM has its owner E1s/ILCP-CDM(2-6-10-14)-PPP-E1-v4二,基站和7750确认传输路由的配合步骤1,7750加数据需要的条件:1)基站RCS号2)基站传输编号,主要基站每条传输E1是第几个155M(7750连接40条155M)的第几个时隙(每条155M有63个时隙),需要电信客户传输部门提供3)基站现场的E1先自环并和7750工程师配合断开测试确认E1正常2,在基站现场确认得到IP地址,网线连接到基站,telnet 192.168.168.16(第一块URC)或192.168.168.32(第二块URC),执行下面的命令:用户名:lucent 密码:password自动出现背板参数击入:mlpppShow检查是否有MY IP和Primary DNS IP及Secondary DNS IP,这三个IP是7750配置的数据,必须全部是有IP地址的,如为0.0.0.0则基站信令不会起来的,需要联系7750工程师确认或添加数据。
AWG5000系列混合信号伪随机波形生成器说明书
Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)The AWG5000 Series of Arbitrary Waveform Generators Delivers the Industry’s Best Mixed Signal Stimulus Solution for Today’s Complex Measurement ChallengesThe AWG5000 Series of Arbitrary Waveform Generators delivers theoptimal combination of industry leading sample rate, vertical resolution, signal fidelity and waveform memory length,all in an easy-to-use self-contained package.The series offers the industry’s best solution to the challenging signal stim-ulus issues faced by designers verifying,characterizing and debugging sophisti-cated electronic designs.Meeting the needs of today’s design engineers, the series provides excellent signal dynamic range and integrity.AWG5000 Series models, with a 14bits DA converter based sample rate from 600MS/s to 1.2GS/s, two to four output channels, synchronized four to eight digital marker outputs, and 28-channels of digital data outputs, easily solve the toughest measurement chal-lenges in wireless base band I/Q communications, digital consumer product design such as imaging devices, data conversion equipment and semiconductor design and test. The open Windows (Windows XP)-based instruments are easy and convenient to use and connect easily with peripherals and third-party software.AWG5000 Series.Features & Benefits1.2Gs/s and 600MS/s Models 14 bit Vertical Resolution 2 or 4Arbitrary WaveformDifferential/Single-ended Outputs –Up to 4.5V p-p Single-ended and 9V p-p at Differential Output into 50Ω–0.95ns Tr/Tf (10 to 90%) at 0.6V p-p–+/– 5ns Range (50ps Resolution) Inter Channel Skew Control–SFDR: 80dBc (1MHz),64dBc (10MHz)4 or 8Variable Level Marker Outputs–Up to 3.7V p-p Single-ended Output into 50Ω–300ps Tr/Tf (20 to 80%)at 0 to 1V–Up to 1ns Range (50ps Resolution) Delay Control28 Bits Ch 1/Ch 2Variable Level Digital Data Output–Up to 3.7V p-p Single-ended Output into 50Ω–300ps Tr/Tf (20 to 80%)at 0 to 1VUp to 32M Point Record Length For Longer Data Streams Down to 800ps Resolution Edge Timing Shift Control Real-time Sequencing Creates Infinite Waveform Loops, Jumps,and Conditional BranchesEasy to Use and Learn Shortens Test TimeIntuitive User Interface Based on Windows 2000 XP Convenient Bench Top Form FactorIntegrated PC Supports Network Integration and Provides a Built-in DVD, Removable Hard Drive,LAN and USB portsApplicationsDesigning, Testing and Deploying Wireless Communications: –High Fidelity QuadratureModulation I and Q Base-band Signals (Polar Modulation:I/Q + Magnitude Control, Two Pair of I/Q for MIMO)Imaging–Stimulus Signals for Imaging Display and Recording Devices (CCD, LCD)Data Conversion–Stimulus Signals for DataConversion Devices (ADC, DAC)Mixed Signal Design and Test –2/4Ch Analog + 4/8Ch Marker Outputs + 28 Bit Digital Data OutputsReal-world, Ideal or Distorted Signal Generation – Including All the Glitches, Anomalies and ImpairmentsEnhanced/Corrupted Playback of DSO Captured SignalsWaveform Vectors Imported from Third-party T ools such as MathCAD,MATLAB, Excel and OthersArbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)AWG5000 Series • /signal_sources2EVM/Constellation measurement.Typical Signal Injection.Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002) RTSA Spectrum view.9-PAM with 250 Mbps.Mixed signal test by TDS/TLA iView.™AWG5000 Series • /signal_sources3Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)4AWG5000 Series • /signal_sourcesArbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)AWG5014AWG5012AWG5004AWG5002Arbitrary WaveformsWaveform Length 1 to 16,200,000 points (or 1 to 32,400,000 points,option 01)Number of Waveforms 1 to 16,000Sequence Length 1 to 4,000stepsSequence Repeat Counter 1 to 65,536 or infiniteSequence Control Repeat count,Trigger,Go-to-N and JumpJump Mode Synchronous and AsynchronousRun ModesContinuous Waveform is iteratively output.If a sequence is defined,the sequence order and repeat functions are appliedTriggered Waveform is output only once when an external,internal,GPIB,LAN or manual trigger is receivedGated Waveform begins output when gate is true and resets to beginning when falseSequence Waveform is output as defined by the sequenceClock GeneratorSampling Frequency10 MS/s to 1.2GS/s10 MS/s to 600 MS/sResolution8digitsInternal ClockAccuracy Within ±(1 ppm + Aging),Aging:within ±1 ppm/yearClock Phase Noise Less than –90dBc/Hz at 100kHz offsetInternal Trigger GeneratorInternal Trigger RateRange 1.0μs to 10.0sResolution3digits,0.1μs minimumSkew Control Between OutputsRange– 5 ns to + 5nsResolution5psAWG5000 Series • /signal_sources5Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)AWG5000 Series • /signal_sources6AWG5014AWG5012AWG5004AWG5002Main Arbitrary Waveform Output Resolution14 bitsAnalog OutputOutput StyleDifferential Output Impedance 50ΩConnectorBNC FrontAmplitude Output Voltage Normal:–4.5 V to + 4.5V,Direct –0.3V to +0.3V Amplitude Normal:20mV p-p to 4.5V p-p ,Direct; 20mV p-p to 0.6V p-pResolution 1mVDC Accuracy±(2.0% of Amplitude + 2mV) at offset = 0V Offset (into 50Ω) Range Normal:–2.25V to +2.25V,Direct:N/A Resolution 1mVAccuracy±(2% of offset +10mV at minimum amplitudePulse Response Rise/Fall time:(10% to 90%).Normal:1.4ns (2.0V p-p ),Direct:0.95ns (0.6V p-p )Bandwidth (–3dB)Normal:250MHz (2.0V p-p ),Direct:370MHz (0.6V p-p )Ringing Normal:750mV p-p (4.5V p-p filter through),80mV p-p (2.0V p-p filter through),Direct:60mV p-p (0.6V p-p )Low Pass Filter High range:100MHz,20MHz,Low range:through,100MHz,20MHz,Direct:N/ADelay from Marker Normal:17.5ns to 19.4ns (20MHz filter),3.8ns to 5.7ns (100MHz filter),0 to 1.9ns (Through),Direct:–1.5ns to 0.4nsSine Wave Characteristics (1.2GS/s clock,32 waveform points,37.5MHz signal frequency)(600MS/s clock,32 waveform points,18.75MHz signal frequency)Harmonics Normal:≤–40dBc (2.0V p-p ),Direct ≤=–49dBc (0.6V p-p )Normal:≤–46dBc (2.0V p-p ),Direct ≤=–55dBc (0.6V p-p )Non Harmonics Normal:≤–60dBc (2.0V p-p ,DC to 600MHz)Normal:≤–60dBc (2.0V p-p ,DC to 300MHz)Phase noise ≤–85dBc/Hz (2.0V p-p ,10kHz offset) –85dBc/Hz (2.0V p-p ,10kHz offset) SFDR 50dBc (Normal,37.5MHz,1.2GS/s,2.0V p-p )56dBc (Normal,18.75MHz,600MS/s,2.0V p-p )60dBc (Normal,10MHz,600MS/s,1.0V p-p )60dBc (Normal,10MHz,600MS/s,1.0V p-p )80dBc (Normal,1MHz,600MS/s,1.0V p-p )80dBc (Normal,1MHz,600MS/s,1.0V p-p )64dBc (Direct,10MHz,600 MS/s,0.6V p-p )64dBc (Direct,10MHz,600MS/s,0.6V p-p )80dBc (Direct,1MHz,600 MS/s,0.6V p-p )80dBc (Direct,1MHz,600MS/s,0.6V p-p )Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002) Auxiliary OutputsOutput Style Single-endedOutput Impedance50ΩConnector BNC FrontLevel (into 50Ω)(Twice for Hi_Z input)Output Windows–1.00 V to + 2.7VAmplitude0.10 Vp-p to 3.7 Vp-pResolution10mVDC Accuracy±(10% of setting +120mV) Maximum Output Current±54mA /chRise/Fall Time (20% to 80%)300 ps(1.0 Vp-p,Hi +1.0V,Lo 0V) Skew Adjust Between MarkersRange0 to 1000ps Resolution50psRandom Jitter (Typical)1010 clock patternRMS5psrmsTotal Jitter (Typical)2^15–1PN data patternPeak to Peak (p-p)80psp-pClock (VCO) OutRange600MHz to 1.2GHzAmplitude0.4 Vp-pinto 50Ωto GND Impedance:50Ω,AC coupling Connector BNC Rear10MHz Reference OutAmplitude 1.2 Vp-p into 50Ω.Max 2.5 Vp-popenImpedance50Ω,AC couplingConnector BNC RearDC OutputsNumber of Outputs4:independently controlled outputsRange–3.0 to +5.0VResolution10mVMax.Current±100mAConnector2x4 pin header on front panelAWG5000 Series • /signal_sources7Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)AWG5000 Series • /signal_sources8Trigger In Impedance 1 k Ωor 50ΩPolarity POS or NEG ConnectorBNC FrontInput Voltage Range1 k Ω:±10V.50 Ω:±5V Threshold Level –5.0 V to 5.0VResolution 0.1VTrigger Jitter2.0ns to 4.5ns (Typical) Trigger Mode Minimum Pulse Width 20nsTrigger Hold-off 832* sampling_period – 100ns Delay to Analog Out128* sampling_period + 250ns Gate Mode Minimum Pulse Width 1024* sampling_period + 10ns Delay to Analog Out640* sampling_period + 260ns Event Input Impedance 1 k Ωor 50ΩPolarity POS or NEG ConnectorBNC FrontInput Voltage Range 1 k Ω:±10V.50 Ω:±5V Threshold –5.0 V to 5.0VResolution0.1VSequence Mode Mode Minimum Pulse Width 20nsEvent Hold Off 1024* Sampling Period + 10nsDelay to Analog Out640* Sampling Period + 280 ns (Jump timing:Asynchronous jump)External Clock IN Input Voltage Range 0.2 V p-p to 0.8 V p-p Impedance50Ω,AC coupledConnectorBNC RearReference Clock IN Input Voltage Range 0.2 V p-p to 3.0 V p-p Impedance50Ω,AC coupledFrequency Range 10MHz,20MHz,100MHz (with ±0.1%)ConnectorBNC RearPhase Lock IN Input Ranges5MHz to 600MHz (acceptable frequency drift is ±0.5%)Input Voltage Range 0.2 V p-p to 3 V p-pConnectorBNC RearAdd IN For each analog channel Impedance 50Ω,DC coupledDC Gain 1BandwidthDC to 100MHz at –3 dBInput Voltage Range ±1.0V ConnectorBNC RearArbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)(Third party software creation waveform data:MATLAB,MathCad,Excel)S/W driver for 3rd party S/W IVI-com driver and MATLAB libraryInstrument Control/Data Transfer PortsGPIB Remote control and data transfer.(Conforms to IEEE-Std 488.1,compatible with IEEE 488.2 and SCPI-1999.0)Ethernet (10/100/1000Base-T)Remote control and data transfer.(Conforms to IEEE 802.3).RJ-45Computer System & Peripherals Windows XP Professional,512 MB SDRAM,80 GB removable Hard Drive at rear (available front mount kit),CD-RW/DVD drive at front,included USB compact keyboard and mousePC I/O Ports USB 2.0 compliant ports (6 total,2 front,4 rear),PS/2mouse and keyboard connectors (rear panel),RJ-45 Ethernet connector (rear panel) supports 10/100/1000BASE-T,XGA outDisplay Characteristics10.4inch,LCD color display with touch screen,1024 (H)x768 (V) (XGA)Power Supply100 to 240VAC,47 to 63HzPower Consumption450WSafety UL61010-1,CAN/CSA-22.2,No.61010-1-04,EN61010-1,IEC61010-1Emissions EN 55011 (Class A),IEC61000-3-2,IEC61000-3-3Immunity IEC61326,IEC61000-4-2/3/4/5/6/8/11Regional CertificationsEurope EN61326Australia/New Zealand AS/NZS 2064AWG5000 Series • /signal_sources9Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)Ordering Information Arbitrary WaveformGenerator MainframeAWG50141.2GS/s,4-channel,14bits,16M point/channel Arbitrary Waveform Generator.AWG50121.2GS/s,2-channel,14bits,16M point/channel Arbitrary Waveform Generator.AWG5004600MS/s,4-channel,14bits,16M point/channel Arbitrary Waveform Generator.AWG5002600MS/s,2-channel,14bits,16M point/channel Arbitrary Waveform Generator.All Models Include:Accessory pouch,front cover, USB mouse,compact USB key board,lead set for DC output,stylus for touch screen 2 each, Windows®XP operating system restore DVD and instructions,AWG5000 Series product software CD and instructions,Document CD with Browser,Quick Start User Manual,registration card,Certificate of Calibration,power cable.Note:Please specify power cord and language option when ordering.Instrument OptionsAWG5014/AWG5012,AWG5004/AWG5002Opt.01 – Waveform Length Expansion (from 16 M to 32 M).AWG5012/AWG5002Opt. 03 –28 bits digital data outputs (digital data of ch 1 and ch 2).Common OptionsInternational Power PlugsOpt. A0 – North America power.Opt. A1 –Universal EURO power.Opt. A2 – United Kingdom power.Opt. A3 – Australia power.Opt. A5 – Switzerland power.Opt.A6 –Japan power.Opt.A10 – China power.Opt.A99 – No power cord or AC adapter.Language OptionsOpt. L0 – English.Opt. L5 – Japanese.Opt. L7 –Simplified Chinese.Opt. L8 – Traditional Chinese.ServiceOpt. CA1 – A single calibration event.Opt. C3 – Calibration service 3 years.Opt. C5 – Calibration service 5 years.Opt. D1 –Calibration data report.Opt. D3 – Calibration data report 3 years (withoption C3).Opt. D5 – Calibration data report 5 years (withoption C5).Opt. R3 –Repair service 3 years.Opt. R5 –Repair service 5 years.Post-sales Service Options:(e.g.,AWG5012-CA1).CA1 – A single calibration event.R3DW – Repair service coverage 3 years.R5DW – Repair service coverage 5 years.R2PW –Repair service coverage 2 yearspost warranty.R1PW –Repair service coverage 1 yearpost warranty.Product UpgradeAWG5014, AWG50UPOpt.M14 – Waveform Length Expansionfrom 16 M point to 32 M point.Product UpgradeAWG5012, AWG50UPOpt. M12 – Waveform Length Expansionfrom 16 M point to 32 M point.Opt.D13 –Digital Data Outputs.Product UpgradeAWG5004, AWG50UPOpt. M04 – Waveform Length Expansionfrom 16 M point to 32 M point.Product UpgradeAWG5002, AWG50UPOpt.M02 – Waveform Length Expansionfrom 16 M point to 32 M point.Opt.D03 –Digital Data Outputs.AWG5000 Series • /signal_sources 10Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)WarrantyOne-year parts and labor.AWG5000 Series • /signal_sources11Arbitrary Waveform GeneratorAWG5000 Series (AWG5014 • AWG5012 • AWG5004 • AWG5002)For Further InformationTektronix maintains a comprehensive, constantly expanding collection of application notes, technical briefs and other resources to help engineers working on the cutting edge of technology. Please visit Copyright © 2008, Tektronix. All rights reserved. Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material.Specification and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of Tektronix, Inc. All other trade names referenced are the service marks, trademarks or registered trademarks of their respective companies. 07/08 JS/WOW 76W-20381-3Contact Tektronix:ASEAN/Australasia (65) 6356 3900Austria +41 52 675 3777Balkans, Israel, South Africa and other ISE Countries +41 52 675 3777Belgium 07 81 60166Brazil & South America (11) 40669400Canada 1 (800) 661-5625Central East Europe, Ukraine and the Baltics +41 52 675 3777Central Europe & Greece +41 52 675 3777Denmark +45 80 88 1401Finland +41 52 675 3777France +33 (0) 1 69 86 81 81Germany +49 (221) 94 77 400Hong Kong (852) 2585-6688India (91) 80-22275577Italy +39 (02) 25086 1Japan 81 (3) 6714-3010Luxembourg +44 (0) 1344 392400Mexico, Central America & Caribbean 52 (55) 5424700Middle East, Asia and North Africa +41 52 675 3777The Netherlands ***********Norway 800 16098People’s Republic of China 86 (10) 6235 1230Poland +41 52 675 3777Portugal 80 08 12370Republic of Korea 82 (2) 6917-5000Russia & CIS +7 (495) 7484900South Africa +27 11 206 8360Spain (+34) 901 988 054Sweden 020 08 80371Switzerland +41 52 675 3777Taiwan 886 (2) 2722-9622United Kingdom & Eire +44 (0) 1344 392400USA 1 (800) 426-2200For other areas contact Tektronix, Inc. at: 1 (503) 627-7111Updated 12 November 2007roduct(s) are manufactured in ISO registered facilitie Product(s) complies with IEEE Standard 488.1-1987,RS-232-C,and with Tektronix Standard Codes and Formats.。
AJA FS2 Installation and Operation Guide
AJA FS2 Installation and Operation Installation and Operation GuideB e c a u s e i t m a t t e r s .7/31/2012 Version: 1.1.0.0TrademarksAJA®, KONA®, Ki Pro®, KUMO®, and XENA® are registered trademarks of AJA Video, Inc. Io Express™,Io HD™ and Io™ are trademarks of AJA Video, Inc. Apple, the Apple logo, AppleShare, AppleTalk,FireWire, iPod, iPod Touch, Mac, and Macintosh are registered trademarks of Apple Computer, Inc.Final Cut Pro, QuickTime and the QuickTime Logo are trademarks of Apple Computer, Inc. All othertrademarks are the property of their respective holders.NoticeCopyright © 2012 AJA Video, Inc. All rights reserved. All information in this manual is subject tochange without notice. No part of the document may be reproduced or transmitted in any form,or by any means, electronic or mechanical, including photocopying or recording, without theexpress written permission of AJA Inc.FCC Emission InformationThis equipment has been tested and found to comply with the limits for a Class A digital device,pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protectionagainst harmful interference when the equipment is operated in a commercial environment. Thisequipment generates, uses and can radiate radio frequency energy and, if not installed and usedin accordance with the instruction manual, may cause harmful interference to radiocommunications. Operation of this equipment in a residential area is likely to cause harmfulinterference in which case the user will be required to correct the interference at his own expense.Changes or modifications not expressly approved by AJA Video can effect emission complianceand could void the user’s authority to operate this equipment.Contacting SupportTo contact AJA Video for sales or support, use any of the following methods:180 Litton Drive, Grass Valley, CA. 95945 USATelephone: +1.800.251.4224 or +1.530.274.2048Fax: +1.530.274.9442Web: SupportEmail:***************SalesEmail:*************1FS2 Installation and Operation Manual — Limited Warranty Limited WarrantyAJA Video warrants that this product will be free from defects in materials and workmanship for aperiod of five years from the date of purchase. If a product proves to be defective during thiswarranty period, AJA Video, at its option, will either repair the defective product without charge forparts and labor, or will provide a replacement in exchange for the defective product.In order to obtain service under this warranty, you the Customer, must notify AJA Video of the defectbefore the expiration of the warranty period and make suitable arrangements for the performanceof service. The Customer shall be responsible for packaging and shipping the defective product to adesignated service center nominated by AJA Video, with shipping charges prepaid. AJA Video shallpay for the return of the product to the Customer if the shipment is to a location within the countryin which the AJA Video service center is located. Customer shall be responsible for paying allshipping charges, insurance, duties, taxes, and any other charges for products returned to any otherlocations.This warranty shall not apply to any defect, failure or damage caused by improper use or improper orinadequate maintenance and care. AJA Video shall not be obligated to furnish service under thiswarranty a) to repair damage resulting from attempts by personnel other than AJA Videorepresentatives to install, repair or service the product, b) to repair damage resulting from improperuse or connection to incompatible equipment, c) to repair any damage or malfunction caused bythe use of non-AJA Video parts or supplies, or d) to service a product that has been modified orintegrated with other products when the effect of such a modification or integration increases thetime or difficulty of servicing the product.THIS WARRANTY IS GIVEN BY AJA VIDEO IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED.AJA VIDEO AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY ORFITNESS FOR A PARTICULAR PURPOSE. AJA VIDEO’S RESPONSIBILITY TO REPAIR OR REPLACEDEFECTIVE PRODUCTS IS THE WHOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FORANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHERAJA VIDEO OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. Important Safety InformationHazard!This symbol, when used in the manual, indicates a serious health hazard with risk of injury ordeath.Warning!This symbol, when used in the manual, indicates a serious risk or threat to personal safety.Caution!This symbol, when used in the manual, indicates important safety and complianceinformation.Table of Contents ContentsAJA FS2 Installation and Operation Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiFCC Emission Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Contacting Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Limited Warranty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Important Safety Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vChapter 1:Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Video Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Available Video Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Audio Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Control and Other Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Typical Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3FS2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Front Panel Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Remote Web Browser Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SNMP Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4GPI Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Optional Remote Control Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Optional Fiber I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Optional Dolby E Decoder and Encoder Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Video Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73G Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Audio Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 What’s In The Box? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9In This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Chapter 2:Controls, Indicators, and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Control and Indicator Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Front Panel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Alphanumeric Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operational Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pushbuttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Control Knobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Incompatibility Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Incompatible Video Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Example Reference and Video Incompatibility Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Rear Panel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Connector Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AES/EBU Digital Audio In and Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Balanced Analog Audio In and Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RS-422 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 GPI Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SDI In and Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Optical Fiber In and Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Component/Composite Analog Video In and Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 HDMI In and Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Composite NTSC/PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reference Video (looping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 About Inputs and Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Chapter 3:Installation & Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Installation Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Installation Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Unpacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Shipping Box Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Installing Optional Fiber Optic I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Installing Optional Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Dolby Decoder Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FS2 Chassis Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Physical Requirements for Mounting the Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chassis Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Cabling and Cooling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Network Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291FS2 Installation and Operation Manual — ContentsNetwork Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Networking Using DHCP or Default Static IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Networking the FS2 Using Your Own Static IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Using Ping to Test the Network Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Mac Ping Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Windows PC Ping Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Web Browser Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Software Update Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Download the Latest FS2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Unpack the Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Uploading and Installing the Software to the FS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33System Cabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34System Video/Audio Cable Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34GPI Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34FS2 Audio Level Choices—Pro or Consumer, US or EBU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Chapter 4:Display Menus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Controlling the FS2 via Front Panel Display Menus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Parameter Menus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Menu Group Buttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39SELECT and ADJUST Knobs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Menu Operation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Status Pages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Simple Menus: Config Format Alarm Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Multiple Parameter Menus: Video 1 ProcAmp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Multiple Field Parameters: IP Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43STATUS Menu Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44S.1 I/O Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44S.2 Vid1 Format Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44S.3 Vid1 Format Alarm Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44S.4 Vid2 Format Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45S.5 Vid 2 Format Alarm Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45S.6 Output Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45S.7 Power/Temp Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45S.8 Caption Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46S.9 Dolby Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46S.10 System Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46REMOTE Menu Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 Remote Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471.1 Authentication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.1–4 GPI IN 1–4 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.1–4 GPI 1–4 OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Interaction of Presets and GPIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Example of a Serial Recall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Example of an Unintended Recall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49CONFIG Menu Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 System Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.1 IP Config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.2 IP Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512.3 Subnet Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512.4 Default Gateway. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 MAC Address (view only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.0 SNMP Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.1 SNMP Trap Destination 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.2 SNMP Trap Port 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.3 SNMP Trap Destination 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.4 SNMP Trap Port 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 Power Supply Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546.1 Vid1 Format Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546.2 Vid2 Format Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Reference Alarm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 Hidden Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Display Intensity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5510 Serial Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5611 Software Version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5612 Reboot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 PRESET Menu Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 Recall Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Store Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Interaction of Presets and GPIs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SYSTEM Menu Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 Component In Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 Component Out Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Analog Audio Std . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 SDI1 3G Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 SDI2 Input Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 Fiber1 3G Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Fiber2 Input Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 Genlock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 Frame Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6110 NTSC Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6211 Composite Downconv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6212 HDMI RGB Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6214.0 AES/EBU SRC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6314.1–14.8 AES/EBU SRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6315 Dolby Decoder Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6416 Dolby Decoder Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6417 Dolby Decoder Aux Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6518 Dolby Decoder Aux Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65。
阿尔卡特朗讯程控话机功能代码
功能前缀0 Attendant Call 呼叫话务员9 Professional Trunk Group Seized 中继组出局*10 Set In/Out of service 退出/进入服务*11 Adjust Display Visibility 显示屏调整*12 Lock 话机锁定/解锁*13 Protect. against barge-in & beeps 临时通话保护*14 Substitution 替代*15 Language 语言选择*16 Sta. group exit 退出连选组*17 Sta. group entry 加入连选组*18 Camp-on Control 呼叫等待控制*19 Password modification 修改个人密码*20 Speed call to associated set 快速呼叫关联话机*21 Select Primary Line 选择主线路*22 Select Secondary Line 选择辅线路*23 Message deposit 回叫文本请求*24 Switch off Message LED 关闭留言灯*25 V oice Mail Deposit 点亮留言灯*26 Conversation Recording 通话录音*27 Recordable V oice Guides 动态语音提示录制*28 Remote Extension Activation 激活远程分机*29 Remote Extension Deactivation 取消远程分机*30 Agent processing group call pickup 坐席组代接*31 Secret/Identity 身份保密*32 Manual Hold 手动保持*33 Business account code 业务帐号代码*34 Access to waiting call 查询等待呼叫*35 Park Call/Retrieve 呼叫驻留*36 Night service answering 夜间服务代接*37 Common Hold 通用保持*38 Malicious call 恶意呼叫追踪*39 Direct trunk seizure 直接抓取中继线*40 ACD Prefixes ACD功能*41 Room status management 客房状态管理*42 Mini-bar 迷你酒吧管理*43 Last Caller Callback 回叫最后主叫*44 Meet-me Conference 遇我会议*45 Manual Add-on Conference 手动主控会议*46 Automatic Add-on Conference 自动主控会议*47 Announcement 广播*48 Explicit Precedence level 优先级别*49 Background Music 背景音乐*50 Remote forward 远端转移(跟我转移)*51 Overfl.busy to assoc.set 忙线时溢出至关联话机*52 Overfl.on no answer to associate 无应答时溢出至关联话机*53 Overf.busy/no answer to assoc.set 忙线或无应答时溢出至关联话机*54 Cancel Overfl.to associate 取消溢出至关联话机*55 Cancel auto. callback on busy 取消自动回叫*56 Personal directory Programming 个人通讯录编辑*57 Personal Directory Use 使用个人通讯录*58 Ubiquity Mobile Programming 一号通移动号码编辑*59 Ubiquity 一号通*60 Immediate forward 无条件立即转移*61 Immediate forward on busy 遇忙立即转移*62 Forward on no answer 无应答延时转移*63 Forward on busy or no answer 遇忙或无应答延时转移*64 Forward cancellation 取消转移*65 Cancel Remote forward 远程取消转移*66 Forward cancel.by destinat. 由目的地取消转移*67 Access Callback list 访问回叫列表*68 Suite Do Not Disturb 套房请勿打扰*69 Associated Direct. No. modif. 修改关联话机号码*70 Redial last number 重拨最后号码*71 Direct call pickup 直接代接*72 Group call pickup 组代接*73 Suite Wake-up 套房叫醒*74 Suite Wake-up Cancel 取消套房叫醒*75 Cancel Wake-up 取消叫醒*76 Wake-up/appointment reminder 约会提醒/叫醒服务*77 V oice Mail Access 查询语音消息*78 Do not disturb 请勿打扰*79 Tone test 音频检测# DTMF end-to-end dialing DTMF双音频透明发送功能后缀1 Broker Call 代理呼叫2 Consultation Call 查询呼叫3 Three-Party Conference 三方会议4 Barge-in 强插5 Callback On Free Or Busy Set 遇忙或无应答自动回叫6 Busy Camp-on 遇忙呼叫等待7 Call Announcement 呼叫通知8 V oice Mail Deposit 语音消息留言* DTMF end-to-end dialing DTMF双音频透明发送#71 Business number 业务帐号代码。
Anritsu Series 560-7XXX 和 5400-71XXX RF 检测器操作与维护手册
SERIES 560-7XXX AND 5400-71XXX RF DETECTORSOPERATION AND MAINTENANCE MANUAL1.INTRODUCTIONThis manual provides descriptions and specifica-tions for ANRITSU Series 560-7XXX and 5400-71XXX RF Detectors (Figure 1).It also con-tains procedures for field replacement of detector di-odes in the model 5400-71B50and 5400-71B75RF detectors and most of the Series 560-7XXX RF detec-tors.2.GENERAL DESCRIPTIONThe ANRITSU Series 560-7XXX and 5400-71XXX RF Detectors use zero-biased Schottky diodes and have a measurement range of –55dBm to +16dBm.The detectors are used with the Model 56100A and 562Scalar Network Analyzers and with Series 541XXA,540XXA,and 54XXA Scalar Measurement Systems for making coaxial transmission loss or gain and power measurements.The detectors are also used with the Site Master and Cable Mate Se-ries Personal SWR/RL and Fault Location Testers for making power measurements.3.PERFORMANCE SPECIFICATIONSPerformance specifications for the Series 560-7XXX and 5400-71XXX RF Detectors are listed in Table 1on page 2.4.PRECAUTIONS FOR USE OF RF DETECTORSANRITSU RF Detectors are high-quality,precision laboratory instruments and should receive the same care and respect afforded such instruments.Follow the precautions listed below when handling or con-necting these plying with these precau-tions will guarantee longer component life and less equipment downtime due to connector or device fail-ure.Also,such compliance will ensure that RF De-tector failures are not due to misuse or abuse—two failure modes not covered under the ANRITSU war-ranty.a.Beware of Destructive Pin Depth of MatingConnectors.Based on RF components re-turned for repair,destructive pin depth of mat-ing connectors is the major cause of failure in the field.When an RF component connector is mated with a connector having a destructive pin depth,damage will usually occur to the RF com-ponent connector.A destructive pin depth is one that is too long in respect ot the reference plane of the connector (Figure 2,page 3).The center pin of a precision RF component con-nector has a precision tolerance measured in mils (1/1000inch).The mating connectors of various RF components may not be precision types.Consequently,the center pins of these de-vices may not have the proper depth.The pin depth of DUT connectors should be measured to assure compatibility before attempting to mate them with RF Detector connectors.An ANRITSU Pin Depth Gauge (Figure 3,page 3),or equivalent,can be used for this purpose.P/N:10100-00035REVISION :CPRINTED:MARCH 2000COPYRIGHT 1997ANRITSU CO.490JARVIS DRIVE l MORGAN HILL,CA 95037-2809Figure 1.Typical Series 560-7XXX and 5400-71XXX RF DetectorsNOTE:ANRITSU Company was formerly known as WILTRON Company.NOTE:ANRITSU was for-merly known as WILTRON1981Model Frequency Range Impedance Return Loss Input Connector Frequency Response560-7A500.01to18GHz50Ω15dB,<0.04GHz22dB,<8GHz17dB,<18GHzGPC-7±0.5dB,18GHz560-7N50B0.01to20GHz50Ω15dB,<0.04GHz22dB,<8GHz17dB,<18GHz14dB,<20GHzN(m)±0.5dB,<18GHz±1.25dB,<20GHz560-7S50B0.01to20GHz50Ω15dB,<0.04GHz22dB,<8GHz17dB,<18GHz14dB,<20GHzWSMA(m)±0.5dB,<18GHz±1.25dB,<20GHz560-7S50-20.01to26.5GHz50Ω15dB,<0.04GHz22dB,<8GHz17dB,<18GHz14dB,<26.5GHzWSMA(m)±0.5dB,<18GHz±1.25dB,<26.5GHz560-7K500.01to40GHz50Ω12dB,<0.04GHz22dB,<8GHz17dB,<18GHz15dB,<26.5GHz14dB,<32GHz13dB,<40GHzK(m)±0.5dB,<18GHz±1.25dB,<26.5GHz±2.2dB,<32GHz±2.5dB,<40GHz560-7VA500.01to50GHz50Ω12dB,<0.04GHz19dB,<20GHz15dB,<40GHz10dB,<50GHzV(m)±0.8dB,<20GHz±2.5dB,<40GHz±3.0dB,<50GHz5400-71B500.001to1.5GHz50Ω20dB BNC(m)±0.2dB,<1.5GHz 5400-71B750.001to1.5GHz75Ω20dB BNC(m)±0.2dB,<1.5GHz5400-7N500.001to3GHz50Ω26dB N(m)±0.2dB,<1GHz ±0.3dB,<3GHz5400-71N750.001to3GHz75Ω26dB,<2GHz20dB,<3GHz N(m)±0.2dB,<1GHz±0.3dB,<3GHz5400-71N75L*0.005to1.2GHz75Ω24dB N(m)±0.2dB,<1GHz ±0.5dB,<1.2GHzAll Models:Maximum Input Power:100mW(+20dBm)Cable Length:122cm(4ft)Dimensions:7.6x2.9x2.2cm(3x1-1/8x7/8in.)Weight:170g(6oz)*The input of the5400-71N75L is limited to extend the damage level to1W(+30dBm)The limit begins compression at10dBm<0.05GHz,15dBm<1GHz,or20dBm<1.2GHzTable1.560-7XXX and5400-71XXX RF Detectors Performance Specifications2DET OMMIf the measured connector is out of tolerance in the “+”region,the center pin is too long (see Ta-ble 2).Mating under this condition will likely damage the precision RF Detector connector.If the test device connector measures out of toler-ance in the “–”region,the center pin is too short.This will not cause damage,but it will result in a poor connection and a consequent degradation in performance.b.Avoid Over Torquing Connectors.O v e rtorquing connectors is destructive;it may dam-age the connector center pin.Finger-tight is usu-ally sufficient for Type N connectors.Always use a connector torque wrench (8inch-pounds)when tightening GPC-7,WSMA,K,or V type connec-tors.Never use pliers to tighten connectors .c.Avoid Mechanical Shock.RF Detectors aredesigned to withstand years of normal benchhandling.However,do not drop or otherwise treat them roughly.Mechanical shock will sig-nificantly reduce their service life.d.Avoid Applying Excessive Power .The Se-ries 560-7XXX and 5400-71XXX RF Detectors are rated at +20dBm (100mW)maximum input power.Exceeding this input power level,even for short durations,will permanently damage their internal components.e.Do Not Disturb Teflon Tuning Washers onConnector Center Pins.The center conduc-tor of many RF component connectors contains a small teflon tuning washer that is located near the point of mating (Figure 4,page 4).This washer compensates for minor impedance dis-continuities at the interface.Do not disturb this washer .The location of this washer is critcal to the performance of the RF component.f.Keep Connectors Clean.The precise geome-try that makes possible the RF component’s high performance can be easily disturbed by dirt or other contamination adhering to connector in-terfaces.When not in use,keep the connectors covered.To clean the connector interfaces,use a clean cotton swab that has been dampened with dena-tured alcohol.Figure 5,page 4illustrates the cleaning of male and female connectors.DET OMM 3DUT Connector Type ANRITSU Gauging Set Model Pin Depth (inches)Pin Depth Gauge Reading N-Male N-Female 01-163.207–0.000+0.030207+0.000–0.030GPC-701-161+0.000–0.030Same as Pin Depth WSMA-Male WSMA-Female 01-162–0.000–0.010Same as Pin Depth SMA-Male,SMA-Female 01-162–0.000–0.010Same as Pin Depth 3.5mm-Male 3.5mm-Female 01-162–0.000–0.010Same as Pin Depth K-Male,K-Female01-162+0.000–0.010Same as Pin DepthTable 2.Allowable Device Under Test (DUT)Connector PinDepth Figure 2.N Connector Pin Depth DefinitionFigure 3.Pin Depth GaugeNOTEMost cotton swabs are too large to fit in the smaller connector types.In these cases it is necessary to peel off most of the cotton and then twist the remaining cotton tight.Be sure that the remaining cotton does not get stuck in the connector.Cotton swabs of the appropriate size can be pur-chased through a medi-cal-laboratory-type supply center.The following are some important tips on clean-ing connectors:•Use only denatured alcohol as a cleaning sol-vent.•Do not use excessive amounts of alcohol as prolonged drying of the connector may be re-quired.•Never put lateral pressure on the center pin of the connector.•If installed,do not disturb the teflon washer on the center conductor pin.•Verify that no cotton or other foreign mate-rial remains in the connector after cleaning it.•If available,use compressed air to remove foreign particles and to dry the connector.•After cleaning,verify that the center pin has not been bent or damaged.5.DETECTOR DIODE REPLACEMENTRF Detector models 5400-71B50and 5400-71B75are equipped with field-replaceable detector diodes;the series 560-7XXX RF Detectors,except for model 560-7VA50,are equipped with field-replaceable de-tector diode modules.Paragraph 5.1provides a pro-cedure for replacing defective diodes in the models 5400-71B50and 5400-71B75;paragraph 5.2pro-vides a procedure for replacing detector diode mod-ules in series 560-7XXX RF Detectors.4DET OMMTEFLON WASHERNOTEThe teflon washer is shown on a GPC-7connector. A similar washer may be installed on any ANRITSU precision connector.Figure 4.Tuning Washer on GPC-7ConnectorFigure 5.Cleaning Male and Female ConnectorsTable 3provides the diode/diode module part num-ber for each RF detector model containing a field-replaceable detector diode or diode module.NOTERF Detector Models 5400-71N50,5400-71N75,and 560-7VA50do not have field-replaceable detector diodes.Contact your local ANRITSU Service Center for assistance.a.Required Adjustments Whenever the detec-tor diode (or diode module)of the RF detector is replaced,the two potentiometers that are part of the RF detector PCB subassembly (Figures 6(below)and 9(page 6))must be readjusted.The potentiometer readjustment is done after the de-fective diode is removed,but before the replace-ment diode is installed.b.Test Equipment Required The detector di-ode replacement procedures require a digital multimeter (DMM)that has a display resolution of at least 3-1/2digits (John Fluke Model 8840A,or equivalent).5.1.Detector Diode Replacement for the Model 5400-71B50and 5400-71B75RF DetectorsThe model 5400-71B50and 5400-71B75RF Detec-tors are equipped with a field-replaceable detector diode.To replace,proceed as follows:1.Unfasten the four detector housing top cover retaining screws.Remove the top cover.2.Unplug the defective diode (Figure 6)from the PCB subassembly and remove.3.Set the potentiometer R1full clockwise (max-imum resistance).4.Connect the DMM leads between pins 1and 2of the RF detector cable connector (Figure 7).Measure the resistance value,which is the maximum resistance of R1(approximately 40.5K Ωis typical).Record this value;it will hereafter be referred to as “R T ”.5.Obtain the “K”value from the replacement di-ode container level (Figure 8,page 6).pute the set value for R1as follows:R K R set T1=×7.Adjust R1counterclockwise until the DMM indicates the R1set value calculated in step 6.8.Connect the DMM leads between pin 3of the RF detector cable connector and the cable shield.9.Obtain the “R O ”value from the replacement diode container label (Figure 8,page 6).DET OMM 5Figure 6.Model 5400-71B50and 5400-71B75RF Detectors Housing Layout DiagramFigure 7.RF Detector Cable Connector Pin LayoutRF Detector ModelDiode or Diode Module Part Number5400-71B5010-215400-71B7510-885400-71N50Factory Replacement Only 5400-71N75Factory Replacement Only560-7A50A7219A 560-7N50B C24441560-7S50B C24441560-7S50-2A7219B 560-7K50ND19393560-7VA50Factory Replacement OnlyTable 3.560-7XXX and 5400-71XXX RF Detector Diode/Diode Module Part Numbers10.Adjust R4until the DMM indicates the “R O ”value.Disconnect the DMM.11.Orient the cathode end (white dot)of the re-placement diode as shown in Figure 6(white dot towards centerline of the detector PCB subassembly).Insert the diode into the socket of the PCB subassembly.12.Reinstall the top cover,securing it with thefour retaining screws.This completes replace-ment of the detector diode.5.2.Detector Diode Module Replacement for the Series 560-7XXX RF DetectorsSeries 560-7XXX RF Detectors,except for model 560-7VA50,are equipped with a field-replaceable di-ode module that contains (in addition to the detector diode)a thermistor,a resistor,and two capacitors.To replace,proceed as follows:1.Unfasten the four detector housing top cover retaining screws.Remove the top cover.2.Unfasten the two retaining screws that hold down the RF detector PCB subassembly (Fig-ure 9).6DET OMMFigure 8.Replacement Diode Container LabelFigure 9.Series 560-7XXX RF Detectors,Exploded View3.Slide the cable retainer out of the RF detector housing assembly.When the cable retainer clears the housing,disconnect the PCB subas-sembly from the diode module.Remove the spring washer.4.Remove the fiberglass module retainer from the detector housing.This retainer can be re-moved by prying it out using a small screw-driver,or by pulling it out using short,round nose pliers.5.Remove the diode module from the rear of the connector body by pulling it straight out.6.Connect the DMM leads between pins 1and 2of the RF detector cable connector (Figure 10).Measure the resistance value,which is the maximum resistance of R1(approximately 40.5K Ωis typical).Record this value;it will hereafter be referred to as “R T ”.7.Obtain the “K”value from the replacement di-ode container label (Figure 11).pute the set value for R1as follows:R K R set T1=×9.Adjust R1counerclockwise until the DMM in-dicates the R1set value calculated in step 8.10.Connect the DMM leads between pin 3of theRF detector cable connector and the cable shield.11.Obtain the “R 0”value from the replacementdiode container label and adjust R4until the DMM indicates this value.Disconnect the DMM.12.Orient the detector housing normally (Figure9,page 6).Insert the replacement diode mod-ule into the rear of the connector body so that the center lead is on top .13.Orient the spring washer so that the twocurved flanges point toward the rear of the detector housing and are positioned horizon-tally (i.e.,3o’clock and 9o’clock positions).14.Insert fiberglass module retainer between thereplacement diode module and the spring washer.push down on the retainer until fully seated.15.Orient the PCB subassembly normally asshown in Figure 9and insert it into the detec-tor housing so that the leads from the replace-ment diode module mate with the connectors on the PCB subassembly.16.Insert the cable retainer into the slot in thedetector housing.17.Fasten the PCB subassembly into the detec-tor housing using two retaining screws.18.Reinstall the top cover,securing it with fourretaining screws.This completes replacement of the detector diode module.6.ANRITSU Service CentersTable 4,page 8,provides names and addresses of ANRITSU Service Centers.DET OMM 7Figure 10.RF Detector CableConnector Pin LayoutFigure 11.Replacement Diode Module Container LabelUNITED STATESANRITSU COMPANY685Jarvis DriveMorgan Hill,CA95037-2809 Telephone:(408)776-8300FAX:408-776-1744COMPANY10Kingsbridge RoadFairfield,NJ07004Telephone:(201)227-8999FAX:201-575-0092AUSTRALIAANRITSU PTY.LTD.Unit3,170Foster RoadMt Waverley,VIC3149AustraliaTelephone:03-9558-8177Fax:03-9558-8255BRAZILANRITSU ELECTRONICA LTDA.Praia de Botafogo,440,Sala2401CEP22250-040,Rio de Janeiro,RJ,Brasil Telephone:021-28-69-141Fax:021-53-71-456CANADAANRITSU INSTRUMENTS LTD.215Stafford Road,Unit102Nepean,Ontario K2H9C1 Telephone:(613)828-4090FAX:(613)828-5400CHINABEIJING SERVICECENTERBeijing Fortune Building416W,5Dong San Huan Bei Lu Chaoyang quBeijing100004,ChinaTelephone:011861065909237FAX:011861065909236FRANCEANRITSU S.A9Avenue du QuebecZone de Courtaboeuf91951Les Ulis CedexTelephone:016-44-66-546FAX:016-44-61-065GERMANYANRITSU GmbHGrafenberger Allee54-56D-40237DusseldorfGermanyTelephone:0211-968550FAX:0211-9685555INDIAMEERA AGENCIES(P)LTD.A-23Hauz KhasNew Delhi110016Telephone:011-685-3959FAX:011-686-6720ISRAELTECH-CENT,LTDHaarad St.No.7,Ramat HaahayalTel-Aviv69701Telephone:(03)64-78-563FAX:(03)64-78-334ITALYANRITSU Sp.ARoma OfficeVia E.Vittorini,12900144Roma EURTelephone:(06)50-22-666FAX:(06)50-22-4252JAPANANRITSU CORPORATION1800Onna Atsugi-shiKanagawa-Prf.243JapanTelephone:0462-23-1111FAX:0462-25-8379KOREAANRITSU KOREA(AWK)#901Daeo Bldg.26-5Yeoido Dong,YoungdeungpoSeoul Korea150010Telephone:02-782-7156FAX:02-782-4590SINGAPOREANRITSU(SINGAPORE)PTE LTD3Shenton Way#24-03Shenton HouseSingapore0106Telephone:2265206FAX:2265207SOUTH AFRICAETESCSA1st Floor Montrose PlaceWaterfall ParkBecker RoadMIDRANDSOUTH AFRICATelephone:011-315-1366Fax:011-315-2175SWEDENANRITSU ABBotvid CenterS-14584Stockholm,SwedenTelephone:(08)534-717-00FAX:(08)534-717-30TAIWANCO.,LTD.8F,No.96,Section3Chien Kuo N.RoadTaipei,Taiwan,R.O.C.Telephone:(02)515-6050FAX:(02)509-5519UNITED KINGDOMANRITSU LTD.200Capability GreenLuton,BedfordshireLU13LU,EnglandTelephone:015-82-41-88-53FAX:015-82-31-303Table4.ANRITSU Service Centers8DET OMMNOTESDET OMM9NOTES10DET OMMWARRANTYThe ANRITSU product(s)listed on the title page is(are)warranted against defects in ma-terials and workmanship for one year from the date of shipment.ANRITSU’s obligation covers repairing or replacing products which prove to be defective during the warranty period.Buyers shall prepay transportation charges for equipment returned to ANRITSU for warranty repairs.Obligation is limited to the original pur-chaser.ANRITSU is not liable for consequential damages.LIMITATION OF WARRANTYThe foregoing warranty does not apply to ANRITSU connectors that have failed due to normal wear.Also,the warranty does not apply to defects resulting from improper or in-adequate maintenance by the Buyer,unauthorized modification or misuse,or operation outside of the environmental specifications of the product.No other warranty is ex-pressed or implied,and the remedies provided herein are the Buyer’s sole and exclusive remedies.TRADEMARK ACKNOWLEDGEMENTSV Connector and K Connector are registered trademarks of ANRITSU Company.NOTICEANRITSU Company has prepared this manual for use by ANRITSU Company personnel and customers as a guide for the proper installation,operation and maintenance of ANRITSU Company equipment and computer programs.The drawings,specifications, and information contained herein are the property of ANRITSU Company,and any unautho-rized use or disclosure of these drawings,specifications,and information is prohibited;theyshall not be reproduced,copied,or used in whole or in part as the basis for manufacture or sale of the equipment or software programs without the prior written consent of ANRITSU Company.。
Lenovo ThinkSystem PM1643a 12Gb SAS SSD产品指南说明书
ThinkSystem PM1643a Entry 12Gb SAS SSDsProduct GuideThe ThinkSystem PM1643a Entry SAS 12Gb solid-state drives (SSDs) are next-generation SSDs suitable for a wide range of applications. The PM1643a SAS SSDs are designed for dense storage and with a 12 Gb SAS interface, these drives feature all the capacity and performance that is needed to replace large numbers of 15K rpm and 10K rpm spinning disks, and consolidate storage into tightly packed server configurations.The PM1643a SSDs are the follow-on to the PM1643 SSDs and offer improved random write performance.Figure 1. ThinkSystem PM1643a 12Gb SAS SSDsDid you know?Unlike SATA drives, the 12 Gb/s SAS interface on PM1643a drives supports full duplex data transfer for higher performance, as well as enterprise-level error recovery for better availability.Rigorous testing of PM1643a Entry SATA SSDs by Lenovo through the ServerProven program assures a high degree of storage subsystem compatibility and reliability. Providing additional peace of mind, these drives are covered under Lenovo warranty.Click here to check for updatesTechnical specificationsThe following tables present technical specifications for the PM1643a Entry SSDs.Table 2. Technical specificationsFeature 960 GB drive 1.92 TB drive 3.84 TB drive 7.68 TB drive 15.36 TB drive Interface 12 Gbps SAS 12 Gbps SAS 12 Gbps SAS 12 Gbps SAS 12 Gbps SAS Capacity 960 GB 1.92 TB 3.84 TB 7.68 TB 15.36 TB SED encryption None None None None None Endurance(drive writes per day for 5 years) 1 DWPD1 DWPD1 DWPD1 DWPD1 DWPDEndurance(total bytes written)1,752 TB 3,504 TB 7,008 TB 14,016 TB 28,032 TB Data reliability (UBER)< 1 in 10 bits read < 1 in 10 bits read < 1 in 10 bits read < 1 in 10 bits read < 1 in 10 bits read MTBF2,000,000 hours 2,000,000 hours 2,000,000 hours 2,000,000 hours 2,000,000 hoursIOPS reads (4 KB blocks)230,000230,000230,000230,000230,000IOPS writes (4 KB blocks)40,00060,00085,00090,00065,000Sequential read rate (128 KB blocks)1,000 MBps 1,000 MBps 1,000 MBps 1,000 MBps 1,000 MBps Sequential write rate (128 KB blocks)1,000 MBps 1,000 MBps 1,000 MBps 1,000 MBps 1,000 MBps Read latency (sequential)240 µs 240 µs 240 µs 240 µs 240 µs Write latency (sequential)220 µs 220 µs 220 µs 220 µs 220 µs Read latency (random)120 µs 120 µs 120 µs 130 µs 130 µs Write latency (random)45 µs 45 µs 45 µs 45 µs 45 µs Shock, non-operating 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms 1,500 G (Max)at 0.5 ms Vibration, non-operating20 G (10-2000 Hz)20 G (10-2000 Hz)20 G (10-2000 Hz)20 G (10-2000 Hz)20 G (10-2000 Hz)Typical power (R / W)9 W / 12 W9 W / 12 W9 W / 12 W9 W / 12 W9 W / 12 W1717171717RMS RMS RMS RMS RMSServer supportThe following tables list the ThinkSystem servers that are compatible. Table 3. Server support (Part 1 of 3)PartNumber Description Edge1S IntelV2AMD V3Intel V32.5-inch hot-swap drives4XB7A17055ThinkSystem 2.5" PM1643a7.68TB Entry SAS 12Gb Hot SwapSSDN N N N N N N N N N N N N N N N N N N4XB7A17056ThinkSystem 2.5" PM1643a15.36TB Entry SAS 12Gb HotSwap SSDN N N N N N N N N N N N N N N N N N N 3.5-inch hot-swap drives4XB7A17059ThinkSystem 3.5" PM1643a7.68TB Entry SAS 12Gb Hot SwapSSD N N N N N N N N N N N N N N N N N N N SE35(7Z46/7D1X)SE35V2(7DA9)SE36V2(7DAM)SE45(7D8T)SE455V3(7DBY)ST5V2(7D8K/7D8J)ST25V2(7D8G/7D8F)SR25V2(7D7R/7D7Q)SR635V3(7D9H/7D9G)SR655V3(7D9F/7D9E)SR645V3(7D9D/7D9C)SR665V3(7D9B/7D9A)SR675V3(7D9Q/7D9R)ST65V3(7D7B/7D7A)SR63V3(7D72/7D73)SR65V3(7D75/7D76)SR85V3(7D97/7D96)SR86V3(7D94/7D93)SR95V3(7DC5/7DC4)Table 4. Server support (Part 2 of 3)Part NumberDescriptionDense V32S Intel V2AMD V1Dense V24S V28S2.5-inch hot-swap drives4XB7A17055ThinkSystem 2.5" PM1643a7.68TB Entry SAS 12Gb Hot Swap SSD N N N N Y Y Y Y Y Y N Y Y N N N N Y YY4XB7A17056ThinkSystem 2.5" PM1643a15.36TB Entry SAS 12Gb Hot Swap SSD N N N N Y Y Y Y N N N Y Y N N N N Y YY3.5-inch hot-swap drives4XB7A17059ThinkSystem 3.5" PM1643a7.68TB Entry SAS 12Gb Hot Swap SSDN N N N Y Y Y N Y Y N Y Y N N N N N NNTable 5. Server support (Part 3 of 3)Part NumberDescription4S V11S Intel V12S Intel V1Dense V12.5-inch hot-swap drives4XB7A17055ThinkSystem 2.5" PM1643a7.68TB Entry SAS 12Gb Hot Swap SSD Y Y N N N N N Y Y Y N N Y Y N N N Y Y4XB7A17056ThinkSystem 2.5" PM1643a15.36TB Entry SAS 12Gb Hot Swap SSD Y N Y N N N N N Y N Y Y Y Y N N N Y Y3.5-inch hot-swap drives4XB7A17059ThinkSystem 3.5" PM1643a7.68TB Entry SAS 12Gb Hot Swap SSDN N N N N N N Y Y Y N N Y Y N N N N N Operating system supportS D 665 V 3 (7D 9P )S D 665-N V 3 (7D A Z )S D 650 V 3 (7D 7M )S D 650-I V 3 (7D 7L )S T 650 V 2 (7Z 75 / 7Z 74)S R 630 V 2 (7Z 70 / 7Z 71)S R 650 V 2 (7Z 72 / 7Z 73)S R 670 V 2 (7Z 22 / 7Z 23)S R 635 (7Y 98 / 7Y 99)S R 655 (7Y 00 / 7Z 01)S R 655 C l i e n t O S S R 645 (7D 2Y / 7D 2X )S R 665 (7D 2W / 7D 2V )S D 630 V 2 (7D 1K )S D 650 V 2 (7D 1M )S D 650-N V 2 (7D 1N )S N 550 V 2 (7Z 69)S R 850 V 2 (7D 31 / 7D 32)S R 860 V 2 (7Z 59 / 7Z 60)S R 950 (7X 11 / 7X 12)S R 850 (7X 18 / 7X 19)S R 850P (7D 2F / 2D 2G )S R 860 (7X 69 / 7X 70)S T 50 (7Y 48 / 7Y 50)S T 250 (7Y 45 / 7Y 46)S R 150 (7Y 54)S R 250 (7Y 52 / 7Y 51)S T 550 (7X 09 / 7X 10)S R 530 (7X 07 / 7X 08)S R 550 (7X 03 / 7X 04)S R 570 (7Y 02 / 7Y 03)S R 590 (7X 98 / 7X 99)S R 630 (7X 01 / 7X 02)S R 650 (7X 05 / 7X 06)S R 670 (7Y 36 / 7Y 37)S D 530 (7X 21)S D 650 (7X 58)S N 550 (7X 16)S N 850 (7X 15)TrademarksLenovo and the Lenovo logo are trademarks or registered trademarks of Lenovo in the United States, other countries, or both. A current list of Lenovo trademarks is available on the Web athttps:///us/en/legal/copytrade/.The following terms are trademarks of Lenovo in the United States, other countries, or both:Lenovo®ServerProven®ThinkSystem®The following terms are trademarks of other companies:Intel® is a trademark of Intel Corporation or its subsidiaries.Other company, product, or service names may be trademarks or service marks of others.。
阿特美 AT97SC3204 信任平台模块数据手册摘要说明书
This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. Features●Fully compliant to the Trusted Computing Group (TCG) Trusted Platform Module(TPM) version 1.2 specification●Compliant with TCG PC client-specific TPM Interface Specification (TIS) version 1.2●Single-chip, turnkey solution●Hardware asymmetric crypto engine●Atmel® AVR® RISC microprocessor●Internal EEPROM storage for RSA keys●33MHz Low Pin Count (LPC) bus for easy PC interface●Secure hardware and firmware design and chip layout●Internal, high-quality Random Number Generator (RNG) – FIPS 140-2 compliant●NV storage space for 1756 bytes of user defined data● 3.3V supply voltage●28-lead thin TSSOP, 28-lead wide TSSOP, or 40-pad QFN packages●Offered in both commercial (0 to 70°C) and industrial (-40 to +85°C)temperature rangesDescriptionThe Atmel AT97SC3204 is a fully integrated security module designed to be integrated into personal computers and other embedded systems. It implements version 1.2 of the Trusted Computing Group (TCG) specification for Trusted Platform Modules (TPM).The TPM includes a cryptographic accelerator capable of computing a 2048-bit RSA signature in 200ms and a 1024-bit RSA signature in 40ms. Performance of the SHA-1 accelerator is 20μs per 64-byte block.The chip communicates with the PC through the LPC interface. The TPM supports SIRQ (for interrupts) and CLKRUN to permit clock stopping for power savings in mobile computers.Atmel AT97SC3204Trusted Platform Module LPC InterfaceSUMMARY DATASHEET1.Pin Configurations and PinoutsTable 1-1.Pin ConfigurationsTable 1-2.Pinouts2.Block DiagramThe TPM includes a hardware random number generator, including a FIPS-approved Pseudo Random NumberGenerator that is used for key generation and TCG protocol functions. The RNG is also available to the system togenerate random numbers that may be needed during normal operation.The chip uses a dynamic internal memory management scheme to store multiple RSA keys. Other than the standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2), no system intervention is required to manage this internal key cache.The TPM is offered to OEM and ODM manufacturers as a turnkey solution, including the firmware integrated on the chip.In addition, Atmel provides the necessary device driver software for integration into certain operating systems, along with BIOS drivers. Atmel will also provide manufacturing support software for use by OEMs and ODMs during initialization and verification of the TPM during board assembly.Full documentation for TCG primitives can be found in the TCG TPM Main Specification, Parts 1 to 3, on the TCG Web site located at https://. TPM features specific to PC Client platforms are specified in the “TCG PC Client Specific TPM Interface Specification, Version 1.2”, also available on the TCG web site. Implementation guidance for 32-bit PC platforms is outlined in the “TCG PC Client Specific Implementation Specification for Conventional BIOS for TCG Version 1.2”, also available on the TCG website.3.Ordering InformationNote: 1.Please see the AT97SC3204 datasheet addendum for the complete catalog number ordering code.4.Package Drawings4.128X1 — 28-lead Thin TSSOP4.240ML1 — 40-pad VQFN5.Revision HistoryAtmel Corporation1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311F: (+1)(408) 436.4200| © 2013 Atmel Corporation. All rights reserved. / Rev.: Atmel-5295ES-TPM-AT97SC3204-LPC-Interface-Datasheet-Summary-032013Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted。
诺基亚智能手机使用指南说明书
C
Capacities Chart .................... 344, 346 Carbon Monoxide Hazard .............. 52 Carrying Cargo .............................. 202 Cassette Player
Charging System Indicator .... 58, 328 Checklist, Before Driving............. 206 Child Safety ...................................... 20 Child Seats........................................ 25
Before Driving ............................... 191 Belts, Seat ..................................... 8, 41 Beverage Holder............................ 101 Body Repair .................................... 310
Maintenance............................... 279 Usage .................................. 111, 117 Air Outlets (Vents)................ 110, 115 Air Pressure, Tires ........................ 282 Alcohol in Gasoline........................ 350 Aluminum Wheels, Cleaning........ 305 Antifreeze ....................................... 253 Anti-lock Brakes (ABS) Indicator................................ 59, 219 Operation .................................... 218 Anti-theft, Audio System............... 179 Anti-theft Steering Column Lock .. 76
S1240用户管理
一、用户基本操作的人机命令1、显示单个用户DISPLAY-SUBSCR/4296该命令用于显示用户的特性和相关数据。
用户的主要数据包括DN棗电话号码,EN棗设备码(由ASM或ISM的NA与TN号组成),用户组(SUBGRP),用户信令(拨号信令)类型(SUBSIG),用户的三张汇总计费表(市话、农话、特服),主叫类别等信息。
2、删除用户REMOVE-SUBSCR/4295删除用户时,可用参数INTCP来采用不同的方法保留被删除用户的信息(如采用录音通知)。
如用户处于通话状态则用FSEIZE参数强拆。
3、创建模拟用户CREATE-ANALOG-SUBSCR/4291该命令用于创建一个新的模拟用户。
4、修改用户数据MODI FY-SUBSCR/4294(1)呼叫观察(OBSERV)呼叫观察分为主叫观察,被叫观察和恶意呼叫观察三种类型,每种类型又可做普通观察或直接呼叫观察。
普通呼叫观察在系统处于过载或话务量很高的状态时,系统不出观察报告,而直接观察报告不管系统当前状态,呼叫结束后便打印呼叫观察报告(RRN=121报告参考号为121)。
做法:MODIFY-SUBSCR:DN=K'5800012,OBSERV=ADD&ORGOBS&DIRRED;(2)呼出阻塞(OCB)定义是否允许用户呼出及用户呼出的权限(如国内长途有权…)。
利用人机命令:DISPLAY-BARRING-PROGRAM/4386可显示系统中权限控制表,从表中可看出OCB与字冠分析所得到的目的码RSTLEV的关系。
系统即根据此表来确定一个用户(OCB)在拨打某一字冠(RSTCEV)时是否阻塞。
如给用户设国内长途有权则命令为:4294:DN=K'5800 022,OCB=ADD&PERM&NAT;注:如显示用户的报告中无OCB的值则该用户具有所有的呼出权限。
(3)投币电话(COINBOX)4294:DN=K'5800022,PAYPHONE=PUBLIC&KH216;做成投币电话后用户只能作主叫,不能作被叫。
阿里斯支持工具CD版说明书
Aries Support Tool CDFeaturing...Aries Support Tool, version 3.2.0For use with Aries Drives(C) Copyright 1998-2011. Parker Hannifin Corporation. All Rights Reserved.Contents•Safety Warning•Aries Support Tool CD-ROM Revision History•System Requirements•Operating System Compatibility•Getting Started with Aries Support Tool•Technical Support==================================================================== Safety WarningThe Aries Support Tool is a software configuration tool for setting up your Aries drive system. Therefore, you should test your system for safety under all potential conditions. Failure to do socan result in damage to equipment and/or serious injury to personnel.====================================================================Aries Support Tool CD-ROM Revision HistoryRevision 3.2.0 (Apr 11, 2011)•Removed skin for better Windows compatibility•Updated AriesMotorDatabase.xml, version 82, to include support for the SMEand SMEA family of rotary servo motors and the 7D feedback for the MPPfamily of servo motors•Support for Hall-less commutation•Added message box if errors occurred during configuration upload•Added message box if errors occurred during loading configuration file•Bug Fix – Configurations for Servo Gains and Misc. Tuning are saved properly•Bug Fix – removed extraneous text from configuration file•Bug Fix – Bit Status Panel updates S33.0 and S44.1 correctly•Bug Fix – Uploading Other Motor correctly displays motor name•Bug Fix – Fixed crash when drive is Returned to Factory Settings whiledisconnected•Bug Fix – Bit Status Panel updates S33.0 and S44.1 correctly•Bug Fix – Version information in configuration file corrected________________1Revision 3.1.1•Bug Fix – K Series motors are now configured properly•Bug Fix – For Position mode, SMPER is now set to equal ERES•Bug Fix – For Position mode, DRES is now set to equal ERES•Updated Aries User Guide•Updated Aries 01-13 Encoder Drive Quick Reference Guide•Updated Aries 01-13 Resolver Drive Quick Reference Guide•Updated Aries 20-30 Encoder Drive Quick Reference Guide________________Revision 3.1.0•Added a Terminal Tool for direct communication to the Aries Drive in it’s native command language•Updated AriesMotorDatabase.xml, version 60, to include support for the Trilogy family of linear servo motors and the K family of frameless kit servomotors.•Bug Fix - ESAVE is no longer sent to motors with Smart Encoders.•Added support for Invert Hall signals in the Configuration Wizard. Relates to SHALL command.•Added support for servo motors with resolver feedback.________________Revision 3.0.2•Added support for Heidenhain single-turn and multi-turn absolute encoders (on MPPxxxxx9D and MPPxxxxx6D motors) in Aries Support Tool, version3.0.2.1.•Updated AriesMotorDatabase.xml, version 51, to correct data for various MPP motors.________________Revision 3.0.1•Consolidated Aries User Guide documentation into one PDF,AriesDriveUserGuide.pdf (rev C).•Added feature to remember last configuration file opened by the Aries Support Tool, version 3.0.1.0.•Fixed a few minor bugs in Aries Support Tool, version 3.0.1.0.________________Revision 3.0.0•Added many new features to Aries Support Tool, version 3.0.0.0.•Added support for MPP series motors in Configuration Wizard.•Added step in Configuration Wizard to allow configuration of the Aries drive fault output, in-position output, and motor thermal sensor input.•Added support for automatic current loop calculations in Servo Tuner.•Added graphical support for current loop tuning in Servo Tuner.•Added graphical support for velocity loop tuning in Servo Tuner.•Added support for notch filter tuning in new Notch Filter Tuning tool.•Added support for alignment tuning and command signal tuning in new Miscellaneous Tuning tool.•Added more bit status to newly organized Bit Status panel.•Added more numeric status to newly organized Numerical Status panel.•Added “system snapshot” feature to Technical Support page in Aries Support2Tool.•Added documentation set for the new AR-20 (2 kW) and AR-30 (3kW) drives.•Fixed a few bugs in Aries Support Tool, version 3.0.0.0.________________Revision 2.0.1•Corrected default current loop proportional gain values for all motors supported by Aries Support Tool, version 2.0.0.2.•Corrected feedback resolutions for all 4xxLXR series motors supported by Aries Support Tool, version 2.0.0.2.•Added support for MPM and SMN motors in Aries Support Tool, version2.0.0.2.________________Revision 2.0• Added Servo Tuner and Auto Tuning features to Aries Support Tool, version2.0.0.0, for tuning the position loop of step/direction Aries drives.________________Revision 1.1•Original release. Provided support for the Aries drive family with the Aries Support Tool.==================================================================== System RequirementsAries Support Tool:•IBM-compatible PC with a Pentium 650 MHz or higher processor•Operating systems: Microsoft Windows 95/98/Me/NT/2K/XP/Vista/7 (x86).•64MB RAM.•Hard disk space: 5 MB minimum.•PCI VGA with 800 x 600 resolution or higher.•CD-ROM drive.•Mouse or pointing device.•RS-232C serial port.==================================================================== Technical SupportPhone Support:•1-800-358-9070 (7am - 5pm Pacific Time)Internet Support:•Web site at •Email support at **********************Please be prepared to state your product serial number when calling or emailing for assistance.3。
阿里萨玛尼LF软件更新包6.0用户操作手册说明书
ALEXA Mini LF Software Update Package 6.0 September 10, 2019Imprint2ImprintCopyright© 2019 Arnold & Richter Cine Technik GmbH & Co. Betriebs KG. All rights reserved. No portionsof this document may be reproduced without prior written consent of Arnold & Richter Cine TechnikGmbH & Co. Betriebs KG. Specifications are subject to change without notice. Errors, omissions, andmodifications excepted.AMIRA, ALEXA, ALEXA XT, ALEXA SXT, ALEXA LF, ALEXA Mini and ALEXA Mini LF are trademarksor registered trademarks of Arnold & Richter Cine Technik GmbH & Co. Betriebs KG. All other brandsor products are trademarks or registered trademarks of their respective holders and should be treatedas such.Original version.For Further AssistanceArnold & Richter Cine Technik GmbH & Co. Betriebs KGTuerkenstr. 89D-80799 MunichGermanyE-mail:****************/en/technical-serviceDocument Revision HistoryDocument ID:Version 6.06.0ReleaseK10155K10213DateJuly 15, 2019September 10, 20191Contents1Contents (3)2Disclaimer (7)3For Your Safety / 为了您的安全 (8)3.1Risk Levels and Alert Symbols / 危险级别和警示标志 (8)3.2Vital Precautions / 重要安全措施 (9)3.3Safety Guidelines (10)4Sensor Related Information / 有关影像传感器的信息 (12)5Audience and Intended Use (14)6Scope of Delivery and Warranty (15)7Introduction to the ALEXA Mini LF (16)8Camera Layout (17)8.1Camera Rear Connectors (19)8.2Camera Left and Front Connectors (21)8.3Media Bay (22)8.4Product Identification (22)9Camera Support (23)10Power Supply (26)11Lens Mounts and Lens Handling (28)11.1LPL Mount and PL-to-LPL Adapter (28)11.2Changing a Lens (29)11.3Maximum Lens Mounting Depth (31)11.4Changing the Lens Mount (31)11.5Lens Data (33)12Multi Viewfinder MVF-2 (35)12.1Flip-out Monitor (37)12.2MVF-2 Cables (38)13Menu Operation (39)13.1HOME Screen (40)13.2Using the On-screen Keyboard (43)13.3Working with Lists and Import of Files (44)13.4Function Button FN (46)13.5User Storage Handling (47)13.6Info Screens (48)13.7Alerts Screen (50)14Main Parameters (51)14.1Project Settings (51)14.2Sensor Frame Rate (52)14.3Shutter (53)14.4Exposure Index (53)14.5ND Filter (54)14.6White Balance (55)14.7Timecode (56)15Look Settings (59)15.1Processing and Color Spaces (61)16Recording (63)16.1Recording Media Handling (63)16.1.1Erase of Recording Media (64)16.1.2Remaining Recording Capacity and Media Information (65)16.2Starting Recording via REC button (65)16.3Recording Format (65)16.4Recording Resolution (67)16.5Audio Recording (68)16.6Rec Beeper and Tally Settings (70)16.7File Naming Scheme (70)16.8Data Handling (71)17Playback (72)18Monitoring (74)18.1Status Information and Status Overlays (74)18.1.1Flip-out Monitor Status Bar (77)18.1.2Overlay Menu (77)18.2Surround View (78)18.3Magnification (79)18.4Frame Lines (80)18.5Anamorphic Desqueeze (81)18.6Exposure Tools (82)18.6.1False Color (82)18.6.2Zebra (84)18.7Focus Tools (84)18.7.1Peaking (84)18.7.2Zoom (85)18.8SDI Configuration (86)18.9EVF/Monitor Settings (88)18.10Color Bars (89)19Synchronization (90)19.1EXT Sync (90)19.2Genlock Synchronization (93)19.3Timecode Synchronization (93)20Sensor Settings (94)20.1Noise Reduction (94)20.2Mirroring the Sensor Image (94)20.3User Pixel Masking (95)21System Settings (97)21.1Language Setting (97)21.2System Time and Date (97)21.3Button and Display Settings (97)21.4Fan Settings (97)21.5Battery Warning (97)21.6Lens Mount Settings (98)21.7Network and WiFi Settings (98)21.8Reset of Electronic Horizon (101)21.9Camera Update (101)21.9.1Update of Camera Software (101)21.9.2Update of Camera Components (102)21.9.3Update of LBUS Devices (102)22User Setups (103)22.1User Setup Parameter Blocks (104)23User Buttons (107)23.1List of User Button Functions (108)24Metadata (111)25Electronic Control System (ECS) (113)25.1White Radio Configuration (113)25.2Lens Motors (114)25.3Lens Data (115)25.3.1Adding Lens Tables (LDA) (116)26Remote Control (117)26.1Wireless Control Unit WCU-4 (117)26.2Web Remote (Beta Version) (117)26.3Camera Access Protocol (CAP) (118)27Transvideo Starlite HD5-ARRI Monitor (119)28Appendix (121)28.1Companion Tools (121)28.2Connector Pin-Outs (124)28.3Technical Data (127)28.4Declarations of Conformity (130)28.5Dimensional Drawings (134)Disclaimer7 2DisclaimerBefore using the products described in this manual be sure to read and understand all respectiveinstruction.The ARRI ALEXA Mini LF is only available to commercial customers. The customer grants by utilizationthat the ARRI ALEXA Mini LF or other components of the system are deployed for commercial use.Otherwise the customer has the obligation to contact ARRI preceding the utilization.While ARRI endeavors to enhance the quality, reliability and safety of their products, customers agreeand acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimizerisk of damage to property or injury (including death) to persons arising from defects in the products,customers must incorporate sufficient safety measures in their work with the system and have to heedthe stated canonic use.ARRI or its subsidiaries do not assume any responsibility for incurred losses due to improper handlingor configuration of the camera or other system components, due to sensor contamination, occurrenceof dead or defective pixels, defective signal connections or incompatibilities with third party recordingdevices.ARRI assumes no responsibility for any errors that may appear in this document. The information issubject to change without notice.For product specification changes since this manual was published, refer to the latest publications ofARRI data sheets or data books, etc., for the most up-to-date specifications. Not all products and/ortypes are available in every country. Please check with an ARRI sales representative for availability andadditional information.Neither ARRI nor its subsidiaries assume any liability for infringement of patents, copyrights or otherintellectual property rights of third parties by or arising from the use of ARRI products or any otherliability arising from the use of such products. No license, express, implied or otherwise, is grantedunder any patents, copyrights or other intellectual property right of ARRI or others.ARRI or its subsidiaries expressly exclude any liability, warranty, demand or other obligation for anyclaim, representation, or cause, or action, or whatsoever, express or implied, whether in contract or tort,including negligence, or incorporated in terms and conditions, whether by statue, law or otherwise. Inno event shall ARRI or its subsidiaries be liable for or have a remedy for recovery of any special, direct,indirect, incidental, or consequential damages, including, but not limited to lost profits, lost savings, lostrevenues or economic loss of any kind or for any claim by third party, downtime, good will, damage to orreplacement of equipment or property, any cost or recovering of any material or goods associated withthe assembly or use of our products, or any other damages or injury of the persons and so on or underany other legal theory.In the case one or all of the foregoing clauses are not allowed by applicable law, the fullest extentpermissible clauses by applicable law are validated.ARRI is a registered trademark ofArnold & Richter Cine Technik GmbH & Co Betriebs KG.Apple ProRes 422 HQ, Apple ProRes 4444, Apple ProRes 4444 XQ, and theProRes logo are trademarks or registered trademarks of Apple Computer, Inc., usedunder license therefrom.3For Your Safety / 为了您的安全Before use, please ensure that all users read, understand and follow the instructions in this documentfully. 使用前,请确保所有的用户都已经阅读、理解,并遵循本文档内的操作说明。
MIAOW_Architecture_Whitepaper
MIAOW WhitepaperHardware Description and Four Research Case StudiesAbstractGPU based general purpose computing is developing as a viable alternative to CPU based computing in many do-mains.Today’s tools for GPU analysis include simulators like GPGPU-Sim,Multi2Sim and Barra.While useful for modeling first-order effects,these tools do not provide a detailed view of GPU microarchitecture and physical design.Further,as GPGPU research evolves,design ideas and modifications de-mand detailed estimates of impact on overall area and power. Fueled by this need,we introduce MIAOW,an open source RTL implementation of the AMD Southern Islands GPGPU ISA,ca-pable of running unmodified OpenCL-based applications.We present our design motivated by our goals to create a realistic,flexible,OpenCL compatible GPGPU capable of emulating a full system.Wefirst explore if MIAOW is realistic and then use four case studies to show that MIAOW enables the following: physical design perspective to“traditional”microarchitecture, new types of research exploration,validation/calibration of simulator-based characterization of hardware.Thefindings and ideas are contributions in their own right,in addition to MIAOW’s utility as a tool for others’research.1.IntroductionThere is active and widespread ongoing research on GPU architecture and more specifically on GPGPU architecture. Tools are necessary for such explorations.First,we compare and contrast GPU tools with CPU tools.On the CPU side,tools span performance simulators,em-ulators,compilers,profiling tools,modeling tools,and more recently a multitude of RTL-level implementations of micro-processors-these include OpenSPARC[39],OpenRISC[38], Illinois Verilog Model[56],LEON[18],and more recently FabScalar[11]and PERSim[7].In other efforts,clean slate CPU designs have been built to demonstrate research ideas. These RTL-level implementations allow detailed microarchi-tecture exploration,understanding and quantifying effects of area and power,technology-driven studies,prototype building studies on CPUs,exploring power-efficient design ideas that span CAD and microarchitecture,understanding the effects of transient faults on hardware structures,analyzing di/dt noise,and hardware reliability analysis.Some specific exam-ple research ideas include the following:Argus[30]showed–with a prototype implementation on OpenRISC how to build lightweight fault detectors;Blueshift[19]and power bal-anced pipelines[46]consider the OpenRISC and OpenSPARC pipelines for novel CAD/microarchitecture work.On the GPU side,a number of performance simula-tors[5,2,12,28],emulators[53,2],compilers[29,13,54],GPUs;ii)Flexible:it should beflexible to accommodate research studies of various types,the exploration of forward-looking ideas,and form an end-to-end open source tool;iii) Software-compatible:It should use standard and widely avail-able software stacks like OpenCL or CUDA compilers to en-able executing various applications and not be tied to in-house compiler technologies and languages.portion of the CU denotes the registerfile and SRAM stor-age as indicated in Figure1(b)).First,observe that in all three designs,the registerfiles need some special treatment besides writing Verilog RTL.A full ASIC design results in reducedflexibility,long design cycle and high cost,and makes it a poor research platform,since memory controller IP and hard macros for SRAM and registerfiles may not be redis-tributable.Synthesizing for FPGA sounds attractive,but there are several resource constraints that must be accommodated tigate case studies along the three perspectives.Section8 1MIAOW was not designed to be a replica of existing commercial GPG-PUs.Building a model that is an exact match of an industry implementation requires reverse engineering of low level design choices and hence was not our goal.The aim when comparing MIAOW to commercial designs was to show that our design is reasonable and that the quantitative results are in similar range.We are not quantifying accuracy since we are defining a new microarchitecture and thus there is no reference to compare to.Instead we compare to a nearest neighbor to show trends are similar.Direction Research idea MIAOW-enabledfindingsTraditional µarch Thread-blockcompaction◦Implemented TBC in RTL◦Significant design complexity◦Increase in critical path lengthNew directions Circuit-failureprediction(Aged-SDMR)◦Implemented entirely inµarch◦Idea works elegantly in GPUs◦Small area,power overheads Timingspeculation(TS)◦Quantified TS error-rate on GPU◦TS framework for future studiesValidation of sim-ulator studiesTransient faultinjection◦RTL-level fault injection◦More gray area than CPUs(dueto large RegFile)◦More silent structuresTable2:Case studies summaryconcludes.The authors have no affiliation with AMD or GPU manufacturers.All information about AMD products used and described is either publicly available(and cited)or reverse-engineered by authors from public documents.2.MIAOW ArchitectureThis section describes MIAOW’s ISA,processor organization, microarchitecture of compute units and pipeline organization, and provides a discussion of design choices.2.1.ISAMIAOW implements a subset of the Southern Islands ISA which we summarize below.The architecture state and regis-ters defined by MIAOW’s ISA includes the program counter, execute mask,status registers,mode register,general purpose registers(scalar s0-s103and vector v0-v255),LDS,32-bit memory descriptor,scalar condition codes and vector con-dition codes.Program control is defined using predication and branch instructions.The instruction encoding is of vari-able length having both32-bit and64-bit instructions.Scalar instructions(both32-bit and64-bit)are organized in5for-mats[SOPC,SOPK,SOP1,SOP2,SOPP].Vector instructions come in4formats of which three[VOP1,VOP2,VOPC]use 32-bit instructions and one[VOP3]uses64-bit instructions to address3operands.Scalar memory reads(SMRD)are 32-bit instructions involved only in memory read operations and use2formats[LOAD,BUFFER_LOAD].Vector memory instructions use2formats[MUBUF,MTBUF],both being 64-bits wide.Data share operations are involved in reading and writing to local data share(LDS)and global data share (GDS).Four commonly used instruction encodings are shown in Table4.Two memory addressing modes are supported-base+offset and base+register.Of a total of over400instructions in SI,MIAOW’s instruc-tion set is a carefully chosen subset of95instructions and the generic instruction set is summarized in Table4.This subset was chosen based on benchmark profiling,the type of operations in the data path that could be practically im-plemented in RTL by a small design team,and elimination of graphics-related instructions.In short,the ISA defines a processor which is a tightly integrated hybrid of an in-order core and a vector core all fed by a single instruction supply and memory supply with massive multi-threading capabil-ity.The complete SI ISA judiciously merges decades of re-search and advancements within each of those designs.From a historical perspective,it combines the ideas of two classical machines:the Cray-1vector machine[45]and the HEP multi-threaded processor[49].The recent Maven[27]design is most closely related to MIAOW and is arguably moreflexible and includes/explores a more diverse design space.From a practical standpoint of exploring GPU architecture,we feel it falls short on realism and software compatibility.2.2.MIAOW Processor Design OverviewFigure1shows a high-level design of a canonical AMD South-ern Islands compliant GPGPU.The system has a host CPU that assigns a kernel to the GPGPU,which is handled by the GPU’s ultra-threaded dispatcher.It computes kernel assign-ments and schedules wavefronts to CUs,allocating wavefront slots,registers and LDS space.The CUs shown in Figure1(b) execute the kernels and are organized as scalar ALUs,vector ALUs,a load-store unit,and an internal scratch pad memory (LDS).The CUs have access to the device memory through the memory controller.There are L1caches for both scalar data accesses and instructions and a unified L2cache.The MIAOW GPGPU adheres to this design and consists of a simple dispatcher,a configurable number of compute units, memory controller,OCN,and a cached memory hierarchy2. MIAOW allows scheduling up to40wavefronts on each CU.2.3.MIAOW Compute Unit MicroarchitectureFigure3shows the high-level microarchitecture of MIAOW with details of the most complex modules and Figure4shows the pipeline organization.Below is a brief description of the functionalities of each microarchitectural component–further details are deferred to an accompanying technical report. Fetch(Fig.3b)Fetch is the interface unit between the Ultra-Threaded Dispatcher and the Compute Unit.When a wave-front is scheduled on a Compute Unit,the Fetch unit receives the initial PC value,the range of registers and local memory which it can use,and a unique identifier for that wavefront. The same identifier is used to inform the Dispatcher when execution of the wavefront is completed.It also keeps track of the current PC for all executing wavefronts.Wavepool(Fig.3b)The wavepool unit serves as an instruc-tion queue for all fetched instructions.Up to40wavefronts–supported by40independent queues–can be resident in the compute unit at any given time.The wavepool works closely with the fetch unit and the issue unit to keep instructionsflow-ing through the compute unit.Decode This unit handles instruction decoding.It also col-lates the two32-bit halves of64-bit instructions.The Decode Unit decides which unit will execute the instruction based on the instruction type and also performs the translation of logical register addresses to physical addresses.2The reference design includes a64KB GDS,which we omitted in our design since it is rarely used in performance targeted benchmarksSI Term nVidia term DescriptionCompute Unit(CU)SM A compute unit is the basic unit of computation and contains computation resources,architectural storage resources(registers),and local memory.Workitem Thread The basic unit of computation.It typically represents one input data point.Sometimesreferred to as a’thread’or a’vector lane’.Wavefront Warp A collection of64work-items grouped for efficient processing on the compute unit.Eachwavefront shares a single program counter.Workgroup Thread-block A collection of work-items working together,capable of sharing data and synchronizingwith each other.Can comprise more than one wavefront,but is mapped to a single CU.Local data store(LDS)Sharedmemory Memory space that enables low-latency communication between work-items within a work-group,including between work-items in a wavefront.Size:32kb limit per workgroup.Global data share(GDS)Global memory Storage used for sharing data across multiple workgroups.Size:64KB. Device memory Device memory Off-chip memory provided by DRAM possibly cached in other on-chip storage.Table3:Definition of Southern Islands ISA terms and correspondence to NVIDIA/CUDA terminologyBase0Instr Q WF0++VTail | Head | Tail+ance which uses evaluation content in Section4.In short,our design choices lead to a realistic and balanced design. Fetch bandwidth(1)We optimized the design assuming instruction cache hits and single instruction fetch.In contrast, the GCN specification has fetch bandwidth on the order of16 or32instructions per fetch,presumably matching a cache-line. It includes an additional buffer between fetch and wavepool to buffer the multiple fetched instructions for each wavefront. MIAOW’s design can be changed easily by changing the inter-face between the Fetch module and Instruction memory. Wavepool slots(6)Based on the back-of-the-envelope anal-ysis of load balance,we decided on6wavepool slots.Our design evaluations show that all6slots of the wavepool are filled50%of the time-suggesting that this is a reasonable and balanced estimate considering our fetch bandwidth.We ex-pect the GCN design has many more slots to accommodate the wider fetch.The number of queue slots is parameterized and can be easily changed.Since this pipeline stage has smaller area,it has less impact on area and power.Issue bandwidth(1)We designed this to match the fetch bandwidth and provide a balanced machine as confirmed in our evaluations.Increasing the number of instructions issued per cycle would require changes to both the issue stage and the register read stage,increasing register read pared to our single-issue width,GCN’s documentation suggests an issue bandwidth of5.For GCN this seems an unbalanced de-sign because it implies issuing4vector and1scalar instruction every cycle,while each wavefront is generally composed of 64threads and the vector ALU being16wide.We suspect the actual issue width for GCN is lower.#of integer&floating point functional units(4,4)We incorporate four integer and fourfloating point vector func-tional units to match industrial designs like the GCN and the high utilization by Rodinia benchmarks indicate the number is justified.These values are parameterizable in the top level module and these are major contributors to area and power. #of register ports(1,5)We use two registerfile designs. Thefirst design is a single ported SRAM based registerfile generated using synopsys design compiler which is heavily banked to reduce contention.In simulations,we observed that there was contention on less then1%of the accesses and hence we are using a behavioral module.This deci-sion will result in a model with a small under-estimation of area and power and over-estimation of performance.This design,however,is likely to be similar to GCN and we report the power/area/performance results based on this registerfile. Since it includes proprietary information and the configuration cannot be distributed,we have a second verison-aflip-flop based registerfile design which hasfive ports.While we have explored these two registerfile designs,many register compil-ers,hard macros,and modeling tools like CACTI are available providing a spectrum of accuracy andfidelity for MIAOW’s users.Researchers can easily study various configurations[4] by swapping out our module.#of slots in Writeback Queue per functional unit(1)To simplify implementation we used one writeback queue slot, which proved to be sufficient in design evaluation.The GCN design indicates a queuing mechanism to arbitrate access to a banked registerfile.Our design choice here probably impacts realism significantly.The number of writeback queue slots is parameterized and thus providesflexibility.The area and power overhead of each slot is negligible.Types of functional units GCN and other industry GPUs have more specialized FUs to support graphic computations. This choice restricts MIAOW’s usefulness to model graph-ics workloads.It has some impact on realism andflexibility depending on the workloads studied.However this aspect is extendable by creating new datapath modules.3.ImplementationIn this section wefirst describe MIAOW’s hybrid implementa-tion strategy of using synthesizable RTL and behavioral mod-els and the tradeoffs introduced.We then briefly describe our verification strategy,physical characteristics of the MIAOW prototype,and a quantitative characterization of the prototype.3.1.Implementation summaryFigure2(c)shows our implementation denoting components implemented in synthesizable RTL vs.PLI or C/C++models. Compute Unit,Ultra-threaded dispatcher As described in AMD’s specification for SI implementations,“the heart of GCN is the new Compute Unit(CU)”and so we focus our attention to the CU which is implemented in synthesizable Verilog RTL.There are two versions of the ultra threaded dis-patcher,a synthesizable RTL module and a C/C++model.The C/C++model can be used in simulations where dispatcher area and power consumption are not relevant,saving simulation time and easing the development process.The RTL design can be used to evaluate complexity,area and power of different scheduling policies.OCN,L2-cache,Memory,Memory Controller Simpler PLI models are used for the implementation of OCN and mem-ory controller.The OCN is modeled as a cross-bar between CUs and memory controllers.To provideflexibility we stick to a behavioral memory system model,which includes device memory(fixed delay),instruction buffer and LDS.This mem-ory model handles coalescing by servicing diverging memory requests.We model a simple and configurable cache which is non-blocking(FIFO based simple MSHR design),set asso-ciative and write back with a LRU replacement policy.The size,associativity,block size,and hit and miss latencies are programmable.A user has the option to integrate more sophis-ticated memory sub-system techniques[48,20].3.2.Verification and Physical DesignWe followed a standard verificationflow of unit tests and in-house developed random program generator based regres-sion tests with architectural trace comparison to an instruction emulator.Specifically,we used Multi2sim as our referenceinstruction emulator and enhanced it in various ways with bug-fixes and to handle challenges in the multithreaded nature and out-of-order retirement of wavefronts.We used the AMD OpenCL compiler and device drivers to generate binaries. Physical design was relatively straight-forward using Syn-opsys Design Compiler for synthesis and IC Compiler for place-and-route with Synopsys32nm library.Based on De-sign Compiler synthesis,our CU design’s area is15mm2and it consumes on average1.1W of power across all benchmarks. We are able to synthesize the design at an acceptable clock period range of4.5ns to8ns,and for our study we have chosen yout introduces challenges because of the dominant usage of SRAM and registerfiles and automaticflat layout withoutfloorplanning fails.While blackboxing these produceda layout,detailed physical design is future work.3.3.FPGA ImplementationIn addition to software emulation,MIAOW was successfully synthesized on a state-of-art very large FPGA.This variant, dubbed Neko,underwent significant modifications in order tofit the FPGA technology process.We used a Xilinx Vir-tex7XC7VX485T,which has303,600LUTs and1,030block RAMs,mounted on a VC707evaluation boardDesign Neko is composed of a MIAOW compute unit at-tached to an embedded Microblaze softcore processor via the AXI interconnect bus.The Microblaze implements the ultra-threaded dispatcher in software,handles pre-staging of data into the registerfiles,and serves as an intermediary for access-ing memory(Neko does not interface directly to a memory controller).Due to FPGA size limits,Neko’s compute unit has a smaller number of ALUs(one SIMD and SIMF)than a standard MIAOW compute unit which has four SIMD and four SIMF units for vector integer andfloating point operations respectively.The consequence of this is that while Neko can perform any operation a full compute unit can,its throughput is lower due to the fewer computational resources.Mapping the ALUs to Xilinx provided IP cores(or DSP slices)may help infitting more onto the FPGA as the SIMD and especially SIMF units consume a large proportion of the LUTs.This however changes the latencies of these significantly(multi-plication using DSP slices is a6stage pipeline,while using 10DSPs can create a1stage pipeline)and will end up re-quiring modifications to the rest of the pipeline and takes away from ASIC realism.We defer this for future work.One other difference is Neko’s registerfile architecture.Mapping MIAOW’s registerfiles naively toflip-flops causes excessive usage and routing difficulties considering,especially with the vector ALU registerfile which ing block RAMs is not straight-forward either,they only support two ports each,fewer than what the registerfiles need.This issue was ultimately resolved by banking and double-clocking the BRAMs to meet port and latency requirements.Resource Utilization and Use Case Table6presents break-downs of resource utilization by the various modules of theModule LUT Count#BRAMs Module LUT Count#BRAMs Decode3474-SGPR6478Exec8689-SIMD36890-Fetch222901SIMF55918-Issue36142-VGPR2162128SALU1240-Wavepool27833-Total195285137Table6:Resource utilizationMIAOW does not aim to be an exact match of any industry implementation.To check if quantitative results of the afore-mentioned metrics follow trends similar to industry GPGPU designs,we compare MIAOW with the AMD Tahiti GPU, which is also a SI GPU.In cases where the relevant data is not available for Tahiti,we use model data,simulator data,or data from NVIDIA GPUs.Table7summarizes the methodology and key results and show MIAOW is realistic.For performance studies we choose six OpenCL bench-marks that are part of the Multi2sim environment,which we list along with three characteristics–#work groups,#wave-fronts per workgroup,and#compute-cycles per work group: BinarySearch(4,1,289),BitonicSort(1,512,97496),Matrix-Transpose(4,16,4672),PrefixSum(1,4,3625),Reduction (4,1,2150),ScanLargeArrays(2,1,4).MIAOW can also run four Rodinia[9]benchmarks at this time–kmeans,nw, backprop and gaussian.We use these longer benchmarks for the case studies in Section5onward3.5.Physical Design PerspectiveDescription:Fung et al.proposed Thread Block Com-paction(TBC)[16].which belongs in a large body of work 3Others don’t run because of they use instructions outside MIAOW’s subset.Area analysisGoal◦Is MIAOW’s total area and breakdown across modules representative of industry designs?Method◦Synthesized with Synopsys1-ported register-file◦For release,5-portedflip-flop based regfile.◦Compare to AMD Tahiti(SI GPU)implemented at28nm;scaled to32nm for absolute comparisonsKey results◦Area breakdown matches intuition;30%in functional units &54%in registerfiles.◦Total area using1-port Synopsys RegFile9.31mm2com-pared to6.92mm2for Tahiti CU◦Higher area is understandable:our design is not mature, designers are not as experienced,our functional units are quite inefficient(from ),and not optimized as indus-try functional units would be.Power analysisGoal◦Is MIAOW’s total power and breakdown across modules representative of industry designs?Method◦Synopsys Power Compiler runs with SAIF activityfile generated by running benchmarks through VCS.◦Compared to GPU power models of NVIDIA GPU[22].Breakdown and total power for industry GPUs not publiclyavailable.Key results◦MIAOW breakdown:FQDS:13.1%,RF:16.9%FU:69.9%◦NVIDIA breakdown:FQDS:36.7%,RF:26.7%FU:36.7%◦Compared to model more power in functional units(likely because of MIAOW’s inefficient FUs);FQDS and RF roughly similar contributions in MIAOW and model.◦Total power is1.1Watts.No comparison reference avail-able.But we feel this is low.Likely because Synopsys32nm technology library is targeted to low power design(1.05V, 300MHz typical frequencyPerformance analysisGoal◦Is MIAOW’s performance realistic?Method◦Failed in comparing to AMD Tahiti performance using AMD performance counters(bugs in vendor drivers).◦Compared to similar style NVIDIA GPU Fermi1-SM GPU.◦Performance analysis done by obtaining CPI for each classof instructions across benchmarks.◦Performed analysis to evaluate balance and sizingKeyresults◦CPI breakdown across execution units is below.CPI DMin DMax BinS BSort MatT PSum Red SLA Scalar13333333Vector16 5.4 2.1 3.1 5.5 5.4 5.5 Memory110014.1 3.8 4.6 6.0 6.8 5.5 Overall1100 5.1 1.2 1.7 3.6 4.4 3.0 NVidia1_20.5 1.9 2.18 4.77.5◦MIAOW is close on3benchmarks.◦On another three,MIAOW’s CPI is2×lower,the reasonsfor which are many:i)the instructions on the NVIDIA GPUare PTX-level and not native assembly;ii)cycle measurementitself introduces noise;and iii)microarchitectures are different,so CPIs will be different.◦CPIs being in similar range shows MIAOW’s realism◦The#of wavepool queue slots was rarely the bottleneck:in50%of the cycles there was at least one free slot available(with2available in20%of cycles).◦The integer vector ALUs were all relatively fully occupiedacross benchmarks,while utilization of the3rd and4th FPvector ALU was less than10%.◦MIAOW seems to be a balanced design.Table7:Summary of investigations of MIAOW’s realism on warp scheduling[31,44,16,43,35,25,24],any of which we could have picked as a case study.TBC,in particular,aims to increase functional unit utilization on kernels with irregular controlflow.The fundamental idea of TBC is that,whenever a group of wavefronts face a branch that forces its work-items to follow the divergent program paths,the hardware should dy-namically reorganize them in new re-formed wavefronts that contain only those work-items following the same path.Thus, we replace the idle work-items with active ones from other wavefronts,reducing the number of idle SIMD lanes.Groups of wavefronts that hit divergent branches are also forced to run in similar paces,reducing even more work-item level diversion on such kernels.Re-formed wavefronts are formed observing the originating lane of all the work-items:if it occupies the lane0in wavefront A,it must reoccupy the same lane0in re-formed wavefront B.Wavefront forming mechanism is com-pletely local to the CU,and it happens without intervention from the ultra-threaded dispatcher.In this study we investigate the level of complexity involved in the implementation of such microarchitecture innovations in RTL.Infrastructure and Methodology We follow the imple-mentation methodology described in[16].In MIAOW,the modules that needed significant modifications were:fetch, wavepool,decode,SALU,issue and the vector registerfile. The fetch and wavepool modules had to be adapted to support the fetching and storage of instructions from the re-formed wavefronts.We added two instructions to the decode mod-ule:fork and join which are used in SI to explicitly indicate divergent branches.We added the PC stack(for recovery after reconvergence)and modified the wavefront formation logic in the SALU module,as it was responsible for handling branches. Although this modification is significant,it does not have a huge impact on complexity,as it does not interfere with any other logic in the SALU apart from the branch unit.The issue and VGPR modules suffered more drastic modifi-cations,shown infigure6.In SI,instructions provide register addresses as an offset with the base address being zero.When a wavefront is being dispatched to the CU,the dispatcher allo-cates registerfile address space and calculates the base vector and scalar registers.Thus,wavefronts access different register spaces on the same registerfile.Normally,all work-items in the wavefront access the same register but different pages of the registerfile as shown in the upper-left corner of6,and the register absolute address is calculated during decode.But with TBC,this assumption does not hold anymore.In a re-formed wavefront all the work-items may access registers with the same offset but different base values(from different originat-ing wavefronts).This leads to modifications in the issue stage, now having to maintain information about register occupancy by offset for each re-formed wavefront,instead of absolute global registers.In the worst case scenario,issue has to keep track of256registers for each re-formed wavefront in contrast to1024for the entire CU in the original implementation.In figure6,the baseline issue stage observed in the lower-leftcorner and in the lower-right are the modifications for TBC, adding a level of dereference to the busy table search.In VGPR,we now must maintain a table with the base registers from each work-item within a re-formed wavefront and reg-ister address is calculated for each work-item in access time. Thus,there are two major sources of complexity overheads in VGPR,the calculation and the routing of different addresses to each register page as shown in the upper-right corner of6. We had to impose some restrictions to our design due to ar-chitectural limitations:first,we disallowed the scalar register file and LDS accesses during divergence,and therefore,wave-front level synchronization had to happen at GDS.We also were not able to generate code snippets that induced the SI compiler to use fork/join instructions,therefore we used hand-written assembly resembling benchmarks in[16].It featured a loop with a divergent region inside,padded with vector instruc-tions.We controlled both the number of vector instructions in the divergent region and the level of diversion.Our baseline used post-denominator stack-based reconver-gence mechanism(PDOM)[33],without any kind of wave-front formation.We compiled our tests and ran them on two versions of MIAOW:one with PDOM and other with TBC. Quantitative results The performance results obtained matched the results from[16]:Similar performance was ob-served when there was no divergence and a performance in-crease was seen for divergent workloads.However,our most important results came from synthesis.We observed that the modifications made to implement TBC were mostly in the regions in the critical paths of the design.The implementation of TBC caused an increase of32%in our critical path delay from8.00ns to10.59ns.We also observed that the issue stage area grew from0.43mm2to1.03mm2.Analysis Our performance results confirm the ones obtained by Fung et al.,however,the RTL model enabled us to imple-ment TBC in further detail and determine that critical path delay increases.In particular,we observed that TBC affects the issue stage significantly where most of the CU control state is present dealing with major microarchitectural events.TBC reinforces the pressure over the issue stage making it harder to track such events.We believe that the added complexity suggests that a microarchitectural innovation may be needed involving further design refinements and re-pipelining,not just implementation modifications.The goal of this case study is not to criticize the TBC work or give afinal word on its feasibility.Our goal here is to show that,by having a detailed RTL model of a GPGPU,one can better evaluate the complexity of any proposed novelties. 6.New types of research exploration6.1.Sampling DMR on GPUsDescription:Balasubramanian et al.proposed a novel tech-nique of unifying the circuit failure prediction and detection in CPUs using Virtually Aged Sampling DMR[6](Aged-SDMR).They show that Aged-SDMR provides low design complexity,low overheads,generality(supporting various types of wearout including soft and hard breakdown)and high accuracy.The key idea was to“virtually”age a processor by reducing its voltage.This effectively slows down the gates, mimicking the effect of wearout and exposes the fault,and Sampling-DMR is used to detect the exposed fault.They show that running in epochs and by sampling and virtually aging1%of the epochs provides an effective system.Their design(shown in Figure7)is developed in the context of multi-core CPUs and requires the following:i)operating system involvement to schedule the sampled threads,ii)some kind of system-level checkpoints(like Revive[41],ReviveIO[34], Safetynet[51])at the end of every epoch,iii)some system and microarchitecture support for avoiding incoherence be-tween the sampled threads[50],iv)some microarchitecture support to compare the results of the two cores,and v)a subtle but important piece,gate-level support to insert a clock-phase shifting logic for fast paths.Because of these issues Aged-SDMR’s ideas cannot directly be implemented for GPUs to achieve circuit failure prediction.With reliability becoming important for GPUs[10],having this capability is desirable. Our Design:GPUs present an opportunity and problem in adapting these ideas.They do not provide system-level check-points nor do they lend themselves to the notion of epochs making(i),(ii)and(iii)hard.However,the thread-blocks(or workgroups)of compute kernels are natural candidates for a piece of work that is implicitly checkpointed and whose gran-ularity allows it to serve as a body of work that is sampled and run redundantly.Furthermore,the ultra-threaded dispatcher can implement all of this completely in the microarchitecture without any OS support.Incoherence between the threads can be avoided by simply disabling global writes from the sampled thread since other writes are local to a workgroup/compute-unit anyway.This assumption will break and cause correctness issues when a single thread in a wavefront does read-modify-writes to a global address.We have never observed this in our workloads and believe programs rarely do pari-sion of results can be accomplished by looking at the global stores instead of all retired instructions.Finally,we reuse the clock-phase shifting circuit design as it is.This overall design, of GPU-Aged-SDMR is a complete microarchitecture-only solution for GPU circuit failure prediction.Figure7shows the implemenation mechanism of GPU-Aged-SDMR.Sampling is done at a workgroup granularity with the ultra-threaded dispatcher issuing a redundant work-group to two compute units(checker and checked compute units)at a specified sampling rate,i.e for a sampling rate of1%,1out of100work groups are dispatched to another compute unit called checker.This is run under the stressed conditions and we disable the global writes so that it does not affect the normal execution of the workgroups in the checked CU.We could use a reliability manager module that compares all retired instructions or we can compute a checksum of the retiring stores written to global memory from the checker and。
INFORTREND配置
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MaxSiz=****MB SetT o ****MB Execute Expand Logical Drive Exp Online **% -----------
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Enter To Select a New Drive
Change LD Name: * Redund Ctlr LG Assign Slot B Ctlr? Add Drv Selected To select drives Add Drv Selected To select drives Free Capacity on logical drive Overwrite When Inconsistency .. Events On When Inconsistency .. Execute Parity Check .. Enter To Select a On-Line Drive ENT x 2 sec. Change Setting Do Reset Ctlr ? C=* I=* ****MB LG=* LN Vendor ID Slot=## ####MB NEW DRV XXXX Expandable Size *****MB .. Initialization Mode Online .. LG=* Parity Regen Completed Select New Drive to add Capacity Migrate Logical Drive ?
6080A AN 信号生成器操作手册说明书
NON· VOLATILE MEMORy...................... 50 instrument states are retained for typically 2 years, even with the power mains disconnec1ed.
Rack Mount Kit
Incluoes MD5-205-6DO (5 1/4-inch Rack Mount Ears) and MOO-280-610 (24-inch Rack Slides)
IEEE·488 Shielded Cable, 1 meter
IEEE-488 Shielded Cable, 2 meters
. 0.50 to \ 024 MHz in 7 bands: . 0.50 to 14.999999 MHz, . 15 to 31.999999 MHz, . 32 to 63.999999 MHz, . 64 to 127.999999 MHz, . 128 to 255.999999 MHz, . 256 to 511.999999 MHz, . 512 to 1024 MHz.
o to 10kHz min
a to lOa kHz min
o to 1 MHz min
Frequency < 1 MHz 1 MHz < Frequency < 32 MHz 32 MHz < Frequency < 128 MHz Frequency> 128 MHz
RESOLUTION
贝尔DSLAM维护命令手册
目录Contents一、编写概述 (3)二、适用范围 (3)三、常用操作及命令 (3)(一)配置操作 (3)1.配置IP地址 (3)2.配置模板 (3)3.配置用户板 (4)4.配置上联口 (5)5.配置VLAN (6)6.配置SNMP (6)7.配置XDSL端口 (7)8.配置ATM PVC (7)9.配置bridge port (7)(二)查看操作 (7)1.查看软件版本 (7)2 .查看上联端口 (8)3.查看板卡 (9)4.查看用户端口 (10)5.查看MAC地址 (11)6.查看用户Bridge端口信息 (12)(三)常用操作命令 (12)1.打开/关闭端口 (12)2.修改端口速率模板 (13)(四)其他操作 (13)1.登陆用户名和口令 (13)2.系统时钟 (14)3.命令提示符 (14)4.ACL访问控制 (14)5.数据备份和恢复 (15)6.告警查询 (15)7.系统重启 (15)四、常见故障及维护建议 (16)(一)常见故障 (16)1.无法同步 (16)2.频繁掉线 (16)3.同步无法拨号 (18)4.自动工单系统操作失败 (18)5.用户上网慢 (19)(二)维护建议 (20)1.检查节点备份文件 (20)2.检查节点板卡温度 (20)附录Trace&Debug命令介绍 (20)一、编写概述为帮助更好维护7302ISAM设备,编写本文档。
本文档所有命令以R2.4为基础,可能因为版本不同而有所变化,具体请参各个版本的命令手册。
二、适用范围本手册适用于所有现场工程师、局方维护人员。
三、常用操作及命令(一)配置操作1.配置IP地址从R2.4开始,7302支持单IP管理地址。
configure system single-public-ipconfigure system management host-ip-address manual:192.168.1.100/24查看配置info configure system management2.配置模板线速模板configure xdsl service-profile 1 name 2M-640K-Fastconfigure xdsl service-profile 1 min-bitrate-up 64 min-bitrate-down 64 plan-bitrate-up 640 plan-bitrate-down 2048 max-bitrate-up 640 max-bitrate-down 2048 max-delay-up 1max-delay-down 1 active其中max-delay-up、max-delay-down定义交织延时,=1表示Fast模式查看配置info configure xdsl service-profile 1协议模板configure xdsl spectrum-profile 1 name adsl2plus g992-5-aconfigure xdsl spectrum-profile 1 active其中7302默认配置如下协议,见表3-2-1:g992-5-a为ADSL2+ over POTS协议,需要单独添加,也可以按需添加其他协议,如AnnexM协议等,具体参照标准协议手册。
PMR的使用步骤
PMR的使用步骤:
说明方法主要是图解,如下图:
Step one:
,入图,选择PMR,单击,
如下图:
Step two:
,如图,选择FILE,弹出菜单:
,选择Initiate Recording…,单击,
如图:
Step three:
,选择CELL,然后,弹出对话框,如下图:
我们在对小区进行工作的时候,主要是用CELL这一个功能,在选择了CELL后,然后,在
RECONRDING NAME写下需要测试的小区名字,然后再选择Insert from list…,单击,出现下面的菜单,如下图:
,选择小区所在的BSC,然后,点击INSERT;
选择了BSC后,然后,定义需要测量的时间,STAR_____-------STOP_____,这个就是需要测量的时间,一般定义35分钟以上;然后,再在Cell related settings下面,选择Insert from list。
,然后,选择需要测试的小区的名字,一定要选择对了。
然后,选择,Start Criterion:CA,这样就定义完了PMR,最后,再选择Initiate,这样就在终端上定义完了。
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RELEVANT TO ACCA QUALIFICATION PAPER F6 (UK) ANDPERFORMANCE OBJECTIVES 19 AND 20Inheritance tax, part 1The Paper F6 (UK) syllabus requires a basic understanding of inheritance tax (IHT), and this two-part article covers those aspects that you need to know. It is relevant to candidates taking Paper F6 (UK) in 2012, and is based on tax legislation as it applies to the tax year 2011–12 (Finance Act 2011).There will always be a minimum of five marks (but no more than 15 marks) on IHT, with these marks being included in either questions three, four or five.The scope of inheritance taxIHT is paid on the value of a person’s estate when they die, but it also applies to certain lifetime transfers of assets. If IHT did not apply to lifetime transfers it would be very easy for a person to avoid tax by giving away all of their assets just before they died.As far as Paper F6 (UK) is concerned the terms ‘transfer’ and ‘gift’ can be taken to mean the same thing. The person making a transfer is known as the donor, whilst the person receiving the transfer is known as the donee.Unlike capital gains tax where, for example, a principal private residence is exempt, all of a person’s estate is generally chargeable to IHT.A person who is domiciled in the UK is liable to IHT in respect of their worldwide assets. As far as Paper F6 (UK) is concerned, people will always be domiciled in the UK.Transfers of valueDuring a person’s lifetime IHT can only arise if a transfer of value is made. A transfer of value is defined as ‘any gratuitous disposition made by a person that results in a diminution in value of that person’s estate’. There are two important terms in this definition:•Gratuitous: Poor business deals, for example, are not normally transfers of value because there is no gratuitous intent.•Diminution in value: Normally there will be no difference between the diminution in value of the donor’s estate and the increase in value of the donee’s estate.However, in some cases it may be necessary to compare the value of thedonor’s estate before the transfer, and the value after the transfer in order tocompute the diminution in value. This will usually be the case where unquoted shares are concerned. Shares forming part of a controlling shareholding will be valued higher than shares forming part of a minority shareholding. EXAMPLE 1On 4 May 2011 Daniel made a gift to his son of 15,000 £1 ordinary shares in ABC Ltd, an unquoted investment company. Before the transfer Daniel owned 60,000 shares out of ABC Ltd’s issued share capital of 100,000 £1 ordinary shares. ABC Ltd’sMARCH 2012shares are worth £8 each for a holding of 15%, £10 each for a holding of 45%, and £18 each for a holding of 60%.Although Daniel’s son received a 15% shareholding valued at £120,000 (15,000 x £8), Daniel’s transfer of value is calculated as follows:£Value of shares held before the transfer60,000 x £18 1,080,000Value of shares held after the transfer45,000 x £10 450,000Value transferred 630,000By contrast, for capital gains tax purposes the valuation will be based on the market value of the shares gifted, which is £120,000.As far as Paper F6 (UK) is concerned a transfer of value will always be a gift of assets.A gift made during a person’s lifetime may be either potentially exempt or chargeable. Potentially exempt transfersAny transfer that is made to another individual is a potentially exempt transfer (PET).A PET only becomes chargeable if the donor dies within seven years of making the gift. If the donor survives for seven years then the PET becomes exempt and can be completely ignored. Hence such a transfer has the potential to be exempt.If the donor dies within seven years of making a PET then it becomes chargeable. Tax will be charged according to the rates and allowances applicable to the tax year in which the donor dies. However, the value of a PET is fixed at the time that the gift is made.EXAMPLE 2Sophie died on 23 January 2012. She had made the following lifetime gifts:8 November 2004 A gift of £450,000 to her son.12 August 2009 A gift of a house valued at £610,000 to her daughter. By 23January 2012 the value of the house had increased to £655,000. The gift to Sophie’s son on 8 November 2004 is a PET for £450,000. As it was made more than seven years before the date of Sophie’s death it is exempt from IHT.The gift to Sophie’s daughter on 12 August 2009 is a PET for £610,000 and is initially ignored. It becomes chargeable as a result of Sophie dying within seven years of making the gift, and the transfer of £610,000 will be charged to IHT based on the rates and allowances for 2011–12.MARCH 2012Chargeable lifetime transfersAny transfer that is made to a trust is a chargeable lifetime transfer (CLT).There is no legal definition of what a trust is, but essentially a trust arises where a person transfers assets to people (the trustees) to hold for the benefit of other people (the beneficiaries). For example, parents may not want to make an outright gift of assets to their young children. Instead, assets can be put into a trust with the trust being controlled by trustees until the children are older.Unlike a PET, a CLT is immediately charged to IHT based on the rates and allowances applicable to the tax year in which the CLT is made. An additional tax liability may then arise if the donor dies within seven years of making the gift. Just as for a PET, the value of a CLT is fixed at the time that the gift is made, but the additional tax liability is calculated using the rates and allowances applicable to the tax year in which the donor dies.EXAMPLE 3Lim died on 4 December 2011. She had made the following lifetime gifts:2 November 2004 A gift of £420,000 to a trust.21 August 2009 A gift of a house valued at £615,000 to a trust. By 4 December2011 the value of the house had increased to £650,000.The gift to the trust on 2 November 2004 is a CLT for £420,000, and will be immediately charged to IHT based on the rates and allowances for 2004–05. There will be no additional tax liability as the gift was made more than seven years before the date of Lim’s death.The gift to the trust on 21 August 2009 is a CLT for £615,000, and will be immediately charged to IHT based on the rates and allowances for 2009–10. Lim has died within seven years of making the gift so an additional tax liability may arise based on the rates and allowances for 2011–12.Rates of taxIHT is payable once a person’s cumulative chargeable transfers over a seven year period exceed a nil rate band. For the tax year 2011–12 the nil rate band is £325,000, and for previous years it has been as follows:£ £2002–03 250,000 2007–08 300,0002003–04 255,000 2008–09 312,0002004–05 263,000 2009–10 325,0002005–06 275,000 2010–11 325,0002006–07 285,000MARCH 2012The rate of IHT payable as a result of a person’s death is 40%. This is the rate that is charged on a person’s estate at death, on PETs that become chargeable as a result of death within seven years, and is also the rate used to see if any additional tax is payable on CLTs made within seven years of death.The rate of IHT payable on CLTs at the time they are made is 20% (half the death rate). This is the lifetime rate.The tax rates information that will be given in the tax rates and allowances section of the June and December 2012 examination papers is as follows:£1 – £325,000 NilExcess – Death rate 40%– Lifetime rate 20%Where nil rate bands are required for previous years then these will be given to you within the question.EXAMPLE 4Sophie died on 26 May 2011 leaving an estate valued at £600,000.The IHT liability is as follows:Death estate£Chargeable estate 600,000IHT liability 325,000 at nil%275,000 at 40% 110,000EXAMPLE 5Ming died on 22 April 2011 leaving an estate valued at £300,000.On 30 April 2009 she had made a gift of £240,000 to her son. This figure is after deducting available exemptions.IHT liabilities are as follows:Lifetime transfer – 30 April 2009£Potentially exempt transfer 240,000• The PET is initially ignored.MARCH 2012Additional liability arising on death – 30 April 2009£Potentially exempt transfer 240,000• The PET utilises £240,000 of the nil rate band of £325,000 for 2011–12.No IHT is payable.Death estate£ Chargeable estate 300,000IHT liability 85,000 at nil%215,000 at 40% 86,000• Only £85,000 (325,000 – 240,000) of the nil rate band is available against the death estate.EXAMPLE 6Joe died on 13 October 2011 leaving an estate valued at £750,000.On 12 November 2008 he had made a gift of £400,000 to a trust. This figure is after deducting available exemptions. The trust paid the IHT arising from the gift.The nil rate band for the tax year 2008–09 is £312,000.Lifetime transfer – 12 November 2008£ Chargeable transfer 400,000IHT liability 312,000 at nil%88,000 at 20% 17,600• The gift to a trust is a CLT. The lifetime IHT liability is calculated using the nil rate band for 2008–09.Additional liability arising on death – 12 November 2008£ Chargeable transfer 400,000IHT liability 325,000 at nil%75,000 at 40% 30,000IHT already paid (17,600)Additional liability 12,400• The additional liability arising on death is calculated using the nil rate band for 2011–12.MARCH 2012Death estate£Chargeable estate 750,000IHT liability 750,000 at 40% 300,000• The CLT made on 12 November 2008 has fully utilised the nil rate bandof £325,000.Taper reliefIt would be somewhat unfair if a donor did not quite live for seven years after making a gift with the result that the gift was fully chargeable to IHT. Therefore taper relief reduces the amount of tax payable where a donor lives for more than three years, but less than seven years, after making a gift. The reduction is as follows:Years before death Percentage reduction %Over three but less than four years 20Over four but less than five years 40Over five but less than six years 60Over six but less than seven years 80Although taper relief reduces the amount of tax payable, it does not reduce the value of a gift for cumulation purposes.The taper relief table will be given in the tax rates and allowances section of the examination paper.EXAMPLE 7Winnie died on 9 January 2012. She had made the following lifetime gifts:2 November 2006 A gift of £460,000 to a trust. The trust paid the IHT arisingfrom this gift.16 August 2008 A gift of £320,000 to her sonThese figures are after deducting available exemptions.The nil rate band for the tax year 2006–07 is £285,000, and for the tax year 2008–09 it is £312,000.MARCH 2012IHT liabilities are as follows:Lifetime transfers £2 November 2006Chargeable transfer 460,000IHT liability 285,000 at nil%175,000 at 20% 35,00016 August 2008Potentially exempt transfer 320,000Additional liabilities arising on death2 November 2006 £Chargeable transfer 460,000IHT liability 325,000 at nil%135,000 at 40% 54,000Taper relief reduction – 60% (32,400)21,600IHT already paid (35,000)Additional liability ______Nil• The taper relief reduction is 60% as the gift to the trust was made between five and six years of the date of Winnie’s death.• Although the final IHT liability of £21,600 is lower than the amount of IHT already paid of £35,000, a refund is never made.16 August 2008£Potentially exempt transfer 320,000IHT liability 320,000 at 40% 128,000Taper relief reduction – 20% (25,600)102,400• The taper relief reduction is 20% as the gift to the son was made between three and four years of the date of Winnie’s death.Transfer of a spouse’s unused nil rate bandAny unused nil rate band on a person’s death can be transferred to their surviving spouse (or registered civil partner). The nil rate band will often not be fully used on the death of the first spouse because any assets left to the surviving spouse are exempt from IHT (see the following section on transfers to spouses).MARCH 2012A claim for the transfer of any unused nil rate band is made by the personal representatives who are looking after the estate of the second spouse to die. The amount that can be claimed is based on the proportion of the nil rate band not used when the first spouse died. Even though the first spouse may have died several years ago when the nil rate band was much lower, the amount that can be claimed on the death of the second spouse is calculated using the current limit of £325,000. EXAMPLE 8Nun died on 29 March 2012.None of her husband’s nil rate band was used when he died on 5 May 2001.When calculating the IHT on Nun’s estate a nil rate band of £650,000 (325,000 + 325,000) can be used, as a claim can be made to transfer 100% of her husband’s nil rate band.EXAMPLE 9Win died on 24 February 2012 leaving an estate valued at £800,000. Only 60% of his wife’s nil rate band was used when she died on 12 May 2002.On 10 May 2009 Win had made a gift of £200,000 to his son. This figure is after deducting available exemptions.The nil rate band for the tax year 2009–10 is £325,000.IHT liabilities are as follows:Lifetime transfer – 10 May 2009£Potentially exempt transfer 200,000Additional liability arising on death – 10 May 2009£Potentially exempt transfer 200,000• No IHT is payable as the transfer is within the nil rate band.Death estate£Chargeable estate 800,000IHT liability 255,000 at nil%545,000 at 40% 218,000MARCH 2012• Win’s personal representatives can claim the wife’s unused nil rate band of £130,000 (325,000 x 40%).• The amount of nil rate band is therefore £455,000 (325,000 + 130,000), of which £200,000 is utilised by the PET made on 10 May 2009.ExemptionsTransfers to spousesGifts to spouses (and registered civil partners) are exempt from IHT. This exemption applies both to lifetime gifts and on death.EXAMPLE 10Sophie died on 25 June 2011.On 12 April 2007 she had made a gift of £400,000 to her husband.Her estate on 25 June 2011 was valued at £900,000. Under the terms of her will Sophie divided her estate equally between her husband and her daughter.The nil rate band for the tax year 2007–08 is £300,000.IHT liabilities are as follows:Lifetime transfers• The gift on 12 April 2007 is exempt as it to Sophie’s husband.Death estate£Value of estate 900,000Spouse exemption (900,000/2) (450,000)Chargeable estate 450,000IHT liability 325,000 at nil%125,000 at 40% 50,000There are a number of other exemptions that only apply to lifetime gifts.Small gifts exemptionGifts up to £250 per person in any one tax year are exempt. If a gift is more than £250 then the small gifts exemption cannot be used, although it is possible to use the exemption any number of times by making gifts to different donees.MARCH 2012EXAMPLE 11During the tax year 2011–12 Peter made the following gifts:On 18 May 2011 he made a gift of £240 to his son.On 5 October 2011 he made a gift of £400 to his daughter.On 20 March 2012 he made a gift of £100 to a friend.The gifts on 18 May 2011 and 20 March 2012 are both exempt as they do not exceed £250. The gift on 5 October 2011 for £400 does not qualify for the small gifts exemption as it is more than £250. It will instead be covered by Peter’s annual exemption for 2011–12 (see the next section).Annual exemptionEach tax year a person has an annual exemption of £3,000. If the whole of the annual exemption is not used in any tax year then the balance is carried forward to the following year. However, the exemption for the current year must be used first, and any unused brought forward exemption cannot be carried forward a second time. Therefore the maximum amount of annual exemptions available in any tax year is £6,000 (£3,000 x 2).EXAMPLE 12Simone made the following gifts:On 10 May 2010 she made a gift of £1,400 to her son.On 25 October 2011 she made a gift of £4,000 to her daughter.The gift on 10 May 2010 utilises £1,400 of Simone’s annual exemption for 2010–11. The balance of £1,600 (3,000 – 1,400) is carried forward to 2011–12.The gift on 25 October 2011 utilises all of the £3,000 annual exemption for 2011–12 and £1,000 (4,000 – 3,000) of the balance brought forward of £1,600. As the annual exemption for 2011–12 must be used first, the unused balance brought forward of £600 (1,600 – 1,000) is lost.The annual exemption is applied on a strict chronological basis, and is therefore given against PETs even where they do not become chargeable.11INHERITANCE TAXMARCH 2012© 2012 ACCA EXAMPLE 13Nigel made the following gifts:On 17 May 2010 he made a gift of £60,000 to his son.On 25 June 2011 he made a gift of £100,000 to a trust.The gift on 17 May 2010 utilises Nigel’s annual exemptions for 2010–11 and 2009–10. The value of the PET is £54,000 (60,000 – 3,000 – 3,000).The gift on 25 June 2011 utilises Nigel’s annual exemption for 2011–12. The value of the CLT is £97,000 (100,000 – 3,000). No lifetime IHT liability is payable as this is within the nil rate band for 2011–12.Normal expenditure out of incomeIHT is not intended to apply to gifts of income. Therefore a gift is exempt if it is made as part of a person’s normal expenditure out of income, provided the gift does not affect that person’s standard of living. To count as normal, gifts must be habitual. Therefore, regular annual gifts of £2,500 made by a person with an annual income of £100,000 would probably be exempt. A one-off gift of £70,000 made by the same person would probably not be, and would instead be a PET or a CLT.Gifts in consideration of marriageThis exemption covers gifts made in consideration of a couple getting married or registering a civil partnership. The amount of exemption depends on the relationship of the donor to the donee (who must be one of the two persons getting married):• £5,000 if the gift if made a by a parent.• £2,500 if the gift is made by a grandparent or by one of the couple getting married to the other.• £1,000 if the gift is made by anyone else.EXAMPLE 14On 19 September 2011 William made a gift of £20,000 to his daughter when she got married. He has not made any other gifts since 6 April 2010.The gift is a PET, but £5,000 will be exempt as a gift in consideration of marriage and William’s annual exemptions for 2011–12 and 2010–11 are also available. The value of the PET is therefore £9,000 (20,000 – 5,000 – 3,000 – 3,000).The second part of the article will cover the more difficult aspects of lifetime transfers, the calculation of the value of a person’s estate, and the payment of inheritance tax.David Harrowven is examiner for Paper F6 (UK)。