CDBQR54;中文规格书,Datasheet资料

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TLV2543CN;TLV2543CDBR;TLV2543CDW;TLV2543IDB;TLV2543IDW;中文规格书,Datasheet资料

Terminal Functions
TERMINAL NAME AIN0 – AIN10 NO. 1 – 9, 11, 12 15 I/O I DESCRIPTION Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing the analog input voltage into a capacitance of 60 pF. Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. Serial data output. This is the 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and the remaining bits are shifted out in order. End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. Ground. This is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. Reference +. The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF – terminal. Reference –. The lower reference voltage value (nominally ground) is applied to REF –. Positive supply voltage.

744230181;中文规格书,Datasheet资料

2.1 2.0 1.02012-07-172012-07-172010-09-30SStSStSBaSStSBaWürth Elektronik eiSos GmbH & Co. KGEMC & Inductive SolutionsMax-Eyth-Str. 174638 WaldenburgGermanyTel. +49 (0) 79 42 945 - 0A Dimensions: [mm]F Typical Impedance Characteristics:H1: Classification Reflow Profile for SMT components:H2: Classification Reflow ProfilesProfile FeaturePreheat- Temperature Min (T smin ) - Temperature Max (T smax ) - Time (t s ) from (T smin to T smax )Ramp-up rate (T L to T P )Liquidous temperature (T L )Time (t L ) maintained above T L Peak package body temperature (T p )Time within 5°C of actual peak temperature (t p )Ramp-down rate (T P to T L )Time 25°C to peak temperature Pb-Free Assembly 150°C 200°C60-180 seconds 3°C/ second max.217°C60-150 seconds See Table H320-30 seconds 6°C/ second max.8 minutes max.refer to IPC/JEDEC J-STD-020DH3: Package Classification Reflow TemperaturePB-Free Assembly PB-Free Assembly PB-Free Assembly Package Thickness< 1.6 mm 1.6 - 2.5 mm ≥ 2.5 mmVolume mm³<350260°C 260°C 250°CVolume mm³350 - 2000260°C 250°C 245°CVolume mm³>2000260°C 245°C 245°Crefer to IPC/JEDEC J-STD-020DH Soldering Specifications:I Cautions and Warnings:The following conditions apply to all goods within the product series of WE-CNSWof Würth Elektronik eiSos GmbH & Co. KG:General:All recommendations according to the general technical specifications of the data sheet have to be complied with.The disposal and operation of the product within ambient conditions which probably alloy or harm the wire isolation has to be avoided.If the product is potted in customer applications, the potting material might shrink during and after hardening. Accordingly to this the product is exposed to the pressure of the potting material with the effect that the core, wire and termination is possibly damaged by this pressure and so the electrical as well as the mechanical characteristics are endanger to be affected. After the potting material is cured, the core, wire and termination of the product have to be checked if any reduced electrical or mechanical functions or destructions have occurred.The responsibility for the applicability of customer specific products and use in a particular customer design is always within the authority of the customer. All technical specifications for standard products do also apply for customer specific products.Cleaning solvents which are used to clean the application might damage or change the characteristics of the component.Direct mechanical impact to the product shall be prevented as the ferrite material of the core could flake or in the worst case it could break. Product specific:Follow all instructions mentioned in the datasheet, especially:•The soldering profile has to be complied with according to the technical reflow soldering specification, otherwise no warranty will be su-stained.•All products are supposed to be used before the end of the period of 12 months based on the transfer of title, if not a 100% solderability can´t be warranted.•Violation of the technical product specifications such as exceeding the nominal rated current will result in the loss of warranty.1. General Customer ResponsibilitySome goods within the product range of Würth Elektronik eiSos GmbH & Co. KG contain statements regarding general suitability for certain application areas. These statements about suitability are based on our knowledge and experience of typical requirements concerning the are-as, serve as general guidance and cannot be estimated as binding statements about the suitability for a customer application. The responsibi-lity for the applicability and use in a particular customer design is always solely within the authority of the customer. Due to this fact it is up to the customer to evaluate, where appropriate to investigate and decide whether the device with the specific product characteristics described in the product specification is valid and suitable for the respective customer application or not.2. Customer Responsibility related to Specific, in particular Safety-Relevant ApplicationsIt has to be clearly pointed out that the possibility of a malfunction of electronic components or failure before the end of the usual lifetime can-not be completely eliminated in the current state of the art, even if the products are operated within the range of the specifications.In certain customer applications requiring a very high level of safety and especially in customer applications in which the malfunction or failure of an electronic component could endanger human life or health it must be ensured by most advanced technological aid of suitable design of the customer application that no injury or damage is caused to third parties in the event of malfunction or failure of an electronic component.3. Best Care and AttentionAny product-specific notes, warnings and cautions must be strictly observed.4. Customer Support for Product SpecificationsSome products within the product range may contain substances which are subject to restrictions in certain jurisdictions in order to serve spe-cific technical requirements. Necessary information is available on request. In this case the field sales engineer or the internal sales person in charge should be contacted who will be happy to support in this matter.5. Product R&DDue to constant product improvement product specifications may change from time to time. As a standard reporting procedure of the Product Change Notification (PCN) according to the JEDEC-Standard inform about minor and major changes. In case of further queries regarding the PCN, the field sales engineer or the internal sales person in charge should be contacted. The basic responsibility of the customer as per Secti-on 1 and 2 remains unaffected.6. Product Life CycleDue to technical progress and economical evaluation we also reserve the right to discontinue production and delivery of products. As a stan-dard reporting procedure of the Product Termination Notification (PTN) according to the JEDEC-Standard we will inform at an early stage about inevitable product discontinuance. According to this we cannot guarantee that all products within our product range will always be available. Therefore it needs to be verified with the field sales engineer or the internal sales person in charge about the current product availability ex-pectancy before or when the product for application design-in disposal is considered.The approach named above does not apply in the case of individual agreements deviating from the foregoing for customer-specific products.7. Property RightsAll the rights for contractual products produced by Würth Elektronik eiSos GmbH & Co. KG on the basis of ideas, development contracts as well as models or templates that are subject to copyright, patent or commercial protection supplied to the customer will remain with Würth Elektronik eiSos GmbH & Co. KG.8. General Terms and ConditionsUnless otherwise agreed in individual contracts, all orders are subject to the current version of the “General Terms and Conditions of Würth Elektronik eiSos Group”, last version available at .J Important Notes:The following conditions apply to all goods within the product range of Würth Elektronik eiSos GmbH & Co. KG:分销商库存信息: WURTH-ELECTRONICS 744230181。

PSD4235G2-70U;PSD4235G2-90U;PSD4235G2-90UI;中文规格书,Datasheet资料

February 2009 Rev 41/129PSD4235G2Flash in-system programmable (ISP)for 16-bit MCUs (5 V supply)Features■Dual bank Flash memories– 4 Mbit of Primary Flash memory (8 uniform sectors, 32K x 16)–256 Kbit Secondary Flash memory with 4 sectors–Concurrent operation: read from onememory while erasing and writing the other ■64 Kbit SRAM■PLD with macrocells–Over 3000 gates of PLD: CPLD and DPLD –CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)–DPLD - user defined internal chip select decoding ■7 L/O ports with 52 I/O pins–52 individually configurable I/O port pins that can be used for the following functions:–MCU I/Os –PLD I/Os–Latched MCU address output –Special function l/Os–l/O ports may be configured as open-drain outputs ■In-system programming (ISP) with JTAG –Built-in JTAG compliant serial port allows full-chip In-System Programmability–Efficient manufacturing allow easy product testing and programmingUse low cost FlashLINK cable with PC■Page register–Internal page register that can be used to expand the microcontroller address space by a factor of 256–Programmable power management ●High endurance–100,000 Erase/write c ycles of Flash memory–1,000 Erase/WRITE Cycles of PLD –15 Y ear Data Retention ■Single supply voltage –5V ±10%■Memory speed–70ns Flash memory and SRAM access time ■Packages are ECOPACK ®Contents PSD4235G2Contents1Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1.1First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1.2Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 121.1.3Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.2In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.2.1Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 131.2.2Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.2.3Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.3PSDsoft™ Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.1Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.2PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.3I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.4MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.5ISP via JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.6In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.7In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.8Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.9Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5PSD register description and address offsets . . . . . . . . . . . . . . . . . . . 266Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1Data-In registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . 286.2Data-out registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . 286.3Direction registers - ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . 286.4Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/129PSD4235G2Contents6.5Drive registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.6Drive registers - Ports C and F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.7Enable-Out registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . 296.8Input macrocells registers- ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . 296.9Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.10Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.11Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.12Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.13JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.14Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.15PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.16PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.17VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.18Memory_ID0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.19Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.1Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.2Primary Flash memory and Secondary Flash memory description . . . . . 367.2.1Memory block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.2.2Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.3Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398.1Power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398.2Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.3Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.4Read Primary Flash identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.5Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 408.6Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 408.7Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 418.8Toggle flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 418.9Error flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428.10Erase timeout flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . 423/129Contents PSD4235G29Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.1Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.2Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449.3Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4510Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.1Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.2Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4810.3Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4811Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.1Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.3Reset (RESET) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5013Memory Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.1Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.2Memory Select configuration for MCUs with separateProgram and Data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.3Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5213.4Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5213.580C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5918Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6118.1Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6218.2Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/129PSD4235G2Contents18.3Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 6418.4The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418.5The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418.6Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6518.7External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6719MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6919.1PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7019.2PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 7119.3Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7119.4MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7219.580C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7319.6MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7419.780C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7519.8H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7619.9MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7719.10C16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7720I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8020.1General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8020.2Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8120.3MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.4PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.5Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.6Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.7Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.8Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.9JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8520.10MCU Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8520.11Port Configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.12Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.13Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.14Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8820.15Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885/129Contents PSD4235G26/12920.16Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.17Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.18Mask macrocell register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.19Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.20Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.21Ports A, B and C - functionality and structure . . . . . . . . . . . . . . . . . . . . . 89 20.22Port D - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 20.23Port E - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 20.24Port F - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 20.25Port G - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9221Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9421.1Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 9521.2Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9521.3Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9621.4PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9621.5PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9721.6Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9721.7Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9822Power-on Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . 9922.1Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9922.2Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9922.3I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 9922.4Reset of Flash Memory Erase and Program cycles . . . . . . . . . . . . . . . . . 9923Programming in-circuit using the JTAG serial interface . . . . . . . . . . 10123.1Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10123.2JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10223.3Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . 102 24Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105PSD4235G2Contents 26DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 27Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 28Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 29Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287/129List of tables PSD4235G2 List of tablesTable 1.Pin names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2.Pin description (for the LQFP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.PLD I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4.JTAG signals on port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5.Methods of programming different functional blocks of the PSD . . . . . . . . . . . . . . . . . . . . 23 Table 6.Register address offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7.Data-In registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8.Data-Out registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9.Direction registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10.Control registers - Ports E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11.Drive registers - Ports A, B, D, E, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12.Drive registers - Ports C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13.Enable-Out registers - Ports A, B, C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14.Input macrocell registers - Port A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15.Output macrocells A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16.Output macrocells B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17.Mask macrocells A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18.Mask macrocells B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19.Flash Memory Protection register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 20.Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 21.JTAG Enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 22.Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 23.PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 24.PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25.VM register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26.Memory_ID0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 27.Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 28.Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 29.Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 30.Status bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 31.Status bits for Motorola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 32.DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 33.Output macrocell Port and Data bit Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 34.MCUs and their control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 35.16-bit data bus with BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 36.16-bit data bus with WRH and WRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 37.16-bit data bus with SIZ0, A0 (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 38.16-bit data bus with LDS, UDS (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 39.Port operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 40.Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 41.I/O port latched address output assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 42.Port Configuration registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 43.Port Pin Direction Control, output Enable P.T. not defined. . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 44.Port Pin Direction Control, output Enable P.T. defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 45.Port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 46.Drive register pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 47.Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 48.Effect of Power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8/129PSD4235G2List of tables Table 49.PSD timing and standby current during Power-down mode. . . . . . . . . . . . . . . . . . . . . . . . 96 Table 50.APD counter operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 51.Status During Power-On Reset, Warm Reset and Power-down mode. . . . . . . . . . . . . . . . 99 Table 52.JTAG port signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 53.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 54.Example of PSD typical power calculation at V CC = 5.0V (with Turbo mode on). . . . . . . 107 Table 55.Example of PSD typical power calculation at V CC = 5.0V (with Turbo mode off). . . . . . . 108 Table 56.Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 57.AC signal letters for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 58.AC signal behavior symbols for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 59.AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 60.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 61.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 62.CPLD Combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 63.CPLD macrocell Synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 64.CPLD macrocell Asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 65.Input macrocell timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 66.Program, WRITE and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 67.READ timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 68.WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 69.Port F Peripheral Data Mode Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 70.Port F Peripheral Data Mode Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 71.Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 72.Power-down timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 73.ISC timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 74.LQFP80 - 80-lead plastic thin, quad, flat package mechanical data. . . . . . . . . . . . . . . . . 124 Table 75.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 76.PSD4235G2 LQFP80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 77.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289/129。

2305;中文规格书,Datasheet资料

Pomona®All dimensions are in inches. Tolerances (except noted): .xx = ±.02” (,51 mm), .xxx = ± .005” (,127 mm).All specifications are to the latest revisions. Specifications are subject to change without notice.Registered trademarks are the property of their respective companies. Made in USA6/9/99Pomona ACCESS 90138 (800) 444-6785 or (425) 446-6010 SY/EH/LS More drawings available at Page 1 of 1 Model 2305 Insulated Low Thermal EMF Spade LugSales: 800-490-2361 Fax: 888-403-3360 Technical Assistance: 800-241-2060 FEATURES:• To ensure accurate low voltage or high resistance precision measurements, Pomona’s durable Model 2305features heavy duty construction with a gold plated tellurium copper base.• The tellurium copper/gold material combination offers superior conductivity and low oxide build-up andminimizes the thermoelectric effect, thus ensuring accurate readings in the nano-volt or 109 ohmic range.• The spade lug attaches to shunt terminals, standard binding posts or ¼” screws. For meter attachment, theModel 2305 is designed with an insulated standard banana jack which will interface to Pomona’s Low EMF Retractable Sheath Banana Plug Cord Model 5291.MATERIALS:Spade Lug Body – Tellurium Copper, Alloy 145, Gold Plated per MIL-G-45204Banana Jack – Tellurium Copper, Alloy 145, Gold Plated per MIL-G-45204Insulation – ABS Molded to Banana Jack and Spade Lug BodyColors: Black and Red, Marking: “Pomona Electronics, Calif.”RATINGS:Operating Temperature: +50°C (+122°F)Operating Voltage – 5000 VDCCurrent: 15 AmperesORDERING INFORMATION: Model 2305Package includes one black, one red spade lug/分销商库存信息: POMONA2305。

2N7002K,215;中文规格书,Datasheet资料

2N7002KTrenchMOS™ logic level FETRev. 01 — 20 October 2003Product dataM3D0881.Product proﬁle1.1DescriptionN-channel enhancement mode ﬁeld-effect transistor in a plastic package using TrenchMOS™ technology.1.2Features1.3Applications1.4Quick reference data2.Pinning informations Logic level compatible s Very fast switchings Subminiature surface mount package s Gate-source ESD protection diodes.s Relay drivers High speed line driver.s V DS ≤60V s I D ≤340mA s P tot ≤0.83Ws R DSon ≤3.9Ω.Table 1:Pinning - SOT23, simpliﬁed outline and symbolPin Description Simpliﬁed outlineSymbol1gate (g)SOT232source (s)3drain (d)MSB003Top view123gds03ab603.Ordering informationTable 2:Ordering informationType number PackageName Description Version2N7002K SOT23Plastic surface mounted package; 3 leads.SOT23 4.Limiting valuesTable 3:Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max Unit V DS drain-source voltage (DC)25°C≤T j≤150°C-60VV DGR drain-gate voltage (DC)25°C≤T j≤150°C; R GS=20kΩ-60VV GS gate-source voltage (DC)-±15VI D drain current (DC)T sp=25°C; V GS=10V;Figure2and3-340mAT sp=100°C; V GS=10V;Figure2-215mA I DM peak drain current T sp=25°C; pulsed; t p≤10µs;Figure3-680mA P tot total power dissipation T sp=25°C;Figure1-0.83W T stg storage temperature−65+150°C T j junction temperature−65+150°C Source-drain diodeI S source (diode forward) current (DC)T sp=25°C-340mA I SM peak source (diode forward) current T sp=25°C; pulsed; t p≤10µs-680mA Electrostatic discharge voltageV esd electrostatic discharge voltage Human Body Model1; C=100pF; R=1.5kΩ-1kVFig 1.Normalized total power dissipation as afunction of solder point temperature.Fig 2.Normalized continuous drain current as afunction of solder point temperature.T sp =25°C; I DM is single pulse; V GS =10VFig 3.Safe operating area; continuous and peak drain currents as a function of drain-source voltage.03aa1704080120050100150200(%)T sp (°C)P der 03aa2504080120050100150200T sp (°C)I der (%)P der P totP tot 25C °()-----------------------100%×=I der I DI D 25C °()-------------------100%×=03an6610-210-11110102V DS (V)I D (A)DC100 ms10 msLimit R DSon = V DS / I D1 mst p = 10 µs100 µs5.Thermal characteristics5.1Transient thermal impedanceTable 4:Thermal characteristicsSymbol ParameterConditionsMin Typ Max Unit R th(j-sp)thermal resistance from junction to solder point Figure 4--150K/W R th(j-a)thermal resistance from junction to ambientminimum footprint;mounted on a printed-circuit board-350-K/WFig 4.Transient thermal impedance from junction to solder point as a function of pulse duration.03aa3911010210310-510-410-310-210-1110t p (s)Z th(j-sp)(K/W)single pulseδ = 0.50.20.10.050.02t pt p TPtTδ =6.CharacteristicsTable 5:CharacteristicsT j=25°C unless otherwise speciﬁed.Symbol Parameter Conditions Min Typ Max Unit Static characteristicsV(BR)DSS drain-source breakdown voltage I D=10µA; V GS=0VT j=25°C6075-VT j=−55°C55--VV(BR)GSS drain-source breakdown voltage I G=±1mA; V DS=0V1622-VV GS(th)gate-source threshold voltage I D=1mA; V DS=V GS;Figure9VT j=25°C12-VT j=150°C0.6--VT j=−55°C-- 3.5VI DSS drain-source leakage current V DS=48V; V GS=0VT j=25°C-0.011µAT j=150°C--10µA I GSS gate-source leakage current V GS=±10V; V DS=0V-50500nA R DSon drain-source on-state resistance V GS=10V; I D=500mA;Figure7and8T j=25°C- 2.8 3.9ΩT j=150°C- 5.27.2ΩV GS=4.5V; I D=200mA;Figure7and8- 3.8 5.3ΩDynamic characteristicsC iss input capacitance V GS=0V; V DS=10V; f=1MHz;Figure11-1340pFC oss output capacitance-830pF C rss reverse transfer capacitance-410pFt on turn-on time V DD=50V; R L=250Ω;V GS=10V;R G=50Ω; R GS=50Ω-310nst off turn-off time-915ns Source-drain diodeV SD source-drain (diode forward) voltage I S=300mA; V GS=0V;Figure12-0.93 1.5Vt rr reverse recovery time I S=300mA; dI S/dt=−100A/µs;V GS=0V; V R=25V -30-nsQ r recovered charge-30-nCT j =25°C T j =25°C and 150°C; V DS >I D x R DSonFig 5.Output characteristics: drain current as afunction of drain-source voltage;typical values.Fig 6.Transfer characteristics: drain current as afunction of gate-source voltage; typical values.T j =25°CFig 7.Drain-source on-state resistance as a functionof drain current; typical values.Fig 8.Normalized drain-source on-state resistance factor as a function of junction temperature.03an7000.10.20.30.40.500.511.52V DS (V)I D (A) 3.5 VT j = 25 °CV GS = 10V4 V4.5 V3 V6 V03an7200.10.20.30.40.50246V GS (V)I D (A)V DS > I D x R DSonT j = 25 °C150 °C03an71024681000.10.20.30.40.5I D (A)R DSon (Ω)V GS = 3.5 VT j = 25 °C4.5 V4 V10 V6 V 03aa2800.61.21.82.4-6060120180a T j (°C)a RDSon R DSon 25C °()----------------------------=I D =1mA; V DS =V GS T j =25°C; V DS =5VFig 9.Gate-source threshold voltage as a function ofjunction temperature.Fig 10.Sub-threshold drain current as a function ofgate-source voltage.V GS =0V; f =1MHzFig 11.Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.03aa3400.61.21.82.4-6060120180T j (°C)V GS(th)(V)typmin03aa3710-610-510-410-310-210-100.61.21.82.4V GS (V)I D (A)typmin03aa4611010210-11 10102V DS (V)C (pF)C issC ossC rssT j =25°C and 150°C; V GS =0V I D =0.5A; V DD =48VFig 12.Source (diode forward) current as a function ofsource-drain (diode forward) voltage; typical values.Fig 13.Gate-source voltage as a function of gatecharge; typical values.03an7300.10.20.30.40.500.30.60.91.2V SD (V)I S (A)T j = 25 °C150 °CV GS = 0 V03ab090510150.30.60.91.2Q G (nC)V GS (V)I D = 0.5AV DD = 48 V T j = 25 °C7.Package outlineFig 14.SOT23.UNIT A 1max.b p c D E e 1H E L p Q w v REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE 97-02-2899-09-13IECJEDEC EIAJmm0.10.480.380.150.093.02.81.41.20.95e 1.92.52.10.550.450.10.2DIMENSIONS (mm are the original dimensions)0.450.15SOT23TO-236ABb pD e 1eAA 1L pQdetail XH EE w M v M ABAB 01 2 mmscaleA 1.10.9cX123Plastic surface mounted package; 3 leadsSOT238.Revision historyTable 6:Revision historyRev Date CPCN Description0120031020Product data (9397 750 11703)分销商库存信息: NXP2N7002K,215。

W25Q128BVEIG;中文规格书,Datasheet资料

Publication Release Date: April 18, 20123V 128M-BITSERIAL FLASH MEMORY WITH DUAL AND QUAD SPITable of Contents1.GENERAL DESCRIPTION (5)2.FEATURES (5)3.PACKAGE TYPES AND PIN CONFIGURATIONS (6)3.1Pad Configuration WSON 8x6-mm (6)3.2Pad Description WSON 8x6-mm (6)3.3Pin Configuration SOIC 300-mil (7)3.4Pin Description SOIC 300-mil (7)3.5Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) (8)3.6Ball Description TFBGA 8x6-mm (8)4.PIN DESCRIPTIONS (9)4.1Chip Select (/CS) (9)4.2Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) (9)4.3Write Protect (/WP) (9)4.4HOLD (/HOLD) (9)4.5Serial Clock (CLK) (9)5.BLOCK DIAGRAM (10)6.FUNCTIONAL DESCRIPTIONS (11)6.1SPI OPERATIONS (11)6.1.1Standard SPI Instructions (11)6.1.2Dual SPI Instructions (11)6.1.3Quad SPI Instructions (11)6.1.4Hold Function (11)6.2WRITE PROTECTION (12)6.2.1Write Protect Features (12)7.STATUS REGISTERS AND INSTRUCTIONS (13)7.1STATUS REGISTERS (13)7.1.1BUSY Status (BUSY) (13)7.1.2Write Enable Latch Status (WEL) (13)7.1.3Block Protect Bits (BP2, BP1, BP0) (13)7.1.4Top/Bottom Block Protect Bit (TB) (13)7.1.5Sector/Block Protect Bit (SEC) (13)7.1.6Complement Protect Bit (CMP) (14)7.1.7Status Register Protect Bits (SRP1, SRP0) (14)7.1.8Erase/Program Suspend Status (SUS) (14)7.1.9Security Register Lock Bits (LB3, LB2, LB1) (14)7.1.10Quad Enable Bit (QE) (15)7.1.11Status Register Memory Protection (CMP = 0) (16)7.1.12 Status Register Memory Protection (CMP = 1) (17)Publication Release Date: April 18, 20127.2 INSTRUCTIONS (18)7.2.1 Manufacturer and Device Identification ................................................................................ 18 7.2.2 Instruction Set Table 1 (Erase, Program Instructions) .......................................................... 19 7.2.3 Instruction Set Table 2 (Read Instructions) .......................................................................... 20 7.2.4 Instruction Set Table 3 (ID, Security Instructions) ................................................................ 21 7.2.5 Write Enable (06h) ............................................................................................................... 22 7.2.6 Write Enable for Volatile Status Register (50h) .................................................................... 22 7.2.7 Write Disable (04h) ............................................................................................................... 23 7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h) ........................................ 24 7.2.9 Write Status Register (01h) .................................................................................................. 24 7.2.10 Read Data (03h) ................................................................................................................. 26 7.2.11 Fast Read (0Bh) ................................................................................................................. 27 7.2.12 Fast Read Dual Output (3Bh) ............................................................................................. 28 7.2.13 Fast Read Quad Output (6Bh) ............................................................................................ 29 7.2.14 Fast Read Dual I/O (BBh) ................................................................................................... 30 7.2.15 Fast Read Quad I/O (EBh) ................................................................................................. 32 7.2.16 Word Read Quad I/O (E7h) ................................................................................................ 34 7.2.17 Octal Word Read Quad I/O (E3h) ....................................................................................... 36 7.2.18 Set Burst with Wrap (77h) .................................................................................................. 38 7.2.19 Continuous Read Mode Bits (M7-0) ................................................................................... 39 7.2.20 Continuous Read Mode Reset (FFh or FFFFh) .................................................................. 39 7.2.21 Page Program (02h) ........................................................................................................... 40 7.2.22 Quad Input Page Program (32h) ........................................................................................ 41 7.2.23 Sector Erase (20h) ............................................................................................................. 42 7.2.24 32KB Block Erase (52h) ..................................................................................................... 43 7.2.25 64KB Block Erase (D8h) ..................................................................................................... 44 7.2.26 Chip Erase (C7h / 60h) ....................................................................................................... 45 7.2.27 Erase / Program Suspend (75h) ......................................................................................... 46 7.2.28 Erase / Program Resume (7Ah) ......................................................................................... 47 7.2.29 Power-down (B9h) .............................................................................................................. 48 7.2.30 Release Power-down / Device ID (ABh) ............................................................................. 49 7.2.31 Read Manufacturer / Device ID (90h) ................................................................................. 51 7.2.32 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 52 7.2.33 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 53 7.2.34 Read Unique ID Number (4Bh)........................................................................................... 54 7.2.35 Read JEDEC ID (9Fh) ........................................................................................................ 55 7.2.36 Read SFDP Register (5Ah) ................................................................................................ 56 7.2.37 Erase Security Registers (44h) ........................................................................................... 57 7.2.38 Program Security Registers (42h) ...................................................................................... 58 7.2.39 Read Security Registers (48h) . (59)8.ELECTRICAL CHARACTERISTICS (60)8.1Absolute Maximum Ratings (60)8.2Operating Ranges (60)8.3Power-up Timing and Write Inhibit Threshold (61)8.4DC Electrical Characteristics (62)8.5AC Measurement Conditions (63)8.6AC Electrical Characteristics (64)8.7AC Electrical Characteristics (cont’d) (65)8.8Serial Output Timing (66)8.9Serial Input Timing (66)8.10HOLD Timing (66)8.11WP Timing (66)9.PACKAGE SPECIFICATION (67)9.18-Pad WSON 8x6-mm (Package Code E) (67)9.216-Pin SOIC 300-mil (Package Code F) (68)9.324-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) (69)9.424-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array) (70)10.ORDERING INFORMATION (71)10.1Valid Part Numbers and Top Side Marking (72)11.REVISION HISTORY (73)Publication Release Date: April 18, 20121. GENERAL DESCRIPTIONThe W25Q128BV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down.The W25Q128BV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128BV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.)The W25Q128BV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual Output and 280MHz (70MHz x 4) for Quad SPI when using the Fast Read Quad SPI instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation.A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number.2. FEATURES• Family of SpiFlash Memories – W25Q128BV: 128M-bit/16M-byte – 256-byte per programmable page– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold– Dual SPI: CLK, /CS, IO 0, IO 1, /WP, /Hold– Quad SPI: CLK, /CS, IO 0, IO 1, IO 2, IO 3• Highest Performance Serial Flash– 104/70MHz Dual Output/Quad SPI clocks– 208/280MHz equivalent Dual /Quad SPI– 35MB/S continuous data transfer rate– Up to 5X that of ordinary Serial Flash– More than 100,000 erase/program cycles (1)– More than 20-year data retention• Efficient “Continuous Read Mode” – Low Instruction overhead– Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash • Low Power, Wide Temperature Range– Single 2.7 to 3.6V supply– 4mA active current, <1µA Power-down current – -40°C to +85/105°C operating range • Flexible Architecture with 4KB sectors– Uniform Sector/Block Erase (4K/32K/64K-Byte)– Program one to 256 bytes– Erase/Program Suspend & Resume• Advanced Security Features – Software and Hardware Write-Protect – Top/Bottom, 4KB complement array protection – Lock-Down and OTP array protection – 64-Bit Unique Serial Number for each device – Discoverable Parameters (SFDP) Register – 3X256-Byte Security Registers with OTP locks– Volatile & Non-volatile Status Register Bits• Space Efficient Packaging – 8-pad WSON 8x6-mm – 16-pin SOIC 300-mil – 24-ball TFBGA 8x6-mm– Contact Winbond for KGD and other options Note 1. More than 100k Block Erase/Program cycles for Industrial and Automotive temperature; more than 10k fullchip Erase/Program cycles tested in compliance with AEC-Q100.3.PACKAGE TYPES AND PIN CONFIGURATIONSW25Q128BV is offered in an 8-pad WSON 8x6-mm (package code E), a 16-pin SOIC 300-mil (package code F) and two 24-ball 8x6-mm TFBGAs (package code B, C) as shown in Figure 1a-c respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.3.1Pad Configuration WSON 8x6-mmFigure 1a. W25Q128BV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E)3.2Pad Description WSON 8x6-mmPAD NO. PAD NAME I/O FUNCTION1 /CS I Chip Select Input2 DO (IO1) I/O Data Output (Data Input Output 1)*1(IO2)I/O Write Protect Input ( Data Input Output 2)*23 /WP4 GND Ground5 DI (IO0) I/O Data Input (Data Input Output 0)*16 CLK I Serial Clock Input(IO3)I/O Hold Input (Data Input Output 3)*27 /HOLD8 VCC PowerSupply*1: IO0 and IO1 are used for Standard and Dual SPI instructions*2: IO0 – IO3 are used for Quad SPI instructionsPublication Release Date: April 18, 20123.3 Pin Configuration SOIC 300-milFigure 1b. W25Q128BV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)3.4 Pin Description SOIC 300-milPIN NO.PIN NAMEI/OFUNCTION1 /HOLD (IO3)I/OHold Input (Data Input Output 3)*22 VCC Power Supply3 N/C No Connect4 N/C No Connect5 N/C No Connect6 N/C No Connect7 /CS I Chip Select Input8DO (IO1)I/O Data Output (Data Input Output 1)*19 /WP (IO2)I/OWrite Protect Input (Data Input Output 2)*210 GND Ground 11 N/C No Connect 12 N/C No Connect 13 N/C No Connect 14 N/C No Connect 15 DI (IO0) I/O Data Input (Data Input Output 0)*116CLKISerial Clock Input*1: IO0 and IO1 are used for Standard and Dual SPI instructions.*2: IO0 – IO3 are used for Quad SPI instructions, /WP or /HOLD functions are only available for Standard/Dual SPI.3.5Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)Figure 1c. W25Q128BV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B, C)3.6Ball Description TFBGA 8x6-mmBALL NO. PIN NAME I/O FUNCTIONB2 CLK I Serial Clock InputB3 GND GroundSupplyB4 VCC PowerC2 /CS I Chip Select Input(IO2)I/O Write Protect Input (Data Input Output 2)*2C4 /WPD2 DO (IO1) I/O Data Output (Data Input Output 1)*1D3 DI (IO0) I/O Data Input (Data Input Output 0)*1(IO3)I/O Hold Input (Data Input Output 3)*2D4 /HOLDMultiple NC NoConnect*1: IO0 and IO1 are used for Standard and Dual SPI instructions.*2: IO0 – IO3 are used for Quad SPI instructions, /WP or /HOLD functions are only available for Standard/Dual SPI.Publication Release Date: April 18, 20124. PIN DESCRIPTIONS4.1 Chip Select (/CS)The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up (see “Write Protection” and Figure 38). If needed a pull-up resister on /CS can be used to accomplish this.4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)The W25Q128BV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK.Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.4.3 Write Protect (/WP)The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin configuration of Quad I/O operation.4.4 HOLD (/HOLD)The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.4.5 Serial Clock (CLK)The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations")5.BLOCK DIAGRAM ArrayFigure 2. W25Q128BV Serial Flash Memory Block Diagram分销商库存信息: WINBONDW25Q128BVEIG。

3342-54;3342-56;3342-07;中文规格书,Datasheet资料

Document No. 70-0091-04 │ ©2005-8 Peregrine Semiconductor Corp. All rights reserved.(UTSi®) CMOS process, offering excellent RF performance with the economy and integration of conventional CMOS.Figure 1. Block DiagramPD_U PD_DLDCextPE3342 Product SpecificationProduct SpecificationPE3342Document No. 70-0091-04 │ ©2005-8 Peregrine Semiconductor Corp. All rights reserved.Table 4. Operating RangesTable 3. Absolute Maximum RatingsSymbol Parameter/Conditions Min Max UnitsV DD Supply voltage –0.3 +4.0 V V I Voltage on any digital input–0.3 V DD +0.3 V T StgStorage temperature range–65+85°CSymbol Parameter/Conditions MinMax UnitsV DD Supply voltage 2.85 3.15 V T A Operatingambient temperature range-40 85 °CSymbol Parameter/Conditions Min Max UnitsV ESD ESD voltage human body model (Note 1)1000 V V ESD(V PP )ESD voltage human body model (Note 1)200VNote 1: Periodically sampled, not 100% tested. Tested per MIL-STD-883, M3015 C2Table 5. ESD RatingsElectrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. Latch-Up AvoidanceUnlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up.Exceeding absolute maximum ratings may cause permanent damage. Operation should berestricted to the limits in the Operating Ranges table. Operation between operating rangemaximum and absolute maximum for extended periods may reduce reliability.PE3342 Product SpecificationProduct SpecificationPE3342Document No. 70-0091-04 │©2005-8 Peregrine Semiconductor Corp. All rights reserved.Table 7. AC CharacteristicsV DD = 3.0 V, -40° C < T A < 85° C, unless otherwise specifiedSymbol ParameterConditions Min Max UnitsControl Interface and Registers (see Figure 4)f Clk Serial data clock frequency (Note 1)10MHz t ClkH Serial clock HIGH time 30 ns t ClkL Serial clock LOW time30 ns t DSU Data set-up time to Clock rising edge 10 ns t DHLD Data hold time after Clock rising edge 10 ns t PW S_WR pulse width30 ns t CWR Clock rising edge to S_WR rising edge 30 ns t CE Clock falling edge to E_WR transition 30 ns t WRC S_WR falling edge to Clock rising edge 30 ns t EC E_WR transition to Clock rising edge30nsEEPROM Erase/Write Programming (see Figures 5 & 6)t EESU EELoad rising edge to V PP rising edge 500 ns t EEPW V PP pulse width25 30 ms t VPPV PP pulse rise and fall times(Note 2) 1 µsMain Divider (Including Prescaler)F In Operating frequency300 2700 MHz F In Operating frequency Speed-grade option (Note 3) 300 3000 MHz P FInInput level rangeExternal AC coupling-55dBmMain Divider (Prescaler Bypassed)F In Operating frequency (Note 4)50 270 MHz P FInInput level rangeExternal AC coupling (Note 4)-55dBmReference Dividerf r Operating frequency(Note 5)100MHz P fr Reference input power (Note 4)Single ended input-2dBmPhase Detectorf cComparison frequency(Note 6)20MHzSSB Phase Noise (F in = 1.3 GHz, f r = 10 MHz, f c = 1.25 MHz, LBW = 70 kHz, V DD = 3.0 V, Temp = -40° C )100 Hz Offset -75 dBc/Hz1 kHz Offset-85dBc/HzNote 1: f Clk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify f Clkspecification.Note 2: Rise and fall times of the V PP programming voltage pulse must be greater than 1 µs.Note 3: The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14,Ordering Information, for ordering details.Note 4: CMOS logic levels can be used to drive F In input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimumof 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum frequency limit exists when operated in this mode.Note 5: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimumphase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.Note 6: Parameter is guaranteed through characterization only and is not tested.PE3342 Product SpecificationProduct SpecificationPE3342Document No. 70-0091-04 │ ©2005-8 Peregrine Semiconductor Corp. All rights reserved.Lock Detect OutputA lock detect signal is provided at pin LD, via the pin C EXT (see Figure 1). C EXT is the logical “NAND” of PD_U and PD_D waveforms, driven through a series 2k ohm resistor. When the loop is locked, this output will be HIGH with narrow pulses LOW. Connecting C EXT to an external shunt capacitor provides integration of this signal.The C EXT signal is sent to the LD pin through an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D .Serial Data PortThe Serial Data Port allows control data to beentered into the device. This data can be directed into one of three registers: the Enhancementregister, the Primary register, and the EE register. Table 7 defines the control line settings required to select one of these destinations.Input data presented on pin 5 (Data) is clocked serially into the designated register on the rising edge of Clock. Data is always loaded LSB (B 0) first into the receiving register. Figure 4 defines the timing requirements for this process .Table 8. Serial InterfaceS_WR E_WR EELoadRegister Loaded0 0 0 Primary Register 0 1 0 Enhancement Register 0X1EE RegisterFigure 4. Serial Interface Timing DiagramE_WREELoadDataClockS_WRPE3342 Product SpecificationProduct SpecificationPE3342Document No. 70-0091-04 │ ©2005-8 Peregrine Semiconductor Corp. All rights reserved.Enhancement RegisterThe Enhancement Register is a buffered serial shift register, loaded from the Serial Data Port. It activates special test and operating modes in the PLL. The bit assignments for these modes are shown in Table 11.The functions of these Enhancement Register bits are shown in Table 12. A function becomes active when its corresponding bit is set HIGH. Note that bits 1, 2, 5, and 6 direct various data to the Dout pin, and for valid operation no more than one should be set HIGH simultaneously .The Enhancement Register is buffered to prevent inadvertent control changes during serial loading. Data that has been loaded into the register is cap-tured in the buffer and made available to the PLL on the falling edge of E_WR.A separate control line is provided to enable and disable the Enhancement mode. Functions are enabled by taking the ENH control line LOW. Note: The enhancement register bit values are unknown during power up. To avoid enabling the enhancement mode during power up, set the Enh pin high (“1”) until the enhancement register bit values are programmed to a known state.Table 12. Enhancement Register Bit AssignmentsReservedEE Register Outputf p outputPower downCounter loadMSEL outputf c outputReservedB 0B 1B 2B 3B 4B 5B 6B 7Table 13. Enhancement Register FunctionsBit FunctionDescriptionBit 0 Reserved Program to 0Bit 1 EE Register OutputAllows the contents of the EE Register to be serially shifted out Dout, LSB (B 0) first. Data is shifted on rising edge of Clock. Bit 2 f p output Provides the M counter output at Dout.Bit 3 Power down Powers down all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming.Bit 5 MSEL output Provides the internal dual modulus prescaler modulus select (MSEL) at Dout. Bit 6 f c output Provides the R counter output at Dout. Bit 7ReservedProgram to 0PE3342 Product Specification分销商库存信息:PSC3342-543342-563342-07。

ADE7878ACPZ;ADE7854ACPZ;ADE7854ACPZ-RL;ADE7858ACPZ-RL;ADE7868ACPZ-RL;中文规格书,Datasheet资料

Polyphase Multifunction Energy Metering ICADE7854/ADE7858/ADE7868/ADE7878 Rev. EInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.FEATURESHighly accurate; supports EN 50470-1, EN 50470-3,IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards Compatible with 3-phase, 3- or 4-wire (delta or wye), and other 3-phase servicesSupplies total (fundamental and harmonic) active, reactive (ADE7878, ADE7868, and ADE7858 only), and apparent energy, and fundamental active/reactive energy (ADE7878 only) on each phase and on the overall systemLess than 0.1% error in active and reactive energy over a dynamic range of 1000 to 1 at T A = 25°CLess than 0.2% error in active and reactive energy over a dynamic range of 3000 to 1 at T A = 25°CSupports current transformer and di/dt current sensors Dedicated ADC channel for neutral current input (ADE7868 and ADE7878 only)Less than 0.1% error in voltage and current rms over a dynamic range of 1000 to 1 at T A = 25°CSupplies sampled waveform data on all three phases and on neutral currentSelectable no load threshold levels for total and fundamental active and reactive powers, as well as for apparent powersLow power battery mode monitors phase currents for antitampering detection (ADE7868 and ADE7878 only) Battery supply input for missing neutral operationPhase angle measurements in both current and voltage channels with a typical 0.3° errorWide-supply voltage operation: 2.4 V to 3.7 VReference: 1.2 V (drift 10 ppm/°C typical) with external overdrive capabilitySingle 3.3 V supply40-lead lead frame chip scale package (LFCSP), Pb-free Operating temperature: −40°C to +85°CFlexible I2C, SPI, and HSDC serial interfaces APPLICATIONSEnergy metering systemsGENERAL DESCRIPTIONThe ADE7854/ADE7858/ADE7868/ADE7878 are high accuracy, 3-phase electrical energy measurement ICs with serial interfaces and three flexible pulse outputs. The ADE78xx devices incorporate second-order sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), a digital integrator, reference circuitry, and all of the signal processing required to perform total (fundamental and harmonic) active, reactive (ADE7878, ADE7868, and ADE7858), and apparent energy measurement and rms calcu-lations, as well as fundamental-only active and reactive energy measurement (ADE7878) and rms calculations. A fixed function digital signal processor (DSP) executes this signal processing. The DSP program is stored in the internal ROM memory. The ADE7854/ADE7858/ADE7868/ADE7878 are suitable for measuring active, reactive, and apparent energy in various 3-phase configurations, such as wye or delta services, with both three and four wires. The ADE78xx devices provide system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, CF2, and CF3 logic outputs provide a wide choice of power information: total active, reactive, and apparent powers, or the sum of the current rms values, and fundamental active and reactive powers.The ADE7854/ADE7858/ADE7868/ADE7878 contain wave-form sample registers that allow access to all ADC outputs. The devices also incorporate power quality measurements, such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement, and angles between phase voltages and currents. Two serial interfaces, SPI and I2C, can be used to communicate with the ADE78xx. A dedicated high speed interface, the high speed data capture (HSDC) port, can be used in conjunction with I2C to provide access to the ADC outputs and real-time power information. The ADE7854/ADE7858/ADE7868/ADE7878 also have two interrupt request pins, IRQ0 and IRQ1, to indicate that an enabled interrupt event has occurred. For the ADE7868/ADE7878, three specially designed low power modes ensure the continuity of energy accumulation when the ADE7868/ADE7878 is in a tam-pering situation. See for a quick reference chart listing each part and its functions. The ADE78xx are available in the 40-lead LFCSP, Pb-free package.Table 1Table 1. Part ComparisonPart No. WATT VARIRMS,VRMS,andVA di/dtFundamentalWATT andVARTamperDetectand LowPowerModes ADE7878 Yes Yes Yes Yes Yes Yes ADE7868 Yes Yes Yes Yes No Yes ADE7858 Yes Yes Yes Yes No No ADE7854 Yes No Yes Yes No NoADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 2 of 96TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Revision History...............................................................................3 Functional Block Diagrams.............................................................4 Specifications.....................................................................................8 Timing Characteristics..............................................................11 Absolute Maximum Ratings..........................................................14 Thermal Resistance....................................................................14 ESD Caution................................................................................14 Pin Configuration and Function Descriptions...........................15 Typical Performance Characteristics...........................................17 Test Circuit......................................................................................19 Terminology....................................................................................20 Power Management........................................................................21 PSM0—Normal Power Mode (All Parts)................................21 PSM1—Reduced Power Mode (ADE7868, ADE7878 Only)21 PSM2—Low Power Mode (ADE7868, ADE7878 Only).......21 PSM3—Sleep Mode (All Parts)................................................22 Power-Up Procedure..................................................................24 Hardware Reset...........................................................................25 Software Reset Functionality....................................................25 Theory of Operation......................................................................26 Analog Inputs..............................................................................26 Analog-to-Digital Conversion..................................................26 Current Channel ADC...............................................................27 di/dt Current Sensor and Digital Integrator..............................29 Voltage Channel ADC...............................................................30 Changing Phase Voltage Datapath...........................................31 Power Quality Measurements...................................................32 Phase Compensation.................................................................37 Reference Circuit........................................................................39 Digital Signal Processor.............................................................39 Root Mean Square Measurement.............................................40 Active Power Calculation..........................................................44 Reactive Power Calculation—ADE7858, ADE7868, ADE7878 Only..............................................................................................49 Apparent Power Calculation.....................................................54 Waveform Sampling Mode.......................................................57 Energy-to-Frequency Conversion............................................57 No Load Condition....................................................................61 Checksum Register.....................................................................63 Interrupts.....................................................................................64 Serial Interfaces..........................................................................65 ADE7878 Evaluation Board......................................................72 Die Version..................................................................................72 Silicon Anomaly.............................................................................73 ADE7854/ADE7858/ADE7868/ADE7878 FunctionalityIssues............................................................................................73 Functionality Issues....................................................................73 Section 1. ADE7854/ADE7858/ADE7868/ADE7878Functionality Issues....................................................................74 Registers List...................................................................................75 Outline Dimensions.......................................................................93 Ordering Guide.. (93)ADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 3 of 96REVISION HISTORY4/11—Rev. D to Rev. EChanges to Input Clock FrequencyParameter, Table 2..............10 Changes to Current RMS Offset Compensation Section..........42 Changes to Voltage RMS Offset Compensation Section...........44 Changes to Note 2, Table 30...........................................................77 Changes to Address 0xE707, Table 33..........................................80 Changes to Table 45........................................................................87 Changes to Table 46........................................................................88 Changes to Bit Location 7:3, Default Value, Table 54.. (92)2/11—Rev. C to Rev. DChanges to Figure 1...........................................................................4 Changes to Figure 2...........................................................................5 Changes to Figure 3...........................................................................6 Changes to Figure 4...........................................................................7 Changes to Table 2............................................................................8 Changed SCLK Edge to HSCLK Edge, Table 5...........................13 Change to Current Channel HPF Section...................................28 Change to di/dt Current Sensor and Digital IntegratorSection..............................................................................................30 Changes to Digital Signal Processor Section...............................39 Changes to Figure 59......................................................................44 Changes to Figure 62......................................................................47 Changes to Figure 65......................................................................49 Changes to Figure 66......................................................................52 Changes to Line Cycle Reactive Energy Accumulation Mode Section and to Figure 67.................................................................53 No Load Detection Based On Total Active, Reactive Powers Section..............................................................................................61 Change to Equation 50...................................................................63 Changes to the HSDC Interface Section......................................70 Changes to Figure 87 and Figure 88.............................................71 Changes to Figure 89......................................................................72 Changes to Table 30 (77)11/10—Rev. B to Rev. CChange to Signal-to-Noise-and-Distortion Ratio, SINADParameter, Table 1.............................................................................9 Changes to Figure 18......................................................................18 Changes to Figure 22......................................................................19 Changes to Silicon Anomaly Section............................................72 Added Table 28 to Silicon Anomaly Section, RenumberedTables Sequentially..........................................................................73 8/10—Rev. A to Rev. BChanges to Figure 1..........................................................................4 Changes to Figure 2..........................................................................5 Changes to Figure 3..........................................................................6 Changes to Figure 4..........................................................................7 Change to Table 8............................................................................16 Changes to Power-Up Procedure Section....................................23 Changes to Equation 6 and Equation 7........................................33 Changes to Equation 17.................................................................43 Changes to Active Power Offset Calibration Section.................45 Changes to Figure 63......................................................................46 Changes to Reactive Power Offset Calibration Section.............49 Changes to Figure 82......................................................................65 Added Silicon Anomaly Section, Renumbered TablesSequentially (71)3/10—Rev. 0 to Rev. AAdded ADE7854, ADE7858, and ADE7878..................Universal Reorganized Layout...........................................................Universal Added Table 1, Renumbered Sequentially.....................................1 Added Figure 1, Renumbered Sequentially...................................3 Added Figure 2..................................................................................4 Added Figure 3..................................................................................5 Changes to Specifications Section..................................................7 Changes to Figure 9........................................................................14 Changes to Table 8..........................................................................14 Changes to Typical Performance Characteristics Section.........16 Changes to Figure 22......................................................................18 Changes to the Power Management Section...............................20 Changes to the Theory of Operation Section..............................25 Changes to Figure 31 and Figure 32.............................................27 Change to Equation 28...................................................................47 Changes to Figure 83......................................................................66 Changes to Figure 86......................................................................68 Changes to the Registers List Section...........................................72 Changes to Ordering Guide.. (91)2/10—Revision 0: Initial VersionADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 4 of 96FUNCTIONAL BLOCK DIAGRAMSR E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DA08510-204Figure 1. ADE7854 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 5 of 96R E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DA08510-203Figure 2. ADE7858 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 6 of 96R E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DAI N I N 08510-202Figure 3. ADE7868 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 7 of 96R E S E TR E F C L K I C L K O U I A I A V A I B I B V B I C I C V C V S C L K/S C LS D AH S DAI N I N 08510-201Figure 4. ADE7878 Functional Block DiagramADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 8 of 96SPECIFICATIONSVDD = 3.3 V ± 10%, AGND = DGND = 0 V , on-chip reference, CLKIN = 16.384 MHz, T MIN to T MAX = −40°C to +85°C. Table 2.Parameter 1, 2 Min Typ Max Unit Test Conditions/Comments ACCURACYActive Energy MeasurementActive Energy Measurement Error (per Phase)Total Active Power0.1%Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onFundamental Active Power (ADE7878 Only) 0.1% Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off 0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onPhase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on Power Factor (PF) = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60° AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx =±100 mV rmsOutput Frequency Variation 0.01 % DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation 0.01 %Total Active Energy MeasurementBandwidth2 kHz REACTIVE ENERGY MEASUREMENT(ADE7858, ADE7868, AND ADE7878)Reactive Energy Measurement Error(per Phase)Total Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;integrator off0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onFundamental Active Power (ADE7878 Only) 0.1% Over a dynamic range of 1000 to 1, PGA = 1, 2, 4; integrator off 0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4;integrator off0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16;integrator onPhase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on PF = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60° AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx =±100 mV rmsOutput Frequency Variation 0.01 %ADE7854/ADE7858/ADE7868/ADE7878Rev. E | Page 9 of 96Parameter 1, 2Min Typ Max Unit Test Conditions/Comments DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation0.01% Total Reactive Energy Measurement Bandwidth2kHzRMS MEASUREMENTSI rms and V rms Measurement Bandwidth2 kHz I rms and V rms Measurement Error (PSM0 Mode)0.1 % Over a dynamic range of 1000 to 1, PGA = 1 MEAN ABSOLUTE VALUE (MAV)MEASUREMENT (ADE7868 AND ADE7878)I mav Measurement Bandwidth (PSM1 Mode)260 Hz I mav Measurement Error (PSM1 Mode) 0.5 % Over a dynamic range of 100 to 1, PGA = 1, 2, 4, 8 ANALOG INPUTSMaximum Signal Levels±500mV peakDifferential inputs between the following pins: IAP and IAN, IBP and IBN, ICP and ICN; single-ended inputs between the following pins: VAP and VN, VBP and VN, VCP and VN Input Impedance (DC)IAP , IAN, IBP , IBN, ICP , ICN, VAP , VBP , and VCP Pins 400 kΩVN Pin130 kΩADC Offset Error±2 mV PGA = 1, uncalibrated error, see the Terminology sectionGain Error±4 % External 1.2 V referenceWAVEFORM SAMPLINGSampling CLKIN/2048, 16.384 MHz/2048 = 8 kSPS Current and Voltage Channels See the Waveform Sampling Mode section Signal-to-Noise Ratio, SNR70 dB PGA = 1 Signal-to-Noise-and-Distortion Ratio, SINAD60 dB PGA = 1Bandwidth (−3 dB)2 kHz TIME INTERVAL BETWEEN PHASESMeasurement Error0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on CF1, CF2, CF3 PULSE OUTPUTSMaximum Output Frequency 8 kHz WTHR = VARTHR = VATHR = PMAX = 33,516,139 Duty Cycle50%If CF1, CF2, or CF3 frequency > 6.25 Hz and CFDEN is even and > 1(1 + 1/CFDEN) × 50% If CF1, CF2, or CF3 frequency > 6.25 Hz andCFDEN is odd and > 1Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz andnominal phase currents are larger than 10% of full scaleREFERENCE INPUT REF IN/OUT Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8% Input Capacitance 10 pF ON-CHIP REFERENCE Nominal 1.207 V at the REF IN/OUT pin at T A = 25°C PSM0 and PSM1 Modes Reference Error ±2 mV Output Impedance 1.2 kΩ Temperature Coefficient 10 50 ppm/°C Maximum value across full temperature rangeof −40°C to +85°CADE7854/ADE7858/ADE7868/ADE78781 See the Typical Performance Characteristics section.2 See the Terminology section for a definition of the parameters.Rev. E | Page 10 of 96分销商库存信息:ANALOG-DEVICESADE7878ACPZ ADE7854ACPZ ADE7854ACPZ-RL ADE7858ACPZ-RL ADE7868ACPZ-RL ADE7878ACPZ-RL ADE7858ACPZ ADE7868ACPZ EVAL-ADE7878EBZ。

CS5460A-BSZ;CS5460A-BSZR;CDB5460AU;中文规格书,Datasheet资料

VD+ High Pass Filter 4 th Order Modulator Digital Filter Power Calculation Engine (Energy I*V I RMS ,V RMS ) Digital Filter High Pass Filter Power Monitor System Clock /K Clock Generator Watch Dog Timer MODE CS Control / Serial Interface SDI SDO SCLK INT
CS5460A
TABLE OF CONTENTS
1. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 5 ANALOG CHARACTERISTICS ................................................................................................ 5 VREFOUT REFERENCE OUTPUT VOLTAGE........................................................................ 7 5V DIGITAL CHARACTERISTICS............................................................................................ 7 3.3 V DIGITAL CHARACTERISTICS................

744314490;中文规格书,Datasheet资料

Bezeichnung :description :Marking = part numberEigenschaften /properties Lerrlaufinduktivität/initial inductance Nenn-Induktivität /33% Umgebungstemperatur / temperature:+20°CWE-Superflux ME08-01-01ME 07-01-01NameDatum / dateArbeitstemperatur / operating temperature: -40°C - +150°C Metra HIT 27I für/for R DCFreigabe erteilt / general release:Kunde / customerF Werkstoffe & Zulassungen / material & approvals :Würth Elektronik..................................................................................G Eigenschaften / general specifications :not exceed 150°C under worst case operating conditions.It is recommended that the temperature of the part does coating:blackHP 34401 A & Fluke 54II für/for I DC; Luftfeuchtigkeit / humidity:WAYNE KERR 3260B für/for L 0; I SAT Elektrische Eigenschaften / electrical properties :Umgebungstemp. / ambient temperature: -40°C - +100°C Basismaterial / base material:Draht / wire: AIEIW-200 D Prüfgeräte / test equipment :http://www.we-online.deDatum / date..................................................................................Unterschrift / signatureKontrolliert / approvedWürth Elektronik eiSos GmbH & Co. KGD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Geprüft / checked .................................................................................................POWER-CHOKE WE-HCIE Testbedingungen / test conditions :Änderung / modificationVersion 1Version 2Bezeichnung :description :H Induktivitätskurve / Inductance curve :ME08-01-01ME 07-01-01NameDatum / dateD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400http://www.we-online.deGeprüft / checked Kontrolliert / approvedÄnderung / modificationWürth Elektronik eiSos GmbH & Co. KGVersion 2..............................................................................................................................................Version 1Datum / dateUnterschrift / signature Würth Elektronik....................................................................................................................................................................Freigabe erteilt / general release:Kunde / customerPOWER-CHOKE WE-HCIDATUM / DATE : 2008-01-01Bezeichnung :description :I Temperaturanstieg / Temperature rise curve :ME08-01-01ME 07-01-01NameDatum / dateWürth ElektronikVersion 2..........................................................................................................................................Freigabe erteilt / general release:Kunde / customerDatum / dateUnterschrift / signature...............................................................................................................................................................Version 1D-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400http://www.we-online.deGeprüft / checked Kontrolliert / approvedÄnderung / modificationWürth Elektronik eiSos GmbH & Co. KGBezeichnung :description :a 330,0± 2,0mmb 21,0± 0,8mmc 13,00± 0,5mmd 100,0± 1,5mmME08-01-01ME 07-01-01NameDatum / dateD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Geprüft / checked Kontrolliert / approvedÄnderung / modificationWürth Elektronik eiSos GmbH & Co. KGVersion 2................................................................................................................................................Version 1Datum / dateUnterschrift / signature Würth Elektronik....................................................................................................................................................................Freigabe erteilt / general release:Kunde / customerRollenspezifikation / Reel specification:SPEICHERDROSSEL WE-HCI POWER-CHOKE WE-HCIThe Force for tearing off cover tape is 20 to 70 grams in arrow direction150°feeding directionThis electronic component has been designed and developed for usage in general electronic equipment. Before incorporating this component into any equipment where higher safety and reliability is especially required or if there is the possibility of direct damage or injury to human body, for example in the range of aerospace, aviation, nuclear control, submarine, transportation, (automotive control, train control, ship control), transportation signal, disaster prevention, medical, public information network etc, Würth Elektronik eiSos GmbH must be informed before the design-in stage. In addition, sufficient reliability evaluation checks for safety must be performed on every electronic component which is used in electrical circuits that require high safety and reliability functions or performance.分销商库存信息: WURTH-ELECTRONICS 744314490。

BAT54;BAT54_D87Z;BAT54A;BAT54C;BAT54S;中文规格书,Datasheet资料

intended to be an exhaustive list of all such trademarks.
2Cool¥ AccuPower¥ AX-CAP¥* BitSiC¥ Build it Now¥ CorePLUS¥ CorePOWER¥ CROSSVOLT¥ CTL¥ Current Transfer Logic¥ DEUXPEED® Dual Cool™ EcoSPARK® EfficientMax¥ ESBC¥
®*
The Power Franchise®
TinyBoost¥ TinyBuck¥ TinyCalc¥ TinyLogic® TINYOPTO¥ TinyPower¥ TinyPWM¥ TinyWire¥ TranSiC¥ TriFault Detect¥ TRUECURRENT®* PSerDes¥
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
UHC® Ultra FRFET¥ UniFET¥ VCX¥ VisualMax¥ VoltagePlus¥ XS™
FPS¥ ®
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

CDB5581;中文规格书,Datasheet资料

Copyright Cirrus Logic, Inc. 2009(All Rights Reserved)CDB5581200 kSps, 16-bit, High-throughput ΔΣ ADCEvaluation BoardFeatures❑ Analog Input Channel to the CS5581 ADC❑Pre-configured to require a minimum number of externalconnections to your data acquisition system.❑All functionality accessible through the connector interfaceand board-level options.❑On-board 4.096V Reference❑Pre-configured for Master mode SPI™ communication to adata capture system.General DescriptionThe CDB5581 is a versatile tool designed for evaluating the func-tionality and performance of the CS5581 ADC (Analog-to-Digital Converter). The SPI serial port on the CDB5581 evaluation board is configured in Master mode and will start transmitting data after power-up upon reset. This evaluation board is designed to connect to your data capture system or will interface to the CapturePlus II data acquisition system available from Cirrus Logic.The CS5581 delta-sigma ADC produces fully settled conversions to full specified accuracy at 200kSps. This ability to produce fully set-tled conversions for every sample makes it suitable for converting multiplexed input signals. To help evaluate this feature, the CDB5581includes two single-ended analog inputs multiplexed into the CS5581. The multiplexer can be switched at the CS5581 ADC sam-ple speed and the ADC will produce fully settled conversion data for each input channel.All evaluation board functionality for evaluating the CS5581 ADC is accessed through the connector interface and board-level options.Schematics in PADS™ PowerLogic™ format are available for download at:/en/products/pro/detail/P1120.html .ORDERING INFORMATIONCDB5581 Evaluation BoardOCT ‘09DS796DB3/CDB55812DS796DB3TABLE OF CONTENTS1. INTRODUCTION (3)1.1 Overview ............................................................................................................................42. QUICK START ..........................................................................................................................53. HARDWARE DESCRIPTION (6)3.1 Absolute Maximum Ratings ...............................................................................................63.2 Power Supply .....................................................................................................................63.3 Analog Section . (6)3.3.1 Analog Input Buffers ..............................................................................................63.3.2 Multiplexer .............................................................................................................73.3.3 ADC Reset ............................................................................................................73.3.4 Voltage Reference ................................................................................................73.3.5 ADC Reference Frequency ...................................................................................73.4 Digital Section .. (8)3.4.1 Hardware Configuration ........................................................................................83.4.2 SPI™ Serial Port Communications .. (8)APPENDIX A. MAXIMIZING THE PERFORMANCE OF THE CS5581 (9)A.1 PCB Layout Considerations.............................................................................................. 9A.2 Hardware Considerations.................................................................................................. 9APPENDIX B. BILL OF MATERIALS ........................................................................................ 10APPENDIX C. SCHEMATICS ..................................................................................................... 11APPENDIX D. LAYER PLOTS ................................................................................................... 16APPENDIX E. CALIBRATION FUNCTION................................................................................. 25APPENDIX E. REVISION HISTORY (26)LIST OF FIGURESFigure 1. CDB5581 Block Diagram.................................................................................................4Figure 2. CDB5581 Board Layout...................................................................................................5Figure 3. Schematic - Block Diagram............................................................................................11Figure 4. Schematic - Power Supplies..........................................................................................12Figure 5. Schematic - Input Buffers and Multiplexer .....................................................................13Figure 6. Schematic - CS5581......................................................................................................14Figure 7. Schematic - Configuration & Misc..................................................................................15Figure 8. Top Silkscreen ...............................................................................................................16Figure 9. Top Solder Mask............................................................................................................17Figure 10. Top Routing..................................................................................................................18Figure 11. Ground Plane...............................................................................................................19Figure 12. Power Plane.................................................................................................................20Figure 13. Bottom Solder Mask.....................................................................................................21Figure 14. Bottom Silkscreen........................................................................................................22Figure 15. Top Solder Paste Mask................................................................................................23Figure 16. Bottom Routing (24)LIST OF TABLESTable 1. Power Supply Connections...............................................................................................6Table 2. Analog Input Connections.................................................................................................6Table 3. Analog Input Channel Selection........................................................................................7Table 4. Hardware Configuration Signals........................................................................................8Table 5. Serial Interface Connections (8)/CDB5581DS796DB331.INTRODUCTIONThe CDB5581 evaluation board is a platform for evaluating the CS5581 ADC performance. The evalua-tion board is designed to connect to the SPI serial port of a processor or data capture system or will inter-face directly to the CapturePlus II data acquisition system available from Cirrus Logic. The CapturePlus II data acquisition system is a powerful integrated hardware/software tool designed to fully exercise the CDB5581 and other Cirrus Logic evaluation boards.The CDB5581 evaluation board is designed to simplify the hardware setup required to evaluate the CS5581. Interfacing the CDB5581 evaluation board to a user-supplied data capture system can be as sim-ple as connecting the SPI port and using the CDB5581 default hardware configuration. In this configura-tion, simply press the Reset switch on the CDB5581 and it will automatically begin transmitting data to the data capture system.All evaluation board functionality for evaluating the CS5581 ADC is accessed through the connector in-terface and board-level options.The CS5581 delta-sigma ADC produces fully settled conversions to full specified accuracy at 200kSps.The ability to produce fully settled conversions for every sample makes it suitable for converting multi-plexed input signals. To help evaluate this feature, the CDB5581 includes two single-ended analog inputs multiplexed into the CS5581 The multiplexer can be switched at the CS5581 ADC sample speed and the ADC will produce fully settled conversion data for each input channel.For detailed information on the CS5581 ADC, please reference data sheet DS796 at ./CDB55814DS796DB31.1OverviewThe CDB5581 evaluation board has both analog and digital circuit sections. The analog section consists of the CS5581 ADC, two analog input signal buffers, controlled through a multiplexer, that condition the signal into the ADC, and a precision 4.096V reference. The digital section consists of board operation configuration control signals, reset circuitry, an SPI™ serial port, a jumper connection for initiating ADC calibration, and an EEPROM for evaluation board identification.The evaluation board operates from +2.5V, -2.5V, +3.3V and communicates through an SPI™ serial port.Figure 1 illustrates the CDB5581 block diagram.Figure 1. CDB5581 Block Diagram/CDB5581DS796DB352.QUICK STARTThe CDB5581 evaluation board is designed to interface with a data acquisition system. To connect and configure the CDB5581 perform the following initialization procedure:1.Verify that the power supplies are off.2.Connect the power supplies to the CDB5581 as shown in Table 1 on page 6.3.Verify that the power is off to the analog input signal & control signal sources.4.Connect the analog input signal source to the evaluation board per Table 2 on page 6. Verify from Table 4on page 8 that the analog input channel selected is IN_A.5.Configure the CDB5581 by connecting the control signal sources to the evaluation board as shown inTable 3 on page 7. Apply logic-level inputs as required to override the resistor pull-ups/pull-downs. 6.Make connections to the SPI™ serial port connector as shown in Table 5 on page 8. The CS5581 ADCserial port is configured by default to operate in the SSC (Synchronous Self Clocking) mode. Refer to the CS5581 data sheet for more information on serial communication modes and signal timing.7.Turn on the power supplies to the evaluation board.8.Apply power to the signal source.9.Press the Reset switch on the evaluation board.10.The CS5581 ADC's SPI™ serial port should now be communicating data.Figure 2. CDB5581 Board Layout/CDB55816DS796DB33.HARDWARE DESCRIPTION 3.1Absolute Maximum RatingsObserve the following limits to ensure the CDB5581 component ratings are not exceeded.•CS5581–The absolute maximum supply voltage that can be applied to the +3.3V power supply connection is +3.6V.–The absolute maximum power supply voltage that can be applied between pins VL and V1- is 6.1V.•CS3004–The absolute maximum power supply voltage that can be applied between the +2.5V and -2.5V power supply connections is +5.5V.3.2Power SupplyPower supply connections and requirements are specified in Table 1. below.Important: It is recommended that all power supplies be isolated from utility ground to prevent the intro-duction of a ground loop. One ground connection may already exist through the serial port connection to utility ground. Using the Cirrus Logic CapturePlus II system simplifies making connections to the CDB5581 by providing electrical isolation between the two.Using twisted/shielded wire will reduce electrical noise induced onto the power supply cables.Power supplies are to be adequately regulated and sufficiently low noise to meet the application require-ments.3.3Analog Section 3.3.1Analog Input BuffersThe analog input signal connections to the input buffers are made at the IN_A and IN_B connectors, as specified in Table 2.There are two analog input channels on the evaluation board. Each analog input channel consists of a low-noise amplifier configured as a unity gain non-inverting buffer. The buffers utilize a Cirrus Logic CS3004 precision, low-noise, low-voltage, dual opamp.. These op-amps enable both the inputs and out-puts of the analog input buffer to operate virtually rail to rail. The channel input impedance is 50 Ohms.Table 1. Power Supply ConnectionsPower Supply RequirementPower Supply ConnectionAssociated Ground ReturnAssociated Test Points +2.5V DC, ±5%, <50mA E5E3TP2, TP1 (GND)-2.5V DC, ±5%, <50mA E9E7TP4, TP3 (GND)+3.3V DC, ±5%, <50mAE16E13TP6, TP5 (GND)Table 2. Analog Input ConnectionsChannel Analog Input ConnectionInput Signal Voltage Range Impedance IN_A J10-2.048V to +2.048V 50 Ohms IN_BJ11-2.048V to +2.048V50 Ohms/CDB5581DS796DB37The analog inputs are designed for connections to single-ended input signals referenced to ground. The usable input voltage range is -2.048V to +2.048V. The theoretical input frequency range of the CS5581is from DC to the Nyquist frequency of 100kHz. The analog input buffer amplifiers are configured for a cutoff frequency of 16.8kHz to band-limit noise into the ADC. Changing the cutoff frequency will change the noise bandwidth accordingly.3.3.2MultiplexerAnalog input channel selection is controlled through the multiplexer. The multiplexer is configured with a pull-down resistor on the MUX control line to enable input channel labeled "INPUT A" by default. To select channel B, apply 3.3V to the multiplexer input control line (MUX).Signal levels for controlling the multiplexer that selects between analog input channels A and B is shown in Table 3.During multiplexing, the maximum sample rate for each channel is half that of the ADC’s maximum sam-ple rate. Additionally, the Nyquist frequency for each channel is half of the ADC’s Nyquist frequency.3.3.3ADC ResetThe CS5581 ADC makes use of an externally generated power-on reset. Therefore, after power is ap-plied to the ADC, the reset pin must be driven low then released. Pressing the Reset button generates a reset cycle. A reset cycle can be generated at any time during ADC operation. The ADC RST pin (active low) is held inactive through a pull-up resistor.3.3.4Voltage ReferenceThe voltage reference IC provided generates a 4.096V precision reference.3.3.5ADC Reference FrequencyThe reference frequency for the CS5581 ADC is provided by a 16.000MHz oscillator.Table 3. Analog Input Channel SelectionMultiplexerControl Input (MUX)Input Channel Enabled0V A 3.3VB/CDB55818DS796DB33.4Digital Section3.4.1Hardware ConfigurationThe CDB5581 evaluation board hardware comes pre-configured so the only connection required between it and a data acquisition system is the serial port connection.The hardware setup is reconfigurable through the hardware control interface connectors. Configure the evaluation board by setting the appropriate control line to the appropriate logic level.3.4.2SPI™ Serial Port CommunicationsThe CS5581 ADC communications port features an SPI™ serial port. It can be configured for SSC mode (Master) or SEC mode (Slave) mode as shown in Table 4. Test points are provided to monitor serial com-munications.Connections to the serial interface are made according to the following table.Table 4. Hardware Configuration SignalsFunction Default Level Label Connector Test Point Input Channel Select =Selected (Low)MUX J6, Pin 16J3, Pin 2Analog Input Buffers Buffers =Enabled (High)BUFEN J1J3, Pin1Serial Port Mode Sync.Self Clock =Enabled (High)SMODE J6, Pin 12J3, Pin 3Data Ready FlagData Ready When Set (Low)RDY J8, Pin 10J3, Pin 4ResetReset =Inactive (High)RST J6, Pin 6; S1J3, Pin 6Bipolar /Unipolar Mode Bipolar =Enabled (High)BP /UP J6, Pin 2J3, Pin 8Serial Port Communication Chip Select =Enabled (Low)CS J8, Pin 2E23Data Conversion ModeContinuous Conversion =Active (Low)CONVJ8, Pin 12E21Table 5. Serial Interface ConnectionsFunction Label Connector Test Point Chip Select CS J8, Pin 2E23Serial Data Input SDI J8, Pin 4E24Serial Data Output SDO J8, Pin 6E25Serial ClockSCLKJ8, Pin 8E26/CDB5581DS796DB39APPENDIX A. MAXIMIZING THE PERFORMANCE OF THE CS5581A.1PCB Layout Considerations•Keep the signal path short between the CS5581 ADC input capacitors C37, C44 and the ADC input pin to minimize trace inductance.•The analog input buffer amplifiers and ADC input buffer capacitors are placed before the multi-plexer. Placing the buffer amplifiers before the multiplexer allows the amplifiers driving the ADC buffer capacitors to be fully settled when sampled by the ADC. Therefore, the multiplexer must be of a low on-resistance type to prevent distortion or latency issues.•Power supply noise is a major design consideration and the power supplies need adequate bypassing and bulk capacitance.•When operating the ADC from +2.5V and -2.5V split supplies, place the power supply & buffer amplifier bypass capacitor ground connections close together.•Keep all ground connections on each differential buffer amplifier as close to the device as pos-sible to avoid introducing differential noise through high-impedance connections.•Keep trace lengths short between the ADC and the voltage reference IC negative supply pins.•Route the oscillator output away from analog circuitry.•Use a solid ground plane in the PCB layout.•Provide adequate separation between analog and digital signals.•To minimize distortion within the analog signal path, consider using components with smaller voltage dependencies.•Minimize ADC digital output edge transition current loading.A.2Hardware ConsiderationsAt a system level, use shielded cable for interconnects. Keep interconnect cable lengths as short as pos-sible. Route analog and digital signals connecting to the PCB away from each other./CDB558110DS796DB3APPENDIX B. BILL OF MATERIALS/分销商库存信息: CIRRUS-LOGIC CDB5581。

CS5368-CQZ;CS5368-CQZR;CS5368-DQZ;中文规格书,Datasheet资料

to 5 V Logic Supplies for Control and Serial Ports
High-Pass Filter for DC Offset Calibration
Overflow Detection
Footprint Compatible with the 4-Channel CS5364 and 6-Channel CS5366
RECOMMENDED OPERATING CONDITIONS ................................................................................. 10 ABSOLUTE RATINGS ....................................................................................................................... 10 SYSTEM CLOCKING ......................................................................................................................... 10 DC POWER ........................................................................................................................................ 11 LOGIC LEVELS ................................................................................................................................. 11 PSRR, VQ AND FILT+ CHARACTERISTICS .................................................................................... 11 ANALOG CHARACTERISTICS (COMMERCIAL) .............................................................................. 12 ANALOG CHARACTERISTICS (AUTOMOTIVE) ............................................................................... 13 DIGITAL FILTER CHARACTERISTICS ............................................................................................. 14 OVERFLOW TIMEOUT ...................................................................................................................... 14 SERIAL AUDIO INTERFACE - I²S/LJ TIMING ................................................................................... 15 SERIAL AUDIO INTERFACE - TDM TIMING ..................................................................................... 16 SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING ................................................... 17 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING .................................................. 18 4. APPLICATIONS ................................................................................................................................... 19 4.1 Power ............................................................................................................................................. 19 4.2 Control Port Mode and Stand-Alone Operation .............................................................................. 19

CS5530-ISZ;CS5530-ISZR;CDB5530U;中文规格书,Datasheet资料

Copyright Cirrus Logic, Inc. 2009CS553024-bit ADC with Ultra-low-noise AmplifierFeatures & Description❑Chopper-stabilized Instrumentation Amplifier, 64X• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)• 1200pA Input Current❑Digital Gain Scaling up to 40x❑Delta-sigma Analog-to-digital Converter • Linearity Error: 0.0015% FS• Noise Free Resolution: Up to 19 bits❑Scalable V REF Input: Up to Analog Supply ❑Simple Three-wire Serial Interface• SPI™ and Microwire™ Compatible• Schmitt-trigger on Serial Clock (SCLK)❑Onboard Offset and Gain Calibration Registers❑Selectable Word Rates: 6.25 to 3,840 Sps ❑Selectable 50 or 60 Hz Rejection❑Power Supply Configurations• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V• VA+ = +3 V; VA- = -3 V; VD+ = +3 V General DescriptionThe CS5530 is a highly integrated ΔΣ Analog-to-Digital Converter (ADC) which uses charge-balance techniques to achieve 24-bit performance. The ADC is optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications.To accommodate these applications, the ADC includes a very-low-noise, chopper-stabilized instrumentation amplifier (12nV/√Hz@0.1Hz) with a gain of 64X. This device also includes a fourth-order ΔΣ modulator fol-lowed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK=4.9152MHz).To ease communication between the ADC and a micro-controller, the converter includes a simple three-wire se-rial interface which is SPI and Microwire compatible with a Schmitt-trigger input on the serial clock (SCLK).High dynamic range, programmable output rates, and flexible power supply options make this device an ideal solution for weigh scale and process control applications.ORDERING INFORMATIONSee page35.VA+C1C2VREF+VREF-VD+DIFFERENTIAL 4TH ORDER ΔΣMODULATOR PROGRAMMABLE SINC FIR FILTERAIN1+AIN1-SERIALINTERFACELATCHCLOCKGENERATOR CALIBRATIONSRAM/CONTROLLOGICDGNDCSSDISDOSCLKOSC2OSC1A1A0VA-64XNOV ‘09TABLE OF CONTENTS 1.CHARACTERISTICS AND SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)TYPICAL NOISE-FREE RESOLUTION (BITS) (6)5 V DIGITAL CHARACTERISTICS (7)3 V DIGITAL CHARACTERISTICS (7)DYNAMIC CHARACTERISTICS (8)ABSOLUTE MAXIMUM RATINGS (8)SWITCHING CHARACTERISTICS (9)2.GENERAL DESCRIPTION (11)2.1.Analog Input (11)2.1.1. Analog Input Span (12)2.1.2. Voltage Noise Density Performance (12)2.1.3. No Offset DAC (12)2.2.Overview of ADC Register Structure and Operating Modes (12)2.2.1. System Initialization (12)2.2.2. Command Register Descriptions (14)2.2.3. Serial Port Interface (16)2.2.4. Reading/Writing On-Chip Registers (17)2.3.Configuration Register (17)2.3.1. Power Consumption (17)2.3.2. System Reset Sequence (17)2.3.3. Input Short (17)2.3.4. Voltage Reference Select (17)2.3.5. Output Latch Pins (18)2.3.6. Filter Rate Select (18)2.3.7. Word Rate Select (18)2.3.8. Unipolar/Bipolar Select (18)2.3.9. Open Circuit Detect (18)2.3.10. Configuration Register Description (19)2.4.Calibration (21)2.4.1. Calibration Registers (21)2.4.2. Gain Register (21)2.4.3. Offset Register (21)2.4.4. Performing Calibrations (22)2.4.5. System Calibration (22)2.4.6. Calibration Tips (22)2.4.7. Limitations in Calibration Range (23)2.5.Performing Conversions (23)2.5.1. Single Conversion Mode (23)2.5.2. Continuous Conversion Mode (24)ing Multiple ADCs Synchronously (25)2.7.Conversion Output Coding (25)2.7.1. Conversion Data Output Descriptions (26)2.8.Digital Filter (27)2.9.Clock Generator (28)2.10.Power Supply Arrangements (28)2.11.Getting Started (31)2.12.PCB Layout (31)3.PIN DESCRIPTIONS (32)Clock Generator (32)Control Pins and Serial Data I/O (32)Measurement and Reference Inputs (33)Power Supply Connections (33)4.SPECIFICATION DEFINITIONS (33)5.PACKAGE DRAWINGS (34)6.ORDERING INFORMATION (35)7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION (35)LIST OF FIGURES Figure 1. SDI Write Timing (Not to Scale) (10)Figure 2. SDO Read Timing (Not to Scale) (10)Figure 3. Front End Configuration (11)Figure 4. Input Model for AIN+ and AIN- Pins (11)Figure 5. Measured Voltage Noise Density (12)Figure 5. Measured Voltage Noise Density (12)Figure 6. CS5530 Register Diagram (13)Figure 7. Command and Data Word Timing (16)Figure 8. Input Reference Model when VRS = 1 (18)Figure 9. Input Reference Model when VRS = 0 (18)Figure 10. System Calibration of Offset (22)Figure 11. System Calibration of Gain (22)Figure 12. Synchronizing Multiple ADCs (25)Figure 13. Digital Filter Response (Word Rate = 60 Sps) (27)Figure 14. 120 Sps Filter Magnitude Plot to 120 Hz (27)Figure 15. 120 Sps Filter Phase Plot to 120 Hz (27)Figure 16. Z-Transforms of Digital Filters (27)Figure 17. On-chip Oscillator Model (28)Figure 18. CS5530 Configured with a Single +5 V Supply (29)Figure 19. CS5530 Configured with ±2.5 V Analog Supplies (29)Figure 20. CS5530 Configured with ±3 V Analog Supplies (30)LIST OF TABLES Table 1. Conversion Timing for Single Mode (24)Table 2. Conversion Timing for Continuous Mode (24)Table 3. Output Coding (25)1. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARCTERISTICS(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode)(See Notes 1 and 2.)Notes: 1.Applies after system calibration at any temperature within -40 °C to +85 °C.2.Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.3.This specification applies to the device only and does not include any effects by external parasiticthermocouples.4.Drift over specified temperature range after calibration at power-up at 25 °C.ParameterCS5530-CSUnit Min Typ Max Accuracy Linearity Error -±0.0015±0.003%FS No Missing Codes 24--Bits Bipolar Offset -±16±32LSB 24Unipolar Offset -±32±64LSB 24Offset Drift(Notes 3 and 4)-10-nV/°C Bipolar full-scale Error -±8±31ppm Unipolar full-scale Error -±16±62ppm full-scale Drift(Note 4)-2-ppm/°CANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)Notes: 5.See the section of the data sheet which discusses input models.6.Input current on VREF+ or VREF- may increase to 250nA if operated within 50mV of VA+ or VA-. Thisis due to the rough charge buffer being saturated under these conditions.ParameterMin TypMaxUnitAnalog InputCommon Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode (VA-) + 1.6-(VA+) - 1.6VCVF Current on AIN+ or AIN--1200-pAInput Current Noise -1-pA/√HzOpen Circuit Detect Current 100300-nACommon Mode Rejection DC 50, 60 Hz --130120--dBdBInput Capacitance -10-pF Voltage Reference Input Range (VREF+) - (VREF-)1 2.5(VA+)-(VA-)V CVF Current (Note 5, 6)-50-nA Common Mode Rejection DC 50, 60 Hz --120120--dB dB Input Capacitance 11-22pF System Calibration Specifications Full-scale Calibration Range Bipolar/Unipolar Mode 3-110%FS Offset Calibration Range Bipolar Mode -100-100%FS Offset Calibration Range Unipolar Mode -90-90%FSANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)7.All outputs unloaded. All input CMOS levels.8.Tested with 100 mV change on VA+ or VA-.TYPICAL NOISE-FREE RESOLUTION (BITS) (See Notes 9 and 10)9.Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The Noise Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the Noise Free Resolution accordingly.10.“Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on theRMS noise value, while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.ParameterCS5530-CSMinTypMaxUnitPower SuppliesDC Power Supply Currents (Normal Mode)I A+, I A-I D+- - 60.681.0mA mA Power ConsumptionNormal Mode (Note 7)Standby Sleep---35550045--mW mW µW Power Supply Rejection (Note 8)DC Positive Supplies DC Negative Supply--115115--dB dBOutput Word Rate (Sps)-3 dB Filter Frequency (Hz)Noise-free BitsNoise (nV rms )7.5 1.94191715 3.881924307.7518346015.51848120311768240621611548012216163960230152291,920390153443,8407801313905 V DIGITAL CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VA-, DGND =0 V; See Notes 2 and 11.)3 V DIGITAL CHARACTERISTICS(T A = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND =0V; See Notes 2 and 11.)11.All measurements performed under static conditions.ParameterSymbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45--VD+VD+V Low-Level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-Level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-Level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45-VD+VD+V Low-Level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-Level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-Level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICS12.The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc 5 filterfollowed by a Sinc 3 filter for the other OWRs. OWR sinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc 5 filter.13.The single conversion mode only outputs fully settled conversions. See Table 1 for more details aboutsingle conversion mode timing. OWR SC is used here to designate the different conversion time associated with single conversions.14.The continuous conversion mode outputs every conversion. This means that the filter’s settling timewith a full-scale step input in the continuous conversion mode is dictated by the OWR.ABSOLUTE MAXIMUM RATINGS(DGND = 0 V; See Note 15.)Notes:15.All voltages with respect to ground.16.VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.17.VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.18.Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.19.Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.20.Total power dissipation, including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Ratef s MCLK/16Sps Filter Settling Time to 1/2 LSB (full-scale Step Input)Single Conversion mode (Notes 12, 13, and 14)Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Spst s t s t s1/OWR SC5/OWR sinc5 + 3/OWR5/OWRs s sParameterSymbol Min Typ Max Unit DC Power Supplies(Notes 16 and 17)Positive Digital Positive Analog Negative Analog VD+VA+VA--0.3-0.3+0.3---+6.0+6.0-3.75V V V Input Current, Any Pin Except Supplies (Notes 18 and 19)I IN --±10mA Output Current I OUT--±25mA Power Dissipation (Note 20)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA (VA-) -0.3(VA-) -0.3--(VA+) + 0.3(VA+) + 0.3V V Digital Input VoltageV IND -0.3-(VD+) + 0.3V Ambient Operating Temperature T A -40-85°C Storage Temperature T stg-65-150°CSWITCHING CHARACTERISTICS(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF; See Figures 1 and 2.)Notes:21.Device parameters are specified with a 4.9152 MHz clock.22.Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.23.Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.ParameterSymbol Min Typ MaxUnitMaster Clock Frequency (Note 21)External Clock or Crystal OscillatorMCLK1 4.91525MHz Master Clock Duty Cycle 40-60%Rise Times(Note 22)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 22)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL = 4.9152 MHz(Note 23)t ost-20-ms Serial Port Timing Serial Clock Frequency SCLK 0-2MHz Serial Clock Pulse Width High Pulse Width Lowt 1t 2250250----ns nsSDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disable t 6100--nsSDO Read Timing CS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150nsFigure 1. SDI Write Timing (Not to Scale)Figure 2. SDO Read Timing (Not to Scale)分销商库存信息:CIRRUS-LOGICCS5530-ISZ CS5530-ISZR CDB5530U。

BAT54CV,115;中文规格书,Datasheet资料

1. Product profile1.1General descriptionTwo planar Schottky barrier double diodes with common cathodes and an integratedguard ring for stress protection encapsulated in a SOT666 ultra small and flat lead Surface-Mounted Device (SMD) plastic package.1.2Features and benefitsLow forward voltage Low capacitance AEC-Q101 qualifiedUltra small and flat lead SMD plastic packageExcellent coplanarity and improved thermal behavior1.3ApplicationsUltra high-speed switching Voltage clamping Line terminationReverse polarity protection1.4Quick reference data[1]Pulse test: t p ≤300μs; δ≤0.02.BAT54CVTwo Schottky barrier double diodesRev. 3 — 15 November 2010Product data sheetTable 1.Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per diode I F forward current --200mA V R reverse voltage --30V V Fforward voltage[1]I F =0.1mA --240mV I F =1mA --320mV I F =10mA --400mV I F =30mA --500mV I F =100mA--800mV2. Pinning information3. Ordering information4. Marking5. Limiting valuesTable 2.PinningPin Description Simplified outlineGraphic symbol1anode (diode 1)2anode (diode 2)3common cathode (diode 3,4)4anode (diode 3)5anode (diode 4)6common cathode (diode 1,2)123456sym057Table 3.Ordering informationType number Package NameDescriptionVersion BAT54CV-plastic surface-mounted package; 6leadsSOT666Table 4.Marking codesType numberMarking code BAT54CVC5Table 5.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max Unit Per diode V R reverse voltage -30V I F forward current -200mA I FRM repetitive peak forward current t p ≤10ms; δ≤0.5-0.85A I FSMnon-repetitive peak forward currentsquare wave; t p =8.3ms[1]-2A[1]T j =25°C prior to surge.[2]Reflow soldering is the only recommended soldering method.[3]Device mounted on an FR4Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.[4]Device mounted on an FR4PCB, single-sided copper, tin-plated, mounting pad for cathode 1cm 2.6. Thermal characteristics[1]For Schottky barrier diodes thermal runaway has to be considered, as in some applications the reverse power losses P R are a significant part of the total power losses.[2]Reflow soldering is the only recommended soldering method.[3]Device mounted on an FR4PCB, single-sided copper, tin-plated and standard footprint.[4]Device mounted on an FR4PCB, single-sided copper, tin-plated, mounting pad for cathode 1cm 2.[5]Soldering point of cathode tab.Per device, one diode loadedP tottotal power dissipationT amb ≤25°C[2][3]-350mW [4]-420mW T j junction temperature -125°C T amb ambient temperature −65+125°C T stgstorage temperature−65+150°CTable 5.Limiting values …continuedIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol ParameterConditions Min Max UnitTable 6.Thermal characteristics Symbol ParameterConditionsMin Typ Max UnitPer device, one diode loadedR th(j-a)thermal resistance from junction to ambientin free air[1][2][3]--360K/W [4]--300K/W R th(j-sp)thermal resistance from junction to solder point[5]--175K/W7. CharacteristicsTable 7.CharacteristicsT amb=25°C unless otherwise specified.Symbol Parameter Conditions Min Typ Max UnitPer diodeV F forward voltage[1]I F=0.1mA--240mVI F=1mA--320mVI F=10mA--400mVI F=30mA--500mVI F=100mA--800mVI R reverse current V R=25V--2μAC d diode capacitance V R=1V; f=1MHz--10pF[1]Pulse test: t p≤300μs; δ≤0.02.8. Test information8.1Quality informationThis product has been qualified in accordance with the Automotive Electronics Council(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and issuitable for use in automotive applications.9. Package outline10. Packing informationTable 8.Packing methodsThe indicated -xxx are the last three digits of the 12NC ordering code.[1]Type number Package Description Packing quantity4000BAT54CV SOT666 4 mm pitch, 8 mm tape and reel-115[1]For further information and the availability of packing methods, see Section14.11. Soldering12. Revision historyTable 9.Revision historyDocument ID Release date Data sheet status Change notice Supersedes BAT54CV v.320101115Product data sheet-BAT54CV_2 Modifications:•Section 1.2 “Features and benefits”: amended.•Table 1 “Quick reference data”: updated.•Table 5 “Limiting values”: P tot amended.•Table 6 “Thermal characteristics”: R th(j-a) amended, R th(j-sp) added.•Figure4: superseded by minimized outline drawing.•Section 8 “Test information”: added.•Section 11 “Soldering”: added.•Section 13 “Legal information”: updated.BAT54CV_220100115Objective data sheet-BAT54CV_1 BAT54CV_120040922Objective data sheet--13. Legal information13.1 Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL .13.2 DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.13.3 DisclaimersLimited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third partycustomer(s). NXP does not accept any liability in this respect.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.Document status[1][2]Product status[3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.Product [short] data sheet Production This document contains the product specification.Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.13.4 TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.14. Contact informationFor more information, please visit: For sales office addresses, please send an email to: salesaddresses@15. Contents1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 General description . . . . . . . . . . . . . . . . . . . . . 11.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 11.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 12 Pinning information. . . . . . . . . . . . . . . . . . . . . . 23 Ordering information. . . . . . . . . . . . . . . . . . . . . 24 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal characteristics . . . . . . . . . . . . . . . . . . 37 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 48 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 58.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 59 Package outline. . . . . . . . . . . . . . . . . . . . . . . . . 510 Packing information . . . . . . . . . . . . . . . . . . . . . 611 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 713 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 813.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 813.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 813.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 Contact information. . . . . . . . . . . . . . . . . . . . . . 915 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© NXP B.V.2010.All rights reserved.For more information, please visit: For sales office addresses, please send an email to: salesaddresses@分销商库存信息: NXPBAT54CV,115。

CDBQR0130R-HF;中文规格书,Datasheet资料

CDBQR0130R-HFA mA V V 11003035I OV R V RRM I FSM 8.3ms single half sine-wave superimposed on rate load(JEDEC method)OC OC+125+125-40T STG T jStorage temperature Junction temperatureAverage forward current Reverse voltageRepetitive peak reverse voltage Forward current,surge peak ParameterConditionsSymbol Min Typ Max UnitOMaximum Rating (at T A =25C unless otherwise noted)OElectrical Characteristics (at T A =25C unless otherwise noted)mW125P D Power Dissipation uAV 0.50.45I RV F Reverse currentForward voltage ParameterConditionsSymbol Min Typ Max UnitV R = 10 VI F = 10 mA Features-Low reverse current.-Designed for mounting on small surface. -Extremely thin / leadless package. -Majority carrier conduction.Mechanical data-Case: 0402/SOD-923F standard package, molded plastic.-Terminals: Gold plated, solderable per MIL-STD-750,method 2026. -Marking code: cathode band & BQ -Mounting position: Any. -Weight: 0.001 gram(approx.).I o = 100 mA V R = 30 VoltsRoHS Device Halogen FreeRATING AND CHARACTERISTIC CURVES (CDBQR0130R-HF)C a p a c i t a n c e b e t w e e n t e r m i n a l s (P F )Reverse voltage (V)R e v e r s e c u r r e n t ( A )Reverse voltage (V)1u 1n10u 100n10202530Fig. 2 - Reverse characteristics20406080100255075100125OAmbient temperature (C)A v e r a g e f o r w a r d c u r r e n t (%)Fig.4 - Current derating curveFig. 3 - Capacitance between terminals characteristics1m 015102011010052530100u15510n 570540580560590550Fig. 5 - VF Dispersion map60008004001000200100300500700900Fig. 6 - IR Dispersion map30040205010515253545Fig. 7 - CT Dispersion mapF o r w a r d v o l t a g e (m V )R e v e r s e c u r r e n t (n A )C a p a c i t a n c e b e t w e e n t e r m i n a l s (p F )F o r w a r d c u r r e n t (m A )0.20.411000.50.10.8Forward voltage (V) Fig. 1 - Forward characteristics10000.60.30.10.710150End W 1Reel Taping SpecificationBCdDD 2D 1EFPP 0P 1TSYMBOLAWW 1(mm)(inch)0.026 0.004±0.045 0.004±0.024 0.004±0.061 + 0.0047.008 0.04± 2.362 MIN.0.512 0.008±SYMBOL(mm)(inch)0.069 0.004±0.138 0.002±0.157 0.004±0.157 0.004±0.079 0.004±0.009 0.002±0.315 0.008±0.531 MAX.0.75 0.10± 1.15 0.10± 4.00 0.10± 1.55 + 0.103.50 0.05±1.75 0.10±60.0 MIN.13.0 0.20±0.60 0.10± 4.00 0.10± 2.00 0.10±0.22 0.05±8.00 0.20±13.5 MAX.178 1±0402(SOD-923F)0402(SOD-923F)Marking CodePark Number CDBQR0130R-HFMarking CodeBQSuggested PAD LayoutSIZE(inch)0.030(mm)0.7500.5000.7000.0200.0281.2500.049E0.2500.010Standard PackageA B C D 0402/SOD-923FCase Type Qty per Reel(Pcs)50000402/SOD-923FReel Size (inch)7分销商库存信息: COMCHIP CDBQR0130R-HF。

BDX54C;BDX54CTU;BDX54BTU;BDX54ATU;BDX54TU;中文规格书,Datasheet资料

BDX54/A/B/CBDX54/A/B/CBDX54/A/B/CTRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.ACEx™Bottomless™CoolFET™CROSSVOLT™E2CMOS™FACT™FACT Quiet Series™FAST®FASTr™GTO™HiSeC™ISOPLANAR™MICROWIRE™POP™PowerTrench®QFET™QS™Quiet Series™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TinyLogic™UHC™VCX™DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL.As used herein:1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONSDefinition of TermsDatasheet Identification Product Status DefinitionAdvance Information Formative or InDesign This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.Preliminary First Production This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.No Identification Needed Full Production This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.分销商库存信息:FAIRCHILDBDX54C BDX54CTU BDX54BTU BDX54ATU BDX54TU。

VN5E160S-E;VN5E160STR-E;中文规格书,Datasheet资料

February 2008Rev 21/34VN5E160S-ESingle channel high side driver for automotive applicationsFeatures■General–Inrush current active management by power limitation–Very low stand-by current– 3.0V CMOS compatible inputs–Optimized electromagnetic emissions –Very low electromagnetic susceptibility –In compliance with the 2002/95/EC european directive ■Diagnostic functions–Open Drain status output –On-state open load detection –Off-state open load detection –Output short to V CC detection–Overload and short to ground (power limitation) indication–Thermal shutdown indication■Protections–Undervoltage shutdown –Overvoltage clamp –Load current limitation–Self limiting of fast thermal transients–Protection against loss of ground and loss of V CC–Over-temperature shutdown with autorestart (thermal shutdown)–Reverse battery protected (a)–Electrostatic discharge protectionApplication■All types of resistive, inductive and capacitive loadsDescriptionThe VN5E160S-E is a single channel high-side driver manufactured in the ST proprietaryVIPower M0-5 technology and housed in the tiny SO-8 package.The VN5E160S-E is designed to drive automotive grounded loads delivering protection, diagnostics and easy 3V and 5V CMOS-compatible interface with any microcontroller.The device integrates advanced protectivefunctions such as load current limitation, inrush and overload active management by power limitation, over-temperature shut-off with auto-restart and over-voltage active clamp.A dedicated active low digital status pin isassociated with every output channel in order to provide Enhanced diagnostic functions including fast detection of overload and short-circuit to ground, over-temperature indication, short-circuit to V CC diagnosis and ON & OFF state open-load detection.The diagnostic feedback of the whole device can be disabled by pulling the STAT_DIS pin up, thus allowing wired-ORing with other similar devices.Max transient supply voltage V CC41VOperating voltage rangeV CC 4.5 to 28V Max On-state resistance (per ch.)R ON 160 m ΩCurrent limitation (typ)I LIMH 10A Off state supply currentI S2 µA (1)1.Typical value with all loads connected. a.See Figure 32: Application schematic .Contents VN5E160S-EContents1Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.4Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.1GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 223.1.1Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 223.1.2Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 233.2Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.3MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.4Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.5Maximum demagnetization energy (VCC=13.5V) . . . . . . . . . . . . . . . . . 254Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.1SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.1ECOP ACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.3Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332/34VN5E160S-E List of tables List of tablesTable 1.Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2.Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4.Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5.Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6.Switching (VCC=13V; Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7.Status pin (V SD=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 8.Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9.Open load detection (8V<V CC<18V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 10.Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 11.Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 12.Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 13.Thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 14.SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 15.Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 16.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333/34List of figures VN5E160S-E List of figuresFigure 1.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3.Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4.Status timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6.Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7.Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8.Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9.Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11.Open Load with external pull-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12.Open Load without external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.Short to V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14.T J evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15.Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16.High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17.Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 18.Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19.Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 20.Low level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21.On state resistance vs T case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22.High level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 23.On state resistance vs V CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 24.Low level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25.I LIM vs T case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 26.Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 27.Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 28.Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 29.STAT_DIS clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 30.High level STAT_DIS voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 31.Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 32.Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 33.Open load detection in Off state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 34.Maximum turn-Off current versus inductance (for each channel). . . . . . . . . . . . . . . . . . . . 25 Figure 35.SO-8 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 36.Rthj-amb Vs. PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . 26 Figure 37.SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 38.Thermal fitting model of a single channel HSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 39.SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 40.SO-8 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 41.SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4/34VN5E160S-E Block diagram and pin configuration5/341 Block diagram and pin configurationTable 1.Pin functionName FunctionV CCBattery connection.OUTPUT Power output.GND Ground connection. Must be reverse battery protected by an external diode/resistor network.INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.STA TUS Open Drain digital diagnostic pin.ST A T_DISActive high CMOS compatible pin, to disable the ST A TUS pin.Block diagram and pin configuration VN5E160S-E6/34Figure 2.Configuration diagram (top view)Table 2.Suggested connections for unused and not connected pins Connection / pin Status N.C.Output Input STAT_DIS Floating X X X X XT o groundNotallowedXNotallowedThrough 10KΩresistorThrough 10KΩresistorV CCV CCOUTPUTOUTPUTSTAT_DISGNDSTATUSINPUT14586723SO-8VN5E160S-E Electrical specifications7/342 Electrical specificationsNote:V F = V OUT - V CC during reverse battery condition.2.1 Absolute maximum ratingsStressing the device above the ratings listed in the “Absolute maximum ratings” tables maycause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in the “Absolute maximum ratings” tables for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and others relevant quality documents.Table 3.Absolute maximum ratingsSymbol ParameterValue Unit V CC DC supply voltage 41V - V CC Reverse DC supply voltage 0.3V - I GND DC reverse ground pin current 200mA I OUT DC output currentInternally limitedA - I OUT Reverse DC output current 6A I IN DC input current +10 / -1mA I STATDC status current+10 / -1mA I STAT_DIS DC status disable current +10 / -1mA E MAXMaximum switching energy (single pulse)(L=8 mH; R L =0Ω; V bat =13.5V; T jstart =150ºC; I OUT = I limL (Typ.) )36mJElectrical specifications VN5E160S-E8/34Symbol Parameter Value Unit V ESDElectrostatic discharge (Human body model: R=1.5KΩ;C=100pF)–INPUT–ST A TUS–ST A T_DIS–OUTPUT–V CC40004000400050005000VVVVV V ESD Charge device model (CDM-AEC-Q100-011)750V T j Junction operating temperature-40 to 150°C T stg Storage temperature- 55 to 150°CTable 4.Thermal dataSymbol Parameter Max. value Unit R thj-pins Thermal resistance junction-pins30°C/W R thj-amb Thermal resistance junction-ambient See Figure 36.°C/W Table 3.Absolute maximum ratings (continued)VN5E160S-E Electrical specifications9/342.2 Electrical characteristicsValues specified in this section are for 8V<V CC <28V; -40°C< Tj <150°C, unless otherwisestated.Table 5.Power sectionSymbol ParameterTest conditionsMin.Typ.Max.Unit V CC Operating supply voltage 4.51328V V USD Undervoltage shutdown 3.5 4.5V V USDhystUndervoltage shutdown hysteresis0.5V R ON On state resistance I OUT =1A; T j =25°C I OUT =1A; T j =150°CI OUT =1A; V CC =5V; T j =25°C 160320210m Ωm Ωm ΩV clampClamp voltageI S =20 mA414652V I SSupply currentOff State; V CC =13V; V IN =V OUT =0V; T j =25°COn State; V IN =5V; V CC =13V; I OUT =0A2(1)1.91.PowerMOS leakage included.5(1)3.5µA mA I L(off1)Off state output current V IN =V OUT =0V; V CC =13V; T j =25°C V IN =V OUT =0V; V CC =13V; T j =125°C 000.0135µA µA V FOutput - V CC diode voltage-I OUT =0.6A; T j =150°C0.7VTable 6.Switching (V CC =13V;T j =25°C)Symbol Parameter Test conditions Min.Typ.Max.Unit t d(on)T urn-On delay time R L =13Ω (see Figure 6.)10µs t d(off)T urn-Off delay timeR L =13Ω (see Figure 6.)15µs dV OUT /dt (on)T urn-On voltage slope R L =13Ω See Figure 26.V/µs dV OUT /dt (off)T urn-Off voltage slopeR L =13Ω See Figure 28.V/µs W ON Switching energy losses during t wonR L =13Ω (see Figure 6.)70µJ W OFFSwitching energy losses during t woffR L =13Ω (see Figure 6.)40µJElectrical specifications VN5E160S-E10/34Table 7.Status pin (V SD=0)Symbol Parameter Test conditions Min.Typ.Max.Unit V STA TStatus low outputvoltageI STA T= 1.6 mA, V SD=0V0.5VI LSTA T Status leakage currentNormal operation or V SD=5V,V STAT= 5V10µAC STA TStatus pin inputcapacitanceNormal operation or V SD=5V,V STAT= 5V100pF V SCL Status clamp voltageI STA T= 1mAI STA T= - 1mA5.5-0.77VV Table 8.Protection (1)1.To ensure long term reliability under heavy overload or short circuit conditions, protection and relateddiagnostic signals must be used together with a proper software strategy. If the device is subjected toabnormal conditions, this software must limit the duration and number of activation cycles.Symbol Parameter Test conditions Min.Typ.Max.UnitI limHDC short circuitcurrentV CC=13V; 5V<V CC<28V7101414AAI limLShort circuit currentduring thermal cyclingV CC=13V; T R<T j<T TSD 2.5A T TSDShutdowntemperature150175200°C T R Reset temperature T RS + 1T RS + 5°C T RSThermal reset ofSTA TUS135°C T HYSTThermal hysteresis(T TSD-T R)7°C t SDLStatus delay inoverload conditionsT j>T TSD (see Figure4)20µs V DEMAGT urn-off output voltageclampI OUT=1A; V IN=0; L=20mH V CC-41V CC-46V CC-52VV ONOutput voltage droplimitationI OUT=0.03A (see Figure 5.)T j= -40°C...+150°C25mV分销商库存信息:STMVN5E160S-E VN5E160STR-E。