errata
美国药典简介
美国药典简介1. 标题和修订（Title and Revision）. 92. 药典地位和法律认可（Official status and legal recognition）92.10 药典正文(Official Text) 92.20 药典物品（Official Articles）. 92.30 法律认可（Legal Recognition）. 103. 与标准的符合性（Conformance to standard）. 103.10 标准的适用性(Applicability of standard) 103.10.10 制剂、原料药、辅料的标准的适用性（Applicability of Standards to Drug Products, Drug Substances, and Excipients）. 103.10.20 医疗器械、营养补充剂、以及其组成成分的标准的适用性（Applicability of Standards to Medical Devices, Dietary Supplements, and Their Components and Ingredients）113.20 一致性的标示（Indicating Conformance）. 114. 药典各论和通则（Monographs and general chapters）124.10 各论(Monographs) 124.10.10 检测程序的适用性(Applicability of Test Procedures) 124.10.20 接受标准(Acceptance Criteria) 124.20 附录（General Chapter）. 125. 各论组成（Monograph Components）. 135.10 分子式（Molecular formula）. 135.20 附加物质、赋形剂、组分(Added Substances, Excipients, and Ingredients) 135.20.10官方原料药中附加的物质、赋形剂、组分（Added Substances, Excipients, and Ingredien ts in Official Substances）. 135.20.20官方制剂中的附加物质、赋形剂、组分（Added Substances, Excipients, and Ingredients in Official Products）. 135.30 性状和溶解性（Description and Solubility）. 145.40 鉴定试验（Identification Test）. 145.50 含量分析（Assay）. 155.50.10 效价单位（生物效价）(Units of Potency (Biological)) 155.60 杂质和外来物质（Impurities and Foreign Substances）. 155.60.10 USP和NF物品的其它杂质（Other Impurities in USP and NF Articles）155.60.20 USP和NF物品中的残留溶剂（Residual Solvents in USP and NF Articles）165.70性能检测（Performance Tests）. 165.80 USP标准品（Residual Solvents in USP and NF Articles）. 166. 检验规范和分析方法（Testing practices and procedures）166.10 安全的实验室规范（Safe Laboratory Practices）. 166.20 自动化程序（Automated Procedures）. 166.30 可选择的和谐的方法与程序（Alternative and Harmonized Methods and Procedures）166.40 干燥的、无水的、灼烧的、无溶剂的（Dried, Anhydrous, Ignited, or Solvent-Free Basis）176.40.10 灼烧至恒重（Ignite To Constant Weight）. 176.40.20 干燥至恒重（Dried To Constant Weight）. 176.50 溶液的制备（Preparation of Solutions）. 186.50.10 过滤（Filtration）. 186.50.20 溶液（Solutions）. 186.60 完成一个实验所需多少单位（Units Necessary to Complete a Test）. 186.60.10 片剂（Tablets）. 186.60.20 胶囊（Capsules）. 196.70 试剂（Reagents）. 196.80 设备（Equipment）. 196.80.10 测量仪器（Apparatus for Measurement）. 196.80.20 仪器设备（Instrumental Apparatus）. 197. 测试结果（Test Results）. 207.10 质量要求的解释(Interpretation of Requirements) 207.10.10 滴定程序中的等效表述(Equivalence Statements in Titrimetric Procedures) 207.20 修约原则(Rounding Rules) 208. 术语和定义(Terms and Definitions) 218.10 缩写(Abbreviations) 218.20 大约(About) 218.30 乙醇含量(Alcohol Content) 218.40 原子量(Atomic Weights) 228.50 空白试验(Blank Determinations) 228.60伴随(Concomitantly) 228.70 干燥器(Desiccator) 228.80 对数（Logarithms）. 228.90 微生物菌株(Microbial Strain) 228.100 可忽略的（Negligible）. 228.110 NLT/NMT 228.120 气味(Odor) 228.130 百分比(Percent) 228.140 百分比浓度(Percentage Concentrations) 238.150 压力(Pressure) 238.160 反应时间(Reaction Time) 238.170 比重(Specific Gravity) 238.180 温度(Temperatures) 238.190 时间(Time) 238.200 转移（Transfer）. 238.210 真空（Vacuum）. 238.220 真空干燥器（Vacuum Desiccator）. 238.230 水（Water）. 248.230.10 水作为官方制剂中的组分（Water as an Ingredient in an Official Product）24 8.230.20 水用于官方原料药的生产（Water in the Manufacture of Official Substances）24 8.230.30 药典实验操作用水（Water in a Compendial Procedure）. 248.240 称量和测量（Weights and Measures）. 249. 开处方和配药（Prescribing and Dispending）. 259.10 公制单位的使用（Use of Metric Units）. 259.20 体积的改变（Changes in Volume）. 2510. 保存、包装、储存、贴签（preservation，packaging，storage and labeling）2510.10 在非特定条件下储存（Storage Under Nonspecific Conditions）. 2510.20 包装容器（Containers）. 2510.20.10显窃启包装（Tamper-Evident Packaging）. 2610.20.20 避光容器（Light-Resistant Container）. 2610.20.30密闭良好的容器（Well-Closed Container）. 2610.20.40密封的容器（Tight Container）. 2610.20.50严封的容器（Hermetic Container）. 2710.20.60单元包装（Single-Unit Container）. 2710.20.70单剂量包装（Single-Dose Container）. 2710.20.80单元剂量容器（Unit-Dose Container）. 2710.20.90单元使用的容器（Unit-of-Use Container）. 2710.20.100多单元容器（Multiple-Unit Container）. 2710.20.110多剂量容器（Multiple-Dose Container）. 2710.20.120毒物保护包装法案（Requirements under the Poison Prevention Packaging Act (PPPA)）2710.30 储存温度和湿度（Storage Temperature and Humidity）. 2810.30.10 冷冻（Freezer）. 2810.30.20冷处（Cold）. 2810.30.30 凉处（Cool）. 2810.30.40 可控的凉爽温度（controlled cold temperature）. 2810.30.50 室温（room temperature）. 2910.30.60 可控的室温（Controlled Room Temperature）. 2910.30.70 温暖（warm）. 2910.30.80 过热（Excessive Heat）. 2910.30.90 防冻（Protection From Freezing）. 2910.30.100 干燥处（Dry Place）. 2910.40 标签（Labeling）. 2910.40.10每个剂量单元中组分的量（Amount of Ingredient Per Dosage Unit）3010.40.20 首位和末位零的使用（Use of Leading and Terminal Zeros）. 3010.40.30药品中盐的标示（Labeling of Salts of Drugs）. 3010.40.40含维生素产品的标示（Labeling Vitamin-Containing Products）. 3010.40.50含植物药材的产品的标示（Labeling Botanical-Containing Products）3110.40.60非肠道和局部制剂的标示（Labeling Parenteral And Topical Preparations）3110.40.70电解液的标示（Labeling Electrolytes）. 3110.40.80乙醇的标示（Labeling Alcohol）. 3110.40.90特殊的胶囊和片剂（Special Capsules and Tablets）. 3110.40.100有效期和失效期（expiration date and beyond-use date）. 3110.50 USP-NF药典正文中关于包装和储存的指南（Guidelines for Packaging and Storage State ments in USP–NF Monographs）. 32General Notices and Requirements(凡例和要求)Change to read:凡例部分为药典的解释和应用提出了基本的假定、定义、默认条件。
2、名词的数(二)：单数与复数
2．服装 jeans（牛仔裤） trousers（长裤） shorts（短裤） briefs（内裤） pants（短裤） slacks（休闲裤） pajamas（睡衣）
汉译英： A：我的眼镜在哪里？ B：它不就在你的鼻子上戴着嘛！
A: Where are my glasses? B: They are right on your nose!
2) There were many people in the room.
比如当“民族”或“部族”讲时，那就是一个普通名词，有单复数 的变化。比如单数要用不定冠词a修饰，即a people（一个民 族），复数要在词尾加-s，即peoples。例句：
The Chinese are an industrious people. 中华民族是一个勤劳的民族。
二、以-man/-woman/-child结尾的复合名词 以-man/-woman/-child结尾的复合名词变复数时，将man/-woman/-child变为复数。例如： fireman/firemen（消防员） chairwoman/chairwomen（女主席） horseman/horsemen（骑兵） grandchild/grandchildren（孙子／女） policeman/policemen（警察） Englishman/Englishmen（英国人） Frenchman/Frenchmen（法国人） 但是German不是一个合成词，所以其复数形式是在词 尾直接加-s，即Germans。
三、以“辅音字母＋y”结尾的名词，变-y为-i，再加-es； 而以“元音字母＋y”结尾的名词，则加-s
country/countries, family/families, baby/babies, lady/ladies; play/plays, boy/boys, guy/guys, donkey/donkeys, monkey/monkeys, key/keys等。
errata2
correlation.” p. 224, 4 below Subsection 9.3.2: replace “3SLS” with “3SLS, which is the same as the IV estimator in equation (8.22)” 13 437. 29” 22 437. 29” should be “ p. 236, 6 down: “ p. 236, 2 up: “can produce” should be “will produce” p. 236, 1 up: After “ 13 0" insert “, if Eu 1 |z 0” p. 261, 5 up: Replace “Section 10.4.4” with “Section 10.4.3” p. 270, 3 below eq. (10.51): Replace the second occurrence of “Eü it ü is ” with “Eu it ū i u is ū i ” p. 272, 8 down: Replace “NT K” with “NT K 1 ” p. 289, 2 up from eq. (10.78): after “variables” insert “or aggregate time variables” FE ” insert “a t statistic version of (10.78),” p. 290, 11 down: Before “ i” p. 291, 7 down: after “pooled OLS” add “estimation of (10.79), or with w i in place of w p. 295, Problem 10.11: Replace “LOWBRTH.RAW” with “LOWBIRTH.RAW” p. 296, Problem 10.13: In the first equation replace “ 2 ” with “ 2 u” p. 297, Problem 10.14, 1 below the equation: add “1 K” after “x it ” and “1 M” after “z i ” p. 300, 2 below eq. (11.4): insert “the sequential exogeneity” before “assumption (11.3)” p. 305, the equation just above Subsection 11.1.2: Delete “^” over the secon32, Problem 11.1, part d: Replace “parts b and c” with “parts a and c” ” nor “” should be boldface p. 333, Problem 11.3: Neither “ FE p. 337, Problem 11.14, part a: Replace “Estimate” with “Use the data in EZUNEM.RAW to estimate”
erratas翻译
erratas翻译Erratas 是指书籍、文件或印刷品中的错误或纰漏。
下面是关于erratas 的翻译和一些用法和中英文对照例句：翻译：- 英文：erratas- 中文：勘误表用法：1. 提交勘误表：- 英文：Submit an errata.- 中文：提交勘误表。
2. 修正错误：- 英文：Correct the erratas.- 中文：纠正勘误表中的错误。
3. 更新版本：- 英文：Publish an updated version with the erratas.- 中文：发布一份包含勘误表的更新版。
4. 修订出版物：- 英文：Revise the publication to address the erratas.- 中文：修订出版物以处理勘误表中的错误。
中英文对照例句：1. The author has provided an errata for the book, addressing the errors found in the previous edition.（作者为这本书提供了一份勘误表，解决了上一版中发现的错误。
）2. The publisher released an updated version of the textbook, including all the erratas that were reported by readers.（出版商发布了一份更新版教科书，其中包含了读者报告的所有勘误表。
）3. The author was quick to acknowledge the erratas in the research paper and issued a formal apology.（作者迅速承认了研究论文中的勘误表，并发表了正式道歉。
）4. The editorial team carefully reviewed the manuscript and identified several erratas that needed to be corrected before publication.（编辑团队仔细审查了手稿，并确定了几处在出版之前需要纠正的勘误表。
拉丁短语——精选推荐
拉丁语译文注疏ab aeterno自从时间开始以来ab imopectore出自内心ab initio从开始起ab origine从起源Absenshaeres non erit.不在场者不得为继承人。
absensreo被告不在abs reab urbe condita罗马城建立后罗马城约建于公元前Accusare nemo se debet.谁都不须控告自己。
ad absurdum反证ad augusta per angusta刻苦成功ad calendasGraecas永远不会ad infinitum无穷ad infad majorem Dei gloriam(AMDG)为上帝增光耶稣会格言ad nauseam令人厌恶ad rem对物ad usumDelphini经过修订的Adsum!在！点名被点到名时的回答advocatusdiaboli魔鬼的辩护士指责圣列候补者的人aereperennius永垂不朽aesalienum债款a fortiori更加alibi不在现场alma mater母校alter ego第二个我密友alumnus校友amantesamentes情近乎痴。
Amicus certus in reincertacernitur.患难知朋友。
amicus humani generis人类之友Amor gignitamorem.爱生爱。
amorhabendi占有欲amor patriae爱国主义Amor vincitomnia.爱情征服一切。
animal bipesimplume 没有羽毛的两腿动物柏拉图为人类下的定义animus iniuriandi伤害的意图annicurrentis本年anno Domini公元 ..... 年耶稣降生后Annuitcoeptis.神佑我邦。
美国国徽背面ante Christum公元前ante meridiem上午AMapplicatio externa外用法（药）applicatiointerna内用法（药）aqua destillata蒸馏水Aquilla non capitmuscas.老鹰不捉苍蝇。
PIC18F1XK22_LF1XK22 Family Silicon Errata and Data Sheet Clarification
© 2009 Microchip Technology Inc.DS80437B-page 1PIC18F1XK22/LF1XK22The PIC18F1XK22/LF1XK22 family devices that you have received conform functionally to the current Device Data Sheet (DS41365B ), except for the anomalies described in this document.The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in T able 2.The errata described in this document will be addressed in future revisions of the PIC18F1XK22/LF1XK22silicon.Data Sheet clarifications and corrections start on page 6,following the discussion of silicon issues.The silicon revision level can be identified using the current version of MPLAB ® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site ().For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ 3:1.Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/debugger or PICkit™ 3.2.From the main menu in MPLAB IDE, select Configure>Select Device , and then select the target part number in the dialog box.3.Select the MPLAB hardware tool (Debugger>Select Tool ).4.Perform a “Connect” operation to the device (Debugger>Connect ). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window.The DEVREV values for the various PIC18F1XK22/LF1XK22 silicon revisions are shown in Table 1.Note:This document summarizes all silicon errata issues from all revisions of silicon,previous as well as current.Note:If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance.TABLE 1:SILICON DEVREV VALUESPart NumberDevice ID Revision ID for Silicon Revision (1)A1A2A3PIC18F14K224F20h 01h 02h 03h PIC18F13K224F40h 01h 02h 03h PIC18LF14K224F60h 01h 02h 03h PIC18LF13K224F80h01h02h03hNote 1:The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. They are shown in hexadecimal in the format “DEVID:DEVREF”.2:Refer to the “PIC18F1XK22/LF1XK22 Flash Memory Programming Specification” (DS41357) for detailed information on Device and Revision IDs for your specific device.PIC18F1XK22/LF1XK22 Family Silicon Errata and Data Sheet ClarificationPIC18F1XK22/LF1XK22DS80437B-page 2© 2009 Microchip Technology Inc.TABLE 2:SILICON ISSUE SUMMARYSilicon Errata Issues1.Module:ADC (Analog-to-DigitalConverter)ADC conversion on AN3/OSC2 will have large INL error up to approximately 8LSb.Work aroundNone for the AN3 pin. For better accuracy, use another analog pin.Affected Silicon Revisions 2.Module:ECCP2.1Changing direction in Full-Bridge mode inserts a dead band time of 4/F OSC *TMR2prescale instead of 1/F OSC *TMR2 prescale as specified in the data sheet.Work around None.Affected Silicon Revisions 2.2In Full-Bridge mode, when PR2=CCPR1L,DC1B<1:0> = 00, and the direction is changed, then the dead time before the modulated output starts is compromised.The modulated signal improperly starts immediately with the direction change and stays on for T OSC *TMR2Presale *DC1B<1:0>.Work aroundAvoid changing direction when the duty cycle is within three least significant steps of 100% duty cycle. Instead, clear the DC1B<1:0> bits before the direction change and then set them to the desired value after the direction change is complete.Affected Silicon Revisions 3.Module:EUSART3.1In Asynchronous Receive mode, the RCIDL bit of the BAUDCON register will properly go low when a low pulse greater than 1/16th of a bit time is received on the RX input. The RCIDL bit will then improperly go high if a low pulse less than 1/16 bit time occurs on the RX input within one bit period after the falling edge of the first pulse. This erratum affects only users monitoring the RCIDL bit as a part of their serial protocol.Module Feature Item Number Issue SummaryAffected Revisions (1)A1A2A3ADC ADC Conversion rge INL error on AN3.X X X ECCP Full Bridge mode2.Delay time with direction change.X X X EUSART — 3.RCIDL bit, clearing the OERR flag, and RX pin.X X X MSSP —4.I 2C™ mode and SPI mode.X XXOscillator LP Osc. 5.Osc. switching and LP Osc. fails at hot.X V REF CV REF output6.RC2 disabled.X ICSP™—7.ICSP works only at V DD >2V.X X X Internal Oscillator —8.Frequency tolerance.XXXNote 1:Only those issues indicated in the last column apply to the current silicon revision.Note:This document summarizes all silicon errata issues from all revisions of silicon,previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A1).A1A2A3XXXA1A2A3XXXA1A2A3XXXPIC18F1XK22/LF1XK22Work aroundNone.Affected Silicon Revisions3.2The OERR flag of the RCSTA register isreset only by either clearing the CREN bit ofthe RCSTA register or by a device Reset.Clearing the SPEN bit of the RCSTA registerdoes not clear the OERR flag.Work aroundClear the OERR flag by clearing the CRENbit in lieu of clearing the SPEN bit.Affected Silicon Revisions3.3When the SPEN bit of the RCSTA register isset and the CREN bit of the RCSTA registeris clear, the RX pin is not available for gen-eral purpose output. Likewise, when theSPEN bit of the RCSTA register is set andthe TXEN bit of the TXSTA register is clear,the TX pin is not available for general pur-pose output. However, both the RX and TXpins can be read regardless of the state ofthe RCSTA and TXSTA control registers.Work aroundNone.Affected Silicon Revisions4.Module:MSSP (Master SynchronousSerial Port)4.1In I2C™ Master mode, baud rates obtainedby setting SSPADD to a value less than 0x03will cause unexpected operation.Work aroundEnsure SSPADD is set to a value greaterthan or equal to 0x03.Affected Silicon Revisions 4.2In SPI Master mode, when the CKE bit iscleared and the SMP bit is set, the last bit ofthe incoming data stream (bit 0) at the SDIpin will not be sampled properly.Work aroundNone.Affected Silicon Revisions4.3When SPI is enabled in Master mode withCKE=1 and CKP=0, a 1/F OSC wide pulsewill occur on the SCK pin.Work aroundConfigure the SCK pin as an input until afterthe MSSP is setup.Affected Silicon Revisions4.4I2C Master mode, SSPADD values of 0x00,0x01, 0x02 are invalid. The current I2C BaudRate Generator (BSG) is not set up togenerate a clock signal for these values.Work aroundNone.Affected Silicon Revisions4.5I2C Master mode, RCEN bit not cleared byhardware if improper Stop is received on thebus.Work aroundReset the module via clearing and settingthe SSPEN bit of SSPCON1.Affected Silicon RevisionsA1A2A3 X X XA1A2A3 X X XA1A2A3 X X XA1A2A3 X X X A1A2A3 X X XA1A2A3 X X XA1A2A3 X X XA1A2A3 X X X© 2009 Microchip Technology Inc.DS80437B-page 3PIC18F1XK22/LF1XK22DS80437B-page 4© 2009 Microchip Technology Inc.4.6SPI Master mode, when the SPI clock is configured for Timer2/2(SSPCON1<3:0>=0011), the first SPI high time may be short.Work around None.Option 1: Ensure TMR2 value rolls over tozero immediately before writing to SSPBUF.Option 2: Turn Timer2 off and clear TMR2before writing SSPBUF. Enable TMR2 after SSPBUF is written.Affected Silicon Revisions 4.7In any SPI Master mode, SCK =TMR2/2; if SSPBUF is written to while shifting out data,a ninth SCK pulse is incorrectly generated.At that point, the module locks user from writ-ing to the SSPBUF register, but a write attempt will still cause 8 or 9 more SCK pulses to be generated.Work aroundThe WCOL bit of the SSPCON register is correctly set to indicate that there was a write collision. Any time this bit is set the module must be disabled and enabled (toggle SSPEN) to return to correct operation. The bus will remain out of synchronization.Affected Silicon Revisions .5.Module:Oscillator5.1Disabling the Primary External Oscillator circuitry (PRI_SD = 1) immediately following a change in system clock from external LP oscillator to the internal oscillator will halt code execution indefinitely.Work aroundAfter changing from external LP oscillator to the internal oscillator, allow at least two instruction cycles before disabling the Primary External Oscillator circuitry.Affected Silicon Revisions 5.2The external LP Oscillator could fail operation at temperatures above 100degrees Celsius.Work around None.Affected Silicon Revisions 6.Module:Programmable VoltageReferenceThe V REF voltage reference can be output to the device CV REF pin by setting the DAC1OE bit of the VREFCON1 register to ‘1’. When the CV REF pin is enabled, pin RC2 is incorrectly set to Analog mode. The digital output buffer and digital input threshold detector functions of that pin are disabled.Work aroundPin RC2 may only be used for analog functions when the voltage reference output is enabled on the CV REF pin. Ensure that the TRIS bit for pin RA0 is set to ‘1’ for proper operation of the CV REF output.Affected Silicon Revisions 7.Module:In-Circuit Serial Programming™(ICSP™)The device cannot be programmed using ICSP when the device V DD is less than 2.0 volts.Work aroundEnsure that the device voltage is 2.0 volts or higher when programming the device.Affected Silicon Revisions A1A2A3X XXA1A2A3XXXA1A2A3XA1A2A3XA1A2A3XA1A2A3XXXPIC18F1XK22/LF1XK228.Module: Internal OscillatorThe frequency tolerance of the HFINTOSC inter-nal oscillator is +2% to -2.5% from 0-85°C.Work aroundNone.Affected Silicon RevisionsA1A2A3X X X© 2009 Microchip Technology Inc.DS80437B-page 5PIC18F1XK22/LF1XK22DS80437B-page 6© 2009 Microchip Technology Inc.Data Sheet ClarificationsThe following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41365B ).1.Module: Electrical SpecificationsIn Table 25-10 Comparator Specifications of the data sheet (DS41365B ), the Input Offset Voltage should be +/-50mV in High-Power mode and +/-80mV in Low-Power mode as shown below.TABLE 25-10:COMPARATOR SPECIFICATIONS2.Module:Device OverviewIn Table 1-2, PIC18F1XK22/LF1XK22 Pin Sum-mary of the data sheet (DS41365B ), under pin name RA2, the Buffer Type should be ‘ST ’.Note:Corrections are shown in bold . Where possible, the original bold text formatting has been removed for clarity.Operating Conditions: 1.8V < V DD < 5.5V, -40°C < T A < +125°C (unless otherwise stated).Param No.Sym.CharacteristicsMin.Typ. Max.UnitsComments CM01V IOFF Input Offset Voltage—±7.5±50 mV High-Power mode ——±80 mV Low-Power modeCM02V ICM Input Common Mode Voltage 0—V DD V CM03CMRR Common Mode Rejection Ratio 55——dB CM04T RESP Response Time—150400ns Note 1CM05T MC 2OVComparator Mode Change to Output Valid*——10μs*These parameters are characterized but not tested.Note 1:Response time measured with one comparator input at V DD /2, while the other input transitions from V SS to V DD .PIC18F1XK22/LF1XK22 APPENDIX A:DOCUMENTREVISION HISTORYRev. A Document (3/2009)Initial release of this document.Rev. B Document (5/2009)Revised Table 1; Added Table 2; Added Module 8:Internal Oscillator.Added Data Sheet Clarifications Module 1: ElectricalSpecifications and Module 2: Device Overview.© 2009 Microchip Technology Inc.DS80437B-page 7PIC18F1XK22/LF1XK22NOTES:DS80437B-page 8© 2009 Microchip Technology Inc.© 2009 Microchip Technology Inc.DS80437B-page 9Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, dsPIC, K EE L OQ , K EE L OQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV , MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, , dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP , ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP , Omniscient Code Generation, PICC, PICC-18, PICkit,PICDEM, , PICtail, PIC 32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.All other trademarks mentioned herein are property of their respective companies.© 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.Printed on recycled paper.Note the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC ® DSCs, K EE L OQ ® code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.AMERICASCorporate Office2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200Fax: 480-792-7277 Technical Support: Web Address: AtlantaDuluth, GATel: 678-957-9614Fax: 678-957-1455BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088 ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075 Cleveland Independence, OHTel: 216-447-0464Fax: 216-447-0643DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitFarmington Hills, MITel: 248-538-2250Fax: 248-538-2260 KokomoKokomo, INTel: 765-864-8360Fax: 765-864-8387Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608Santa ClaraSanta Clara, CATel: 408-961-6444Fax: 408-961-6445 TorontoMississauga, Ontario, CanadaTel: 905-673-0699Fax: 905-673-6509ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHarbour City, KowloonHong KongTel: 852-2401-1200Fax: 852-2401-3431Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8528-2100Fax: 86-10-8528-2104China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889China - Hong Kong SARTel: 852-2401-1200Fax: 852-2401-3431China - NanjingTel: 86-25-8473-2460Fax: 86-25-8473-2470China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205China - ShanghaiTel: 86-21-5407-5533Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660Fax: 86-755-8203-1760China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118China - XiamenTel: 86-592-2388138Fax: 86-592-2388130China - XianTel: 86-29-8833-7252Fax: 86-29-8833-7256China - ZhuhaiTel: 86-756-3210040Fax: 86-756-3210049ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444Fax: 91-80-3090-4080India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632India - PuneTel: 91-20-2566-1512Fax: 91-20-2566-1513Japan - YokohamaTel: 81-45-471- 6166Fax: 81-45-471-6122Korea - DaeguTel: 82-53-744-4301Fax: 82-53-744-4302Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or82-2-558-5934Malaysia - Kuala LumpurTel: 60-3-6201-9857Fax: 60-3-6201-9859Malaysia - PenangTel: 60-4-227-8870Fax: 60-4-227-4068Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - Hsin ChuTel: 886-3-6578-300Fax: 886-3-6578-370Taiwan - KaohsiungTel: 886-7-536-4818Fax: 886-7-536-4803Taiwan - TaipeiTel: 886-2-2500-6610Fax: 886-2-2508-0102Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-5820 W ORLDWIDE S ALES AND S ERVICE03/26/09DS80437B-page 10© 2009 Microchip Technology Inc.。
英语名词变复数表
英语不规则名词复数表一、分类1.以f 或fe 结尾：大多数以f 或fe 结尾的名词的复数形式时将其转为ves，但个别直接加s：roof →roofs 屋顶[ru:f]gulf →gulfs 海湾[gʌlf]grief →griefs 悲伤, 悲痛, 担心英[ɡriːf ] 美[grif]cliff →cliffs 悬崖, 峭壁[klif]beef →beefs 牛肉英[bi:f] 美[bif]chief →chiefs 首长, 首领[tʃi:f]proof →proofs 证明英[pru:f] 美[pruf]staff →staffs 全体职员英[stɑːf]美[stæf; stɑf]2.元音：有些名称的复数形式是改变它们的元音声：man →men 男[mæn]woman →women 女[ˈwʊmən]fireman →firemen 消防员[ˈfaɪəmən]foot →feet 脚[fʊt]goose →geese 鹅[guːs]tooth →teeth 牙齿英[tu:θ] 美[tuθ]mouse →mice 老鼠[maus]louse →lice 虱子英[laʊs] 美[laʊs; laʊz]3.古代英语：有些是沿用古代英语：child →children 小孩, 儿童[tʃaɪld]ox →oxen 牛, 阉牛英[ɒks] 美[ɑks]4.以o 结尾：有的以o 结尾的单词加“s”：auto →autos [美口] 汽车英[ˈɔːtəʊ] 美[ˈɔtoʊ; ˈɑtoʊ]kangaroo →kangaroos 袋鼠英[ˌkæŋɡəˈruː]美[ˌkæŋgəˈru]kilo →kilos 千克, 公斤['ki:ləu]memo →memos [口] 备忘录英[ˈmɛməʊ; ˈmiːməʊ] 美[ˈmɛmoʊ]photo →photos 照片['fəutəu]piano →pianos 钢琴英[pɪˈænəʊ] 美[piˈɑnoʊ; pjˈænoʊ ]pimento →pimentos 多香果[pi'mentəu] n. 1.蒲桃树的干果制成的香料2.西班牙甘椒pro →pros 赞成意见英[prəʊ] 美[proʊ]con →cons 反对意见英[kɒn] 美[kɑn]solo →solos, soli 独唱, 独奏英[ˈsəʊləʊ] 美[ˈsoʊloʊ]soprano →sopranos 女高音英[səˈprɑːnəʊ] 美[səˈprænoʊ]studio →studios 工作室英[ˈstjuːdɪˌəʊ] 美[ˈstudiˌoʊ; ˈstjudioʊ]tattoo →tattoos 文身英[tæˈtuː]美[tæˈtu]video →videos 视频英[ˈvɪdɪˌəʊ] 美[ˈvɪdiˌoʊ]zoo →zoos 动物园英[zuː]美[zu]bamboo →bamboos 竹子[bæm'bu:]radio →radios 收音机英[ˈreɪdɪəʊ] 美[ˈreɪdiˌoʊ]mulatto →mulattos 白黑混血儿[mju'lætəu]有的则加“es”：echo →echoes 回声, 反响英[ˈɛkəʊ] 美[ˈɛkoʊ]embargo →embargoes 禁运, 禁运令英[ɛmˈbɑːɡəʊ] 美[ɛmˈbɑrgoʊ; ɪmˈbɑrgoʊ]hero →heroes 英雄英['hiərəu] 美['hɪro]potato →potatoes 土豆英[pəˈteɪtəʊ] 美[pəˈteɪtoʊ; pəˈteɪtə]tomato →tomatoes 番茄英[tə'mɑ:təu] 美[tə'meitəu]torpedo →torpedoes 鱼雷, 水雷英[tɔːˈpiːdəʊ] 美[tɔrˈpidoʊ]veto →vetoes 否决, 否决权['vi:təu]negro →negroes 黑人英[ˈniːgrəʊ] 美[ˈnigroʊ]jingo →jingoes 侵略主义,沙文主义['dʒingəu]mango →mangoes 芒果英[ˈmæŋɡəʊ] 美[ˈmæŋgoʊ]有的两种都可以：buffalo →buffalos / buffaloes / buffalo 水牛英[ˈbʌfəˌləʊ] 美[ˈbʌfəˌloʊ]cargo →cargos / cargoes (船/飞机的)货物英[ˈkɑːɡəʊ] 美[ˈkɑrgoʊ]halo →halos / haloes 光环英[ˈheɪləʊ] 美[ˈheɪloʊ]mosquito →mosquitos / mosquitoes 蚊子[məs'ki:təu]motto →mottos / mottoes 箴言, 格言['mɔtəu]no →nos / noes 没有英[nəʊ] 美[noʊ]tornado →tornados / tornadoes 龙卷风英[tɔːˈneɪdəʊ] 美[tɔrˈneɪdoʊ]volcano →volcanos / volcanoes 火山英[vɒlˈkeɪnəʊ] 美[vɑlˈkeɪnoʊ; vɔlˈkeɪnoʊ]zero →zeros / zeroes 零英[ˈzɪərəʊ] 美[ˈzɪroʊ; ˈziroʊ]commando →commands / commandoes 突击员英[kəˈmɑːndəʊ] 美[kəˈmændoʊ; kəˈmɑndoʊ ]5.不变：有的则不变：cod →cod 鳕鱼英[kɒd] 美[kɑd]deer →deer 鹿[diə]fish →fish 鱼, 鱼类[fɪʃ]offspring →offspring 子孙, 后裔, 幼崽英['ɔ:fspriŋ]美['ɔf,sprɪŋ]perch →perch 鲈鱼英[pɜːtʃ] 美[pɜrtʃ]sheep →sheep 绵羊英[ʃiːp]美[ʃip]trout →trou 鲑鱼[traʊt]bison →bison 野牛['baisn]moose →moose 驼鹿英[muːs]美[mus]aircraft →aircraft 飞机, 飞行器英[ˈɛəˌkrɑːft]美[ˈɛrˌkræft]barracks →barracks 兵营[ˈbærəks]crossroads →crossroads 十字路口英[ˈkrɒsˌrəʊdz] 美[ˈkrɔsˌroʊdz]dice →dice 骰子[dais]gallows →gallows 绞刑架['gæləuz]headquarters →headquarters 总部英[ˌhɛdˈkwɔːtəz] 美[ˈhɛdˌkwɔrtərz]means →means 方法, 手段, 途径英[miːnz]美[minz]series →series 系列英[ˈsɪəriːz]美[ˈsɪriz]species →species 物种['spi:ʃiz]6.借用单词：英语中有些单词是借用其他语言的。
IGLOO2 M2GL050 (T, TS) 设备 Errata 表说明书
IGLOO2 M2GL050 (T , TS) Device ErrataER0200 v1.3 April 2016April 2016This Errata sheet contains information about known Errata specific to the IGLOO ®2 M2GL050 (T, TS) device family and provides available fixes and solutions.Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Revisions Released per Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Errata for IGLOO2 M2GL050 (T, TS) All Temperature Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Summary of IGLOO2 M2GL050 (T,TS) Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Errata Descriptions and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Usage Guidelines for IGLOO2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Revision 0 and Revision 1 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Revision 2 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 1: Revision HistoryDate Version ChangesApril 2016 1.3Added Errata item 19.January 20161.2Updated Table 4 and Table 5: AutoProgramming and 2 Step IAP use SC_SPI programming interface.January 2016 1.1Added the following:•Information about Revision 2 of the M2GL050 device •Errata item 18.•Table 5June 20151.0Combined all M2GL050 (T,TS) device Errata.Table 2: Revisions Released per DeviceSilicon Devices Revisions Device Status M2GL050 (T, TS)All Temperature GradesProduction2IGLOO2 M2GL050 (T, TS) Device Errata ER0200 v1.3 April 2016Errata for IGLOO2 M2GL050 (T, TS) All Temperature GradesTable 3 lists the specific device Errata and the affected IGLOO2 M2GL050 (T, TS) revisions of all temperature grade devices .Table 3: Summary of IGLOO2 M2GL050 (T, TS) Device ErrataErrata No.ErrataSilicon Revisions M2GL050 (T, TS)Software ErrataRev (0, 1)Rev 21.MDDR and FDDR AXI interface does not support exclusive access X X –2.Apply DEVRST_N after ISP programmingX ––3.AXI wrap transfers with more than 32 bytes in burst mode are not supported for MDDR and FDDRX X –4.The MDDR/FDDR controller must be used with sequential burst mode with BL = 8 and PHY = 32, or PHY = 16X X –5.HPMS may reset when ENC_DATA_AUTHENTICATION or DEVICE_INFO STAPL commands are sentX ––6.VPP must be set to 2.5 V when programming/writing the eNVM at Industrial temperature rangeX ––7.Over-voltage support on MSIOs during Flash*Freeze mode X ––8.Verification of the FPGA fabric at junction temperatures higher than 50°C erroneously indicates a failureX ––9.DDR_OUT and I/O-Reg functional Errata due to a software bug ––X 10.Dedicated differential I/O driving the reference clock of the CCC may cause a functional failure due to a software bug––X 11.NVM Ready bit in eNVM Status register can generate a false READY signalX ––12.Power-up Digest is not supportedX ––13.Programming of the eNVM must only occur as part of a bitstream also containing the FPGA fabric––X 14.Updating eNVM from the FPGA fabric requires changes in the NV_FREQRNG registerX X –15.SYSCTRL_RESET_STATUS macro is not supported X X –16.Zeroization is not supportedX X –17.PCIe Hot Reset support requires a soft reset solutionX X –18.The DDR I/Os in M2GL050 (T, TS)-FG896 are non-compliant with the DDR3 standardX X –19.For S (security) grade devices, user must not enable write protection for Protected 4 K Regions, also known as Special Sectors in the eNVMXX–Note:Contact Microsemi SoC technical support , if you have additional questions. To order a specific die, contact your localMicrosemi sales office.IGLOO2 M2GL050 (T, TS) Device ErrataER0200 v1.3 April 20163Errata Descriptions and Solutions1.MDDR and FDDR AXI interface does not support exclusive accessThe MDDR and FDDR AXI interface in the M2GL050 device is compliant with AMBA AXI Protocol Specification v1.0, except for the exclusive access functionality. The future version of the Errata will have an updated information about the exclusive access functionality for the AXI interface.2.Apply DEVRST_N after ISP programmingM2GL050 devices support device programming in JTAG, Slave SPI, and ISP programming modes. However, after ISP programming, DEVRST_N needs to be asserted to reset the device or power cycle the device to run the new design.3.AXI wrap transfers with more than 32 bytes in burst mode are not supported for MDDR and FDDRDo not use wrap transfers with more than 32 bytes.4.The MDDR/FDDR controller must be used with sequential burst mode with BL = 8 and PHY = 32, or PHY = 16Though the MDDR and FDDR controllers in the M2GL050 devices support various burst modes/ lengths and PHY settings (as specified in the UG0446: SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces User Guide), only a subset of these settings are supported.Recommendation:Only use sequential burst mode with BL = 8 for PHY16, or PHY32 modes for the MDDR or FDDR.5.HPMS may reset when ENC_DATA_AUTHENTICATION or DEVICE_INFO STAPL commands are sentThe HPMS resets after executing one of the following STAPL actions:•ENC_DATA_AUTHENTICATION •DEVICE_INFOAdditionally, if any of these actions are executed while a SmartDebug session is active, HPMS resets are observed.6.VPP must be set to 2.5 V when programming/writing the eNVM at Industrial temperature rangeVPP can be set to 2.5 V or 3.3 V. However, when writing or programming the eNVM of the M2GL050 devices below 0°C, VPP must be set to 2.5 V.Refer to the DS0128: IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet for VPP minimum and maximum settings. Note that the eNVM reading with VPP set to 3.3 V or 2.5 V operates as intended.7.Over-voltage support on MSIOs during Flash*Freeze modeWhen the input voltage is driven above the reference voltage for that bank, additional current can be consumed in Flash*Freeze mode.4IGLOO2 M2GL050 (T, TS) Device Errata ER0200 v1.3 April 20168.Verification of the FPGA fabric at junction temperatures higher than 50°C erroneously indicates a failureStandalone verification (STAPL VERIFY action) must run at temperatures lower than 50°C. If aVERIFY action is run at temperatures higher than 50°C, a false verify failure may be reported. Note that the Check Digest system services can be used to confirm design integrity at temperatures within the recommended operation conditions.9.DDR_OUT and I/O-Reg functional Errata due to a software bugThis Errata is applicable only if you have created or updated the design using Libero ® SoC v11.1 SP1 or v11.1 SP2.The corresponding I/O does not function properly in the silicon due to the wrong software implementation of the I/O macro, if you have one of the following in the design:•If you use DDR_OUT macro in the design•If you combine an output or output enable register with an I/O using the PDC command set_io<portName> -register yesSolution:Both Errata are fixed in Libero SoC v11.1 SP3. Migrate the design to Libero SoC v11.1 SP3 or a newer version, and re-run Compile and Layout.10.Dedicated differential I/O driving the reference clock of the CCC may cause afunctional failure due to a software bugIf the design has a dedicated differential I/O pair driving the reference clock of the CCC, the input clock may not propagate to CCC due to a software bug and the device fails during silicon testing. There are several options to drive the ref clock of the CCC. One of the options is to drive from"Dedicated Input PAD x" (x = 0 to 3); this uses hardwired routing. In this option, choose single-ended I/O or differential I/O as the ref clock. This Errata exists when you choose the differential I/O option (dedicated differential I/O is used as CCC reference clock input).This Errata cannot be detected in any functional simulation, and can only be detected in silicon testing.Solution:The Errata is fixed in the Libero SoC 11.1 SP3. Migrate the design to Libero SoC 11.1 SP3 or newer version, and re-run Compile and Layout.11.NVM Ready bit in eNVM Status register can generate a false READY signalIf you send an instruction to the eNVM controller and then start polling the READY signal (bit0 of the eNVM Status register) to check when the eNVM controller is ready for the next function, the first assertion of the READY signal occurs when the eNVM controller is not yet ready, resulting in the generation of a false READY signal. However, the immediate next assertion of the READY signal correctly indicates that the eNVM controller is ready.Workaround:Add an extra eNVM Status bit read that polls/reads the eNVM Status bit twice as READY .12.Power-up Digest is not supportedWorkaround:Use NVM Data Integrity Check System service after the device is switched ON, and check the data integrity.IGLOO2 M2GL050 (T, TS) Device ErrataER0200 v1.3 April 2016513.Programming of the eNVM must only occur as part of a bitstream alsocontaining the FPGA fabricThe Bitstream Configuration Dialog Box in the Libero SoC allows the user to program eNVM and the FPGA fabric separately. However, for the current production of IGLOO2 FPGAs, the user needs to program the eNVM along with the FPGA fabric. The fabric can be programmed separately if needed.Solution:The Errata is fixed in the Libero SoC 11.1 SP3. Migrate the design to the Libero SoC 11.1 SP3 or newer version, and re-run Compile and Layout.14.Updating eNVM from the FPGA fabric requires changes in the NV_FREQRNGregisterWhen updating the eNVM from the FPGA fabric, NV_FREQRNG register must be changed from 0x07(default) to 0x0F, eNVM reads are not affected.15.SYSCTRL_RESET_STATUS macro is not supported 16.Zeroization is not supported17.PCIe Hot Reset support requires a soft reset solutionOn the IGLOO2 devices, a PCIe ® Hot Reset requires a soft FPGA logic reset scheme which clears the sticky bits of the PCI configuration space.Workaround:The application note AC437: Implementing PCIe Reset Sequence in SmartFusion2 and IGLOO2 Devices describes the PCIe Hot Reset reset scheme. However, this reset scheme causes PCIe violations in some cases.•At Gen1 rates, there are no violations.•At Gen2 rates, there are two PCIe CV violations.–Test case 1: TD_1_7 (Advanced Error Reporting Capability)–Test case 2: TD_1_41 (LinkCap2Control2Status2 Reg)18.The DDR I/Os in M2GL050 (T, TS)-FG896 are non-compliant with the DDR3standardThe DDR controller in the M2GL050-FG896 device is non-compliant with the DDR3 standard. Contact SoC tech support for additional information.19.For S (security) grade devices, user must not enable write protection forProtected 4 K Regions, also known as Special Sectors in the eNVMFor S (security) devices, there are two or four 4 KB regions per eNVM array that can be protected for read and write, these regions are known as Protected 4 K Regions or Special Sectors. If writeprotection is enabled for any of these regions, none of the locked pages inside the same eNVM block can be unlocked.6IGLOO2 M2GL050 (T, TS) Device Errata ER0200 v1.3 April 2016Usage Guidelines for IGLOO2 DevicesMicrosemi recommends the following conditions for the IGLOO2 device usage.1. Programming SupportThere may be package dependencies that may not expose certain programming interfaces. Refer to the DS0124: IGLOO2 Pin Descriptions Datasheet for device/package specific features.2. SHA-256 System ServiceMicrosemi recommends the message required to be on byte boundary when using SHA-256 System Service for the IGLOO2 devices.3. Accessing the PCIe Bridge Register in High-speed Serial InterfaceThe PCIe Bridge registers must not be accessed before the PHY is ready. Wait for the PHY_READY signal (which indicates when PHY is ready) to be asserted before updating the PCIe Bridge registers.The PHY_READY signal is normally asserted within 200 μs after the device is powered up. Wait for 200 μs before accessing the PCIe Bridge registers.Table 4: Revision 0 and Revision 1 DevicesProgramming Mode JTAG SPI Slave AutoProgramming Auto Update2 Step IAP Programming RecoveryProgramming Interface JTAG SC_SPI SC_SPI SPI_0SC_SPI SPI_0M2GL050 (T,TS)YesYesNoNoNoNoTable 5: Revision 2 DeviceProgramming Mode JTAG SPI Slave AutoProgramming Auto Update2 Step IAP Programming RecoveryProgramming Interface JTAG SC_SPI SC_SPI SPI_0SC_SPI SPI_0M2GL050 (T,TS)YesYesYesNoYesNoIGLOO2 M2GL050 (T, TS) Device ErrataER0200 v1.3 April 20167Product SupportMicrosemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services.Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization.From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world 650. 318.8044Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creatingapplication notes, answers to common design cycle questions, documentation of known Errata and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions.Technical SupportFor Microsemi SoC Products Support, visit/products/fpga-soc/design-support/fpga-soc-supportWebsiteYou can browse a variety of technical and non-technical information on the SoC home page , at /products/fpga-soc/fpga-and-soc .Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website.EmailYou can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request.The technical support email address is **********************.My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases .Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email(**********************) or contact a local sales office. Visit About Us for sales office listings and corporate contacts.8IGLOO2 M2GL050 (T, TS) Device Errata ER0200 v1.3 April 2016ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in ArmsRegulations (ITAR), contact us via **********************. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi Corporate Headquarters One Enterprise, Aliso Viejo,CA 92656 USAWithin the USA : +1 (800) 713-4113 Outside the USA : +1 (949) 380-6100Sales : +1 (949) 380-6136Fax : +1 (949) 215-4996E-mail: ***************************© 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks andservice marks are the property of their respective owners.Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services.Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at .55900200-1.3/04.16。
英语不规则名词复数表
英语不规则名词复数表一、分类1. 以f或fe结尾：大多数以f或fe结尾的名词的复数形式时将其转为ves，但个别直接加s：* roof →roofs 屋顶* gulf →gulfs 海湾* grief →griefs 悲伤, 悲痛, 担心* cliff →cliffs 悬崖, 峭壁* beef →beefs 牛肉* chief →chiefs 首长, 首领* proof →proofs 证明* staff →staffs 全体职员2. 元音：有些名称的复数形式是改变它们的元音声：* -man →-men 男……* -woman →-women 女……* fireman →firemen 消防员* foot →feet 脚* goose →geese 鹅* tooth →teeth 牙齿* mouse →mice 老鼠* louse →lice 虱子3. 古代英语：有些是沿用古代英语：* child →children 小孩, 儿童* ox →oxen 牛, 阉牛4. 以o结尾：有的以o结尾的单词加“s”：* auto →autos [美口] 汽车* kangaroo →kangaroos 袋鼠* kilo →kilos 千克, 公斤* memo →memos [口] 备忘录* photo →photos 照片* piano →pianos 钢琴* pimento →pimentos 多香果* pro →pros 赞成意见* con →cons 反对意见* solo →solos, soli 独唱, 独奏* soprano →sopranos 女高音* studio →studios 工作室* tattoo →tattoos 文身* video →videos 视频* zoo →zoos 动物园* bamboo →bamboos 竹子⌝有的则加“es”：* echo →echoes 回声, 反响* embargo →embargoes 禁运, 禁运令* hero →heroes 英雄* potato →potatoes 土豆* tomato →tomatoes 番茄* torpedo →torpedoes 鱼雷, 水雷* veto →vetoes 否决, 否决权* negro →negroes 黑人⌝有的两种都可以：* buffalo →buffalos / buffaloes / buffalo 水牛* cargo →cargos / cargoes (船/飞机的)货物* halo →halos / haloes 光环* mosquito →mosquitos / mosquitoes 蚊子* motto →mottos / mottoes 箴言, 格言* no →nos / noes 没有* tornado →tornados / tornadoes 龙卷风* volcano →volcanos / volcanoes 火山* zero →zeros / zeroes 零* commando →commands / commandoes突击员5. 不变：有的则不变：* cod →cod 鳕鱼* deer →deer 鹿* fish →fish 鱼, 鱼类* offspring →offspring 子孙, 后裔, 幼崽* perch →perch 鲈鱼* sheep →sheep 绵羊* trout →trou 鲑鱼* bison →bison 野牛* moose →moose 驼鹿* aircraft →aircraft 飞机, 飞行器* barracks →barracks 兵营* crossroads →crossroads 十字路口* dice →dice 骰子* gallows →gallows 绞刑架* headquarters →headquarters 总部* means →means 方法, 手段, 途径* series →series 系列* species →species 物种6. 借用单词：英语中有些单词是借用其他语言的。
802[1].3ae-2002_errata
![802[1].3ae-2002_errata](https://img.taocdn.com/s3/m/b190af2f7375a417866f8fad.png)
IEEE 802.3ae™-2002(Amendment to IEEE Std 802.3™2002)Corrections toIEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirementsPart 3: Carrier Sense Multiple Access withCollision Detection (CSMA/CD) Access Methodand Physical Layer SpecificationsAmendment: Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s OperationS ponsorLAN/MAN Standards Committeeof theIEEE Computer SocietyCorrection SheetIssued 20 July 2004Copyright © 2004 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 2004. Printed in the United States of America.This correction sheet may be freely reproduced and distributed in order to maintainthe utility and currency of the underlying Standard. This correction sheet may notbe sold, licensed or otherwise distributed for any commercial purposes whatso-ever. The content of this correction sheet may not be modified.4.2.7 – 4.2.9 is incorrect and should be replaced with the following 4.2.7 – 4.2.9:4.2.7 Global declarationsChange 4.2.7 and its related subclauses to read as follows:This subclause provides detailed formal specifications for the CSMA/CD MAC sublayer. It is a specification of generic features and parameters to be used in systems implementing this media access method. Subclause 4.4 provides values for these sets of parameters for recommended implementations of this media access mechanism.4.2.7.1 Common constants, types, and variablesThe following declarations of constants, types and variables are used by the frame transmission and reception sections of each CSMA/CD sublayer:constaddressSize = ... ; {48 bits in compliance with 3.2.3}addressSize = 48; {In bits, in compliance with 3.2.3}lengthOrTypeSize = 16; {iIn bits}clientDataSize = ...; {in bits, MAC client Data, see 4.2.2.2, (1)(c)}clientDataSize = ...; {In bits, size of MAC client data; see 4.2.2.2, a) 3)}padSize = ...; {iIn bits, = max (0, minFrameSize – (2 x addressSize + lengthOrTypeSize +clientDataSize + crcSize))} dataSize = ...; {iIn bits, = clientDataSize + padSize}crcSize = 32; {In bits, 32-bit CRC = 4 octets}frameSize = ...; {in bits, = 2 x addressSize + lengthOrTypeSize + dataSize + crcSize, see 4.2.2.2, (1)}frameSize = ...; {In bits, = 2 x addressSize + lengthOrTypeSize + dataSize + crcSize; see 4.2.2.2, a)}minFrameSize = ... ; {iIn bits, implementation-dependent, see 4.4}maxUntaggedFrameSize = ... ; {iIn octets, implementation-dependent, see 4.4}qTagPrefixSize = 4; {iIn octets, length of QTag Prefix, see 3.5}extend = ...; {Boolean, true if (slotTime – minFrameSize) > 0, false otherwise}extensionBit = ...; {aA nondata value which is used for carrier extension and interframe during bursts}extensionErrorBit = ...; {aA nondata value which is used to jam during carrier extension}minTypeValue = 1536; {mMinimum value of the Length/Type field for Type interpretation}maxValidFrame = maxUntaggedFrameSize – (2 x addressSize + lengthOrTypeSize + crcSize) / 8;{iIn octets, the maximum length of the MAC client data field. This constant isdefined for editorial convenience, as a function of other constants}slotTime = ... ; {In bit times, unit of time for collision handling, implementation-dependent, see 4.4}preambleSize = ...; {56 bits, see 4.2.5}preambleSize = 56; {In bits, see 4.2.5}sfdSize = 8; {8 bitIn bits, start frame delimiter}headerSize = ...; {64 bits, sum of preambleSize and sfdSize}headerSize = 64; {In bits, sum of preambleSize and sfdSize}typeBit = 0..1(0, 1);PhysicalBit = 0,1, extensionBit, extensionErrorBit(0, 1, extensionBit, extensionErrorBit);{bBits transmitted to the Physical Layer can be either 0, 1, extensionBit orextensionErrorBit. Bits received from the Physical Layer can be either 0, 1or extensionBit.}AddressValue = array [1..addressSize] of Bit;LengthOrTypeValue = array [1..lengthOrTypeSize] of Bit;DataValue = array [1..dataSize] of Bit; {Contains the portion of the frame that starts with the first bitfollowing the Length/Type field and ends with the last bitprior to the FCS field. For VLAN Tagged frames, this valueincludes the Tag Control Information field and the originalMAC client Length/Type field. See 3.5}CRCValue = array [1..crcSize] of Bit;PreambleValue = array [1..preambleSize] of Bit;SfdValue = array [1..sfdSize] of Bit;ViewPoint = (fields, bits); {Two ways to view the contents of a frame}HeaderViewPoint = (headerFields, headerBits);Frame = record {Format of Media Access frame}case view: ViewPoint offields: (destinationField: AddressValue;sourceField: AddressValue;lengthOrTypeField: LengthOrTypeValue;dataField: DataValue;fcsField: CRCValue);bits: (contents: array [1..frameSize] of Bit)end; {Frame}Header = record {Format of preamble and start frame delimiter}case headerView : HeaderViewPoint ofheaderFields : (preamble : PreambleValue;sfd : SfdValue);headerBits : (headerContents : array [1..headerSize] of Bit)headerBits: (headerContents: array [1..headerSize] of Bit)end; {dDefines header for MAC frame}varhalfDuplex: Boolean; {Indicates the desired mode of operation. halfDuplex is a static variable; its valueshall only be changed by the invocation of the Initialize procedure}its value does not change between invocations of the Initialize procedure}4.2.7.2 Transmit state variablesThe following items are specific to frame transmission. (See also 4.4.)constinterFrameSpacing = ... ; {In bit times, minimum time gap between frames. Equal to interFrameGap,see 4.4}interFrameSpacingPart1 = ... ; {In bit times, duration of the first portion of interFrameSpacing. In therange of 0 up to 2/3 of interFrameSpacing}interFrameSpacingPart2 = ... ; {In bit times, duration of the remainder of interFrameSpacing. Equal tointerFrameSpacing – interFrameSpacingPart1}interFrameSize = ... ; {in bits, length of interframe fill during a burst. Equal to interFrameGapdivided by the bit period}ifsStretchRatio = ...; {In bits, determines the number of bits in a frame that require one octet ofinterFrameSpacing extension, when ifsStretchMode is enabled; implementationdependent, see 4.4}attemptLimit = ... ; {Max number of times to attempt transmission}backOffLimit = ... ; {Limit on number of times to back off}burstLimit= ... ; {in bits: LimitIn bits, limit for initiation of frame transmission in Burst Mode,implementation dependent, see 4.4}jamSize = ... ; {in bits:In bits, the value depends upon medium and collision detect implementation} varoutgoingFrame: Frame; {The frame to be transmitted}outgoingHeader: Header;currentTransmitBit, lastTransmitBit: 1..frameSize; {Positions of current and last outgoing bits inoutgoingFrame}lastHeaderBit: 1..headerSize;deferring: Boolean; {Implies any pending transmission must wait for the medium to clear}frameWaiting: Boolean; {Indicates that outgoingFrame is deferring}attempts: 0..attemptLimit; {Number of transmission attempts on outgoingFrame}newCollision: Boolean; {Indicates that a collision has occurred but has not yet been jammed}transmitSucceeding: Boolean; {Running indicator of whether transmission is succeeding}burstMode: Boolean:; {Indicates the desired mode of operation, and enables the transmission ofmultiple frames in a single carrier event. burstMode is a static variable; itsvalue does not change between invocations of the Initialize procedure.}value shall only be changed by the invocation of the Initialize procedure} bursting: Boolean; {In burstMode, the given station has acquired the medium and the burst timer hasnot yet expired}burstStart: Boolean; {In burstMode, indicates that the first frame transmission is in progress}extendError: Boolean; {Indicates a collision occurred while sending extension bits}ifsStretchMode: Boolean; {Indicates the desired mode of operation, and enables the lowering of theaverage data rate of the MAC sublayer (with frame granularity), usingextension of the minimum interFrameSpacing. ifsStretchMode is a staticvariable; its value shall only be changed by the invocation of the Initializeprocedure}ifsStretchCount: 0..ifsStretchRatio; {In bits, a running counter that counts the number of bits during aframe’s transmission that are to be considered for the minimuminterFrameSpacing extension, while operating in ifsStretchMode} ifsStretchSize: 0..(((maxUntaggedFrameSize + qTagPrefixSize) x 8 + headerSize + interFrameSpacing + ifsStretchRatio – 1) div ifsStretchRatio);{In octets, a running counter that counts the integer number of octets that are to beadded to the minimum interFrameSpacing, while operating in ifsStretchMode}4.2.7.3 Receive state variablesThe following items are specific to frame reception. (See also 4.4.)varincomingFrame: Frame; {The frame being received}receiving: Boolean; {Indicates that a frame reception is in progress}excessBits: 0..7; {Count of excess trailing bits beyond octet boundary}receiveSucceeding: Boolean; {Running indicator of whether reception is succeeding}validLength: Boolean; {Indicator of whether received frame has a length error}exceedsMaxLength: Boolean; {Indicator of whether received frame has a length longer than themaximum permitted length}extending: Boolean; {Indicates whether the current frame is subject to carrier extension}extensionOK: Boolean; {Indicates whether any bit errors were found in the extension part of a frame,which is not checked by the CRC}passReceiveFCSMode: Boolean; {Indicates the desired mode of operation, and enables passing ofthe frame check sequence field of all received frames from theMAC sublayer to the MAC client. passReceiveFCSMode is astatic variable}4.2.7.4 Summary of interlayer interfacesa)The interface to the MAC client, defined in 4.3.2, is summarized below:typeTransmitStatus = (transmitDisabled, transmitOK, excessiveCollisionError, lateCollisionErrorStatus);{Result of TransmitFrame operation, reporting of lateCollisionErrorStatus isoptional for MACs operating at speeds at or below 100Mb/s}ReceiveStatus = (receiveDisabled, receiveOK, frameTooLong, frameCheckError, lengthError,alignmentError); {Result of ReceiveFrame operation}function TransmitFrame (destinationParam: AddressValue;sourceParam: AddressValue;lengthOrTypeParam: LengthOrTypeValue;dataParam: DataValue): TransmitStatus; {Transmits one frame}dataParam: DataValue;fcsParamValue: CRCValue;fcsParamPresent: Bit): TransmitStatus; {Transmits one frame}function ReceiveFrame (var destinationParam: AddressValue;var sourceParam: AddressValue;var lengthOrTypeParam: LengthOrTypeValue;var dataParam: DataValue): ReceiveStatus; {Receives one frame}var dataParam: DataValue;var fcsParamValue: CRCValue;var fcsParamPresent: Bit): ReceiveStatus; {Receives one frame}b)The interface to the Physical Layer, defined in 4.3.3, is summarized in the following:varreceiveDataValid: Boolean; {Indicates incoming bits}carrierSense: Boolean; {In half duplex mode, indicates that transmission should defer}transmitting: Boolean; {Indicates outgoing bits}collisionDetect: Boolean; {Indicates medium contention}procedure TransmitBit (bitParam: PhysicalBit); {Transmits one bit}function ReceiveBit: PhysicalBit; {Receives one bit}procedure Wait (bitTimes: integer); {Waits for indicated number of bit times}4.2.7.5 State variable initializationThe procedure Initialize must be run when the MAC sublayer begins operation, before any of the processes begin execution. Initialize sets certain crucial shared state variables to their initial values. (All other global variables are appropriately reinitialized before each use.) Initialize then waits for the medium to be idle, and starts operation of the various processes.NOTE—Care should be taken to ensure that the time from the completion of the Initialize process to when the first packet transmission begins is at least an interFrameGap.If Layer Management is implemented, the Initialize procedure shall only be called as the result of the initializeMAC action (30.3.1.2.1).procedure Initialize;begin beginframeWaiting := false;deferring := false;newCollision := false;transmitting := false; {IAn interface to Physical Layer; see below}receiving := false;halfDuplex := ...; {tTrue for half duplex operation, false for full duplex operation. For operation atspeeds above 1000 Mb/s, halfDuplex shall always be false}halfDuplex is a staticvariable; its value does not change between invocations of the Initialize bursting := false;burstMode := ...; { tTrue for half duplex operation at speeds above 100 Mb/s an operating speed of 1000Mb/s, when multiple frames’ transmission in a single carrier event is desired andsupported, false otherwise}. burstMode is a static variable; its value does not changebetween invocations of the Initialize procedure}extending := extend and and halfDuplex;ifsStretchMode := ...; {True for operating speeds above 1000 Mb/s when lowering the average data rateof the MAC sublayer (with frame granularity) is desired and supported, falseotherwise}ifsStretchCount := 0;ifsStretchSize := 0;passReceiveFCSMode := ...; {True when enabling the passing of the frame check sequence of allreceived frames from the MAC sublayer to the MAC client is desired andsupported, false otherwise}while carrierSense or receiveDataValid do nothingif halfDuplex then while carrierSense or receiveDataValid do nothingelse while receiveDataValid do nothing{Start execution of all processes}end; {Initialize}4.2.8 Frame transmissionChange subclause 4.2.8 to read as follows:The algorithms in this subclause define MAC sublayer frame transmission. The function TransmitFrame implements the frame transmission operation provided to the MAC client:function TransmitFrame (destinationParam: AddressValue;sourceParam: AddressValue;lengthOrTypeParam: LengthOrTypeValue;dataParam: DataValue): TransmitStatus;dataParam: DataValue;fcsParamValue: CRCValue;fcsParamPresent: Bit): TransmitStatus;procedure TransmitDataEncap; ... {n{Nested procedure; see body below}beginif transmitEnabled thenbeginTransmitDataEncap;TransmitFrame := TransmitLinkMgmtendelse TransmitFrame := transmitDisabledend; {TransmitFrame}If transmission is enabled, TransmitFrame calls the internal procedure TransmitDataEncap to construct the frame. Next, TransmitLinkMgmt is called to perform the actual transmission. The TransmitStatus returned indicates the success or failure of the transmission attempt.TransmitDataEncap builds the frame and places the 32-bit CRC in the frame check sequence field:procedure TransmitDataEncap;beginwith outgoingFrame dobegin {aAssemble frame}view := fields;destinationField := destinationParam;sourceField := sourceParam;lengthOrTypeField := lengthOrTypeParam;dataField := ComputePad (dataParam);fcsField := CRC32(outgoingFrame);if fcsParamPresent thenbegindataField := dataParam; {No need to generate pad if the FCS is passed from MAC client}fcsField := fcsParamValue {Use the FCS passed from MAC client}endelsebegindataField := ComputePad(dataParam);fcsField := CRC32(outgoingFrame)end;view := bitsend {aAssemble frame}with outgoingHeader dobeginheaderView := headerFields;preamble := ...; {* ‘1010...10,’ LSB to MSB*}sfd := ...; {* ‘10101011,’ LSB to MSB*}headerView := headerBitsendend; {TransmitDataEncap}If the MAC client chooses to generate the frame check sequence field for the frame, it passes this field to the MAC sublayer via the fcsParamValue parameter. If the fcsParamPresent parameter is true, TransmitDataEncap uses the fcsParamValue parameter as the frame check sequence field for the frame. Such a frame shall not require any padding, since it is the responsibility of the MAC client to ensure that the frame meets the minFrameSize constraint. If the fcsParamPresent parameter is false, the fcsParamValue parameter is unspecified.TransmitDataEncap first calls the ComputePad function, followed by a call to the CRC32 function to generate the padding (if necessary) and the frame check sequence field for the frame internally to the MAC sublayer.ComputePad appends an array of arbitrary bits to the MAC client data to pad the frame to the minimum frame size.: function ComputePad(var dataParam: DataValue): DataValue;beginComputePad := {Append an array of size padSize of arbitrary bits to the MAC client dataField} end; {ComputePadParam}function ComputePad(var dataParam: DataValue): DataValue;beginComputePad := {Append an array of size padSize of arbitrary bits to the MAC client dataField} end; {ComputePad}TransmitLinkMgmt attempts to transmit the frame. In half duplex mode, it first defers to any passing traffic. In half duplex mode, if a collision occurs, transmission is terminated properly and retransmission is scheduled following a suitable backoff interval:function TransmitLinkMgmt: TransmitStatus;beginattempts := 0;transmitSucceeding := false;lateCollisionCount := 0;deferred := false; {iInitialize}excessDefer := false;while (attempts < attemptLimit) and (not transmitSucceeding)and (not extend or lateCollisionCount = 0) do{nNo retransmission after late collision if operating at > 100 1000 Mb/s} begin {lLoop}if bursting then {tThis is a burst continuation}frameWaiting := true {sStart transmission without checking deference}else {nNon bursting case, or first frame of a burst}beginif attempts > 0 then BackOff;if halfDuplex then frameWaiting := true;frameWaiting := true;while deferring do {dDefer to passing frame, if any1}if halfDuplex then deferred := true;beginnothing;‡if halfDuplex then deferred := trueend;burstStart := true;if burstMode then bursting := trueend;lateCollisionError := false;StartTransmit;frameWaiting := false;if halfDuplex thenbeginframeWaiting := false;1. The Deference process ensures that the reception of traffic does not cause deferring to be true when in full duplex mode. Deferring is used in full duplex mode to enforce the minimum interpacket gap spacing.while transmitting do WatchForCollision;if lateCollisionError then lateCollisionCount := lateCollisionCount + 1;lateCollisionCount := lateCollisionCount + 1;attempts := attempts + 1end {hHalf duplex mode}else while transmitting do nothing {fFull duplex mode}end; {lLoop}LayerMgmtTransmitCounters; {uUpdate transmit and transmit error counters in 5.2.4.2}if transmitSucceeding thenbeginif burstMode then burstStart := false; {Can’t be the first frame anymore}TransmitLinkMgmt := transmitOKendelse if (extend and lateCollisionCount > 0) then TransmitLinkMgmt := lateCollisionErrorStatus;TransmitLinkMgmt := lateCollisionErrorStatus;else TransmitLinkMgmt := excessiveCollisionErrorend; {TransmitLinkMgmt}Each time a frame transmission attempt is initiated, StartTransmit is called to alert the BitTransmitter process that bit transmission should begin:procedure StartTransmit;begincurrentTransmitBit := 1;lastTransmitBit := frameSize;transmitSucceeding := true;transmitting := true;lastHeaderBit: = := headerSizeend; {StartTransmit}In half duplex mode, TransmitLinkMgmt monitors the medium for contention by repeatedly calling WatchForCollision, once frame transmission has been initiated:procedure WatchForCollision;beginif transmitSucceeding and collisionDetect thenbeginif currentTransmitBit > (slotTime –headerSize) then lateCollisionError := true;lateCollisionError := true;newCollision := true;transmitSucceeding := false;if burstMode thenbegin:=false;burstingif not burstStart thenlateCollisionError := true {Every collision is late, unless it hits the first frame in a burst} endendend; {WatchForCollision}WatchForCollision, upon detecting a collision, updates newCollision to ensure proper jamming by the BitTransmitter process. The current transmit bit number is checked to see if this is a late collision. If the collision occurs later than a collision window of slotTime bits into the packet, it is considered as evidence of a late collision. The point at which the collision is received is determined by the network media propagation time and the delay time through a station and, as such, is implementation-dependent (see 4.1.2.2). While operating at speeds of 100 Mb/s or lower, an implementation may optionally elect to end retransmission attempts after a late collision is detected. While operating at speeds above 100 Mb/s the speed of 1000 Mb/s, an implementation shall end retransmission attempts after a late collision is detected.After transmission of the jam has been completed, if TransmitLinkMgmt determines that another attempt should be made, BackOff is called to schedule the next attempt to retransmit the frame.function Random (low, high: integer): integer;beginRandom := ...{uUniformly distributed random integer r, such that low ≤ r < high}end; {Random}BackOff performs the truncated binary exponential backoff computation and then waits for the selected multiple of the slot time.:var maxBackOff: 2..1024; {Working variable of BackOff}procedure BackOff;beginif attempts = 1 then maxBackOff := 2else if attempts ≤ backOffLimit then maxBackOff := maxBackOff x 2;Wait(slotTime x Random(0, maxBackOff))end; {BackOff}BurstTimer is a process that does nothing unless the bursting variable is true. When bursting is true, BurstTimer increments burstCounter until the burstLimit limit is reached, whereupon BurstTimer assigns the value false to bursting.:process BurstTimer;var burstCounter: integer;begincyclewhile not bursting do nothing; {wait for a burst}burstCounter := 0;while bursting and (burstCounter < burstLimit) dobeginWait(1);burstCounter := burstCounter + 1end;bursting := falseend {burstMode cycle}end; {BurstTimer}process BurstTimer;begincyclewhile not bursting do nothing; {Wait for a burst}Wait(burstLimit);bursting := falseend {burstMode cycle}end; {BurstTimer}The Deference process runs asynchronously to continuously compute the proper value for the variable deferring. In the case of half duplex burst mode, deferring remains true throughout the entire burst. Interframe spacing may be used to lower the average data rate of a MAC at operating speeds above 1000 Mb/s in the full duplex mode, when it is necessary to adapt it to the data rate of a WAN-based physical layer. When interframe stretching is enabled, deferring remains true throughout the entire extended interframe gap, which includes the sum of interFrameSpacing and the interframe extension as determined by the BitTransmitter:process Deference;var realTimeCounter: integer; wasTransmitting: Boolean;beginif halfDuplex then cycle{hHalf duplex loop}while not carrierSense do nothing; {wWatch for carrier to appear}deferring := true; {dDelay start of new transmissions}wasTransmitting := transmitting;while carrierSense or transmitting do wasTransmitting := wasTransmitting or transmitting;wasTransmitting: = wasTransmitting or transmitting;if wasTransmitting then Wait(interFrameSpacingPart1) {Time out first part of interframe gap} beginStartRealTimeDelay; {time out first part interframe gap}while RealTimeDelay(interFrameSpacingPart1) do nothingendelsebeginStartRealTimeDelay;repeatwhile carrierSense do StartRealTimeDelayuntil not RealTimeDelay(interFrameSpacingPart1)realTimeCounter := interFrameSpacingPart1;repeatwhile carrierSense do realTimeCounter := interFrameSpacingPart1;Wait(1);realTimeCounter := realTimeCounter – 1until (realTimeCounter = 0)end;StartRealTimeDelay; {time out second part interframe gap}while RealTimeDelay(interFrameSpacingPart2) do nothing;Wait(interFrameSpacingPart2); {Time out second part of interframe gap}deferring: = := false; {aAllow new transmissions to proceed}while frameWaiting do nothing {aAllow waiting transmission, if any}end {hHalf duplex loop}else cycle {fFull duplex loop}while not transmitting do nothing; {wWait for the start of a transmission}deferring := true; {iInhibit future transmissions}while transmitting do nothing; {wWait for the end of the current transmission}StartRealTimeDelay; {time out an interframe gap}while RealTimeDelay(interFrameSpacing) do nothing;Wait(interFrameSpacing + ifsStretchSize x 8); {Time out entire interframe gap and IFS extension}if not frameWaiting then {Don’t roll over the remainder into the next frame}beginWait(8);ifsStretchCount := 0enddeferring := false {dDon’t inhibit transmission}end {fFull duplex loop}end; {Deference}If the ifsStretchMode is enabled, the Deference process continues to enforce interframe spacing for an additional number of bit times, after the completion of timing the interFrameSpacing. The additional number of bit times is reflected by the variable ifsStretchSize. If the variable ifsStretchCount is less than ifsStretchRatio and the next frame is ready for transmission (variable frameWaiting is true), the Deference process enforces interframe spacing only for the integer number of octets, as indicated by ifsStretchSize, and saves ifsStretchCount for the next frame’s transmis-sion. If the next frame is not ready for transmission (variable frameWaiting is false), then the Deference process ini-tializes the ifsStretchCount variable to zero.procedure StartRealTimeDelaybegin{reset the realtime timer and start it timing}end; {StartRealTimeDelay}function RealTimeDelay (µsec:real): Boolean;begin{return the value true if the specified number of microseconds havenot elapsed since the most recent invocation of StartRealTimeDelay,otherwise return the value false}end; {RealTimeDelay}The BitTransmitter process runs asynchronously, transmitting bits at a rate determined by the Physical Layer’s Trans-mitBit operation:process BitTransmitter;begincycle {oOuter loop}if transmitting thenbegin {iInner loop}extendError := false;if ifsStretchMode then {Calculate the counter values}beginifsStretchSize := (ifsStretchCount + headerSize + frameSize + interFrameSpacing) divifsStretchRatio; {Extension of the interframe spacing}ifsStretchCount := (ifsStretchCount + headerSize + frameSize + interFrameSpacing)mod ifsStretchRatio {Remainder to carry over into the next frame’s transmission} end;PhysicalSignalEncap; {Send preamble and start of frame delimiter}while transmitting dobeginif (currentTransmitBit > lastTransmitBit) then TransmitBit(extensionBit)else if extendError then TransmitBit(extensionErrorBit) {Jam in extension}if extendError thenTransmitBit(extensionErrorBit) {jam in extension}else TransmitBit(outgoingFrame[currentTransmitBit]);TransmitBit(outgoingFrame[currentTransmitBit]);if newCollision then StartJam else NextBitend;if bursting thenbegin。
ULPI_v1_0 Errata
Errata to “UTMI+ Low Pin Interface Specification Revision 1.0” This document lists the fixes, clarifications, and additions required to the ULPI Specification, Revision 1.0. Each errata has a sequence number and a type. An explanation of the types is given in Table 1. Changes to text in the ULPI specification are highlighted in red. Check the website for the latest errata.Errata Type Errata Type DescriptionFix Fixes a problem in the specification. The purpose of a fix is to correctspecification behavior that would otherwise cause a failure.Clarification Clarifies existing behavior in the specification. The purpose of a clarification is toexpand the existing description, providing further information for implementers. Addition Adds new behavior to the specification. The purpose of an addition is to detailnew and optional functionality.Table 1 – Errata typesErrata 01 – Incorrect hold time numbers (2)Errata 02 – Sending RX CMDs during USB packet transmit and receive (3)Errata 03 – De-assertion of dir when exiting FS/LS Serial Mode (4)Errata 04 – Control and monitoring of internal charge pump and external V BUS supplies (5)Errata 05 – How to send Test_J and Test_K signaling / Updated Table 34 (10)Errata 06 – SuspendM setting when exiting Low Power Mode (12)Errata 07 – Validity of hostdisconnect in Low Power Mode (13)Errata 08 – Enabling detection of the ID pin (14)Errata 09 – Clarifications on HS SOF packets (15)Errata 10 – Power Control of Interrupt Sources (16)Errata 11 – Enabling Interrupts in Low Power, Serial, and Carkit Modes (17)Errata 12 – Carkit data during audio (18)Errata 13 – Protecting the PHY when the link tri-states stp and data (21)Errata 14 – Corrections for OpMode=11b (No SYNC/EOP generation) (25)Errata 15 – Increased RXCMD delay when LineState indicates SE0 (26)Errata 16 – Clock and SuspendM behavior during AutoResume (27)Errata 17 – OpMode typo in 3.8.5.1 (29)Errata 18 – Host PHY must first detect peripheral resume-K before transmitting automatic Resume-K30 Errata 19 – Section 3.9.3 “Exiting Low Power Mode” makes incorrect reference to 3.8.5.4.4 “Autoresume” (31)Errata 01 – Incorrect hold time numbersType:Fix.Issue:The hold time numbers given in Table 5 were calculated wrongly, and given the wrong polarity.Resolution:The correct numbers must be given in Table 5.Documentation Changes:Table 5 must be replaced with the table below to update the hold time numbers.UnitsMaxMinParameter SymbolOutput clockSetup time (control in, 8-bit data in) T SC, T SD 6.0 nsHold time (control in, 8-bit data in) T HC, T HD 0.0 nsOutput delay (control out, 8-bit data out) T DC, T DD9.0 nsnsSetup time (4-bit data in) (optional) T SDD 3.0Hold time (4-bit data in) (optional) T HDD-0.8 nsOutput delay (4-bit data out) (optional) T DDD 4.0nsInput clock (optional)Setup time (control in, 8-bit data in) T SC, T SD 3.0 nsHold time (control in, 8-bit data in) T HC, T HD 1.5 nsOutput delay (control out, 8-bit data out) T DC, T DD 6.0 nsnsSetup time (4-bit data in) T SDD 2.5Hold time (4-bit data in) T HDD0.8 nsnsOutput delay (4-bit data out) T DDD 3.5Table 5 – ULPI Interface TimingErrata 02 – Sending RX CMDs during USB packet transmit and receive Type:Clarification.Issue:It is not clear what the PHY should do when an RX CMD needs to be sent when the ULPI bus is carrying USB transmit or receive data.Resolution:An RX CMD should never abort USB transmit or receive data. Instead, the PHY must flag the RX CMD internally and send an RX CMD when nxt is de-asserted or when the receive packet has completed. Documentation Changes:For clarification on USB packet receive, the following text should be appended to the end of paragraph 1 in section 3.8.2.4.“All RX CMD changes during the USB packet receive must be signaled when nxt is low. If nxt is never low during the packet receive, all RX CMD changes must be replaced with a single RX CMD update that is sent at the end of the USB packet receive, when the ULPI bus is available. The RX CMD update must always convey the current RX CMD values, not a previous or old value.”Similarly, text in the USB packet transmit sections 3.8.2.1 and 3.8.2.2 should also be updated to reflect the text below.“All RX CMD changes during the USB packet transmit must be replaced with a single RX CMD update that is sent at the end of the USB transmit, when the ULPI bus is available. The RX CMD update must always convey the current RX CMD values, not a previous or old value.”Errata 03 – De-assertion of dir when exiting FS/LS Serial ModeType:Clarification.Issue:In section 3.10.3 “Exiting FsLsSerialMode”, the text describing the de-assertion of dir when exiting serial mode with the clock running is wrong, and does not match Figure 52. This also applies to exiting Carkit mode, where it is defined that “Entering and exiting Carkit mode is identical to Serial mode”. Resolution:The dir signal does not need to be de-asserted in the cycle after the link asserts stp to exit serial mode, but can be de-asserted 1 or more cycles after the link asserts stp.Documentation Changes:The second paragraph in section 3.10.3 should be replaced with the text below. Figure 53 should be replaced with the figure below.“If the clock is running, the Link signals the PHY to exit FsLsSerialMode by asserting stp. The PHY will de-assert dir1 or more cycles after it detects stp asserted, as shown in Figure 53. The Link de-asserts stp in the cycle following the de-assertion of dir. Like Low Power Mode, there is a single cycle of bus turnaround on data in the cycle following the de-assertion of dir. During the turnaround cycle, the value on data is not valid. The PHY stops driving the serial mode signals immediately before the turnaround cycle.”Errata 04 – Control and monitoring of internal charge pump and external V BUS suppliesType:Fix, clarification, and addition.Issue:Control of the internal V BUS charge pump or external V BUS supply causes an unnecessary burden on link hardware. Also, when the V BUS supply is external to the PHY, it is not clear how the Link is informed whenV BUS has an over-current condition.Resolution:This issue applies only to controllers with host capability.For control of the V BUS source, the definition of DrvVbus and DrvVbusExternal can be simplified, leading to a more practical link architecture.For monitoring an external V BUS supply, the external V BUS valid or fault indicator should be routed to an input pin on the PHY, replacing any internal V A_VBUS_VLD comparator. This removes the need for extra pins on the link and keeps all V BUS indicators in-band to the ULPI bus.Documentation Changes:This change effects the external pin descriptions, the OTG Operations section and the Immediate Register Set description.The following paragraphs and table should replace the paragraph titled DrvVbusExternal in section 3.3. The optional VbusValidExternal pin should also be shown on Figure 5.DrvVbusExternal and ExternalVbusIndicatorThe PHY may optionally control an external V BUS power source via the optional pin DrvVbusExternal. For example, the external supply could be a charge pump or 5V power supply controlled using a power switch. The external supply is controlled by the DrvVbus and the optional DrvVbusExternal bits in the OTG Control register. The polarity of the DrvVbusExternal output pin is implementation dependent.If control of an external V BUS source is provided the PHY may optionally provide for a V BUS power source feed back signal on the optional pin ExternalVbusIndicator. If this pin is provided, the use of the pin is defined by the optional control bits in the OTG Control and Interface Control registers. See Section 3.8.6.3 for further detail.The following text will be appended to section 3.8.6.Vbus Power Control (internal and external)The link turns on V BUS by setting the DrvVbus bit in the OTG Control Register. If the Vbus supply is external to the PHY, the link sets DrvVbus and the optional DrvVbusExternal bit in the OTG Control register. TheV BUS control settings are detailed in Table XX.DrvVbus DrvExternalVbus Power Source used0 X Internal and external V BUS power sources disabled.1 0V BUS charge pump enabled.Internal1 1 External 5V V BUS supply enabled.Table XX – OTG Control register power control bitsSection 3.8.6.3 will be replaced with the following text, table, and figure.Vbus Comparator ThresholdsIf the V BUS power supply is external to the PHY, and the external supply provides a signal indicating when V BUS is valid, it is recommended that this signal be an input to the PHY on an optional pin ExternalVbusIndicator, and that the state of that pin be reflected to the Link via the V A_VBUS_VLD ≤V BUS indication in the RX CMD byte. The optional UseExternalVbusIndicator bit in the OTG Control register selects between the internal and external VbusValid indicators.To support industry standard USB power control devices, the PHY may optionally support two additional bits in the Interface Control register, IndicatorPassThru and IndicatorComplement. These two bits allow the optional ExternalVbusIndicator pin to interoperate with either a power valid signal or an over-current fault output from the power control device, and to adapt to either active high or active low signals from the power control device. When a power fault signal is provided on the ExternalVbusIndicator pin, the PHY must use a logical combination of the output from the internal VbusValid comparator and the external power fault signal to generate the V A_VBUS_VLD ≤V BUS indication. Table YY defines the use of the UseExternalVbusIndicator, IndicatorPassThru and IndicatorComplement register bits to control the use of the ExternalVbusIndicator input pin and the internal VbusValid comparator output to generate theV A_VBUS_VLD ≤V BUS indication in the RX CMD byte. Table YY also indicates typical applications of each setting. Figure YY provides a graphical representation of the logical combination of the internal and external VbusValid sources, and how the control register bits effect the V A_VBUS_VLD ≤V BUS indication in the RX CMD byte. The UseExternalVbusIndicator, IndicatorPassThru and IndicatorComplement control register bits are individually optional. The PHY may implement any combination of the optional control bits, however, if the control bits are implemented they must provide the function defined in Table YY. If any of the control bits are not implemented it is the responsibility of the PHY to define how the optional ExternalVbusIndicator pin effects the state of the V A_VBUS_VLD ≤V BUS indication in the RX CMD byte.Typical Application UseExternalVbusIndicatorIndicatorPassThruIndicatorComplementRxCmd V BUS Valid source0 don’t care don’t care Internal V A_VBUS_VLD comparator.1 1 0 External active high V A_VBUS_VLD signal.1 1 1 External active low V A_VBUS_VLD_Nsignal.1 0 1 External active high power fault signalqualified with internal V A_VBUS_VLDcomparator.OTG Device1 0 0 External active low power fault signalqualified with internal V A_VBUS_VLDcomparator.1 1 0 External active high power fault signal. Standard Host1 1 1 External active low power fault signal.StandardPeripheral0 don’t care don’t care Internal V A_VBUS_VLD comparator.1Table YY – RxCmd V BUS Valid over-current conditions1 A standard peripheral should not use Vbus Valid to begin operation. The internal VbusValid may not indicate Vbus is valid on the 5th hub tier, which is allowed to be as low as 4.375V. Therefore the peripheral should use Session Valid.Figure YY – RxCmd V A_VBUS_VLD ≤V BUS indication sourceDepending on the application, the link should enable or disable the appropriate Vbus interrupts. Example settings for typical applications are given in Table ZZ.Application VbusValid2 SessValid SessEndStandard Host Yes No NoStandard Peripheral No Yes NoOTG A-Device Yes Yes NoOTG B-Device No Yes YesTable ZZ – Vbus indicators in the RXCMD required for typical applications2 The VbusValid indicator in the RXCMD comes from either the internal VbusValid comparator, or the external Vbus indicator input.A new register bit is defined in the OTG Control register replacing reserved bit 7 as follows:Field name Bit Access Reset DescriptionUseExternal VbusIndicator 7 rd/wr/s/c 0b Tells the PHY to use an external V BUS over-currentindicator. This bit is optional. Refer to 3.8.6.3.0b: Use the internal OTG comparator (V A_VBUS_VLD)or internal V BUS valid indicator (default).1b: Use external V BUS valid indicator signalTwo new register bits are defined in the Interface Control register replacing reserved bits 5 and 6 as follows:Field name Bit Access Reset Description IndicatorComplement 5 rd/wr/s/c 0b Tells the PHY to invert the ExternalVbusIndicatorinput signal, generating the Complement Output.Refer to 3.8.6.3 and Figure YY for more details.0b: PHY will not invert ExternalVbusIndicator signal(default).1b: PHY will invert ExternalVbusIndicator signal.IndicatorPassThru 6 rd/wr/s/c 0b Controls whether the Complement Output is qualifiedwith the Internal VbusValid comparator before beingused in the Vbus State in the RXCMD. Refer to 3.8.6.3and Figure YY for more details.0b: Complement Output signal is qualified with theInternal VbusValid comparator.1b: Complement Output signal is not qualified with theInternal VbusValid comparator.The DrvVbus and DrvVbusExternal are redefined in the OTG Control register as follows.Field name Bit Access Reset DescriptionDrvVbus 5 rd/wr/s/c 0b Signals the internal charge pump or external supply todrive 5V on Vbus.0b : do not drive Vbus(default).1b : drive 5V on VbusDrvVbusExternal 6 rd/wr/s/c 0b Selects between the internal and the external 5V Vbussupply. This bit is optional and does not need to bepresent if only one Vbus power source is supported.0b : Drive Vbus using the internal charge pump(default). Support of an internal charge pump isoptional.1b : Drive Vbus using external supply. Support of anexternal Vbus power source is optional.The following change will be made to the Vbus State bits in the RXCMD byte definition in 3.8.1.2.Encoded Vbus Voltage stateValue V BUS Voltage SessEnd SessValid VbusValid 300 V BUS < V B_SESS_END 1 0 0 01 V B_SESS_END ≤ V BUS < V SESS_VLD 0 0 0 10 V SESS_VLD ≤ V BUS < V A_VBUS_VLDX1 03:2 Vbus State11V A_VBUS_VLD ≤ V BUSX X 13The VbusValid indicator in the RXCMD comes from either the internal VbusValid comparator, or the external Vbusindicator input.Errata 05 – How to send Test_J and Test_K signaling / Updated Table 34Type:Clarification.Issue:It is not clear how a ULPI PHY can send Test_J and Test_K signaling, as required by USB section 7.1.20.Also, the contents of Table 34 (Signalling Modes) are difficult to read and are causing confusion for implementers.Resolution:For peripherals, Test_J and Test_K signalling is already detailed in UTMI section 5.16.1. The link controller places the PHY into HS mode, and disables bit stuffing and NRZI encoding. The link controller then transmits a constant stream of 1’s to generate the Test_J, or a constant stream of 0’s to generate the Test_K. The same applies to peripheral, host, and OTG devices.The contents of Table 34 should be clarified using groupings.Documentation Changes:The following changes should be made to Table 34 in section 4.4.Register SettingsResistor Settings Signalling modeX c v r S e l e c tT e r m S e l e c tO p M o d eD p P u l l d o w nD m P u l l d o w n r p u _d p _e nr p u _d m _e nr p d _d p _e nr p d _d m _e n h s t e r m _e nGeneral Settings Tristate DriversXXb Xb01b XbXb0b 0b 0b 0b 0b Power-up or Vbus < Vth(SESSEND ) 01b 0b 00b 1b 1b0b 0b 1b 1b 0bHost Settings Host Chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b Host Hi-Speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b Host Full Speed X1b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host HS/FS Resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Low Speed10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host Low Speed Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b Host Low Speed Resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b Host Test_J/Test_K 00b 0b 10b 1b 1b0b 0b 1b 1b 1bPeripheral Settings Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b Peripheral Hi-Speed00b 0b 00b 0b 0b0b 0b 0b 0b 1bPeripheral Full Speed 01b 1b 00b 0b 0b1b 0b 0b 0b 0b Peripheral HS/FS Suspend 01b 1b 00b 0b 0b1b 0b 0b 0b 0b Peripheral HS/FS Resume 01b 1b 10b 0b 0b1b 0b 0b 0b 0b Peripheral Low Speed 10b 1b 00b 0b 0b0b 1b 0b 0b 0b Peripheral Low Speed Suspend 10b 1b 00b 0b 0b0b 1b 0b 0b 0b Peripheral Low Speed Resume 10b 1b 10b 0b 0b0b 1b 0b 0b 0b Peripheral Test_J/Test_K 00b 0b 10b 0b 0b0b 0b 0b 0b 1b OTG device, Peripheral Chirp 00b 1b 10b 0b 1b1b 0b 0b 1b 0b OTG device, Peripheral Hi-Speed 00b 0b 00b 0b 1b0b 0b 0b 1b 1b OTG device, Peripheral Full Speed 01b 1b 00b 0b 1b1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b1b 0b 0b 1b 0b OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b1b 0b 0b 1b 0b OTG device, Peripheral Test_J/Test_K 00b 0b 10b 0b 1b0b 0b 0b 1b 1b Table 34 – Upstream and downstream signaling modesErrata 06 – SuspendM setting when exiting Low Power ModeType:Clarification.Issue:In section 3.9.3, Figure 46 and Figure 47, of the ULPI specification, it is not clear if it is the responsibility of the link or the PHY to set the SuspendM register bit to a 1 after exiting Low Power Mode. Unless a clear responsibility is stated, both link and PHY might assume that the other sets SuspendM to 1b, resulting in a hung bus that is always in Low Power Mode.Resolution:This is clarified in the SuspendM definition in Table 19, which states “The PHY must automatically set this bit to ‘1’ when Low Power Mode is exited.”To make this even clearer to the reader, a clarification should be added to section 3.9.3. Documentation Changes:The following changes will be added to the first paragraph of section 3.9.3.“As shown in Figure 46 and Figure 47, the Link signals the PHY to exit Low Power Mode by asynchronously asserting stp. The PHY immediately starts to wake up its internal circuitry. When the PHY clock meets ULPI timing requirements, the PHY de-asserts dir. The PHY must ensure a minimum of 5 cycles of clock have been driven prior to de-asserting dir. The PHY must also ensure that the SuspendM register is automatically set to 1b prior to de-asserting dir. The Link de-asserts stp in the cycle following the de-assertion of dir. There is one cycle of data bus turnaround provided after the de-assertion of dir, during which the value on data is not valid. The PHY stops driving the signals of Table 12 immediately before the turnaround cycle.”Figure 46 will also be changed to reflect that the SuspendM register bit must be set to 1b prior to de-asserting dir.Errata 07 – Validity of hostdisconnect in Low Power ModeType:Clarification.Issue:It is not clear if hostdisconnect is valid when the PHY is acting as a host and Low Power Mode is enabled. Resolution:This is clarified in the UTMI+ specification, but should be indicated in ULPI for clarity. The hostdisconnect status signal must be reset to 0b when the PHY enters Low Power Mode. Since the disconnect detection circuitry is powered down in Low Power Mode, no detection is possible. The link must look at LineState on the data bus for connect and disconnect events.Documentation Changes:The hostdisconnect description in Table 24 already states that “Applicable only in host mode”. This text must be expanded to state that:“Applicable only in host mode. Automatically reset to 0b when Low Power Mode is entered.”Errata 08 – Enabling detection of the ID pinType:Clarification.Issue:It is not clear when the IdGnd status is valid.Resolution:This is clarified in the UTMI+ specification, but should also be clarified in ULPI. The IdGnd status is valid50ms after IdPullup is set to 1b, and the OTG state machines should sample IdGnd only after the 50ms time. Documentation Changes:The IdGnd definition in Tables 22, 23, 24, and 25 require the following extra text:“IdGnd is valid 50ms after IdPullup is set to 1b, otherwise IdGnd is undefined and should be ignored.”Errata 09 – Clarifications on HS SOF packetsType:Clarification.Issue:HS SOF packets are not mentioned in the specification. This can cause confusion and could lead to implementations with different behaviors.Resolution:There are two important items to mention. First, the PHY must automatically append a 40-bit EOP when executing a TX CMD with the PID field set to A5. Second, HS SOF packets have a larger TX End Delay. Documentation Changes:The following text will be added to section 3.8.2.2:"For all PID packets, the PHY must automatically prepend a SYNC pattern and append an EOP pattern. In High Speed, when the PID field of the TX CMD is 5h, the PHY must recognize that this is a Start-Of-Frame (SOF) packet and automatically append a long EOP."A new row will be added to Table 9 to expand the TX End Delay parameters, as shown below.TX End Delay2-5 N/A N/ANumber of clocks between the PHY detecting stp on theULPI bus to completing transmission of EOP on the USBbus. Used for HS packets only. The Link can use TX EndDelay to calculate when the packet has completedtransmitting on the USB.HS EOP is completed when all 8 consecutive 1’s havefinished transmitting on the USB bus.FS and LS packets finish many clock cycles after stp isasserted. The Link must look for RX CMD bytes indicatingSE0-to-J transition to determine when the transmission hascompleted on the USB bus.6-9 N/A N/A HS SOF packets have a long EOP. The link must wait atleast 9 clocks or for an RX CMD indicating squelch(LineState = 00b) before transmitting the next packet.Errata 10 – Power Control of Interrupt SourcesType:Clarification.Issue:It is not known which interrupts should be powered down in each mode.Resolution:To ensure multi-vendor interoperability, the link must control the power state of the interrupts. Whenever an interrupt rising/falling enable bit is set, the associated circuit must be powered, regardless of the mode. There are two exceptions:1. IdGnd is gated with IdPullup.2. Hostdisconnect is never valid during Low Power Mode.Documentation Changes:The following text will be added to the first paragraph of Section 3.6, Interrupt Event Notification.“If an interrupt is enabled, the PHY must power the needed circuitry regardless of which mode the PHY is in. The only exceptions are the HostDisconnect interrupt which is valid only in Synchronous Mode, and the IdGnd interrupt which is controlled by IdPullup.”The following change will be made to the first paragraph of Section 3.9, Low Power Mode.“The Link can optionally place the PHY into Low Power Mode when the USB bus is suspended. The PHY can power down all circuitry except the interface pins and full speed receiver. The bus resistors must also be powered if V BUS is present. Any function must be powered if its corresponding register bit is set, including interrupt sources and the charge pump. If the PLL is powered down, the clock must be stopped without glitches.”The following change will be made to the first paragraph of Section 3.10, Full Speed / Low Speed Serial Mode.“Full Speed / Low Speed Serial Mode (FsLsSerialMode) gives the Link direct access to the FS/LS serial analog transmitter and receiver. Two types of serial mode are defined in ULPI: 3-pin FsLsSerialMode, and 6-pin FsLsSerialMode. Both modes are optional. The PHY can power down all circuitry except the interface pins, full speed transmitter and receiver. Any function must be powered if its corresponding register bit is set, including interrupt sources and the charge pump.”The following line will be added to the text describing interrupt registers in sections 4.2.5, 4.2.6, 4.2.7, and 4.2.8.“Interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled.”Errata 11 – Enabling Interrupts in Low Power, Serial, and Carkit Modes Type:Clarification.Issue:It is not known if both rising and falling edges should be enabled when the clock is powered down. Resolution:A clarification will be added that the link/software should set both the rising and falling interrupt enables whenever entering a mode where clock is off, such as Low Power Mode and Serial Mode. Documentation Changes:The following line will be added to the text describing interrupt registers in sections 3.6, 4.2.5, 4.2.6, 4.2.7, and 4.2.8.“To ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges.”Errata 12 – Carkit data during audioType:Addition.Issue:The carkit specification was not complete at the time of releasing ULPI 1.0. New additions are required to the ULPI register set to comply with the latest carkit specification. Specifically, carkit has added a data during audio feature.Resolution:Four new registers at a total of 6 addresses are required in the reserved area of the ULPI register set to provide the data during audio feature.Documentation Changes:The following text will be added to Section 3.11, Carkit.In cases of conflict between this specification and the Carkit specification, the Carkit specification shall take precedence.Four new registers are defined in Table 16, replacing 6 of the reserved addresses.Address (6 bits)Field nameSize (bits) Rd Wr Set Clr Immediate Register SetCarkit Pulse Control (Optional) 8 22-24h 22h 23h 24h Transmit Positive Width (Optional) 8 25h 25h - - Transmit Negative Width (Optional) 8 26h 26h - - Receive Polarity Recovery (Optional)8 27h 27h - -Register details will be inserted after section 4.2.15 as follows:4.2.16 Carkit Pulse ControlAddress: 22h-24h (Read), 22h (Write), 23h (Set), 24h (Clear).This register is optional. It controls the operation of the carkit data-during-audio function within the PHY. The TxPlsEn and RxPlsEn bits are ignored if the CarkitMode bit in the Interface Control register is not set.Refer to [Ref 7] for more information on carkit.Field name Bits Access Reset Description TxPlsEn 0rd/wr/s/c0bEnables data-during-audio pulse transmitRxPlsEn 1 rd/wr/s/c 0b Enables data-during-audio pulse receive SpkrLeftBiasEn 2 rd/wr/s/c 0b Enables bias for left speaker. SpkrRightBiasEn3rd/wr/s/c0bEnables bias for right speaker.Reserved 7:4 - 0000b Reserved.Table 2 – Carkit Pulse ControlTxPlsEnWhen the TxPlsEn bit is set, and the SpkLeftEn bit in the Carkit Control register is set, then the PHY shall output a positive pulse followed by a negative pulse on the D- line after each rising or falling edge on the data(0) line. When generating such a pulse pair, the PHY shall perform the steps, as defined in the Carkit specification [Ref 7]. The following list of steps provides information on the intent of the Carkit specification.• tri-state the speaker buffer that drives the D- line• drive the D- line to a voltage of 3.3V +/- 10%• wait for the time specified in the Transmit Positive Width register• drive the D- line to ground• wait for the time specified in the Transmit Negative Width register• stop driving the D- line to ground• enable the speaker buffer that drives the D- lineRxPlsEnWhen the RxPlsEn bit is set, and the MicEn bit in the Carkit Control register is set, then the PHY shall toggle the data(1) output each time a falling edge is detected on the D+ line that crosses the carkit interrupt threshold of V PH_DP_LO. When the RxPlsEn bit is set, the Receive Polarity Recovery timer shall be enabled.4.2.17 Transmit Positive WidthAddress: 25h (Read), 25h (Write)This register is optional. It specifies the width of the positive pulse that is output on the D- line when the TxPlsEn bit is set. The time is measured in units of 60MHz clock periods. The minimum TxPosWdth that must be supported is 8. The maximum TxPosWdth that must be supported is 64.Refer to [Ref 7] for more information on carkit.Field name Bits Access Reset DescriptionTxPosWdth 7:0 rd/wr 10h Transmit positive pulse widthTable 3 – Transmit Positive Width4.2.18 Transmit Negative WidthAddress: 26h (Read), 26h (Write)This register is optional. It specifies the width of the negative pulse that is output on the D- line when the TxPlsEn bit is set. The time is measured in units of 60MHz clock periods. The minimum TxNegWdth that must be supported is 8. The maximum TxNegWdth that must be supported is 64.Refer to [Ref 7] for more information on carkit.Field name Bits Access Reset DescriptionTxNegWdth 7:0 rd/wr 20h Transmit negative pulse widthTable 4 – Transmit Negative Width4.2.19 Receive Polarity RecoveryAddress: 27h (Read), 27h (Write)This register is optional.When the data-during-audio feature is enabled in the Carkit [Ref 7], then the carkit sends UART data to the phone by converting the non-return-to-zero (NRZ) UART signal into a series of pulses, and transmitting。
名词复数特殊变化的单词
名词复数特殊变化的单词以is结尾的单词：oasis—oases 绿洲crisis—crises 危机analysis—analyses 分析axis—axes 轴basis—bases 基础diagnosis—diagnoses 诊断thesis—theses 论文nemesis—nemeses 报应ellipsis—ellipses 省略号synopsis—synopses 大纲emphasis—emphases 强调antithesis（对立面）、parenthesis（括号）、hypothesis（假说）的复数形式可以参考thesis。
以x结尾的单词：appendix—appendixes/appendices 附录，阑尾index—indices 索引matrix—matrixes/matrices 矩阵vortex—vortices/vortexes 旋涡以um结尾的单词：bacterium—bacteria 细菌datum—data 数据medium—media 媒体phylum—phyla 门类curriculum—curricula/curriculums 课程momentum—momenta 动量quantum—quanta 量子stratum—strata 阶层memorandum—memoranda 备忘录ovum—ova 卵desideratum—desiderata 渴求之物erratum—errata 印刷错误gymnasium—gymnasiums/gymnasia 健身房millennium—millennia 千禧年forum—fora/forums 论坛aquarium—aquaria/aquariums 水族馆symposium—symposia/symposiums 座谈会referendum—referenda/referendums 公民投票dictum—dicta/dictums 名言以us结尾的单词：thesaurus—thesauri/thesauruses 同义词辞典fungus—fungi/funguses 真菌nucleus—nuclei 核uterus—uteri/uteruses 子宫focus—foci/focuses 焦点stimulus—stimuli 刺激syllabus—syllabi/syllabuses 课程表radius—radii/radiuses 半径abacus—abaci/abacuses 算盘terminus—termini/terminuses 终点cactus—cacti/cactuses/cactus 仙人掌genus—genera 属octopus—octopi/octopuses 八爪鱼colossus—colossi 巨像incubus—incubi/incubuses 梦魇corpus—corpora 文集以on结尾的单词：etymon—etymons/etyma 词源phenomenon—phenomena 现象criterion—criteria/criterions 准则lexicon—lexica/lexicons 词汇表automaton—automata/automatons 自动装置以a结尾的单词：larva—larvae 幼虫alga—algae 绿藻aurora—auroras/aurorae 极光antenna—antennae/antennas 触角formula—formulas/formulae 公式nebula—nebulae/nebulas 星云retina—retinae/retinas 视网膜vertebra—vertebrae/vertebras 脊椎vita—vitae个人简历其它：anecdote: anecdotes/anecdota 轶事rhinoceros—rhinoceri/rhinoceros(es) 犀牛trauma—traumata/traumas 创伤bandit—banditti/bandits 强盗dilettante—dilettanti/dilettantes 半吊子virtuoso—virtuosi/virtuosos 技艺精湛者在拉丁语中名词有性、数、格的语法概念，英语在借词过程中甚至也会将这些特征借过来，如：alumnus—alumni 男校友alumna—alumnae 女校友。
Errata 4437A 衰减器运行和维修手册说明书
1981ErrataTitle & Document Type: 4437A Attenuator Operating and Service Manual Manual Part Number: 04437-90003Revision Date: November 1981About this ManualWe’ve added this manual to the Agilent website in an effort to help you support your product. This manual provides the best information we could find. It may be incompleteor contain dated information, and the scan quality may not be ideal. If we find a bettercopy in the future, we will add it to the Agilent website.HP References in this ManualThis manual may contain references to HP or Hewlett-Packard. Please note that Hewlett- Packard's former test and measurement, life sciences, and chemical analysisbusinesses are now part of Agilent Technologies. The HP XXXX referred to in this document is now the Agilent XXXX. For example, model number HP8648A is now model number Agilent 8648A. We have made no changes to this manual copy.Support for Your ProductAgilent no longer sells or supports this product. You will find any other availableproduct information on the Agilent Test & Measurement website:Search for the model number of this product, and the resulting product page will guideyou to any available information. Our service centers may be able to perform calibrationif no repair parts are needed, but no other support from Agilent is available.。
802.3-2002_errata
IEEE Std 802.3™-2002(Revision of IEEE Std 802.3-2000 Edition) Corrections toInformation technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements—Part 3: Carrier sense multiple accesswith collision detection (CSMA/CD)access method and physical layer specificationsS ponsorLAN/MAN Standards Committeeof theIEEE Computer SocietyCorrection SheetIssued 29 June 2004Copyright © 2004 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 2004. Printed in the United States of America.This correction sheet may be freely reproduced and distributed in order to maintainthe utility and currency of the underlying Standard. This correction sheet may not besold, licensed or otherwise distributed for any commercial purposes whatsoever.The content of this correction sheet may not be modified.CORRECTIONS TO IEEE Std 802.3-2002IEEE Std 802.3-2002 Section 3: page 50: subclause 36.2.5.1.3 Variables.cgbadAlias for the following terms: ((rx_code-groupŒ/INVALID/) + (rx_code-group=/COMMA/*rx_even=TRUE)) * PMA_UNITDATA.indicateshould readcgbadAlias for the following terms: ((rx_code-group∈/INV ALID/) + (rx_code-group=/COMMA/*rx_even=TRUE)) * PMA_UNITDATA.indicateIEEE Std 802.3-2002 Section 3: page 50: subclause 36.2.5.1.3 Variables.cggoodAlias for the following terms: !((rx_code-group Œ/INVALID/) + (rx_code-group=/COMMA/*rx_even=TRUE)) * PMA_UNITDATA.indicateshould readcggoodAlias for the following terms: !((rx_code-group∈/INVALID/) + (rx_code-group=/COMMA/*rx_even=TRUE)) * PMA_UNITDATA.indicateIEEE Std 802.3-2002 Section 3: page 54: subclause 36.2.5.1.4 Functions.VOID(x)x Œ/D/, /T/, /R/, /K28.5/. Substitutes /V/ on a per code-group basis as requested by the GMII. should readVOID(x)x ∈/D/, /T/, /R/, /K28.5/. Substitutes /V/ on a per code-group basis as requested by the GMII. IEEE Std 802.3-2002 Section 3: page 360: 40C.1 State variables.Delete the following variable from 40C.1:1000T_capableThis variable is used merely to show the local device is 1000Base-T capable. It is shown toillustrate the path that a non-1000Base-T device would take within the auto negotiation mechanism. Insert the following variable in 40C.1 (this should be inserted in alphabetical order):desire_1000T_advThe local device desires a 1000BASE-T link.Values: true; bit 9.8 or 9.9 do not contain a logic zero.false; bits 9.8 and 9.9 both contain a logic zero.IEEE Std 802.3-2002 Section 3: page 363: 40C-2 Auto-Negotiation Transmit state diagram add on for 1000BASE-T.Change note 3 of Figure 40C-23—(Flp_Link_Good_Check) This is shown for illustration only. This state is from the Auto-Negotiation arbitration state diagram and indicates the conclusion of pages being sent. (The transition desire_1000T_adv = false is to show sequence for non 1000BASE-T implementations.)。
Verrata Plus压力导丝和IntraSight介入应用平台说明书
One wire, one system,multi-modalityVerrata Plus pressure guide wire• Quickly disconnect and reliably reconnect• Proximal wire design resists kinks and repels moisture• Clip connector has multiple back-up contact points for a secure signalIntraSight interventional applications platform• Delivers today’s best-in-class imaging, physiology and co-registration* tools including iFR and iFR Co-registration• Minimizes learning curves, increases workflow confidence and provides an outstanding user* Co-registration tools available within IntraSight 7 configuration via SyncVision.1. Davies JE, et al., Use of the Instantaneous Wave-free Ratio or Fractional Flow Reserve in PCI. N Engl J Med. 2017 May 11;376(19):1824-18342. Gotberg M, et al., iFR-SWEDEHEART Investigators.. Instantaneous Wave-free Ratio versus Fractional Flow Reserve to Guide PCI. N Engl J Med. 2017 May11;376(19):1813-18233. An iFR cut-point of 0.89 matches best with an FFR ischemic cut-point of 0.80 with a specificity of 87.8% and sensitivity of 73.0%. (iFR Operator’s Manual505-0101.23)Make the shift from justification to guidance with the iFR modality© 2019 Koninklijke Philips N.V. All rights reserved. Approved for external distribution.D041648-01 062019Philips3721 Valley Centre Drive, Suite 500San Diego, CA 92130 USA/IGTdevicesiFRModalityThe iFR Scout pullback shows that the vessel is physiologicallysignificant, with areas of focal disease (1 and 2) and diffuse disease (3).The most significant gradient is in the mid-vessel lesion with diffuse proximal disease.Plan the treatment strategy1.000.950.900.850.80510152025303540iFR Distal0.84Confirm the result1.000.950.900.85332211。
芯片手册-AT83C51SND2C errata 说明书
1.Active AT83C51SND2C Errata List•SPI Controller – Bad Transfer in Slave Mode with CPHA = 0•C51 Core – Bad Exit of Power-down in X2 Mode•MP3 Decoder – Extra Power Consumption after Reset •Modulation2.AT83C51SND2C Errata History3.AT83C51SND2C Errata Description1.SPI Controller – Bad Transfer in Slave Mode with CPHA = 0SPI controller used in slave mode with CPHA = 0 leads to erratic data reception and transmission.WorkaroundUse slave mode only with CPHA = 1.2.C51 Core – Bad Exit of Power-down in X2 ModeWhen exiting Power-down mode by interrupt while CPU is in X2 mode, it leads to bad execution of first instruction executed when CPU restarts.WorkaroundPut the CPU in X1 mode just before entering power-down mode.3.MP3 Decoder – Extra Power Consumption after ResetUnder certain power-up conditions, MP3 decoder may not be well reset leading to an extra power consumption. This extra consumption disappears after playing one MP3 song.WorkaroundThe software workaround consists of enabling and disabling the MP3 macrocell while PLL is running. This starts internal decoder reset process and removes the extra power consumption.Implemented in latest firmware packages. 4.ModulationApproximately 1 KHz, for pure sinus wave input, depending on the volume band. Some modulation may appear for input signal levels above -9dB.WorkaroundUse input signal level lower than -9dB.Lot Number Errata List All lot numbers1, 2, 3, 44413A–MP3–01/05© Atmel Corporation 2005. All rights reserved. Atmel ®, logo and combinations thereof, [insert any additional, applicable Atmel registered marks here] are registered trademarks, and Everywhere You Are SM are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80Literature Requests/literature。
张欣：可计算一般均衡模型的基本原理与编程Errata勘误10-2010
张欣：可计算一般均衡模型的基本原理与编程Errata勘误10-2010《可计算一般均衡模型的基本原理和编程》勘误表 (Errata)张欣，上海人民出版社，格致出版社，2010p.7, 第7行，“收入产出表”应为“投入产出表”p.10, 等式2.2.5, 一些Q 的下标有误，应为:111111111111........................j j n n i ij j in n i i in nj j nn n n n na Q a Q a Q H I Q a Q a Q a Q H I Q a Q a Q a Q H I Q ++++++=++++++=++++++=p.11, 等式2.2.7，原等式缺了加号。
应为: 11......i i n n H I H I H I +=+??????+??Dp.21 练习 1 的最上一行表头的“中间投入合计”，应为“中间使用合计”；p.26, 表 3.2.2，中间使用列的表头“部门i ” 应为“部门j ”p. 41，练习题1 第三行应为“国外要素收入”，期中“国”字缺失。
p. 45, 表5.2.2.最后一列的128应为209.p. 45, 等式5.2.4 缺少了一个243(192)Q -，应为222221112142122222224313243min(52)(45)(150)(95)(48)(90)(120)(89)(192)z Q Q Q Q Q Q Q Q Q =-+-+-+-+-+-+-+-+-p. 55, 等式 5.6.4 中两个分母ij X 应该是ij Qp. 56, 第12行，*ij X 应该是*ij Qp. 62，练习题1d 的表中，2060 应为 2900p. 64, 第1行，*i y 应该改为*i qp. 65 , 第9行, 定义中**(,)p x ，应为**(,)p qp. 80, 图 7.3.2 中以及下面解释一行中 rho 的值应该是负无穷大。
修正书：文档勘误与致歉
修正书：文档勘误与致歉在撰写英文作文修正书时，我们需要考虑几个关键要素：文档勘误（Errata）、致歉（Apologies）、以及对读者的尊重和感谢。
以下是一个英文作文修正书的示例，您可以根据具体情况进行调整：---**Errata and Apology Letter**Dear [Recipient's Name],Subject: Correction of Errors in [Document/Essay Title]I hope this letter finds you well. I am writing to bring to your attention several errors that were inadvertently included in the [Document/Essay Title] that was [submitted/published] on [Date ofSubmission/Publication]. It is with sincere regret that I acknowledge these oversights, and I would like to take this opportunity to provide the necessary corrections and extend my apologies for any confusion or inconvenience this may have caused.**Errata:**1. On page [Page Number], the sentence " [Incorrect Sentence] " should read " [Corrected Sentence] ".2. The reference to [Specific Information] on page [Page Number] is incorrect. The accurate information is [Correct Information].3. In the section titled [Section Title], the data presented in Table [Table Number] was mistakenly [describe the error, e.g., transposed, miscalculated]. The corrected table is attached for your reference.**Apologies:**I deeply apologize for these mistakes and any impact they may have had on the integrity and clarity of the [Document/Essay]. It is my responsibility to ensure that all work is accurate and I am committed to upholding this standard moving forward.**Acknowledgements:**I would like to express my gratitude to [anyone who pointed out the errors or assisted in identifying them] for their vigilance and assistance in identifying these errors. Their feedback is invaluable and willcontribute to improving the quality of my future work.**Action Plan:**To prevent similar issues in the future, I will [describe any steps you plan to take to prevent such errors, e.g., implement a more rigorous review process, use spell-check and grammar-check tools more effectively, etc.].Once again, I apologize for any inconvenience caused by these errors. Please find the corrected document attached to this letter. Should you require any further clarification or assistance, do not hesitate to contact me.Thank you for your understanding and continued support.Sincerely,[Your Name][Your Contact Information]---请根据您的具体情况调整上述模板，包括文档标题、错误详情、致歉内容以及您个人的联系信息等。
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《COM原理与应用》勘误表
(2000年5月修订)
作者说明：有一些文字上的错误或者显而易见的错误不再说明，这里给出的是一些重要的错误或者遗漏。
42页：
(1)
(2)接口自反性。
对一个接口查询其自身总应该成功，比如
pDictionary->QueryInterface(IID_Dictionary, ...) 应该返回S_OK。
(3)接口对称性。
如果从一个接口指针查询到另一个接口指针，
67页最后一段：
CoCreateInstance是一个被包装过的辅助函数，在它的内部实际上也调用了CoGetClassObject函数，CoCreateInstance的参数clsid、dwClsContext、iid和ppv的含义与CoGetClassObject相应的参数一致，
*说明：这里的iid和ppv在两个函数CoCreateInstance和CoGetClassObject不一样，一个是指向对象的接口信息，另一个是指向类厂的接口信息。
85页下左：
CoGetClassObject(clsid,
CLSCTX_LOCAL_SERVER,
NULL,
IID_IClassFactory,
(void **)&pClf);
86页下右：
调用CoUninitialize
组件程序退出
113页中间：
HRESULT CoMarshalInterface( IStream *pStm,
REFIID riid,
IUnknown *pUnk,
DWORD dwDestContext,
void * pvDestContext,
unsigned long mshlflags);
192页：
图6.5 用CCmdTarget实现源对象的程序结构图
342页：
在DISPPARAMS结构中，rg v arg数组成员包括调用的所有参数，每个参数的类型为V ARIANTARG，V ARIANTARG结构的定义与V ARIANT完全一致，我们可以等同处理。
一般来说，对于设置属性调用，rg v arg只包含一个参数；对于方法调用，rg v arg可能包含0个或多个参数。
除非在参数的vt域中指定了VT_BYREF标志，否则我们认为rg v arg数组的成员为只读的。
若参数的vt域没有指定VT_BYREF标志，那么字符串或者指针变量所有权在于客户程序，资源释放也由客户负责，如果对象要保留引用的话，必须拷贝数据或者调用AddRef函数；若参数的vt域指定了VT_BYREF标志，那么我们可以把它用作输出参数。
351页：
MIDL_INTERFACE("3C591B25-1F13-101B-B826-00DD01103DE1")
IPoint : public IUnknown
{
public:
virtual /* [helpstring][propget] */ HRESULT STDMETHODCALLTYPE get_x(
/* [retval][out] */ int __RPC_FAR *retval) = 0;
virtual /* [helpstring][propput] */ HRESULT STDMETHODCALLTYPE put_x(
/* [in] */ int Value) = 0;
virtual /* [helpstring][propget] */ HRESULT STDMETHODCALLTYPE get_y(
/* [retval][out] */ int __RPC_FAR *retval) = 0;
virtual /* [helpstring][propput] */ HRESULT STDMETHODCALLTYPE put_y(
/* [in] */ int Value) = 0;
virtual /* [helpstring] */ HRESULT STDMETHODCALLTYPE MoveTo(
/* [in] */ int newX,
/* [in] */ int newy) = 0;
};
MIDL_INTERFACE("3C591B26-1F13-101B-B826-00DD01103DE1")
DIPoint : public IDispatch
{
};
377-379页：
class IOleWindow : public IUnknown
{
virtual HRESULT GetWindow(HWND *phwnd) = 0;
virtual HRESULT ContextSensitiveHelp(BOOL fEnterMode) = 0;
};
class IOleInPlaceSite : public IOleWindow
{
virtual HRESULT CanInPlaceActivate(void) = 0;
virtual HRESULT OnInPlaceActivate(void) = 0;
virtual HRESULT OnUIActivate(void) = 0;
virtual HRESULT GetWindowContext(LPOLEINPLACEFRAME *ppFrame,
LPOLEINPLACEUIWINDOW *ppDoc, LPRECT prcPosRect,
LPRECT prcClipRect, LPOLEINPLACEFRAMEINFO pFrameInfo) = 0;
virtual HRESULT Scroll(SIZE scrollExtent) = 0;
virtual HRESULT OnUIDeactivate(BOOL fUndoable) = 0;
virtual HRESULT OnInPlaceDeactivate(void) = 0;
virtual HRESULT DiscardUndoState(void) = 0;
virtual HRESULT DeactivateAndUndo(void) = 0;
virtual HRESULT OnPosRectChange(LPCRECT prcPosRect) = 0;
};
class IOleInPlaceUIWindow : public IOleWindow
{
virtual HRESULT GetBorder(LPRECT prcBorder) = 0;
virtual HRESULT RequestBorderSpace(LPCBORDERWIDTHS pBW) = 0;
virtual HRESULT SetBorderSpace(LPCBORDERWIDTHS pBW) = 0;
virtual HRESULT SetActiveObject(LPOLEINPLACEACTIVEOBJECT pActiveObject,
LPCOLESTR pszObjName) = 0;
};
class IOleInPlaceFrame : public IOleInPlaceUIWindow
{
virtual HRESULT InsertMenus(HMENU hMenuShared,
LPOLEMENUGROUPWIDTHS lpMenuWidths) = 0;
virtual HRESULT SetMenu(HMENU hMenuShared, HOLEMENU hOLEMenu,
HWND hWndActiveObj) = 0;
virtual HRESULT RemoveMenus(HMENU hMenuShared) = 0;
virtual HRESULT SetStatusText(LPCOLESTR pszStatusText) = 0;
virtual HRESULT EnableModeless(BOOL fEnable) = 0;
virtual HRESULT TranslateAccelerator(LPMSG pMsg, WORD wID) = 0;
};
*说明：这一章后面许多接口的定义都缺少成员函数前面的virtual声明。
379页：
嵌入对象的其它接口
IOleInPlaceObject
IOleInPlaceActiveObject
图12.2 支持实地激活特性的对象结构图
407页：
<OBJECT CLASSID="clsid:5220CB21-C88D-11CF-B347-00AA00A28331">
<PARAM NAME="LPKPath" V ALUE="MyPage.lpk">
</OBJECT>
424页倒数第三段：
MTS推荐使用基于角色的安全模型，这种模型以MTS服务进程为安全单元，它不单独定义组件的安全角色。
同时，MTS还提供了另一种高级安全模型，环境对象除了实现IObjectContext接口，它还实现了另一个安全属性接口ISecurityProperty，利用此接口，对象可以获得创建对象的客户的安全标识符(SID)以及当前调用此对象的客户的安全标识符。
应用系统可以通过这些信息实现自定义的访问控制，犹如使用Win32的安全编程接口一样。
*说明：IObjectControl是由MTS对象实现的接口。