EDA实验报告 -状态机
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EDA实验报告
1状态机程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY circle IS
PORT(CLK1,RESET1 :IN STD_LOGIC;
D0,D1,D2,D3,D4:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END circle;
ARCHITECTURE behv OF circle IS
TYPE FSM_ST IS (s0,s1,s2,s3,s4,s5,s6);
SIGNAL current_state,next_state:FSM_ST;
BEGIN
REG:PROCESS(CLK1,RESET1)
BEGIN
IF RESET1='0' THEN current_state<=s0;
ELSIF CLK1='1'AND CLK1'EVENT THEN
current_state<=next_state;
END IF;
END PROCESS;
COM:PROCESS(current_state,next_state)
BEGIN
CASE current_state IS
WHEN s0=> D0<="1111001";D1<="1111111";D2<="1111111";D3<="1111111";D4<="1111111"; next_state<=s1;
WHEN s1=> D0<="0100100";D1<="1111001";D2<="1111111";D3<="1111111";D4<="1111111"; next_state<=s2;
WHEN s2=> D0<="0110000";D1<="0100100";D2<="1111001";D3<="1111111";D4<="1111111";
next_state<=s3;
WHEN s3=> D0<="1111111";D1<="0110000";D2<="0100100";D3<="1111001";D4<="1111111";
next_state<=s4;
WHEN s4=> D0<="1111111";D1<="1111111";D2<="0110000";D3<="0100100";D4<="1111001";
next_state<=s5;
WHEN s5=> D0<="1111001";D1<="1111111";D2<="1111111";D3<="0110000";D4<="0100100";
next_state<=s6;
WHEN s6=> D0<="0010010";D1<="1111001";D2<="1111111";D3<="1111111";D4<="0110000";
next_state<=s2;
END CASE;
END PROCESS;
END behv;
2.1秒时间程序：
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY timer1 IS
PORT(CLK,RESET:IN STD_LOGIC;
CONT:OUT STD_LOGIC);
END ENTITY timer1;
ARCHITECTURE bhv OF timer1 IS
BEGIN
PROCESS(CLK,RESET)
V ARIABLE Q:INTEGER RANGE 0 TO 50000000;
BEGIN
IF RESET='0' THEN CONT<='0';
ELSIF CLK'EVENT AND CLK ='1' THEN Q:=Q+1;
END IF;
IF Q=50000000 THEN Q:=0;CONT<='1';
ELSE CONT<='0';
END IF;
END PROCESS;
END bhv;
3.总程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY circle123 IS
PORT(CLK2,RESET2:IN STD_LOGIC;
b1,b2,b3,b4,b5:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END ENTITY circle123;
ARCHITECTURE one OF circle123 IS
COMPONENT timer1
PORT(CLK,RESET:IN STD_LOGIC;
CONT:OUT STD_LOGIC);
END COMPONENT;
COMPONENT circle
PORT(CLK1,RESET1 :IN STD_LOGIC;
D0,D1,D2,D3,D4:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
SIGNAL H:STD_LOGIC;
BEGIN
u1:timer1 PORT MAP(CLK=>CLK2,RESET=>RESET2,CONT=>H);
u2:circle PORT MAP(CLK1=>H,RESET1=>RESET2,D0=>b1,D1=>b2,D2=>b3,D3=>b4,D4=>b5);
END ARCHITECTURE one;