数字通信系统设计实验报告
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实验1:用 Verilog HDL 程序实现乘法器
1实验要求:
(1) 编写乘法器的 Veirlog HDL 程序.
(2) 编写配套的测试基准.
(3) 通过 QuartusII 编译下载到目标 FPGA器件中进行验证
(4) 注意乘法逻辑电路的设计.
2 试验程序：
Module multiplier(input rst,input clk,input [3:0]multiplicand,
input [3:0]multiplier,input start_sig,output done_sig,output [7:0]result); reg [3:0]i;
reg [7:0]r_result;
reg r_done_sig;
reg [7:0]intermediate;
always @ ( posedge clk or negedge rst )
if( !rst )
begin
i<=4'b0;
r_result<=8'b0;
end
else
if(start_sig)
begin
case(i)
0:
begin
intermediate<={4'b0,multiplicand};
r_result<=8'b0;
i<=i+1;
end
1,2,3,4:
begin
if(multiplier[i-1])
begin
r_result<=r_result+intermediate;
end
intermediate<={intermediate[6:0],1'b0};
i<=i+1;
end
5:
begin
r_done_sig<=1'b1;
i<=i+1;
end
6:
begin
r_done_sig<=1'b0;
i<=1'b0;
end
endcase
end
assign result=r_done_sig?r_result:8'bz; assign done_sig=r_done_sig;
endmodule3
测试基准：
`timescale 1 ps/ 1 ps
module multiplier_simulation();
reg clk;
reg rst;
reg [3:0]multiplicand;
reg [3:0]multiplier;
reg start_sig;
wire done_sig;
wire [7:0]result;
/***********************************/ initial
begin
rst = 0; #10; rst = 1;
clk = 1; forever #10 clk = ~clk;
end
/***********************************/ multiplier U1
(
.clk(clk),
.rst(rst),
.multiplicand(multiplicand),
.multiplier(multiplier),
.result(result),
.done_sig(done_sig),
.start_sig(start_sig)
);
reg [3:0]i;
always @ ( posedge clk or negedge rst ) if( !rst )
begin
i <= 4'd0;
start_sig <= 1'b0;
multiplicand <= 4'd0;
multiplier <= 4'd0;
end
else
case( i )
0: // multiplicand = 10 , multiplier = 2
if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
else begin multiplicand <= 4'd10; multiplier <= 4'd2; start_sig <= 1'b1; end
1: // multiplicand = 15 , multiplier = 15
if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
else begin multiplicand <= 4'd15; multiplier <= 4'd15; start_sig <= 1'b1; end
2: // multiplicand = 0 , multiplier = 0
if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
else begin multiplicand <= 4'd0; multiplier <= 4'd1; start_sig <= 1'b1; end
3: // multiplicand = 7 , multiplier = 11
if( done_sig ) begin start_sig <= 1'b0; i <= i + 1'b1; end
else begin multiplicand <= 4'd7; multiplier <= 4'd11; start_sig <= 1'b1; end
4:begin i <= i; end
endcase
endmodule4
仿真图形：